# The HIOMAP protocol is used to access PNOR
unset SFC_IS_AST2500
unset SFC_IS_AST2400
set   PNORDD_IS_IPMI
unset PNORDD_IS_SFC
unset ALLOW_MICRON_PNOR
unset ALLOW_MACRONIX_PNOR

# VPD options - Enable EECACHE
set MVPD_READ_FROM_HW
set MVPD_WRITE_TO_HW
unset MVPD_READ_FROM_PNOR
unset MVPD_WRITE_TO_PNOR

set DJVPD_READ_FROM_HW
set DJVPD_WRITE_TO_HW
unset DJVPD_READ_FROM_PNOR
unset DJVPD_WRITE_TO_PNOR

set MEMVPD_READ_FROM_HW
set MEMVPD_WRITE_TO_HW
unset MEMVPD_READ_FROM_PNOR
unset MEMVPD_WRITE_TO_PNOR

# PLDM will be read via PLDM which is not supported yet
#set PVPD_READ_FROM_HW
#set PVPD_WRITE_TO_HW
#unset PVPD_READ_FROM_PNOR
#unset PVPD_WRITE_TO_PNOR

# gpio config
set GPIODD
unset PALMETTO_VDDR

# Enable consecutive SBE updates
set SBE_UPDATE_CONSECUTIVE
unset SBE_UPDATE_INDEPENDENT
unset SBE_UPDATE_SEQUENTIAL
unset SBE_UPDATE_SIMULTANEOUS
unset NO_SBE_UPDATES
# NOTE: Aggressive LRU currently required to free enough memory for SBE updates
set AGGRESSIVE_LRU

#unset PCIE_HOTPLUG_CONTROLLER

# turn on console output
set CONSOLE

set BMC_AST2500

#set DISABLE_HOSTBOOT_RUNTIME

# Compile in hostboot runtime PRD
#unset HBRT_PRD

# PNOR flags
unset PNOR_TWO_SIDE_SUPPORT

set BMC_BT_LPC_IPMI

# AXONE configs must be set until those flags are reworked in Hostboot
set AXONE
set AXONE_BRINGUP

# Enable hardware access to the EEPROMs with a cache
set SUPPORT_EEPROM_CACHING
set SUPPORT_EEPROM_HWACCESS

# set for trace debug to console
unset CONSOLE_OUTPUT_TRACE

# Output FFDC to console
set CONSOLE_OUTPUT_FFDCDISPLAY

# RTC TODO 248361
# Remove some time before product ships
set PRINT_SYSTEM_INFO

# Terminate Hostboot when errors occur in manufacturing mode
#   (relies on BMC to not trigger reboot)
#unset HANG_ON_MFG_SRC_TERM

set ENABLE_HDAT_IN_HOSTBOOT

# Temporary workaround for SW461052
set P10_BRING_UP

# Load lids via PLDM File IO
unset LOAD_PHYP_FROM_BOOTKERNEL
set LOAD_LIDS_VIA_PLDM

# enable multi-chip
unset FORCE_SINGLE_CHIP