tree 3403acd3c405af0a8c0e2221a58853895be129be
parent 8cf51efe213bce8790e69961d334c304531f7385
author hostboot <hostboot@us.ibm.com> 1505948543 -0500
committer hostboot <hostboot@us.ibm.com> 1505948543 -0500

op-build update 9-20-2017

Changes Included for sbe:
ff713df - Dean Sanner - 2017-09-19 - Prime PSSCR reg on thread 1 so istep 16 works in SMT1
4466b70 - Thi Tran - 2017-09-17 - L3 Update - p9_hcd_cache_stopclocks HWP
3cd9368 - Ben Gass - 2017-09-17 - Updates for HW416934 and HW417233
d0fd50d - Nick Klazynski - 2017-09-17 - HW415528 and HW419742
60ec50c - Sachin Gupta - 2017-09-15 - Make DD2 as default in debug tools
79722ff - Sachin Gupta - 2017-09-15 - Mask special attention in MPIPL
f978e9c - Doug Gilbert - 2017-09-14 - PK,IOTA: Enter idle state at a known location
d7db485 - spashabk-in - 2017-09-14 - Update sbe local reg dump options
e2db15c - Yue Du - 2017-09-13 - StopClocks: Fence Refresh region if L3 region clock is stopped
260d2b4 - Lennard Streat - 2017-09-13 - Expanding MCU tag fifo settings to be freq dependent.
4d82267 - spashabk-in - 2017-09-12 - SBE debug tool - stack usage from pibmem dump
a61ac11 - Prasad Bg Ranganath - 2017-09-12 - PSTATE: Safe mode implmentation in PPB
364d444 - spashabk-in - 2017-09-12 - [Whitelist/Blacklist] - Adding test cases for table generation
ba90b50 - Nick Klazynski - 2017-09-12 - Add updates for NDD2.1, Serialize TB, Perf workarounds
f0d4e05 - Andre Marin - 2017-09-12 - Remove logic to disable memory clocks in STR if in PD_AND_STR_CLK_STOP mode
306dcd7 - Abhishek Agarwal - 2017-09-12 - ATTR_CHIP_EC_FEATURE_HW406337 support for Axone
0816100 - Joachim Fenkes - 2017-09-12 - HW415692: Make workaround permanent
ded5e86 - John Rell - 2017-09-12 - jgr17082300 Setting changes for HW41801 HW419305
0e0569f - dchowe - 2017-09-12 - disable lpc_ed in fbc to match mc setting
a89a1a5 - Nick Klazynski - 2017-09-12 - Add perf inits: HW418850,HW418789; Add clockgate issue HW418738
97617be - Joe McGill - 2017-09-12 - resolve Zeppelin DMI channel framelock issues
b6fa4d1 - Nick Klazynski - 2017-09-12 - Mistakenly pulled workaround for HW410212 - readd for CDD1.0
bb90b27 - Nick Klazynski - 2017-09-12 - Reverting chickenswitches for issues fixed in Cumulus DD1.0
e3fcca0 - Nick Klazynski - 2017-09-12 - Update core initfiles for Cumulus DD1.0
14adfe3 - Andre Marin - 2017-09-12 - Modified gen_accessors script for greater support
ffbd9a7 - crgeddes - 2017-09-12 - Use DD1 SW reset for XIVE unit until we get HW reset working in DD2
79b3257 - Joe McGill - 2017-09-12 - p9.int.scom.initfile -- mask SUE FIR for Nimbus DD2
4c4301c - Nick Klazynski - 2017-09-12 - Add additional dials to risklevel
b23c89f - Andre Marin - 2017-09-12 - Remove reset_dll from scominit, enable delay line tap points
db03365 - Joe McGill - 2017-09-12 - p9.npu.scom.initfile -- FIR updates to align with RAS XML documentation
cd6f911 - Joe McGill - 2017-09-12 - TP, Nest FIR updates -- DD2 updates to match RAS XML
891fed6 - Sumit Kumar - 2017-09-12 - GPTR/Overlays stage-2 support
b28f571 - Joachim Fenkes - 2017-09-12 - p9_sbe_tracearray: Nimbus DD2 updates
75accc4 - Ben Gass - 2017-09-12 - Create dmi.pll.scan.initfile
614e6e5 - Nick Klazynski - 2017-09-12 - Add WA for HW415988
75a8f58 - Luke C. Murray - 2017-09-12 - HW414700 checkstop on UEs and disable core ECC counter
fd64d4f - Claus Michael Olsen - 2017-09-12 - xip_customize: GPTR/overlays stage 1 support
14ef379 - Nick Klazynski - 2017-09-12 - Add WA for HW415236
75adc1a - Nick Klazynski - 2017-09-12 - Add Workarounds for HW415114 HW415013 HW413853 HW414384
bb69b45 - dchowe - 2017-09-12 - Update FBC cd_hp initfile to reference serial mode spys directly
2c5edb2 - Prasad Bg Ranganath - 2017-09-12 - PSTATE_PARAMETER_BLOCK structure alignment and error handling
dc290bc - Luke C. Murray - 2017-09-12 - Disabling LVext for all P9 parts
5ea62f2 - Joe McGill - 2017-09-12 - p9.npu.scom.initfile -- Nimbus DD2 updates
c355473 - Anusha Reddy Rangareddygari - 2017-09-12 - Cumulus proc updates
1f819e6 - Joe McGill - 2017-09-12 - p9.pci.scan.initfile -- initial release
4f6b637 - dchowe - 2017-09-12 - DD2 updated scan overrides, Cumulus DD1 initfile updates
df6f0a3 - Nick Klazynski - 2017-09-12 - Add WAs for HW413799 HW413853 HW413917 HW414249 HW414375 HW414871 HW414829
31e85b6 - Jenny Huynh - 2017-09-12 - Adding HW414702 workaround to INT scan initfiles
2b0a68e - Joe McGill - 2017-09-12 - PCIe updates for Nimbus DD2 GEN4 operation
d3966eb - Joe McGill - 2017-09-12 - p9.core.scan.initfile -- set disable 241 for Nimbus DD2
e8bee77 - Stephen Glancy - 2017-09-12 - Fixed DLL workarounds to always run
82afec3 - Nick Klazynski - 2017-09-12 - Workarounds for HW407385 HW408629 HW410389 HW408901
c461678 - Alex Taft - 2017-09-12 - L3 Initfile: Qualify divide_minor setting
44bbce4 - Shelton Leung - 2017-09-12 - dd2 phy scom inits
02aec23 - Ben Gass - 2017-09-12 - Use obus p9ndd1 spy name attribute for obus initfile
cf9e511 - Nick Klazynski - 2017-09-12 - Add core workaround for HW407136
a47f103 - Andre Marin - 2017-09-12 - Disable mem clk stop when in STR for DD2.* only
c543770 - Joe McGill - 2017-09-12 - L3 update -- p9_pcie_config
71cf01b - Greg Still - 2017-09-12 - PM: refine enablement attributes for advanced functions (VDM,RESCLK,WOF,IVRM)
3d13bb9 - Thi Tran - 2017-09-12 - Undo some p9 Cumulus spy workarounds in initfiles
bbc370f - Soma BhanuTej - 2017-09-12 - Cumulus initfile update for OBUS & XBUS PLLs
1706ced - Shelton Leung - 2017-09-12 - adjusted mem 2400 nest 1600 workaround and make dd1 only
4ce41e0 - Thi Tran - 2017-09-12 - P9 Cumulus InitCompiler supportis - Part 3
28f741b - Joe McGill - 2017-09-12 - future proof EC feature attributes, add missing P9N DD2 inits
f20979a - John Rell - 2017-09-12 - jgr17050500 Added Centaur and DMI IO SCOM initfiles
1690ba9 - Nick Klazynski - 2017-09-12 - Update core inits for DD2
ecdc612 - Stephen Glancy - 2017-09-12 - Updated memory DD1 vs DD2 attribute
d41dd21 - Joe McGill - 2017-09-12 - L3 updates -- p9_build_smp, p9_fbc_utils
908dc3c - Stephen Glancy - 2017-09-12 - Adds DCD calibration control attributes
f73f399 - dchowe - 2017-09-12 - Initfile updates for FBC DD2
c6d8110 - Joe McGill - 2017-09-12 - p9.int.scan.initfile -- init PSIHB to LSI mode
ae010d8 - David Kauer - 2017-09-12 - Update INT DD2 initfiles
2f3ac4c - Chris Hanudel - 2017-09-12 - Updates for P9 NX DD2 initfiles
06bc854 - Andre Marin - 2017-09-12 - Add DLL workaround and unit tests
70b78cd - Emmanuel Sacristan - 2017-09-12 - NMMU Nimbus dd2 scom/scan updates, updated comments
8b5cfa9 - Michael Koch - 2017-09-12 - Implementing Michael Floyds improvements.
8e1da2d - Stephen Glancy - 2017-09-12 - Added DQS alignment workaround
6716537 - Joe McGill - 2017-09-12 - p9.xbus.pll.scan.initfile -- restore full frequency settings for Nimbus DD2+
e3b9ee6 - Shelton Leung - 2017-09-12 - dd2 inits
74dc55f - Joe McGill - 2017-09-12 - derate NVLINK frequency for Nimbus DD1
4342ff5 - Luke Murray - 2017-09-12 - Performance updates for HW409069
c5cc11b - Jacob Harvey - 2017-09-12 - Change RD_CTR workaround val and update attr name
16c9664 - Alex Taft - 2017-09-12 - L3 initfile updates
2930128 - Jenny Huynh - 2017-09-12 - Adding HW401552 to cxa initfile to workaround clockgating bug
470c09c - Luke Murray - 2017-09-12 - Updating HW363605 workaround to be applied to all chips
1264c63 - Luke Murray - 2017-09-12 - Disable cp_me from the L3 for Nimbus DD1 and DD2.0.
9fe2db1 - Jenny Huynh - 2017-09-12 - INT scan initfile change to add workaround for HW408972
0b0b9a6 - CHRISTINA L. GRAVES - 2017-09-12 - p9_setup_bars -- support DD2 NPU SCOM address changes
612e61c - Luke Murray - 2017-09-12 - Updating optimal larx/stcx dials for performance
2028349 - Stephen Glancy - 2017-09-12 - Added read ctr bad delay workaround
328a82a - Jenny Huynh - 2017-09-12 - HW407123: Slow down xlink command rate for Nimbus DD1/2
659025b - Ben Gass - 2017-09-12 - Update filter pll settings as per HW407180
de5ca5f - CHRISTINA L. GRAVES - 2017-09-12 - Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabled
55fb179 - Luke Murray - 2017-09-12 - Updating L3 LCO watermarks for HW406803
d7c4d9c - Luke Murray - 2017-09-12 - Adding good LCO settings to initfile
ea615d5 - Joe McGill - 2017-09-12 - update DPLL and IVRM inits
6ccd736 - Anusha Reddy Rangareddygari - 2017-09-12 - p9_sbe_chiplet_reset,p9_sbe_arrayinit
11bd8e2 - Shelton Leung - 2017-09-12 - disable noise window for DD1 HW406577
f16bbce - Thi Tran - 2017-09-12 - Attribute support of customization of Nimbus DD1 PCI reference clock speed.
09a3953 - Jenny Huynh - 2017-09-12 - HW406130: Reduce dma read requests from 16->8 in NX inits
d1f5b4d - Nick Klazynski - 2017-09-12 - Add risklevel for HW399624 due to perf penalty; Add HW405851
c10a0cf - Markus Dobler - 2017-09-12 - p9_abist: Support for p9ndd2
71f9f4c - Thi Tran - 2017-09-12 - Add ec_abst ring to p9n.hw_image
c298ad3 - Alex Taft - 2017-09-12 - HW405413 : NCU sends data out of order
8f90f7c - Juan Medina - 2017-09-12 - Scrubbing needs to stay off for DD2, bug HW405443
075cf1d - Greg Still - 2017-09-12 - PM: GPE timer fix (HW389045 - Update Shadow copy of TSEL)
312eee1 - Ben Gass - 2017-09-12 - Set NDL IOValids based on configured NV links.
82b4ded - Anusha Reddy Rangareddygari - 2017-09-12 - p9_start_cbs updates
96cda2e - Shelton Leung - 2017-09-12 - enable prefetch drop for better MC fairness
4cb5454 - Jenny Huynh - 2017-09-12 - Reducing rng pace rate from 2000 -> 300 for HW403701
0548e2a - Stephen Glancy - 2017-09-12 - Updates to run HW VREF cal by default
bce2afe - Joe McGill - 2017-09-12 - adjust SRAM timings
af9e54a - Alex Taft - 2017-09-12 - New dummy pulse pok bits (for L2/L3)
bc03d94 - Ryan Black - 2017-09-12 - NPU scan/scom init updates
f7c0ca3 - Nick Klazynski - 2017-09-12 - Add three WATs, remove IMC2, replace stop2 workaround
0bc21a1 - Louis Stermole - 2017-09-12 - Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)
f9f8eca - Raja Das - 2017-09-12 - Workaround to fix issue where Powerbus loses track of EQs in DD1
49acd4a - Juan Medina - 2017-09-12 - reverting FIRs to master values, setting only bit 8
9f76433 - Joshua Hannan - 2017-09-12 - adding insert for soft fail threshold for dd1 and dd2
93e1c32 - Nick Klazynski - 2017-09-12 - WAs for HW401811 HW402145 HW403465; DIS_MULTIPLE_TBLW on all modes
be747be - Shelton Leung - 2017-09-12 - amo cache disabled for dd1 for HW401780
7e1aaea - Jenny Huynh - 2017-09-12 - Adding HW363780 to NPU scom initfiles
5d5304e - Nick Klazynski - 2017-09-12 - workarounds for HW399919 HW400898 HW398269 HW398269 HW399765
cafbc55 - Stephen Glancy - 2017-09-12 - Added periodic cal fix - fixes bad delays
36aba35 - Shelton Leung - 2017-09-12 - workaround for hw400932 atag corruptin in presp
6db38c3 - Shelton Leung - 2017-09-12 - dd1 workaround for hw400075 coherency error
ad68c9c - Anusha Reddy Rangareddygari - 2017-09-12 - VITAL cleaning for DD2
c654301 - Joe McGill - 2017-09-12 - p9.core.scan.initfile -- mask local error from CC in EC perv LFIR
9dc8b5a - Joe McGill - 2017-09-12 - p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulse
32f92e4 - Luke Murray - 2017-09-12 - Updating P9 L2 scan initfile to use attributes
86c1dbb - Joe McGill - 2017-09-12 - FBC updates for HW383616, HW384245
8ca4b4d - Luke Murray - 2017-09-12 - Adding skip group dials for cache when chip=group
31004f4 - Ben Gass - 2017-09-12 - Adding chip_ec_feature attributes for dd2 build
91640c5 - Joe McGill - 2017-09-12 - add SS PLL settings to support 94 MHz PCI operation
d6156c1 - Joe McGill - 2017-09-12 - p9_getecid -- set PCIE DD1.0x workaround attributes
816a0de - Joe McGill - 2017-09-12 - Add MSS customization support from CRP0 Lx MVPD
4eaba78 - Soma BhanuTej - 2017-09-12 - Security control override disable support - p9_setup_sbe_config
ec6c2ec - Joe McGill - 2017-09-12 - p9.fbc.scan.initfile -- clock off MCSYNC staging latches
70391c1 - Yue Du - 2017-09-12 - HW396520: DD1 workaround skip flushmode inhibit drop in cache hwp
a19a587 - Brian Silver - 2017-09-12 - Add Memory Subsystem FIR support
7582fd4 - Jenny Huynh - 2017-09-12 - Adding in defect HW395947,HW930007 to INT initfiles
1835b8d - Brian Silver - 2017-09-12 - Add EC workaround for PHY training bad bit processing
6f0f203 - Shelton Leung - 2017-09-12 - scan inits for lab workaround for DI bug HW392781
7372030 - CHRISTINA L. GRAVES - 2017-09-12 - p9_sbe_lpc_init fix with GPIO reset
c15e056 - Jenny Huynh - 2017-09-12 - Adding workaround for HW930007 and HW386013
13d024a - Yue Du - 2017-09-12 - Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setup
f675600 - Brian Silver - 2017-09-12 - Add EC feature levels to MSS workarounds
894b68c - Joe McGill - 2017-09-12 - p9_psi_init -- parametrize link speed (half/full)
920c88b - Christopher Riedl - 2017-09-12 - PPM reg collision (HW389511) work-around: Special Wake-up
728cddd - Joe McGill - 2017-09-12 - p9.fbc.scan.initfile -- create initfile, add workaround for HW376651
e52933e - Joe McGill - 2017-09-12 - HW388878 VCS workaround
844735a - Yue Du - 2017-09-12 - Cache HWP: DD1 VCS Workaround
d5844a7 - Soma BhanuTej - 2017-09-12 - Change chip to unsecure always for DD1 chips
6d38db7 - Anusha Reddy Rangareddygari - 2017-09-12 - DD2 updates:p9_sbe_arrayinit,p9_sbe_tp_arrayinit
79a54b7 - Sunil.Kumar - 2017-09-12 - Procedures modified for DD1 changes
44e74b8 - Anusha Reddy Rangareddygari - 2017-09-12 - Ec_level attribute support for DD1 attributes
9934c7d - Joachim Fenkes - 2017-09-12 - Add p9_proc_gettracearray procedure
200b0ea - Richard J. Knight - 2017-09-12 - Procedure crashes when trying to query an EC feature
076e8c7 - spashabk-in - 2017-09-12 - Deleting chip_ec_attributes.xml to fix mirroring
4a86fb4 - spashabk-in - 2017-09-11 - [Whitelist/Blacklist] - table generation