diff --git a/openpower/configs/barreleye_defconfig b/openpower/configs/barreleye_defconfig
index c39b30b..917b4f7 100644
--- a/openpower/configs/barreleye_defconfig
+++ b/openpower/configs/barreleye_defconfig
@@ -17,7 +17,7 @@
 BR2_ROOTFS_POST_BUILD_SCRIPT="../openpower/scripts/fixup-target-var ../openpower/scripts/firmware-whitelist"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.13"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.10.1"
 BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_OP_BUILD_PATH)/linux"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/linux/skiroot_defconfig"
diff --git a/openpower/configs/firenze_defconfig b/openpower/configs/firenze_defconfig
index 32d731b..7336a40 100644
--- a/openpower/configs/firenze_defconfig
+++ b/openpower/configs/firenze_defconfig
@@ -16,7 +16,7 @@
 BR2_ROOTFS_POST_BUILD_SCRIPT="../openpower/scripts/fixup-target-var ../openpower/scripts/firmware-whitelist"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.13"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.10.1"
 BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_OP_BUILD_PATH)/linux"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/linux/skiroot_defconfig"
diff --git a/openpower/configs/firestone_defconfig b/openpower/configs/firestone_defconfig
index 2af53b8..ec329b5 100644
--- a/openpower/configs/firestone_defconfig
+++ b/openpower/configs/firestone_defconfig
@@ -17,7 +17,7 @@
 BR2_ROOTFS_POST_BUILD_SCRIPT="../openpower/scripts/fixup-target-var ../openpower/scripts/firmware-whitelist"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.13"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.10.1"
 BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_OP_BUILD_PATH)/linux"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/linux/skiroot_defconfig"
diff --git a/openpower/configs/garrison_defconfig b/openpower/configs/garrison_defconfig
index 054937a..ba67719 100644
--- a/openpower/configs/garrison_defconfig
+++ b/openpower/configs/garrison_defconfig
@@ -17,7 +17,7 @@
 BR2_ROOTFS_POST_BUILD_SCRIPT="../openpower/scripts/fixup-target-var ../openpower/scripts/firmware-whitelist"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.13"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.10.1"
 BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_OP_BUILD_PATH)/linux"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/linux/skiroot_defconfig"
diff --git a/openpower/configs/habanero_defconfig b/openpower/configs/habanero_defconfig
index 9697567..8209421 100644
--- a/openpower/configs/habanero_defconfig
+++ b/openpower/configs/habanero_defconfig
@@ -17,7 +17,7 @@
 BR2_ROOTFS_POST_BUILD_SCRIPT="../openpower/scripts/fixup-target-var ../openpower/scripts/firmware-whitelist"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.13"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.10.1"
 BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_OP_BUILD_PATH)/linux"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/linux/skiroot_defconfig"
diff --git a/openpower/configs/openpower_mambo_defconfig b/openpower/configs/openpower_mambo_defconfig
index 95b8431..09d2ebc 100644
--- a/openpower/configs/openpower_mambo_defconfig
+++ b/openpower/configs/openpower_mambo_defconfig
@@ -15,7 +15,7 @@
 BR2_ROOTFS_POST_BUILD_SCRIPT="../openpower/scripts/fixup-target-var ../openpower/scripts/firmware-whitelist"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.13"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.10.1"
 BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_OP_BUILD_PATH)/linux"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/linux/skiroot_defconfig"
diff --git a/openpower/configs/palmetto_defconfig b/openpower/configs/palmetto_defconfig
index 147b227..0fa0ccf 100644
--- a/openpower/configs/palmetto_defconfig
+++ b/openpower/configs/palmetto_defconfig
@@ -16,7 +16,7 @@
 BR2_ROOTFS_POST_BUILD_SCRIPT="../openpower/scripts/fixup-target-var ../openpower/scripts/firmware-whitelist"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.13"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.10.1"
 BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_OP_BUILD_PATH)/linux"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/linux/skiroot_defconfig"
diff --git a/openpower/linux/0001-xhci-Use-xhci_pci_remove-for-xhci-device-shutdown.patch b/openpower/linux/0001-xhci-Use-xhci_pci_remove-for-xhci-device-shutdown.patch
index bf42988..97fe3f6 100644
--- a/openpower/linux/0001-xhci-Use-xhci_pci_remove-for-xhci-device-shutdown.patch
+++ b/openpower/linux/0001-xhci-Use-xhci_pci_remove-for-xhci-device-shutdown.patch
@@ -1,7 +1,7 @@
 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
 From: Thadeu Lima De Souza Cascardo <thadeul@br.ibm.com>
 Date: Tue, 25 Mar 2014 10:45:16 -0400
-Subject: [PATCH 1/4] xhci: Use xhci_pci_remove for xhci device shutdown
+Subject: [PATCH 01/15] xhci: Use xhci_pci_remove for xhci device shutdown
 
 Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
 Signed-off-by: Joel Stanley <joel@jms.id.au>
diff --git a/openpower/linux/0002-drivers-drm-ast-Switch-SCU-to-VGA-output-on-POST.patch b/openpower/linux/0002-drivers-drm-ast-Switch-SCU-to-VGA-output-on-POST.patch
deleted file mode 100644
index c1a82ba..0000000
--- a/openpower/linux/0002-drivers-drm-ast-Switch-SCU-to-VGA-output-on-POST.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jeremy Kerr <jk@ozlabs.org>
-Date: Wed, 2 Mar 2016 11:25:47 +0800
-Subject: [PATCH 2/4] drivers/drm/ast: Switch SCU to VGA output on POST
-
-On AST BMC platforms, the BMC may be using the VGA device for UART
-mirroring. In this case, we need to switch the DAC output to
-VGA mode.
-
-Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
-Signed-off-by: Joel Stanley <joel@jms.id.au>
----
- drivers/gpu/drm/ast/ast_post.c | 32 ++++++++++++++++++++++++++++++++
- 1 file changed, 32 insertions(+)
-
-diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
-index 810c51d92b99..703dba2ba84b 100644
---- a/drivers/gpu/drm/ast/ast_post.c
-+++ b/drivers/gpu/drm/ast/ast_post.c
-@@ -32,6 +32,7 @@
- #include "ast_dram_tables.h"
- 
- static void ast_init_dram_2300(struct drm_device *dev);
-+static void ast_init_output_control(struct drm_device *dev);
- 
- void ast_enable_vga(struct drm_device *dev)
- {
-@@ -384,6 +385,9 @@ void ast_post_gpu(struct drm_device *dev)
- 	else
- 		ast_init_dram_reg(dev);
- 
-+	if (ast->chip == AST2400)
-+		ast_init_output_control(dev);
-+
- 	ast_init_3rdtx(dev);
- }
- 
-@@ -1655,3 +1659,31 @@ static void ast_init_dram_2300(struct drm_device *dev)
- 	} while ((reg & 0x40) == 0);
- }
- 
-+static void ast_init_output_control(struct drm_device *dev)
-+{
-+	struct ast_private *ast = dev->dev_private;
-+	const uint32_t scu_addr = 0x1e6e2000;
-+	const uint32_t scu_key = 0x1688a8a8;
-+	uint32_t val;
-+
-+	/* unlock write access to SCUs */
-+	val = ast_mindwm(ast, scu_addr);
-+	ast_moutdwm(ast, scu_addr, scu_key);
-+
-+	/* configure SCU2C with the appropriate video output mode */
-+	val = ast_mindwm(ast, scu_addr | 0x2c);
-+
-+	switch (ast->tx_chip_type) {
-+	case AST_TX_SIL164:
-+	case AST_TX_DP501:
-+		/* Enable DVO output */
-+		val &= ~0x40000;
-+		break;
-+	default:
-+		/* VGA only: enable DAC output */
-+		val &= ~0x30000;
-+		break;
-+	}
-+
-+	ast_moutdwm(ast, scu_addr | 0x2c, val);
-+}
--- 
-2.11.0
-
diff --git a/openpower/linux/0003-xhci-do-not-halt-the-secondary-HCD.patch b/openpower/linux/0002-xhci-do-not-halt-the-secondary-HCD.patch
similarity index 84%
rename from openpower/linux/0003-xhci-do-not-halt-the-secondary-HCD.patch
rename to openpower/linux/0002-xhci-do-not-halt-the-secondary-HCD.patch
index 1ed8cbe4..44cb3f0 100644
--- a/openpower/linux/0003-xhci-do-not-halt-the-secondary-HCD.patch
+++ b/openpower/linux/0002-xhci-do-not-halt-the-secondary-HCD.patch
@@ -1,23 +1,22 @@
 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
 From: Joel Stanley <joel@jms.id.au>
 Date: Tue, 19 Jul 2016 22:43:26 +0930
-Subject: [PATCH 3/4] xhci: do not halt the secondary HCD
+Subject: [PATCH 02/15] xhci: do not halt the secondary HCD
 
 We can't halt the secondary HCD, because it's also the primary HCD,
 which will cause problems if we have devices attached to the primary
 HCD, like a keyboard.
 
-Sined-off-by: Joel Stanley <joel@jms.id.au>
 Signed-off-by: Joel Stanley <joel@jms.id.au>
 ---
  drivers/usb/host/xhci.c | 20 +++++++++++++++-----
  1 file changed, 15 insertions(+), 5 deletions(-)
 
 diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
-index 34e23c7d7797..4c6d135319c3 100644
+index 9a0ec116654a..315020dac049 100644
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
-@@ -683,6 +683,21 @@ void xhci_stop(struct usb_hcd *hcd)
+@@ -689,6 +689,21 @@ void xhci_stop(struct usb_hcd *hcd)
  
  	mutex_lock(&xhci->mutex);
  
@@ -39,7 +38,7 @@
  	if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
  		spin_lock_irq(&xhci->lock);
  
-@@ -694,11 +709,6 @@ void xhci_stop(struct usb_hcd *hcd)
+@@ -699,11 +714,6 @@ void xhci_stop(struct usb_hcd *hcd)
  		spin_unlock_irq(&xhci->lock);
  	}
  
diff --git a/openpower/linux/0003-drm-ast-Fix-AST2400-POST-failure-without-BMC-FW-or-V.patch b/openpower/linux/0003-drm-ast-Fix-AST2400-POST-failure-without-BMC-FW-or-V.patch
new file mode 100644
index 0000000..f988f8a
--- /dev/null
+++ b/openpower/linux/0003-drm-ast-Fix-AST2400-POST-failure-without-BMC-FW-or-V.patch
@@ -0,0 +1,72 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: "Y.C. Chen" <yc_chen@aspeedtech.com>
+Date: Thu, 23 Feb 2017 15:52:33 +0800
+Subject: [PATCH 03/15] drm/ast: Fix AST2400 POST failure without BMC FW or
+ VBIOS
+
+The current POST code for the AST2300/2400 family doesn't work properly
+if the chip hasn't been initialized previously by either the BMC own FW
+or the VBIOS. This fixes it.
+
+Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_post.c | 38 +++++++++++++++++++++++++++++++++++---
+ 1 file changed, 35 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
+index 5331ee1df086..6c5391cb90eb 100644
+--- a/drivers/gpu/drm/ast/ast_post.c
++++ b/drivers/gpu/drm/ast/ast_post.c
+@@ -1638,12 +1638,44 @@ static void ast_init_dram_2300(struct drm_device *dev)
+ 		temp |= 0x73;
+ 		ast_write32(ast, 0x12008, temp);
+ 
++		param.dram_freq = 396;
+ 		param.dram_type = AST_DDR3;
++		temp = ast_mindwm(ast, 0x1e6e2070);
+ 		if (temp & 0x01000000)
+ 			param.dram_type = AST_DDR2;
+-		param.dram_chipid = ast->dram_type;
+-		param.dram_freq = ast->mclk;
+-		param.vram_size = ast->vram_size;
++                switch (temp & 0x18000000) {
++		case 0:
++			param.dram_chipid = AST_DRAM_512Mx16;
++			break;
++		default:
++		case 0x08000000:
++			param.dram_chipid = AST_DRAM_1Gx16;
++			break;
++		case 0x10000000:
++			param.dram_chipid = AST_DRAM_2Gx16;
++			break;
++		case 0x18000000:
++			param.dram_chipid = AST_DRAM_4Gx16;
++			break;
++		}
++                switch (temp & 0x0c) {
++                default:
++		case 0x00:
++			param.vram_size = AST_VIDMEM_SIZE_8M;
++			break;
++
++		case 0x04:
++			param.vram_size = AST_VIDMEM_SIZE_16M;
++			break;
++
++		case 0x08:
++			param.vram_size = AST_VIDMEM_SIZE_32M;
++			break;
++
++		case 0x0c:
++			param.vram_size = AST_VIDMEM_SIZE_64M;
++			break;
++		}
+ 
+ 		if (param.dram_type == AST_DDR3) {
+ 			get_ddr3_info(ast, &param);
+-- 
+2.11.0
+
diff --git a/openpower/linux/0004-drm-ast-Handle-configuration-without-P2A-bridge.patch b/openpower/linux/0004-drm-ast-Handle-configuration-without-P2A-bridge.patch
new file mode 100644
index 0000000..acc3fbd
--- /dev/null
+++ b/openpower/linux/0004-drm-ast-Handle-configuration-without-P2A-bridge.patch
@@ -0,0 +1,434 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Russell Currey <ruscur@russell.cc>
+Date: Fri, 17 Feb 2017 14:33:01 +1100
+Subject: [PATCH 04/15] drm/ast: Handle configuration without P2A bridge
+
+The ast driver configures a window to enable access into BMC
+memory space in order to read some configuration registers.
+
+If this window is disabled, which it can be from the BMC side,
+the ast driver can't function.
+
+Closing this window is a necessity for security if a machine's
+host side and BMC side are controlled by different parties;
+i.e. a cloud provider offering machines "bare metal".
+
+A recent patch went in to try to check if that window is open
+but it does so by trying to access the registers in question
+and testing if the result is 0xffffffff.
+
+This method will trigger a PCIe error when the window is closed
+which on some systems will be fatal (it will trigger an EEH
+for example on POWER which will take out the device).
+
+This patch improves this in two ways:
+
+ - First, if the firmware has put properties in the device-tree
+containing the relevant configuration information, we use these.
+
+ - Otherwise, a bit in one of the SCU scratch registers (which
+are readable via the VGA register space and writeable by the BMC)
+will indicate if the BMC has closed the window. This bit has been
+defined by Y.C Chen from Aspeed.
+
+If the window is closed and the configuration isn't available from
+the device-tree, some sane defaults are used. Those defaults are
+hopefully sufficient for standard video modes used on a server.
+
+Signed-off-by: Russell Currey <ruscur@russell.cc>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+--
+
+v2. [BenH]
+    - Reworked on top of Aspeed P2A patch
+    - Cleanup overall detection via a "config_mode" and log the
+      selected mode for diagnostics purposes
+    - Add a property for the SCU straps
+
+v3. [BenH]
+    - Moved the config mode detection to a separate functionn
+    - Add reading of SCU 0x40 D[12] to detect the window is
+      closed as to not trigger a bus error by just "trying".
+      (change provided by Y.C. Chen)
+v4. [BenH]
+    - Only devices with the AST2000 PCI ID have a P2A bridge
+    - Update the P2A presence test to account for VGA only
+      mode as provided by Y.C. Chen.
+v5. [BenH]
+    - Fixup prefix of OF properties based on Joel Stanley
+      review comments.
+
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_drv.h  |   6 +-
+ drivers/gpu/drm/ast/ast_main.c | 264 +++++++++++++++++++++++++----------------
+ drivers/gpu/drm/ast/ast_post.c |   7 +-
+ 3 files changed, 168 insertions(+), 109 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
+index 7abda94fc2cf..3bedcf7ddd2a 100644
+--- a/drivers/gpu/drm/ast/ast_drv.h
++++ b/drivers/gpu/drm/ast/ast_drv.h
+@@ -113,7 +113,11 @@ struct ast_private {
+ 	struct ttm_bo_kmap_obj cache_kmap;
+ 	int next_cursor;
+ 	bool support_wide_screen;
+-	bool DisableP2A;
++	enum {
++		ast_use_p2a,
++		ast_use_dt,
++		ast_use_defaults
++	} config_mode;
+ 
+ 	enum ast_tx_chip tx_chip_type;
+ 	u8 dp501_maxclk;
+diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
+index 533e762d036d..fb9976254224 100644
+--- a/drivers/gpu/drm/ast/ast_main.c
++++ b/drivers/gpu/drm/ast/ast_main.c
+@@ -62,13 +62,84 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast,
+ 	return ret;
+ }
+ 
++static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
++{
++	struct device_node *np = dev->pdev->dev.of_node;
++	struct ast_private *ast = dev->dev_private;
++	uint32_t data, jregd0, jregd1;
++
++	/* Defaults */
++	ast->config_mode = ast_use_defaults;
++	*scu_rev = 0xffffffff;
++
++	/* Check if we have device-tree properties */
++	if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
++					scu_rev)) {
++		/* We do, disable P2A access */
++		ast->config_mode = ast_use_dt;
++		DRM_INFO("Using device-tree for configuration\n");
++		return;
++	}
++
++	/* Not all families have a P2A bridge */
++	if (dev->pdev->device != PCI_CHIP_AST2000)
++		return;
++
++	/*
++	 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
++	 * is disabled. We force using P2A if VGA only mode bit
++	 * is set D[7]
++	 */
++	jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
++	jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
++	if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
++		/* Double check it's actually working */
++		data = ast_read32(ast, 0xf004);
++		if (data != 0xFFFFFFFF) {
++			/* P2A works, grab silicon revision */
++			ast->config_mode = ast_use_p2a;
++
++			DRM_INFO("Using P2A bridge for configuration\n");
++
++			/* Read SCU7c (silicon revision register) */
++			ast_write32(ast, 0xf004, 0x1e6e0000);
++			ast_write32(ast, 0xf000, 0x1);
++			*scu_rev = ast_read32(ast, 0x1207c);
++			return;
++		}
++	}
++
++	/* We have a P2A bridge but it's disabled */
++	DRM_INFO("P2A bridge disabled, using default configuration\n");
++}
+ 
+ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
+ {
+ 	struct ast_private *ast = dev->dev_private;
+-	uint32_t data, jreg;
++	uint32_t jreg, scu_rev;
++
++	/*
++	 * If VGA isn't enabled, we need to enable now or subsequent
++	 * access to the scratch registers will fail. We also inform
++	 * our caller that it needs to POST the chip
++	 * (Assumption: VGA not enabled -> need to POST)
++	 */
++	if (!ast_is_vga_enabled(dev)) {
++		ast_enable_vga(dev);
++		DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
++		*need_post = true;
++	} else
++		*need_post = false;
++
++
++	/* Enable extended register access */
++	ast_enable_mmio(dev);
+ 	ast_open_key(ast);
+ 
++	/* Find out whether P2A works or whether to use device-tree */
++	ast_detect_config_mode(dev, &scu_rev);
++
++	/* Identify chipset */
+ 	if (dev->pdev->device == PCI_CHIP_AST1180) {
+ 		ast->chip = AST1100;
+ 		DRM_INFO("AST 1180 detected\n");
+@@ -80,12 +151,7 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
+ 			ast->chip = AST2300;
+ 			DRM_INFO("AST 2300 detected\n");
+ 		} else if (dev->pdev->revision >= 0x10) {
+-			uint32_t data;
+-			ast_write32(ast, 0xf004, 0x1e6e0000);
+-			ast_write32(ast, 0xf000, 0x1);
+-
+-			data = ast_read32(ast, 0x1207c);
+-			switch (data & 0x0300) {
++			switch (scu_rev & 0x0300) {
+ 			case 0x0200:
+ 				ast->chip = AST1100;
+ 				DRM_INFO("AST 1100 detected\n");
+@@ -110,26 +176,6 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
+ 		}
+ 	}
+ 
+-	/*
+-	 * If VGA isn't enabled, we need to enable now or subsequent
+-	 * access to the scratch registers will fail. We also inform
+-	 * our caller that it needs to POST the chip
+-	 * (Assumption: VGA not enabled -> need to POST)
+-	 */
+-	if (!ast_is_vga_enabled(dev)) {
+-		ast_enable_vga(dev);
+-		ast_enable_mmio(dev);
+-		DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
+-		*need_post = true;
+-	} else
+-		*need_post = false;
+-
+-	/* Check P2A Access */
+-	ast->DisableP2A = true;
+-	data = ast_read32(ast, 0xf004);
+-	if (data != 0xFFFFFFFF)
+-		ast->DisableP2A = false;
+-
+ 	/* Check if we support wide screen */
+ 	switch (ast->chip) {
+ 	case AST1180:
+@@ -146,17 +192,12 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
+ 			ast->support_wide_screen = true;
+ 		else {
+ 			ast->support_wide_screen = false;
+-			if (ast->DisableP2A == false) {
+-				/* Read SCU7c (silicon revision register) */
+-				ast_write32(ast, 0xf004, 0x1e6e0000);
+-				ast_write32(ast, 0xf000, 0x1);
+-				data = ast_read32(ast, 0x1207c);
+-				data &= 0x300;
+-				if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
+-					ast->support_wide_screen = true;
+-				if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
+-					ast->support_wide_screen = true;
+-			}
++			if (ast->chip == AST2300 &&
++			    (scu_rev & 0x300) == 0x0) /* ast1300 */
++				ast->support_wide_screen = true;
++			if (ast->chip == AST2400 &&
++			    (scu_rev & 0x300) == 0x100) /* ast1400 */
++				ast->support_wide_screen = true;
+ 		}
+ 		break;
+ 	}
+@@ -220,85 +261,102 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
+ 
+ static int ast_get_dram_info(struct drm_device *dev)
+ {
++	struct device_node *np = dev->pdev->dev.of_node;
+ 	struct ast_private *ast = dev->dev_private;
+-	uint32_t data, data2;
+-	uint32_t denum, num, div, ref_pll;
++	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
++	uint32_t denum, num, div, ref_pll, dsel;
+ 
+-	if (ast->DisableP2A)
+-	{
++	switch (ast->config_mode) {
++	case ast_use_dt:
++		/*
++		 * If some properties are missing, use reasonable
++		 * defaults for AST2400
++		 */
++		if (of_property_read_u32(np, "aspeed,mcr-configuration",
++					 &mcr_cfg))
++			mcr_cfg = 0x00000577;
++		if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
++					 &mcr_scu_mpll))
++			mcr_scu_mpll = 0x000050C0;
++		if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
++					 &mcr_scu_strap))
++			mcr_scu_strap = 0;
++		break;
++	case ast_use_p2a:
++		ast_write32(ast, 0xf004, 0x1e6e0000);
++		ast_write32(ast, 0xf000, 0x1);
++		mcr_cfg = ast_read32(ast, 0x10004);
++		mcr_scu_mpll = ast_read32(ast, 0x10120);
++		mcr_scu_strap = ast_read32(ast, 0x10170);
++		break;
++	case ast_use_defaults:
++	default:
+ 		ast->dram_bus_width = 16;
+ 		ast->dram_type = AST_DRAM_1Gx16;
+ 		ast->mclk = 396;
++		return 0;
+ 	}
+-	else
+-	{
+-		ast_write32(ast, 0xf004, 0x1e6e0000);
+-		ast_write32(ast, 0xf000, 0x1);
+-		data = ast_read32(ast, 0x10004);
+-
+-		if (data & 0x40)
+-			ast->dram_bus_width = 16;
+-		else
+-			ast->dram_bus_width = 32;
+ 
+-		if (ast->chip == AST2300 || ast->chip == AST2400) {
+-			switch (data & 0x03) {
+-			case 0:
+-				ast->dram_type = AST_DRAM_512Mx16;
+-				break;
+-			default:
+-			case 1:
+-				ast->dram_type = AST_DRAM_1Gx16;
+-				break;
+-			case 2:
+-				ast->dram_type = AST_DRAM_2Gx16;
+-				break;
+-			case 3:
+-				ast->dram_type = AST_DRAM_4Gx16;
+-				break;
+-			}
+-		} else {
+-			switch (data & 0x0c) {
+-			case 0:
+-			case 4:
+-				ast->dram_type = AST_DRAM_512Mx16;
+-				break;
+-			case 8:
+-				if (data & 0x40)
+-					ast->dram_type = AST_DRAM_1Gx16;
+-				else
+-					ast->dram_type = AST_DRAM_512Mx32;
+-				break;
+-			case 0xc:
+-				ast->dram_type = AST_DRAM_1Gx32;
+-				break;
+-			}
+-		}
++	if (mcr_cfg & 0x40)
++		ast->dram_bus_width = 16;
++	else
++		ast->dram_bus_width = 32;
+ 
+-		data = ast_read32(ast, 0x10120);
+-		data2 = ast_read32(ast, 0x10170);
+-		if (data2 & 0x2000)
+-			ref_pll = 14318;
+-		else
+-			ref_pll = 12000;
+-
+-		denum = data & 0x1f;
+-		num = (data & 0x3fe0) >> 5;
+-		data = (data & 0xc000) >> 14;
+-		switch (data) {
+-		case 3:
+-			div = 0x4;
++	if (ast->chip == AST2300 || ast->chip == AST2400) {
++		switch (mcr_cfg & 0x03) {
++		case 0:
++			ast->dram_type = AST_DRAM_512Mx16;
+ 			break;
+-		case 2:
++		default:
+ 		case 1:
+-			div = 0x2;
++			ast->dram_type = AST_DRAM_1Gx16;
+ 			break;
+-		default:
+-			div = 0x1;
++		case 2:
++			ast->dram_type = AST_DRAM_2Gx16;
++			break;
++		case 3:
++			ast->dram_type = AST_DRAM_4Gx16;
++			break;
++		}
++	} else {
++		switch (mcr_cfg & 0x0c) {
++		case 0:
++		case 4:
++			ast->dram_type = AST_DRAM_512Mx16;
++			break;
++		case 8:
++			if (mcr_cfg & 0x40)
++				ast->dram_type = AST_DRAM_1Gx16;
++			else
++				ast->dram_type = AST_DRAM_512Mx32;
++			break;
++		case 0xc:
++			ast->dram_type = AST_DRAM_1Gx32;
+ 			break;
+ 		}
+-		ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
+ 	}
++
++	if (mcr_scu_strap & 0x2000)
++		ref_pll = 14318;
++	else
++		ref_pll = 12000;
++
++	denum = mcr_scu_mpll & 0x1f;
++	num = (mcr_scu_mpll & 0x3fe0) >> 5;
++	dsel = (mcr_scu_mpll & 0xc000) >> 14;
++	switch (dsel) {
++	case 3:
++		div = 0x4;
++		break;
++	case 2:
++	case 1:
++		div = 0x2;
++		break;
++	default:
++		div = 0x1;
++		break;
++	}
++	ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
+index 6c5391cb90eb..64549cebcc5b 100644
+--- a/drivers/gpu/drm/ast/ast_post.c
++++ b/drivers/gpu/drm/ast/ast_post.c
+@@ -379,17 +379,14 @@ void ast_post_gpu(struct drm_device *dev)
+ 	ast_open_key(ast);
+ 	ast_set_def_ext_reg(dev);
+ 
+-	if (ast->DisableP2A == false)
+-	{
++	if (ast->config_mode == ast_use_p2a) {
+ 		if (ast->chip == AST2300 || ast->chip == AST2400)
+ 			ast_init_dram_2300(dev);
+ 		else
+ 			ast_init_dram_reg(dev);
+ 
+ 		ast_init_3rdtx(dev);
+-	}
+-	else
+-	{
++	} else {
+ 		if (ast->tx_chip_type != AST_TX_NONE)
+ 			ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);	/* Enable DVO */
+ 	}
+-- 
+2.11.0
+
diff --git a/openpower/linux/0005-drm-ast-const-ify-mode-setting-tables.patch b/openpower/linux/0005-drm-ast-const-ify-mode-setting-tables.patch
new file mode 100644
index 0000000..c14c5a3
--- /dev/null
+++ b/openpower/linux/0005-drm-ast-const-ify-mode-setting-tables.patch
@@ -0,0 +1,277 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Date: Fri, 17 Feb 2017 13:45:24 +1100
+Subject: [PATCH 05/15] drm/ast: const'ify mode setting tables
+
+And fix some comment alignment & space/tabs while at it
+
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_drv.h    |   4 +-
+ drivers/gpu/drm/ast/ast_mode.c   |   8 +--
+ drivers/gpu/drm/ast/ast_tables.h | 106 +++++++++++++++++++--------------------
+ 3 files changed, 59 insertions(+), 59 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
+index 3bedcf7ddd2a..3fd9d6e96bce 100644
+--- a/drivers/gpu/drm/ast/ast_drv.h
++++ b/drivers/gpu/drm/ast/ast_drv.h
+@@ -304,8 +304,8 @@ struct ast_vbios_dclk_info {
+ };
+ 
+ struct ast_vbios_mode_info {
+-	struct ast_vbios_stdtable *std_table;
+-	struct ast_vbios_enhtable *enh_table;
++	const struct ast_vbios_stdtable *std_table;
++	const struct ast_vbios_enhtable *enh_table;
+ };
+ 
+ extern int ast_mode_init(struct drm_device *dev);
+diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
+index e26c98f51eb4..1ff596e90225 100644
+--- a/drivers/gpu/drm/ast/ast_mode.c
++++ b/drivers/gpu/drm/ast/ast_mode.c
+@@ -80,9 +80,9 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
+ {
+ 	struct ast_private *ast = crtc->dev->dev_private;
+ 	u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
++	const struct ast_vbios_enhtable *best = NULL;
+ 	u32 hborder, vborder;
+ 	bool check_sync;
+-	struct ast_vbios_enhtable *best = NULL;
+ 
+ 	switch (crtc->primary->fb->bits_per_pixel) {
+ 	case 8:
+@@ -146,7 +146,7 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
+ 	refresh_rate = drm_mode_vrefresh(mode);
+ 	check_sync = vbios_mode->enh_table->flags & WideScreenMode;
+ 	do {
+-		struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
++		const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
+ 
+ 		while (loop->refresh_rate != 0xff) {
+ 			if ((check_sync) &&
+@@ -225,7 +225,7 @@ static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
+ 			    struct ast_vbios_mode_info *vbios_mode)
+ {
+ 	struct ast_private *ast = crtc->dev->dev_private;
+-	struct ast_vbios_stdtable *stdtable;
++	const struct ast_vbios_stdtable *stdtable;
+ 	u32 i;
+ 	u8 jreg;
+ 
+@@ -381,7 +381,7 @@ static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mo
+ 			     struct ast_vbios_mode_info *vbios_mode)
+ {
+ 	struct ast_private *ast = dev->dev_private;
+-	struct ast_vbios_dclk_info *clk_info;
++	const struct ast_vbios_dclk_info *clk_info;
+ 
+ 	clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
+ 
+diff --git a/drivers/gpu/drm/ast/ast_tables.h b/drivers/gpu/drm/ast/ast_tables.h
+index 3608d5aa7451..a4ddf901a54f 100644
+--- a/drivers/gpu/drm/ast/ast_tables.h
++++ b/drivers/gpu/drm/ast/ast_tables.h
+@@ -78,37 +78,37 @@
+ #define VCLK97_75     		0x19
+ #define VCLK118_25			0x1A
+ 
+-static struct ast_vbios_dclk_info dclk_table[] = {
+-	{0x2C, 0xE7, 0x03},					/* 00: VCLK25_175	*/
+-	{0x95, 0x62, 0x03},				        /* 01: VCLK28_322	*/
+-	{0x67, 0x63, 0x01},				        /* 02: VCLK31_5         */
+-	{0x76, 0x63, 0x01},				        /* 03: VCLK36         	*/
+-	{0xEE, 0x67, 0x01},				        /* 04: VCLK40          	*/
+-	{0x82, 0x62, 0x01}, 			        /* 05: VCLK49_5        	*/
+-	{0xC6, 0x64, 0x01},                        	        /* 06: VCLK50          	*/
+-	{0x94, 0x62, 0x01},                        	        /* 07: VCLK56_25       	*/
+-	{0x80, 0x64, 0x00},                        	        /* 08: VCLK65		*/
+-	{0x7B, 0x63, 0x00},                        	        /* 09: VCLK75	        */
+-	{0x67, 0x62, 0x00},				        /* 0A: VCLK78_75       	*/
+-	{0x7C, 0x62, 0x00},                        	        /* 0B: VCLK94_5        	*/
+-	{0x8E, 0x62, 0x00},                        	        /* 0C: VCLK108         	*/
+-	{0x85, 0x24, 0x00},                        	        /* 0D: VCLK135         	*/
+-	{0x67, 0x22, 0x00},                        	        /* 0E: VCLK157_5       	*/
+-	{0x6A, 0x22, 0x00},				        /* 0F: VCLK162         	*/
+-	{0x4d, 0x4c, 0x80},				        /* 10: VCLK154      	*/
+-	{0xa7, 0x78, 0x80},					/* 11: VCLK83.5         */
+-	{0x28, 0x49, 0x80},					/* 12: VCLK106.5        */
+-	{0x37, 0x49, 0x80},					/* 13: VCLK146.25       */
+-	{0x1f, 0x45, 0x80},					/* 14: VCLK148.5        */
+-	{0x47, 0x6c, 0x80},					/* 15: VCLK71       */
+-	{0x25, 0x65, 0x80},					/* 16: VCLK88.75    */
+-	{0x77, 0x58, 0x80},					/* 17: VCLK119      */
+-	{0x32, 0x67, 0x80},				    /* 18: VCLK85_5     */
+-	{0x6a, 0x6d, 0x80},					/* 19: VCLK97_75	*/
+-	{0x3b, 0x2c, 0x81},					/* 1A: VCLK118_25	*/
++static const struct ast_vbios_dclk_info dclk_table[] = {
++	{0x2C, 0xE7, 0x03},			/* 00: VCLK25_175	*/
++	{0x95, 0x62, 0x03},			/* 01: VCLK28_322	*/
++	{0x67, 0x63, 0x01},			/* 02: VCLK31_5		*/
++	{0x76, 0x63, 0x01},			/* 03: VCLK36		*/
++	{0xEE, 0x67, 0x01},			/* 04: VCLK40		*/
++	{0x82, 0x62, 0x01},			/* 05: VCLK49_5		*/
++	{0xC6, 0x64, 0x01},			/* 06: VCLK50		*/
++	{0x94, 0x62, 0x01},			/* 07: VCLK56_25	*/
++	{0x80, 0x64, 0x00},			/* 08: VCLK65		*/
++	{0x7B, 0x63, 0x00},			/* 09: VCLK75		*/
++	{0x67, 0x62, 0x00},			/* 0A: VCLK78_75	*/
++	{0x7C, 0x62, 0x00},			/* 0B: VCLK94_5		*/
++	{0x8E, 0x62, 0x00},			/* 0C: VCLK108		*/
++	{0x85, 0x24, 0x00},			/* 0D: VCLK135		*/
++	{0x67, 0x22, 0x00},			/* 0E: VCLK157_5	*/
++	{0x6A, 0x22, 0x00},			/* 0F: VCLK162		*/
++	{0x4d, 0x4c, 0x80},			/* 10: VCLK154		*/
++	{0xa7, 0x78, 0x80},			/* 11: VCLK83.5		*/
++	{0x28, 0x49, 0x80},			/* 12: VCLK106.5	*/
++	{0x37, 0x49, 0x80},			/* 13: VCLK146.25	*/
++	{0x1f, 0x45, 0x80},			/* 14: VCLK148.5	*/
++	{0x47, 0x6c, 0x80},			/* 15: VCLK71		*/
++	{0x25, 0x65, 0x80},			/* 16: VCLK88.75	*/
++	{0x77, 0x58, 0x80},			/* 17: VCLK119		*/
++	{0x32, 0x67, 0x80},			/* 18: VCLK85_5		*/
++	{0x6a, 0x6d, 0x80},			/* 19: VCLK97_75	*/
++	{0x3b, 0x2c, 0x81},			/* 1A: VCLK118_25	*/
+ };
+ 
+-static struct ast_vbios_stdtable vbios_stdtable[] = {
++static const struct ast_vbios_stdtable vbios_stdtable[] = {
+ 	/* MD_2_3_400 */
+ 	{
+ 		0x67,
+@@ -181,21 +181,21 @@ static struct ast_vbios_stdtable vbios_stdtable[] = {
+ 	},
+ };
+ 
+-static struct ast_vbios_enhtable res_640x480[] = {
++static const struct ast_vbios_enhtable res_640x480[] = {
+ 	{ 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175,	/* 60Hz */
+ 	  (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E },
+ 	{ 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5,	/* 72Hz */
+ 	  (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E  },
+ 	{ 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5,	/* 75Hz */
+ 	  (SyncNN | Charx8Dot) , 75, 3, 0x2E },
+-	{ 832, 640, 56, 56, 509, 480, 1, 3, VCLK36,		/* 85Hz */
++	{ 832, 640, 56, 56, 509, 480, 1, 3, VCLK36,	/* 85Hz */
+ 	  (SyncNN | Charx8Dot) , 85, 4, 0x2E },
+-	{ 832, 640, 56, 56, 509, 480, 1, 3, VCLK36,		/* end */
++	{ 832, 640, 56, 56, 509, 480, 1, 3, VCLK36,	/* end */
+ 	  (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E },
+ };
+ 
+-static struct ast_vbios_enhtable res_800x600[] = {
+-	{1024, 800, 24, 72, 625, 600, 1, 2, VCLK36,		/* 56Hz */
++static const struct ast_vbios_enhtable res_800x600[] = {
++	{1024, 800, 24, 72, 625, 600, 1, 2, VCLK36,	/* 56Hz */
+ 	 (SyncPP | Charx8Dot), 56, 1, 0x30 },
+ 	{1056, 800, 40, 128, 628, 600, 1, 4, VCLK40,	/* 60Hz */
+ 	 (SyncPP | Charx8Dot), 60, 2, 0x30 },
+@@ -210,7 +210,7 @@ static struct ast_vbios_enhtable res_800x600[] = {
+ };
+ 
+ 
+-static struct ast_vbios_enhtable res_1024x768[] = {
++static const struct ast_vbios_enhtable res_1024x768[] = {
+ 	{1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65,	/* 60Hz */
+ 	 (SyncNN | Charx8Dot), 60, 1, 0x31 },
+ 	{1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75,	/* 70Hz */
+@@ -223,7 +223,7 @@ static struct ast_vbios_enhtable res_1024x768[] = {
+ 	 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 },
+ };
+ 
+-static struct ast_vbios_enhtable res_1280x1024[] = {
++static const struct ast_vbios_enhtable res_1280x1024[] = {
+ 	{1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108,	/* 60Hz */
+ 	 (SyncPP | Charx8Dot), 60, 1, 0x32 },
+ 	{1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135,	/* 75Hz */
+@@ -234,7 +234,7 @@ static struct ast_vbios_enhtable res_1280x1024[] = {
+ 	 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 },
+ };
+ 
+-static struct ast_vbios_enhtable res_1600x1200[] = {
++static const struct ast_vbios_enhtable res_1600x1200[] = {
+ 	{2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162,	/* 60Hz */
+ 	 (SyncPP | Charx8Dot), 60, 1, 0x33 },
+ 	{2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162,	/* end */
+@@ -242,23 +242,23 @@ static struct ast_vbios_enhtable res_1600x1200[] = {
+ };
+ 
+ /* 16:9 */
+-static struct ast_vbios_enhtable res_1360x768[] = {
+-	{1792, 1360, 64,112, 795,  768, 3, 6, VCLK85_5,	         /* 60Hz */
++static const struct ast_vbios_enhtable res_1360x768[] = {
++	{1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5,		/* 60Hz */
+ 	 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 },
+-	{1792, 1360, 64,112, 795,  768, 3, 6, VCLK85_5,	         /* end */
++	{1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5,	         /* end */
+ 	 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 },
+ };
+ 
+-static struct ast_vbios_enhtable res_1600x900[] = {
+-	{1760, 1600, 48, 32, 926,  900, 3, 5, VCLK97_75,	/* 60Hz CVT RB */
++static const struct ast_vbios_enhtable res_1600x900[] = {
++	{1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75,		/* 60Hz CVT RB */
+ 	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A },
+-	{2112, 1600, 88,168, 934,  900, 3, 5, VCLK118_25,	/* 60Hz CVT */
++	{2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25,	/* 60Hz CVT */
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A },
+-	{2112, 1600, 88,168, 934,  900, 3, 5, VCLK118_25,	/* 60Hz CVT */
++	{2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25,	/* 60Hz CVT */
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A },
+ };
+ 
+-static struct ast_vbios_enhtable res_1920x1080[] = {
++static const struct ast_vbios_enhtable res_1920x1080[] = {
+ 	{2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5,	/* 60Hz */
+ 	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 },
+ 	{2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5,	/* 60Hz */
+@@ -267,8 +267,8 @@ static struct ast_vbios_enhtable res_1920x1080[] = {
+ 
+ 
+ /* 16:10 */
+-static struct ast_vbios_enhtable res_1280x800[] = {
+-	{1440, 1280, 48, 32,  823,  800, 3, 6, VCLK71,	/* 60Hz RB */
++static const struct ast_vbios_enhtable res_1280x800[] = {
++	{1440, 1280, 48, 32,  823,  800, 3, 6, VCLK71,		/* 60Hz RB */
+ 	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 },
+ 	{1680, 1280, 72,128,  831,  800, 3, 6, VCLK83_5,	/* 60Hz */
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 },
+@@ -277,7 +277,7 @@ static struct ast_vbios_enhtable res_1280x800[] = {
+ 
+ };
+ 
+-static struct ast_vbios_enhtable res_1440x900[] = {
++static const struct ast_vbios_enhtable res_1440x900[] = {
+ 	{1600, 1440, 48, 32,  926,  900, 3, 6, VCLK88_75,	/* 60Hz RB */
+ 	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 },
+ 	{1904, 1440, 80,152,  934,  900, 3, 6, VCLK106_5,	/* 60Hz */
+@@ -286,8 +286,8 @@ static struct ast_vbios_enhtable res_1440x900[] = {
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 },
+ };
+ 
+-static struct ast_vbios_enhtable res_1680x1050[] = {
+-	{1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119,	/* 60Hz RB */
++static const struct ast_vbios_enhtable res_1680x1050[] = {
++	{1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119,		/* 60Hz RB */
+ 	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },
+ 	{2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25,	/* 60Hz */
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 },
+@@ -295,10 +295,10 @@ static struct ast_vbios_enhtable res_1680x1050[] = {
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 },
+ };
+ 
+-static struct ast_vbios_enhtable res_1920x1200[] = {
+-	{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,	/* 60Hz RB*/
++static const struct ast_vbios_enhtable res_1920x1200[] = {
++	{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,		/* 60Hz RB*/
+ 	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 },
+-	{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,	/* 60Hz RB */
++	{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,		/* 60Hz RB */
+ 	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 },
+ };
+ 
+-- 
+2.11.0
+
diff --git a/openpower/linux/0006-drm-ast-Remove-spurrious-include.patch b/openpower/linux/0006-drm-ast-Remove-spurrious-include.patch
new file mode 100644
index 0000000..9b6d7a1
--- /dev/null
+++ b/openpower/linux/0006-drm-ast-Remove-spurrious-include.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Date: Fri, 17 Feb 2017 13:55:58 +1100
+Subject: [PATCH 06/15] drm/ast: Remove spurrious include
+
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_main.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
+index fb9976254224..f01a937165b7 100644
+--- a/drivers/gpu/drm/ast/ast_main.c
++++ b/drivers/gpu/drm/ast/ast_main.c
+@@ -32,8 +32,6 @@
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ 
+-#include "ast_dram_tables.h"
+-
+ void ast_set_index_reg_mask(struct ast_private *ast,
+ 			    uint32_t base, uint8_t index,
+ 			    uint8_t mask, uint8_t val)
+-- 
+2.11.0
+
diff --git a/openpower/linux/0007-drm-ast-Fix-calculation-of-MCLK.patch b/openpower/linux/0007-drm-ast-Fix-calculation-of-MCLK.patch
new file mode 100644
index 0000000..5cc3e2c
--- /dev/null
+++ b/openpower/linux/0007-drm-ast-Fix-calculation-of-MCLK.patch
@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Date: Fri, 17 Feb 2017 13:57:30 +1100
+Subject: [PATCH 07/15] drm/ast: Fix calculation of MCLK
+
+Some braces were missing causing an incorrect calculation.
+
+Y.C. Chen from Aspeed provided me with the right formula
+which I tested on AST2400 and 2500.
+
+The MCLK isn't currently used by the driver (it will eventually
+to filter modes) so the issue isn't catastrophic.
+
+Also make the printed value a bit more meaningful
+
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_main.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
+index f01a937165b7..8d87d3ca439b 100644
+--- a/drivers/gpu/drm/ast/ast_main.c
++++ b/drivers/gpu/drm/ast/ast_main.c
+@@ -354,7 +354,7 @@ static int ast_get_dram_info(struct drm_device *dev)
+ 		div = 0x1;
+ 		break;
+ 	}
+-	ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
++	ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
+ 	return 0;
+ }
+ 
+@@ -498,7 +498,9 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
+ 		if (ret)
+ 			goto out_free;
+ 		ast->vram_size = ast_get_vram_info(dev);
+-		DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size);
++		DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
++			 ast->mclk, ast->dram_type,
++			 ast->dram_bus_width, ast->vram_size);
+ 	}
+ 
+ 	if (need_post)
+-- 
+2.11.0
+
diff --git a/openpower/linux/0008-drm-ast-Base-support-for-AST2500.patch b/openpower/linux/0008-drm-ast-Base-support-for-AST2500.patch
new file mode 100644
index 0000000..c081740
--- /dev/null
+++ b/openpower/linux/0008-drm-ast-Base-support-for-AST2500.patch
@@ -0,0 +1,325 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: "Y.C. Chen" <yc_chen@aspeedtech.com>
+Date: Fri, 17 Feb 2017 14:36:46 +1100
+Subject: [PATCH 08/15] drm/ast: Base support for AST2500
+
+Add detection and mode setting updates for AST2500 generation chip,
+code originally from Aspeed and slightly reworked for coding style
+mostly by Ben. This doesn't contain the BMC DRAM POST code which
+is in a separate patch.
+
+Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+---
+
+v2. Add 800Mhz default mclk for AST2500
+
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_drv.h    |  2 ++
+ drivers/gpu/drm/ast/ast_main.c   | 32 +++++++++++++++++++---
+ drivers/gpu/drm/ast/ast_mode.c   | 30 ++++++++++++++++-----
+ drivers/gpu/drm/ast/ast_tables.h | 58 +++++++++++++++++++++++++++++++++-------
+ 4 files changed, 103 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
+index 3fd9d6e96bce..d1c1d530abaa 100644
+--- a/drivers/gpu/drm/ast/ast_drv.h
++++ b/drivers/gpu/drm/ast/ast_drv.h
+@@ -64,6 +64,7 @@ enum ast_chip {
+ 	AST2150,
+ 	AST2300,
+ 	AST2400,
++	AST2500,
+ 	AST1180,
+ };
+ 
+@@ -80,6 +81,7 @@ enum ast_tx_chip {
+ #define AST_DRAM_1Gx32   3
+ #define AST_DRAM_2Gx16   6
+ #define AST_DRAM_4Gx16   7
++#define AST_DRAM_8Gx16   8
+ 
+ struct ast_fbdev;
+ 
+diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
+index 8d87d3ca439b..5a83d3793000 100644
+--- a/drivers/gpu/drm/ast/ast_main.c
++++ b/drivers/gpu/drm/ast/ast_main.c
+@@ -142,7 +142,10 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
+ 		ast->chip = AST1100;
+ 		DRM_INFO("AST 1180 detected\n");
+ 	} else {
+-		if (dev->pdev->revision >= 0x30) {
++		if (dev->pdev->revision >= 0x40) {
++			ast->chip = AST2500;
++			DRM_INFO("AST 2500 detected\n");
++		} else if (dev->pdev->revision >= 0x30) {
+ 			ast->chip = AST2400;
+ 			DRM_INFO("AST 2400 detected\n");
+ 		} else if (dev->pdev->revision >= 0x20) {
+@@ -196,6 +199,9 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
+ 			if (ast->chip == AST2400 &&
+ 			    (scu_rev & 0x300) == 0x100) /* ast1400 */
+ 				ast->support_wide_screen = true;
++			if (ast->chip == AST2500 &&
++			    scu_rev == 0x100)           /* ast2510 */
++				ast->support_wide_screen = true;
+ 		}
+ 		break;
+ 	}
+@@ -291,7 +297,10 @@ static int ast_get_dram_info(struct drm_device *dev)
+ 	default:
+ 		ast->dram_bus_width = 16;
+ 		ast->dram_type = AST_DRAM_1Gx16;
+-		ast->mclk = 396;
++		if (ast->chip == AST2500)
++			ast->mclk = 800;
++		else
++			ast->mclk = 396;
+ 		return 0;
+ 	}
+ 
+@@ -300,7 +309,23 @@ static int ast_get_dram_info(struct drm_device *dev)
+ 	else
+ 		ast->dram_bus_width = 32;
+ 
+-	if (ast->chip == AST2300 || ast->chip == AST2400) {
++	if (ast->chip == AST2500) {
++		switch (mcr_cfg & 0x03) {
++		case 0:
++			ast->dram_type = AST_DRAM_1Gx16;
++			break;
++		default:
++		case 1:
++			ast->dram_type = AST_DRAM_2Gx16;
++			break;
++		case 2:
++			ast->dram_type = AST_DRAM_4Gx16;
++			break;
++		case 3:
++			ast->dram_type = AST_DRAM_8Gx16;
++			break;
++		}
++	} else if (ast->chip == AST2300 || ast->chip == AST2400) {
+ 		switch (mcr_cfg & 0x03) {
+ 		case 0:
+ 			ast->dram_type = AST_DRAM_512Mx16;
+@@ -523,6 +548,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
+ 	    ast->chip == AST2200 ||
+ 	    ast->chip == AST2300 ||
+ 	    ast->chip == AST2400 ||
++	    ast->chip == AST2500 ||
+ 	    ast->chip == AST1180) {
+ 		dev->mode_config.max_width = 1920;
+ 		dev->mode_config.max_height = 2048;
+diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
+index 1ff596e90225..e4db1c72940c 100644
+--- a/drivers/gpu/drm/ast/ast_mode.c
++++ b/drivers/gpu/drm/ast/ast_mode.c
+@@ -271,7 +271,11 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
+ {
+ 	struct ast_private *ast = crtc->dev->dev_private;
+ 	u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
+-	u16 temp;
++	u16 temp, precache = 0;
++
++	if ((ast->chip == AST2500) &&
++	    (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
++		precache = 40;
+ 
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
+ 
+@@ -297,12 +301,12 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
+ 		jregAD |= 0x01;  /* HBE D[5] */
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
+ 
+-	temp = (mode->crtc_hsync_start >> 3) - 1;
++	temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
+ 	if (temp & 0x100)
+ 		jregAC |= 0x40; /* HRS D[5] */
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
+ 
+-	temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f;
++	temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
+ 	if (temp & 0x20)
+ 		jregAD |= 0x04; /* HRE D[5] */
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
+@@ -363,6 +367,11 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
+ 
++	if (precache)
++		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
++	else
++		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
++
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
+ }
+ 
+@@ -383,12 +392,16 @@ static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mo
+ 	struct ast_private *ast = dev->dev_private;
+ 	const struct ast_vbios_dclk_info *clk_info;
+ 
+-	clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
++	if (ast->chip == AST2500)
++		clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
++	else
++		clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
+ 
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
+-			       (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4));
++			       (clk_info->param3 & 0xc0) |
++			       ((clk_info->param3 & 0x3) << 4));
+ }
+ 
+ static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
+@@ -421,7 +434,8 @@ static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
+ 
+ 	/* Set Threshold */
+-	if (ast->chip == AST2300 || ast->chip == AST2400) {
++	if (ast->chip == AST2300 || ast->chip == AST2400 ||
++	    ast->chip == AST2500) {
+ 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
+ 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
+ 	} else if (ast->chip == AST2100 ||
+@@ -794,7 +808,9 @@ static int ast_mode_valid(struct drm_connector *connector,
+ 		if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
+ 			return MODE_OK;
+ 
+-		if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
++		if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
++		    (ast->chip == AST2300) || (ast->chip == AST2400) ||
++		    (ast->chip == AST2500) || (ast->chip == AST1180)) {
+ 			if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
+ 				return MODE_OK;
+ 
+diff --git a/drivers/gpu/drm/ast/ast_tables.h b/drivers/gpu/drm/ast/ast_tables.h
+index a4ddf901a54f..5f4c2e833a65 100644
+--- a/drivers/gpu/drm/ast/ast_tables.h
++++ b/drivers/gpu/drm/ast/ast_tables.h
+@@ -47,6 +47,7 @@
+ #define SyncPN			(PVSync | NHSync)
+ #define SyncNP			(NVSync | PHSync)
+ #define SyncNN			(NVSync | NHSync)
++#define AST2500PreCatchCRT		0x00004000
+ 
+ /* DCLK Index */
+ #define VCLK25_175     		0x00
+@@ -108,6 +109,36 @@ static const struct ast_vbios_dclk_info dclk_table[] = {
+ 	{0x3b, 0x2c, 0x81},			/* 1A: VCLK118_25	*/
+ };
+ 
++static const struct ast_vbios_dclk_info dclk_table_ast2500[] = {
++	{0x2C, 0xE7, 0x03},			/* 00: VCLK25_175	*/
++	{0x95, 0x62, 0x03},			/* 01: VCLK28_322	*/
++	{0x67, 0x63, 0x01},			/* 02: VCLK31_5		*/
++	{0x76, 0x63, 0x01},			/* 03: VCLK36		*/
++	{0xEE, 0x67, 0x01},			/* 04: VCLK40		*/
++	{0x82, 0x62, 0x01},			/* 05: VCLK49_5		*/
++	{0xC6, 0x64, 0x01},			/* 06: VCLK50		*/
++	{0x94, 0x62, 0x01},			/* 07: VCLK56_25	*/
++	{0x80, 0x64, 0x00},			/* 08: VCLK65		*/
++	{0x7B, 0x63, 0x00},			/* 09: VCLK75		*/
++	{0x67, 0x62, 0x00},			/* 0A: VCLK78_75	*/
++	{0x7C, 0x62, 0x00},			/* 0B: VCLK94_5		*/
++	{0x8E, 0x62, 0x00},			/* 0C: VCLK108		*/
++	{0x85, 0x24, 0x00},			/* 0D: VCLK135		*/
++	{0x67, 0x22, 0x00},			/* 0E: VCLK157_5	*/
++	{0x6A, 0x22, 0x00},			/* 0F: VCLK162		*/
++	{0x4d, 0x4c, 0x80},			/* 10: VCLK154		*/
++	{0xa7, 0x78, 0x80},			/* 11: VCLK83.5		*/
++	{0x28, 0x49, 0x80},			/* 12: VCLK106.5	*/
++	{0x37, 0x49, 0x80},			/* 13: VCLK146.25	*/
++	{0x1f, 0x45, 0x80},			/* 14: VCLK148.5	*/
++	{0x47, 0x6c, 0x80},			/* 15: VCLK71		*/
++	{0x25, 0x65, 0x80},			/* 16: VCLK88.75	*/
++	{0x58, 0x01, 0x42},			/* 17: VCLK119		*/
++	{0x32, 0x67, 0x80},			/* 18: VCLK85_5		*/
++	{0x6a, 0x6d, 0x80},			/* 19: VCLK97_75	*/
++	{0x44, 0x20, 0x43},			/* 1A: VCLK118_25	*/
++};
++
+ static const struct ast_vbios_stdtable vbios_stdtable[] = {
+ 	/* MD_2_3_400 */
+ 	{
+@@ -246,12 +277,14 @@ static const struct ast_vbios_enhtable res_1360x768[] = {
+ 	{1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5,		/* 60Hz */
+ 	 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 },
+ 	{1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5,	         /* end */
+-	 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 },
++	 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 0xFF, 1, 0x39 },
+ };
+ 
+ static const struct ast_vbios_enhtable res_1600x900[] = {
+ 	{1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75,		/* 60Hz CVT RB */
+-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A },
++	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 60, 1, 0x3A },
+ 	{2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25,	/* 60Hz CVT */
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A },
+ 	{2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25,	/* 60Hz CVT */
+@@ -260,16 +293,19 @@ static const struct ast_vbios_enhtable res_1600x900[] = {
+ 
+ static const struct ast_vbios_enhtable res_1920x1080[] = {
+ 	{2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5,	/* 60Hz */
+-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 },
++	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 60, 1, 0x38 },
+ 	{2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5,	/* 60Hz */
+-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 },
++	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 0xFF, 1, 0x38 },
+ };
+ 
+ 
+ /* 16:10 */
+ static const struct ast_vbios_enhtable res_1280x800[] = {
+ 	{1440, 1280, 48, 32,  823,  800, 3, 6, VCLK71,		/* 60Hz RB */
+-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 },
++	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 60, 1, 0x35 },
+ 	{1680, 1280, 72,128,  831,  800, 3, 6, VCLK83_5,	/* 60Hz */
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 },
+ 	{1680, 1280, 72,128,  831,  800, 3, 6, VCLK83_5,	/* 60Hz */
+@@ -279,7 +315,8 @@ static const struct ast_vbios_enhtable res_1280x800[] = {
+ 
+ static const struct ast_vbios_enhtable res_1440x900[] = {
+ 	{1600, 1440, 48, 32,  926,  900, 3, 6, VCLK88_75,	/* 60Hz RB */
+-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 },
++	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 60, 1, 0x36 },
+ 	{1904, 1440, 80,152,  934,  900, 3, 6, VCLK106_5,	/* 60Hz */
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 },
+ 	{1904, 1440, 80,152,  934,  900, 3, 6, VCLK106_5,	/* 60Hz */
+@@ -288,7 +325,8 @@ static const struct ast_vbios_enhtable res_1440x900[] = {
+ 
+ static const struct ast_vbios_enhtable res_1680x1050[] = {
+ 	{1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119,		/* 60Hz RB */
+-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },
++	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 60, 1, 0x37 },
+ 	{2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25,	/* 60Hz */
+ 	 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 },
+ 	{2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25,	/* 60Hz */
+@@ -297,9 +335,11 @@ static const struct ast_vbios_enhtable res_1680x1050[] = {
+ 
+ static const struct ast_vbios_enhtable res_1920x1200[] = {
+ 	{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,		/* 60Hz RB*/
+-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 },
++	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 60, 1, 0x34 },
+ 	{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,		/* 60Hz RB */
+-	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 },
++	 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
++	  AST2500PreCatchCRT), 0xFF, 1, 0x34 },
+ };
+ 
+ #endif
+-- 
+2.11.0
+
diff --git a/openpower/linux/0009-drm-ast-Fixed-vram-size-incorrect-issue-on-POWER.patch b/openpower/linux/0009-drm-ast-Fixed-vram-size-incorrect-issue-on-POWER.patch
new file mode 100644
index 0000000..0879919
--- /dev/null
+++ b/openpower/linux/0009-drm-ast-Fixed-vram-size-incorrect-issue-on-POWER.patch
@@ -0,0 +1,55 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: "Y.C. Chen" <yc_chen@aspeedtech.com>
+Date: Fri, 17 Feb 2017 10:56:47 +0800
+Subject: [PATCH 09/15] drm/ast: Fixed vram size incorrect issue on POWER
+
+The default value of VGA scratch may incorrect.
+Should initial h/w before get vram info.
+
+Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_main.c | 6 +++---
+ drivers/gpu/drm/ast/ast_post.c | 2 +-
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
+index 5a83d3793000..eefc5124eeb3 100644
+--- a/drivers/gpu/drm/ast/ast_main.c
++++ b/drivers/gpu/drm/ast/ast_main.c
+@@ -518,6 +518,9 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
+ 
+ 	ast_detect_chip(dev, &need_post);
+ 
++	if (need_post)
++		ast_post_gpu(dev);
++
+ 	if (ast->chip != AST1180) {
+ 		ret = ast_get_dram_info(dev);
+ 		if (ret)
+@@ -528,9 +531,6 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
+ 			 ast->dram_bus_width, ast->vram_size);
+ 	}
+ 
+-	if (need_post)
+-		ast_post_gpu(dev);
+-
+ 	ret = ast_mm_init(ast);
+ 	if (ret)
+ 		goto out_free;
+diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
+index 64549cebcc5b..e8024502e749 100644
+--- a/drivers/gpu/drm/ast/ast_post.c
++++ b/drivers/gpu/drm/ast/ast_post.c
+@@ -79,7 +79,7 @@ ast_set_def_ext_reg(struct drm_device *dev)
+ 	const u8 *ext_reg_info;
+ 
+ 	/* reset scratch */
+-	for (i = 0x81; i <= 0x8f; i++)
++	for (i = 0x81; i <= 0x9f; i++)
+ 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
+ 
+ 	if (ast->chip == AST2300 || ast->chip == AST2400) {
+-- 
+2.11.0
+
diff --git a/openpower/linux/0010-drm-ast-Factor-mmc_test-code-in-POST-code.patch b/openpower/linux/0010-drm-ast-Factor-mmc_test-code-in-POST-code.patch
new file mode 100644
index 0000000..855c7d8
--- /dev/null
+++ b/openpower/linux/0010-drm-ast-Factor-mmc_test-code-in-POST-code.patch
@@ -0,0 +1,174 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Date: Sat, 18 Feb 2017 14:19:10 +1100
+Subject: [PATCH 10/15] drm/ast: Factor mmc_test code in POST code
+
+There's a some duplication for what's essentially copies of
+two loops, so factor it. The upcoming AST2500 POST code adds
+more of them. Also cleanup return types for the test functions,
+most of them return a boolean, some return a u32.
+
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+--
+
+v2. - Keep the split between the "test" and "test2" functions
+      as they have a different exit condition in the loop and
+      a different return type.
+    - Fix the return types accross the call chain
+
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_post.c | 82 ++++++++++++++++--------------------------
+ 1 file changed, 31 insertions(+), 51 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
+index e8024502e749..c55067ccb0b1 100644
+--- a/drivers/gpu/drm/ast/ast_post.c
++++ b/drivers/gpu/drm/ast/ast_post.c
+@@ -445,85 +445,65 @@ static const u32 pattern[8] = {
+ 	0x7C61D253
+ };
+ 
+-static int mmc_test_burst(struct ast_private *ast, u32 datagen)
++static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
+ {
+ 	u32 data, timeout;
+ 
+ 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+-	ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
++	ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
+ 	timeout = 0;
+ 	do {
+ 		data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
+-		if (data & 0x2000) {
+-			return 0;
+-		}
++		if (data & 0x2000)
++			return false;
+ 		if (++timeout > TIMEOUT) {
+ 			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+-			return 0;
++			return false;
+ 		}
+ 	} while (!data);
+-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+-	return 1;
++	ast_moutdwm(ast, 0x1e6e0070, 0x0);
++	return true;
+ }
+ 
+-static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
++static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
+ {
+ 	u32 data, timeout;
+ 
+ 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+-	ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
++	ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
+ 	timeout = 0;
+ 	do {
+ 		data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
+ 		if (++timeout > TIMEOUT) {
+ 			ast_moutdwm(ast, 0x1e6e0070, 0x0);
+-			return -1;
++			return 0xffffffff;
+ 		}
+ 	} while (!data);
+ 	data = ast_mindwm(ast, 0x1e6e0078);
+ 	data = (data | (data >> 16)) & 0xffff;
+-	ast_moutdwm(ast, 0x1e6e0070, 0x0);
++	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+ 	return data;
+ }
+ 
+-static int mmc_test_single(struct ast_private *ast, u32 datagen)
++
++static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
+ {
+-	u32 data, timeout;
++	return mmc_test(ast, datagen, 0xc1);
++}
+ 
+-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+-	ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
+-	timeout = 0;
+-	do {
+-		data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
+-		if (data & 0x2000)
+-			return 0;
+-		if (++timeout > TIMEOUT) {
+-			ast_moutdwm(ast, 0x1e6e0070, 0x0);
+-			return 0;
+-		}
+-	} while (!data);
+-	ast_moutdwm(ast, 0x1e6e0070, 0x0);
+-	return 1;
++static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
++{
++	return mmc_test2(ast, datagen, 0x41);
+ }
+ 
+-static int mmc_test_single2(struct ast_private *ast, u32 datagen)
++static bool mmc_test_single(struct ast_private *ast, u32 datagen)
+ {
+-	u32 data, timeout;
++	return mmc_test(ast, datagen, 0xc5);
++}
+ 
+-	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
+-	ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
+-	timeout = 0;
+-	do {
+-		data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
+-		if (++timeout > TIMEOUT) {
+-			ast_moutdwm(ast, 0x1e6e0070, 0x0);
+-			return -1;
+-		}
+-	} while (!data);
+-	data = ast_mindwm(ast, 0x1e6e0078);
+-	data = (data | (data >> 16)) & 0xffff;
+-	ast_moutdwm(ast, 0x1e6e0070, 0x0);
+-	return data;
++static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
++{
++	return mmc_test2(ast, datagen, 0x05);
+ }
+ 
+ static int cbr_test(struct ast_private *ast)
+@@ -601,16 +581,16 @@ static u32 cbr_scan2(struct ast_private *ast)
+ 	return data2;
+ }
+ 
+-static u32 cbr_test3(struct ast_private *ast)
++static bool cbr_test3(struct ast_private *ast)
+ {
+ 	if (!mmc_test_burst(ast, 0))
+-		return 0;
++		return false;
+ 	if (!mmc_test_single(ast, 0))
+-		return 0;
+-	return 1;
++		return false;
++	return true;
+ }
+ 
+-static u32 cbr_scan3(struct ast_private *ast)
++static bool cbr_scan3(struct ast_private *ast)
+ {
+ 	u32 patcnt, loop;
+ 
+@@ -621,9 +601,9 @@ static u32 cbr_scan3(struct ast_private *ast)
+ 				break;
+ 		}
+ 		if (loop == 2)
+-			return 0;
++			return false;
+ 	}
+-	return 1;
++	return true;
+ }
+ 
+ static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
+-- 
+2.11.0
+
diff --git a/openpower/linux/0011-drm-ast-Rename-ast_init_dram_2300-to-ast_post_chip_2.patch b/openpower/linux/0011-drm-ast-Rename-ast_init_dram_2300-to-ast_post_chip_2.patch
new file mode 100644
index 0000000..0bdfc10
--- /dev/null
+++ b/openpower/linux/0011-drm-ast-Rename-ast_init_dram_2300-to-ast_post_chip_2.patch
@@ -0,0 +1,50 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Date: Fri, 17 Feb 2017 13:51:34 +1100
+Subject: [PATCH 11/15] drm/ast: Rename ast_init_dram_2300 to
+ ast_post_chip_2300
+
+The function does more than initializing the DRAM and in turns
+calls other functions to do the actual init. This will keeping
+things more consistent with the upcoming AST2500 POST code.
+
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_post.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
+index c55067ccb0b1..561fd7d3a0cf 100644
+--- a/drivers/gpu/drm/ast/ast_post.c
++++ b/drivers/gpu/drm/ast/ast_post.c
+@@ -31,7 +31,7 @@
+ 
+ #include "ast_dram_tables.h"
+ 
+-static void ast_init_dram_2300(struct drm_device *dev);
++static void ast_post_chip_2300(struct drm_device *dev);
+ 
+ void ast_enable_vga(struct drm_device *dev)
+ {
+@@ -381,7 +381,7 @@ void ast_post_gpu(struct drm_device *dev)
+ 
+ 	if (ast->config_mode == ast_use_p2a) {
+ 		if (ast->chip == AST2300 || ast->chip == AST2400)
+-			ast_init_dram_2300(dev);
++			ast_post_chip_2300(dev);
+ 		else
+ 			ast_init_dram_reg(dev);
+ 
+@@ -1589,7 +1589,7 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
+ 
+ }
+ 
+-static void ast_init_dram_2300(struct drm_device *dev)
++static void ast_post_chip_2300(struct drm_device *dev)
+ {
+ 	struct ast_private *ast = dev->dev_private;
+ 	struct ast2300_dram_param param;
+-- 
+2.11.0
+
diff --git a/openpower/linux/0012-drm-ast-POST-code-for-the-new-AST2500.patch b/openpower/linux/0012-drm-ast-POST-code-for-the-new-AST2500.patch
new file mode 100644
index 0000000..34ad9aa
--- /dev/null
+++ b/openpower/linux/0012-drm-ast-POST-code-for-the-new-AST2500.patch
@@ -0,0 +1,559 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: "Y.C. Chen" <yc_chen@aspeedtech.com>
+Date: Fri, 17 Feb 2017 14:45:07 +1100
+Subject: [PATCH 12/15] drm/ast: POST code for the new AST2500
+
+This is used when the BMC isn't running any code and thus has
+to be initialized by the host.
+
+The code originates from Aspeed (Y.C. Chen) and has been cleaned
+up for coding style purposes by BenH.
+
+Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+--
+
+v2. - Fix bug in ddr_test_2500 reported by Emil Velikov
+    - Rebase on updated mmc_test factoring patch
+    - Fix missing else statement in 2500 POST code
+
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_dram_tables.h |  62 +++++
+ drivers/gpu/drm/ast/ast_post.c        | 417 +++++++++++++++++++++++++++++++++-
+ 2 files changed, 476 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_dram_tables.h b/drivers/gpu/drm/ast/ast_dram_tables.h
+index cc04539c0ff3..1d9c4e75d303 100644
+--- a/drivers/gpu/drm/ast/ast_dram_tables.h
++++ b/drivers/gpu/drm/ast/ast_dram_tables.h
+@@ -141,4 +141,66 @@ static const struct ast_dramstruct ast2100_dram_table_data[] = {
+ 	{ 0xffff, 0xffffffff },
+ };
+ 
++/*
++ * AST2500 DRAM settings modules
++ */
++#define REGTBL_NUM           17
++#define REGIDX_010           0
++#define REGIDX_014           1
++#define REGIDX_018           2
++#define REGIDX_020           3
++#define REGIDX_024           4
++#define REGIDX_02C           5
++#define REGIDX_030           6
++#define REGIDX_214           7
++#define REGIDX_2E0           8
++#define REGIDX_2E4           9
++#define REGIDX_2E8           10
++#define REGIDX_2EC           11
++#define REGIDX_2F0           12
++#define REGIDX_2F4           13
++#define REGIDX_2F8           14
++#define REGIDX_RFC           15
++#define REGIDX_PLL           16
++
++static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
++	0x64604D38,		     /* 0x010 */
++	0x29690599,		     /* 0x014 */
++	0x00000300,		     /* 0x018 */
++	0x00000000,		     /* 0x020 */
++	0x00000000,		     /* 0x024 */
++	0x02181E70,		     /* 0x02C */
++	0x00000040,		     /* 0x030 */
++	0x00000024,		     /* 0x214 */
++	0x02001300,		     /* 0x2E0 */
++	0x0E0000A0,		     /* 0x2E4 */
++	0x000E001B,		     /* 0x2E8 */
++	0x35B8C105,		     /* 0x2EC */
++	0x08090408,		     /* 0x2F0 */
++	0x9B000800,		     /* 0x2F4 */
++	0x0E400A00,		     /* 0x2F8 */
++	0x9971452F,		     /* tRFC  */
++	0x000071C1		     /* PLL   */
++};
++
++static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
++	0x63604E37,		     /* 0x010 */
++	0xE97AFA99,		     /* 0x014 */
++	0x00019000,		     /* 0x018 */
++	0x08000000,		     /* 0x020 */
++	0x00000400,		     /* 0x024 */
++	0x00000410,		     /* 0x02C */
++	0x00000101,		     /* 0x030 */
++	0x00000024,		     /* 0x214 */
++	0x03002900,		     /* 0x2E0 */
++	0x0E0000A0,		     /* 0x2E4 */
++	0x000E001C,		     /* 0x2E8 */
++	0x35B8C106,		     /* 0x2EC */
++	0x08080607,		     /* 0x2F0 */
++	0x9B000900,		     /* 0x2F4 */
++	0x0E400A00,		     /* 0x2F8 */
++	0x99714545,		     /* tRFC  */
++	0x000071C1		     /* PLL   */
++};
++
+ #endif
+diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
+index 561fd7d3a0cf..c15f643915af 100644
+--- a/drivers/gpu/drm/ast/ast_post.c
++++ b/drivers/gpu/drm/ast/ast_post.c
+@@ -32,6 +32,7 @@
+ #include "ast_dram_tables.h"
+ 
+ static void ast_post_chip_2300(struct drm_device *dev);
++static void ast_post_chip_2500(struct drm_device *dev);
+ 
+ void ast_enable_vga(struct drm_device *dev)
+ {
+@@ -82,7 +83,8 @@ ast_set_def_ext_reg(struct drm_device *dev)
+ 	for (i = 0x81; i <= 0x9f; i++)
+ 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
+ 
+-	if (ast->chip == AST2300 || ast->chip == AST2400) {
++	if (ast->chip == AST2300 || ast->chip == AST2400 ||
++	    ast->chip == AST2500) {
+ 		if (dev->pdev->revision >= 0x20)
+ 			ext_reg_info = extreginfo_ast2300;
+ 		else
+@@ -106,7 +108,8 @@ ast_set_def_ext_reg(struct drm_device *dev)
+ 
+ 	/* Enable RAMDAC for A1 */
+ 	reg = 0x04;
+-	if (ast->chip == AST2300 || ast->chip == AST2400)
++	if (ast->chip == AST2300 || ast->chip == AST2400 ||
++	    ast->chip == AST2500)
+ 		reg |= 0x20;
+ 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
+ }
+@@ -380,7 +383,9 @@ void ast_post_gpu(struct drm_device *dev)
+ 	ast_set_def_ext_reg(dev);
+ 
+ 	if (ast->config_mode == ast_use_p2a) {
+-		if (ast->chip == AST2300 || ast->chip == AST2400)
++		if (ast->chip == AST2500)
++			ast_post_chip_2500(dev);
++		else if (ast->chip == AST2300 || ast->chip == AST2400)
+ 			ast_post_chip_2300(dev);
+ 		else
+ 			ast_init_dram_reg(dev);
+@@ -506,6 +511,11 @@ static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
+ 	return mmc_test2(ast, datagen, 0x05);
+ }
+ 
++static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
++{
++	return mmc_test(ast, datagen, 0x85);
++}
++
+ static int cbr_test(struct ast_private *ast)
+ {
+ 	u32 data;
+@@ -1672,3 +1682,404 @@ static void ast_post_chip_2300(struct drm_device *dev)
+ 	} while ((reg & 0x40) == 0);
+ }
+ 
++static bool cbr_test_2500(struct ast_private *ast)
++{
++	ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
++	ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
++	if (!mmc_test_burst(ast, 0))
++		return false;
++	if (!mmc_test_single_2500(ast, 0))
++		return false;
++	return true;
++}
++
++static bool ddr_test_2500(struct ast_private *ast)
++{
++	ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
++	ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
++	if (!mmc_test_burst(ast, 0))
++		return false;
++	if (!mmc_test_burst(ast, 1))
++		return false;
++	if (!mmc_test_burst(ast, 2))
++		return false;
++	if (!mmc_test_burst(ast, 3))
++		return false;
++	if (!mmc_test_single_2500(ast, 0))
++		return false;
++	return true;
++}
++
++static void ddr_init_common_2500(struct ast_private *ast)
++{
++	ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
++	ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
++	ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
++	ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
++	ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
++	ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
++	ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
++	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
++	ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
++	ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
++	ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
++	ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
++	ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
++	ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
++	ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
++	ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
++	ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
++	ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
++	ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
++}
++
++static void ddr_phy_init_2500(struct ast_private *ast)
++{
++	u32 data, pass, timecnt;
++
++	pass = 0;
++	ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
++	while (!pass) {
++		for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
++			data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
++			if (!data)
++				break;
++		}
++		if (timecnt != TIMEOUT) {
++			data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
++			if (!data)
++				pass = 1;
++		}
++		if (!pass) {
++			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
++			udelay(10); /* delay 10 us */
++			ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
++		}
++	}
++
++	ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
++}
++
++/*
++ * Check DRAM Size
++ * 1Gb : 0x80000000 ~ 0x87FFFFFF
++ * 2Gb : 0x80000000 ~ 0x8FFFFFFF
++ * 4Gb : 0x80000000 ~ 0x9FFFFFFF
++ * 8Gb : 0x80000000 ~ 0xBFFFFFFF
++ */
++static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
++{
++	u32 reg_04, reg_14;
++
++	reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
++	reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
++
++	ast_moutdwm(ast, 0xA0100000, 0x41424344);
++	ast_moutdwm(ast, 0x90100000, 0x35363738);
++	ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
++	ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
++
++	/* Check 8Gbit */
++	if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
++		reg_04 |= 0x03;
++		reg_14 |= (tRFC >> 24) & 0xFF;
++		/* Check 4Gbit */
++	} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
++		reg_04 |= 0x02;
++		reg_14 |= (tRFC >> 16) & 0xFF;
++		/* Check 2Gbit */
++	} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
++		reg_04 |= 0x01;
++		reg_14 |= (tRFC >> 8) & 0xFF;
++	} else {
++		reg_14 |= tRFC & 0xFF;
++	}
++	ast_moutdwm(ast, 0x1E6E0004, reg_04);
++	ast_moutdwm(ast, 0x1E6E0014, reg_14);
++}
++
++static void enable_cache_2500(struct ast_private *ast)
++{
++	u32 reg_04, data;
++
++	reg_04 = ast_mindwm(ast, 0x1E6E0004);
++	ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
++
++	do
++		data = ast_mindwm(ast, 0x1E6E0004);
++	while (!(data & 0x80000));
++	ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
++}
++
++static void set_mpll_2500(struct ast_private *ast)
++{
++	u32 addr, data, param;
++
++	/* Reset MMC */
++	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
++	ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
++	for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
++		ast_moutdwm(ast, addr, 0x0);
++		addr += 4;
++	}
++	ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
++
++	ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
++	data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
++	if (data) {
++		/* CLKIN = 25MHz */
++		param = 0x930023E0;
++		ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
++	} else {
++		/* CLKIN = 24MHz */
++		param = 0x93002400;
++	}
++	ast_moutdwm(ast, 0x1E6E2020, param);
++	udelay(100);
++}
++
++static void reset_mmc_2500(struct ast_private *ast)
++{
++	ast_moutdwm(ast, 0x1E78505C, 0x00000004);
++	ast_moutdwm(ast, 0x1E785044, 0x00000001);
++	ast_moutdwm(ast, 0x1E785048, 0x00004755);
++	ast_moutdwm(ast, 0x1E78504C, 0x00000013);
++	mdelay(100);
++	ast_moutdwm(ast, 0x1E785054, 0x00000077);
++	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
++}
++
++static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
++{
++
++	ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
++	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
++	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
++	ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
++	ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);	     /* MODEREG4/6 */
++	ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);	     /* MODEREG5 */
++	ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
++	ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);	     /* MODEREG1/3 */
++
++	/* DDR PHY Setting */
++	ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
++	ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
++	ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
++	ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
++	ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
++	ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
++	ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
++	ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
++	ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
++	ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
++	ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
++	ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
++	ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
++	ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
++
++	/* Controller Setting */
++	ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
++
++	/* Wait DDR PHY init done */
++	ddr_phy_init_2500(ast);
++
++	ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
++	ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
++	ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
++
++	check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
++	enable_cache_2500(ast);
++	ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
++	ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
++}
++
++static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
++{
++	u32 data, data2, pass, retrycnt;
++	u32 ddr_vref, phy_vref;
++	u32 min_ddr_vref = 0, min_phy_vref = 0;
++	u32 max_ddr_vref = 0, max_phy_vref = 0;
++
++	ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
++	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
++	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
++	ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
++	ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);	     /* MODEREG4/6 */
++	ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);	     /* MODEREG5 */
++	ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
++	ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);	     /* MODEREG1/3 */
++
++	/* DDR PHY Setting */
++	ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
++	ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
++	ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
++	ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
++	ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
++	ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
++	ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
++	ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
++	ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
++	ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
++	ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
++	ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
++	ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
++	ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
++	ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
++
++	/* Controller Setting */
++	ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
++
++	/* Train PHY Vref first */
++	pass = 0;
++
++	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
++		max_phy_vref = 0x0;
++		pass = 0;
++		ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
++		for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
++			ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
++			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
++			ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
++			/* Fire DFI Init */
++			ddr_phy_init_2500(ast);
++			ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
++			if (cbr_test_2500(ast)) {
++				pass++;
++				data = ast_mindwm(ast, 0x1E6E03D0);
++				data2 = data >> 8;
++				data  = data & 0xff;
++				if (data > data2)
++					data = data2;
++				if (max_phy_vref < data) {
++					max_phy_vref = data;
++					min_phy_vref = phy_vref;
++				}
++			} else if (pass > 0)
++				break;
++		}
++	}
++	ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
++
++	/* Train DDR Vref next */
++	pass = 0;
++
++	for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
++		min_ddr_vref = 0xFF;
++		max_ddr_vref = 0x0;
++		pass = 0;
++		for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
++			ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
++			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
++			ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
++			/* Fire DFI Init */
++			ddr_phy_init_2500(ast);
++			ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
++			if (cbr_test_2500(ast)) {
++				pass++;
++				if (min_ddr_vref > ddr_vref)
++					min_ddr_vref = ddr_vref;
++				if (max_ddr_vref < ddr_vref)
++					max_ddr_vref = ddr_vref;
++			} else if (pass != 0)
++				break;
++		}
++	}
++
++	ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
++	ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
++	ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
++	ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
++
++	/* Wait DDR PHY init done */
++	ddr_phy_init_2500(ast);
++
++	ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
++	ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
++	ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
++
++	check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
++	enable_cache_2500(ast);
++	ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
++	ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
++}
++
++static bool ast_dram_init_2500(struct ast_private *ast)
++{
++	u32 data;
++	u32 max_tries = 5;
++
++	do {
++		if (max_tries-- == 0)
++			return false;
++		set_mpll_2500(ast);
++		reset_mmc_2500(ast);
++		ddr_init_common_2500(ast);
++
++		data = ast_mindwm(ast, 0x1E6E2070);
++		if (data & 0x01000000)
++			ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
++		else
++			ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
++	} while (!ddr_test_2500(ast));
++
++	ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
++
++	/* Patch code */
++	data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
++	ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
++
++	return true;
++}
++
++void ast_post_chip_2500(struct drm_device *dev)
++{
++	struct ast_private *ast = dev->dev_private;
++	u32 temp;
++	u8 reg;
++
++	reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
++	if ((reg & 0x80) == 0) {/* vga only */
++		/* Clear bus lock condition */
++		ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
++		ast_moutdwm(ast, 0x1e600084, 0x00010000);
++		ast_moutdwm(ast, 0x1e600088, 0x00000000);
++		ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
++		ast_write32(ast, 0xf004, 0x1e6e0000);
++		ast_write32(ast, 0xf000, 0x1);
++		ast_write32(ast, 0x12000, 0x1688a8a8);
++		while (ast_read32(ast, 0x12000) != 0x1)
++			;
++
++		ast_write32(ast, 0x10000, 0xfc600309);
++		while (ast_read32(ast, 0x10000) != 0x1)
++			;
++
++		/* Slow down CPU/AHB CLK in VGA only mode */
++		temp = ast_read32(ast, 0x12008);
++		temp |= 0x73;
++		ast_write32(ast, 0x12008, temp);
++
++		/* Reset USB port to patch USB unknown device issue */
++		ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
++		temp  = ast_mindwm(ast, 0x1e6e2094);
++		temp |= 0x00004000;
++		ast_moutdwm(ast, 0x1e6e2094, temp);
++		temp  = ast_mindwm(ast, 0x1e6e2070);
++		if (temp & 0x00800000) {
++			ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
++			mdelay(100);
++			ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
++		}
++
++		if (!ast_dram_init_2500(ast))
++			DRM_ERROR("DRAM init failed !\n");
++
++		temp = ast_mindwm(ast, 0x1e6e2040);
++		ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
++	}
++
++	/* wait ready */
++	do {
++		reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
++	} while ((reg & 0x40) == 0);
++}
+-- 
+2.11.0
+
diff --git a/openpower/linux/0013-drm-ast-Fix-test-for-VGA-enabled.patch b/openpower/linux/0013-drm-ast-Fix-test-for-VGA-enabled.patch
new file mode 100644
index 0000000..f27d6c1
--- /dev/null
+++ b/openpower/linux/0013-drm-ast-Fix-test-for-VGA-enabled.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: "Y.C. Chen" <yc_chen@aspeedtech.com>
+Date: Wed, 22 Feb 2017 15:10:50 +1100
+Subject: [PATCH 13/15] drm/ast: Fix test for VGA enabled
+
+The test to see if VGA was already enabled is doing an unnecessary
+second test from a register that may or may not have been initialized
+to a valid value. Remove it.
+
+Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_post.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
+index c15f643915af..a5a780921553 100644
+--- a/drivers/gpu/drm/ast/ast_post.c
++++ b/drivers/gpu/drm/ast/ast_post.c
+@@ -59,13 +59,9 @@ bool ast_is_vga_enabled(struct drm_device *dev)
+ 		/* TODO 1180 */
+ 	} else {
+ 		ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
+-		if (ch) {
+-			ast_open_key(ast);
+-			ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
+-			return ch & 0x04;
+-		}
++		return !!(ch & 0x01);
+ 	}
+-	return 0;
++	return false;
+ }
+ 
+ static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
+-- 
+2.11.0
+
diff --git a/openpower/linux/0014-drm-ast-Call-open_key-before-enable_mmio-in-POST-cod.patch b/openpower/linux/0014-drm-ast-Call-open_key-before-enable_mmio-in-POST-cod.patch
new file mode 100644
index 0000000..b84131e
--- /dev/null
+++ b/openpower/linux/0014-drm-ast-Call-open_key-before-enable_mmio-in-POST-cod.patch
@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: "Y.C. Chen" <yc_chen@aspeedtech.com>
+Date: Wed, 22 Feb 2017 15:14:19 +1100
+Subject: [PATCH 14/15] drm/ast: Call open_key before enable_mmio in POST code
+
+open_key enables access the registers used by enable_mmio
+
+Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
+Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+---
+ drivers/gpu/drm/ast/ast_post.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
+index a5a780921553..f7d421359d56 100644
+--- a/drivers/gpu/drm/ast/ast_post.c
++++ b/drivers/gpu/drm/ast/ast_post.c
+@@ -374,8 +374,8 @@ void ast_post_gpu(struct drm_device *dev)
+ 	pci_write_config_dword(ast->dev->pdev, 0x04, reg);
+ 
+ 	ast_enable_vga(dev);
+-	ast_enable_mmio(dev);
+ 	ast_open_key(ast);
++	ast_enable_mmio(dev);
+ 	ast_set_def_ext_reg(dev);
+ 
+ 	if (ast->config_mode == ast_use_p2a) {
+-- 
+2.11.0
+
diff --git a/openpower/linux/0004-Release-4.9.13-openpower1.patch b/openpower/linux/0015-Release-OpenPower-kernel.patch
similarity index 68%
rename from openpower/linux/0004-Release-4.9.13-openpower1.patch
rename to openpower/linux/0015-Release-OpenPower-kernel.patch
index 656bb52..db8831f 100644
--- a/openpower/linux/0004-Release-4.9.13-openpower1.patch
+++ b/openpower/linux/0015-Release-OpenPower-kernel.patch
@@ -1,7 +1,7 @@
 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
 From: Joel Stanley <joel@jms.id.au>
-Date: Tue, 16 Aug 2016 23:00:23 +0930
-Subject: [PATCH 4/4] Release 4.9.13-openpower1
+Date: Tue, 28 Feb 2017 12:15:10 +1030
+Subject: [PATCH 15/15] Release OpenPower kernel
 
 Signed-off-by: Joel Stanley <joel@jms.id.au>
 ---
@@ -9,16 +9,16 @@
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/Makefile b/Makefile
-index 14dc2758345b..c298688d38f3 100644
+index 09eccff4f569..e291929b4fd0 100644
 --- a/Makefile
 +++ b/Makefile
 @@ -1,7 +1,7 @@
  VERSION = 4
- PATCHLEVEL = 9
- SUBLEVEL = 13
+ PATCHLEVEL = 10
+ SUBLEVEL = 1
 -EXTRAVERSION =
 +EXTRAVERSION = -openpower1
- NAME = Roaring Lionus
+ NAME = Fearless Coyote
  
  # *DOCUMENTATION*
 --