Add p8dtu platform
This contains the p8dtu platform from SuperMicro.
It has previously lived out of tree.
Like other POWER8 platforms, several Hostboot patches are required.
Since Hostboot does not have the ability to have per-platform code,
this comes in as patches.
Signed-off-by: Jim Yuan <jim.yuan@supermicro.com>
[stewart: cleanup and longer commit message]
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
diff --git a/openpower/patches/p8dtu-patches/hostboot-p8/0007-read-riser-id-from-CPLD.patch b/openpower/patches/p8dtu-patches/hostboot-p8/0007-read-riser-id-from-CPLD.patch
new file mode 100644
index 0000000..af19f74
--- /dev/null
+++ b/openpower/patches/p8dtu-patches/hostboot-p8/0007-read-riser-id-from-CPLD.patch
@@ -0,0 +1,95 @@
+From 94de2f7f944a2cabbdf699adcbc6679a091ad324 Mon Sep 17 00:00:00 2001
+From: Leoluo <leoluo@supermicro.com>
+Date: Tue, 8 Mar 2016 17:01:26 -0800
+Subject: [PATCH 07/14] read riser id from CPLD
+
+Signed-off-by: Jim Yuan <jim.yuan@supermicro.com>
+---
+ src/include/usr/ipmi/ipmiif.H | 3 ++
+ src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C | 42 +++++++++++++++++++++++++-
+ 2 files changed, 44 insertions(+), 1 deletion(-)
+
+diff --git a/src/include/usr/ipmi/ipmiif.H b/src/include/usr/ipmi/ipmiif.H
+index 8039adbf7..9dfd8ee63 100644
+--- a/src/include/usr/ipmi/ipmiif.H
++++ b/src/include/usr/ipmi/ipmiif.H
+@@ -238,6 +238,9 @@ namespace IPMI
+ inline const command_t get_capabilities(void)
+ { return std::make_pair(NETFUN_APP, 0x36); }
+
++ inline const command_t master_readwrite(void)
++ { return std::make_pair(NETFUN_APP, 0x52); }
++
+
+ // Chassis messages
+ inline const command_t chassis_power_off(void)
+diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
+index d122ae4de..73f1a0a3f 100644
+--- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
++++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
+@@ -58,6 +58,8 @@
+ // MVPD
+ #include <devicefw/userif.H>
+ #include <vpd/mvpdenums.H>
++#include <ipmi/ipmiif.H>
++
+
+ #include <config.h>
+
+@@ -1743,7 +1745,40 @@ errlHndl_t computeProcPcieConfigAttrs(
+ effectiveLaneSwap[iop] = laneSwap;
+ }
+ #endif
+-
++ uint8_t riser_id = 0 ;
++ errlHndl_t l_err = NULL;
++
++
++ size_t len = 4;
++
++ //create request data buffer
++ uint8_t* data = new uint8_t[len];
++
++ IPMI::completion_code cc = IPMI::CC_UNKBAD;
++
++ data[0] = 0x3;
++ data[1] = 0x70;
++ data[2] = 0x1;
++ data[3] = 0x1;
++ l_err = IPMI::sendrecv(IPMI::master_readwrite(), cc, len, data);
++
++ if( l_err == NULL )
++ {
++ if( cc == IPMI::CC_OK )
++ {
++ riser_id = data[0];
++ }
++
++ delete[] data;
++ }
++
++
++ if((i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>()) == 0x50001 && (riser_id == 0xE) ){
++ effectiveLaneMask[1][0] = 0xFFFF;
++ effectiveLaneMask[1][1] = 0x0000;
++ effectiveLaneSwap[1] = 0x0;
++ }
++
+ i_pProcChipTarget->setAttr<
+ TARGETING::ATTR_PROC_PCIE_LANE_MASK>(effectiveLaneMask);
+
+@@ -1797,6 +1832,11 @@ errlHndl_t computeProcPcieConfigAttrs(
+ iopConfig = laneConfigItr->laneConfig;
+ phbActiveMask = laneConfigItr->phbActive;
+
++ if((i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>()) == 0x50001 && (riser_id == 0xE) ){
++ iopConfig = 0 ;
++ phbActiveMask = PHB0_MASK|PHB1_MASK;
++ }
++
+ // Disable applicable PHBs
+ phbActiveMask &= (~disabledPhbs);
+ (void)_deconfigPhbsBasedOnPciState(
+--
+2.16.2.windows.1
+