commit b4db03b5260c03bd761c9dfb00def9410ee1491f
author Ramesh Iyyar <rameshi1@in.ibm.com> Thu Jan 20 00:57:28 2022 -0600
committer Andrew Geissler <geissonator@yahoo.com> Thu Jan 20 20:20:35 2022 +0000
tree f51d5e0f97c9b35f9d452231c95b8c44f373b80f
parent 53961c2d8a97d0f9e5a90c17ca48380657e79c3e

meta-openpower: ipl: Bumped 4102a54..75b471c

Ramesh Iyyar (2):
      libipl: p10: Fix, use macro instead numeric value
      libipl: p10: Don't apply primary processor guard record

rajerpp1 (2):
      libipl: Returning error IPL_ERR_PLAT, for all error with FFDC
      libipl: Lab support for skipping clock soft reset

Signed-off-by: Ramesh Iyyar <rameshi1@in.ibm.com>
Change-Id: I8caf7c5dbf3bd397d2a7ab7d0e22a7727632d436

meta-openpower/recipes-bsp/ipl/ipl_git.bb

diff --git a/meta-openpower/recipes-bsp/ipl/ipl_git.bb b/meta-openpower/recipes-bsp/ipl/ipl_git.bb
index e5b21ec..263b3f8 100644
--- a/meta-openpower/recipes-bsp/ipl/ipl_git.bb
+++ b/meta-openpower/recipes-bsp/ipl/ipl_git.bb
@@ -12,7 +12,7 @@
 S = "${WORKDIR}/git"
 
 SRC_URI = "git://git@github.com/open-power/ipl;branch="main""
-SRCREV = "4102a5410f877f0c7d20f6afc694243bf3a6ef6b"
+SRCREV = "75b471c171b444e4daa9ec867e7e233f339149c4"
 
 DEPENDS = " \
         libekb pdbg autoconf-archive guard pdata \