| From 68fa519a6cb455005317bd61f95214b58b2f1e69 Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <f4bug@amsat.org> |
| Date: Fri, 16 Oct 2020 15:20:37 +0200 |
| Subject: [PATCH] target/mips: Increase number of TLB entries on the 34Kf core |
| (16 -> 64) |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| Per "MIPS32 34K Processor Core Family Software User's Manual, |
| Revision 01.13" page 8 in "Joint TLB (JTLB)" section: |
| |
| "The JTLB is a fully associative TLB cache containing 16, 32, |
| or 64-dual-entries mapping up to 128 virtual pages to their |
| corresponding physical addresses." |
| |
| There is no particular reason to restrict the 34Kf core model to |
| 16 TLB entries, so raise its config to 64. |
| |
| This is helpful for other projects, in particular the Yocto Project: |
| |
| Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit |
| MIPS CI loop. It was observed that in this case CI test execution |
| time was almost twice longer than 64bit MIPS variant that runs |
| under MIPS64R2-generic model. It was investigated and concluded |
| that the difference in number of TLBs 16 in 34Kf case vs 64 in |
| MIPS64R2-generic is responsible for most of CI real time execution |
| difference. Because with 16 TLBs linux user-land trashes TLB more |
| and it needs to execute more instructions in TLB refill handler |
| calls, as result it runs much longer. |
| |
| (https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html) |
| |
| Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 |
| Reported-by: Victor Kamensky <kamensky@cisco.com> |
| Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| Message-Id: <20201016133317.553068-1-f4bug@amsat.org> |
| |
| Upstream-Status: Backport [https://github.com/qemu/qemu/commit/68fa519a6cb455005317bd61f95214b58b2f1e69] |
| Signed-off-by: Victor Kamensky <kamensky@cisco.com> |
| |
| --- |
| target/mips/translate_init.c.inc | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| Index: qemu-5.1.0/target/mips/translate_init.inc.c |
| =================================================================== |
| --- qemu-5.1.0.orig/target/mips/translate_init.inc.c |
| +++ qemu-5.1.0/target/mips/translate_init.inc.c |
| @@ -254,7 +254,7 @@ const mips_def_t mips_defs[] = |
| .CP0_PRid = 0x00019500, |
| .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| (MMU_TYPE_R4000 << CP0C0_MT), |
| - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
| + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
| (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| (1 << CP0C1_CA), |