| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "xlnx,microblaze"; |
| model = "Xilinx MicroBlaze"; |
| cpus { |
| #address-cells = <1>; |
| #cpus = <1>; |
| #size-cells = <0>; |
| microblaze_0: cpu@0 { |
| bus-handle = <&amba_pl>; |
| clock-frequency = <200000000>; |
| clocks = <&clk_cpu>; |
| compatible = "xlnx,microblaze-10.0"; |
| d-cache-baseaddr = <0x0000000080000000>; |
| d-cache-highaddr = <0x00000000bfffffff>; |
| d-cache-line-size = <0x20>; |
| d-cache-size = <0x4000>; |
| device_type = "cpu"; |
| i-cache-baseaddr = <0x0000000080000000>; |
| i-cache-highaddr = <0x00000000bfffffff>; |
| i-cache-line-size = <0x10>; |
| i-cache-size = <0x4000>; |
| interrupt-handle = <µblaze_0_axi_intc>; |
| model = "microblaze,10.0"; |
| timebase-frequency = <200000000>; |
| xlnx,addr-size = <0x20>; |
| xlnx,addr-tag-bits = <0x10>; |
| xlnx,allow-dcache-wr = <0x1>; |
| xlnx,allow-icache-wr = <0x1>; |
| xlnx,area-optimized = <0x0>; |
| xlnx,async-interrupt = <0x1>; |
| xlnx,async-wakeup = <0x3>; |
| xlnx,avoid-primitives = <0x0>; |
| xlnx,base-vectors = <0x0000000000000000>; |
| xlnx,branch-target-cache-size = <0x0>; |
| xlnx,cache-byte-size = <0x4000>; |
| xlnx,d-axi = <0x1>; |
| xlnx,d-lmb = <0x1>; |
| xlnx,d-lmb-mon = <0x0>; |
| xlnx,daddr-size = <0x20>; |
| xlnx,data-size = <0x20>; |
| xlnx,dc-axi-mon = <0x0>; |
| xlnx,dcache-addr-tag = <0x10>; |
| xlnx,dcache-always-used = <0x1>; |
| xlnx,dcache-byte-size = <0x4000>; |
| xlnx,dcache-data-width = <0x0>; |
| xlnx,dcache-force-tag-lutram = <0x0>; |
| xlnx,dcache-line-len = <0x8>; |
| xlnx,dcache-use-writeback = <0x0>; |
| xlnx,dcache-victims = <0x0>; |
| xlnx,debug-counter-width = <0x20>; |
| xlnx,debug-enabled = <0x1>; |
| xlnx,debug-event-counters = <0x5>; |
| xlnx,debug-external-trace = <0x0>; |
| xlnx,debug-interface = <0x0>; |
| xlnx,debug-latency-counters = <0x1>; |
| xlnx,debug-profile-size = <0x0>; |
| xlnx,debug-trace-async-reset = <0x0>; |
| xlnx,debug-trace-size = <0x2000>; |
| xlnx,div-zero-exception = <0x1>; |
| xlnx,dp-axi-mon = <0x0>; |
| xlnx,dynamic-bus-sizing = <0x0>; |
| xlnx,ecc-use-ce-exception = <0x0>; |
| xlnx,edge-is-positive = <0x1>; |
| xlnx,enable-discrete-ports = <0x0>; |
| xlnx,endianness = <0x1>; |
| xlnx,fault-tolerant = <0x0>; |
| xlnx,fpu-exception = <0x0>; |
| xlnx,freq = <0xbebc200>; |
| xlnx,fsl-exception = <0x0>; |
| xlnx,fsl-links = <0x0>; |
| xlnx,i-axi = <0x0>; |
| xlnx,i-lmb = <0x1>; |
| xlnx,i-lmb-mon = <0x0>; |
| xlnx,iaddr-size = <0x20>; |
| xlnx,ic-axi-mon = <0x0>; |
| xlnx,icache-always-used = <0x1>; |
| xlnx,icache-data-width = <0x0>; |
| xlnx,icache-force-tag-lutram = <0x0>; |
| xlnx,icache-line-len = <0x4>; |
| xlnx,icache-streams = <0x1>; |
| xlnx,icache-victims = <0x8>; |
| xlnx,ill-opcode-exception = <0x1>; |
| xlnx,imprecise-exceptions = <0x0>; |
| xlnx,instr-size = <0x20>; |
| xlnx,interconnect = <0x2>; |
| xlnx,interrupt-is-edge = <0x0>; |
| xlnx,interrupt-mon = <0x0>; |
| xlnx,ip-axi-mon = <0x0>; |
| xlnx,lockstep-master = <0x0>; |
| xlnx,lockstep-select = <0x0>; |
| xlnx,lockstep-slave = <0x0>; |
| xlnx,mmu-dtlb-size = <0x4>; |
| xlnx,mmu-itlb-size = <0x2>; |
| xlnx,mmu-privileged-instr = <0x0>; |
| xlnx,mmu-tlb-access = <0x3>; |
| xlnx,mmu-zones = <0x2>; |
| xlnx,num-sync-ff-clk = <0x2>; |
| xlnx,num-sync-ff-clk-debug = <0x2>; |
| xlnx,num-sync-ff-clk-irq = <0x1>; |
| xlnx,num-sync-ff-dbg-clk = <0x1>; |
| xlnx,num-sync-ff-dbg-trace-clk = <0x2>; |
| xlnx,number-of-pc-brk = <0x1>; |
| xlnx,number-of-rd-addr-brk = <0x0>; |
| xlnx,number-of-wr-addr-brk = <0x0>; |
| xlnx,opcode-0x0-illegal = <0x1>; |
| xlnx,optimization = <0x0>; |
| xlnx,pc-width = <0x20>; |
| xlnx,piaddr-size = <0x20>; |
| xlnx,pvr = <0x2>; |
| xlnx,pvr-user1 = <0x00>; |
| xlnx,pvr-user2 = <0x00000000>; |
| xlnx,reset-msr = <0x00000000>; |
| xlnx,reset-msr-bip = <0x0>; |
| xlnx,reset-msr-dce = <0x0>; |
| xlnx,reset-msr-ee = <0x0>; |
| xlnx,reset-msr-eip = <0x0>; |
| xlnx,reset-msr-ice = <0x0>; |
| xlnx,reset-msr-ie = <0x0>; |
| xlnx,sco = <0x0>; |
| xlnx,trace = <0x0>; |
| xlnx,unaligned-exceptions = <0x1>; |
| xlnx,use-barrel = <0x1>; |
| xlnx,use-branch-target-cache = <0x0>; |
| xlnx,use-config-reset = <0x0>; |
| xlnx,use-dcache = <0x1>; |
| xlnx,use-div = <0x1>; |
| xlnx,use-ext-brk = <0x0>; |
| xlnx,use-ext-nm-brk = <0x0>; |
| xlnx,use-extended-fsl-instr = <0x0>; |
| xlnx,use-fpu = <0x0>; |
| xlnx,use-hw-mul = <0x2>; |
| xlnx,use-icache = <0x1>; |
| xlnx,use-interrupt = <0x2>; |
| xlnx,use-mmu = <0x3>; |
| xlnx,use-msr-instr = <0x1>; |
| xlnx,use-non-secure = <0x0>; |
| xlnx,use-pcmp-instr = <0x1>; |
| xlnx,use-reorder-instr = <0x1>; |
| xlnx,use-stack-protection = <0x0>; |
| }; |
| }; |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clk_cpu: clk_cpu@0 { |
| #clock-cells = <0>; |
| clock-frequency = <200000000>; |
| clock-output-names = "clk_cpu"; |
| compatible = "fixed-clock"; |
| reg = <0>; |
| }; |
| clk_bus_0: clk_bus_0@1 { |
| #clock-cells = <0>; |
| clock-frequency = <200000000>; |
| clock-output-names = "clk_bus_0"; |
| compatible = "fixed-clock"; |
| reg = <1>; |
| }; |
| }; |
| amba_pl: amba_pl { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| ranges ; |
| axi_ethernet: ethernet@40c00000 { |
| axistream-connected = <&axi_ethernet_dma>; |
| axistream-control-connected = <&axi_ethernet_dma>; |
| clock-frequency = <100000000>; |
| compatible = "xlnx,axi-ethernet-1.00.a"; |
| device_type = "network"; |
| interrupt-parent = <µblaze_0_axi_intc>; |
| interrupts = <4 2>; |
| phy-mode = "gmii"; |
| reg = <0x40c00000 0x40000>; |
| xlnx = <0x0>; |
| xlnx,axiliteclkrate = <0x0>; |
| xlnx,axisclkrate = <0x0>; |
| xlnx,clockselection = <0x0>; |
| xlnx,enableasyncsgmii = <0x0>; |
| xlnx,gt-type = <0x0>; |
| xlnx,gtinex = <0x0>; |
| xlnx,gtlocation = <0x0>; |
| xlnx,gtrefclksrc = <0x0>; |
| xlnx,include-dre ; |
| xlnx,instantiatebitslice0 = <0x0>; |
| xlnx,phy-type = <0x1>; |
| xlnx,phyaddr = <0x1>; |
| xlnx,rable = <0x0>; |
| xlnx,rxcsum = <0x0>; |
| xlnx,rxlane0-placement = <0x0>; |
| xlnx,rxlane1-placement = <0x0>; |
| xlnx,rxmem = <0x1000>; |
| xlnx,rxnibblebitslice0used = <0x0>; |
| xlnx,tx-in-upper-nibble = <0x1>; |
| xlnx,txcsum = <0x0>; |
| xlnx,txlane0-placement = <0x0>; |
| xlnx,txlane1-placement = <0x0>; |
| axi_ethernet_mdio: mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| axi_ethernet_dma: dma@41e00000 { |
| #dma-cells = <1>; |
| axistream-connected = <&axi_ethernet>; |
| axistream-control-connected = <&axi_ethernet>; |
| clock-frequency = <200000000>; |
| clock-names = "s_axi_lite_aclk"; |
| clocks = <&clk_bus_0>; |
| compatible = "xlnx,eth-dma"; |
| interrupt-parent = <µblaze_0_axi_intc>; |
| interrupts = <3 2 2 2>; |
| reg = <0x41e00000 0x10000>; |
| xlnx,include-dre ; |
| }; |
| axi_timer_0: timer@41c00000 { |
| clock-frequency = <200000000>; |
| clocks = <&clk_bus_0>; |
| compatible = "xlnx,xps-timer-1.00.a"; |
| interrupt-parent = <µblaze_0_axi_intc>; |
| interrupts = <5 2>; |
| reg = <0x41c00000 0x10000>; |
| xlnx,count-width = <0x20>; |
| xlnx,gen0-assert = <0x1>; |
| xlnx,gen1-assert = <0x1>; |
| xlnx,one-timer-only = <0x0>; |
| xlnx,trig0-assert = <0x1>; |
| xlnx,trig1-assert = <0x1>; |
| }; |
| calib_complete_gpio: gpio@40010000 { |
| #gpio-cells = <2>; |
| compatible = "xlnx,xps-gpio-1.00.a"; |
| gpio-controller ; |
| reg = <0x40010000 0x10000>; |
| xlnx,all-inputs = <0x1>; |
| xlnx,all-inputs-2 = <0x0>; |
| xlnx,all-outputs = <0x0>; |
| xlnx,all-outputs-2 = <0x0>; |
| xlnx,dout-default = <0x00000000>; |
| xlnx,dout-default-2 = <0x00000000>; |
| xlnx,gpio-width = <0x1>; |
| xlnx,gpio2-width = <0x20>; |
| xlnx,interrupt-present = <0x0>; |
| xlnx,is-dual = <0x0>; |
| xlnx,tri-default = <0xFFFFFFFF>; |
| xlnx,tri-default-2 = <0xFFFFFFFF>; |
| }; |
| dip_switches_4bits: gpio@40020000 { |
| #gpio-cells = <2>; |
| compatible = "xlnx,xps-gpio-1.00.a"; |
| gpio-controller ; |
| reg = <0x40020000 0x10000>; |
| xlnx,all-inputs = <0x1>; |
| xlnx,all-inputs-2 = <0x0>; |
| xlnx,all-outputs = <0x0>; |
| xlnx,all-outputs-2 = <0x0>; |
| xlnx,dout-default = <0x00000000>; |
| xlnx,dout-default-2 = <0x00000000>; |
| xlnx,gpio-width = <0x4>; |
| xlnx,gpio2-width = <0x20>; |
| xlnx,interrupt-present = <0x0>; |
| xlnx,is-dual = <0x0>; |
| xlnx,tri-default = <0xFFFFFFFF>; |
| xlnx,tri-default-2 = <0xFFFFFFFF>; |
| }; |
| iic_main: i2c@40800000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <200000000>; |
| clocks = <&clk_bus_0>; |
| compatible = "xlnx,xps-iic-2.00.a"; |
| interrupt-parent = <µblaze_0_axi_intc>; |
| interrupts = <1 2>; |
| reg = <0x40800000 0x10000>; |
| }; |
| led_8bits: gpio@40030000 { |
| #gpio-cells = <2>; |
| compatible = "xlnx,xps-gpio-1.00.a"; |
| gpio-controller ; |
| reg = <0x40030000 0x10000>; |
| xlnx,all-inputs = <0x0>; |
| xlnx,all-inputs-2 = <0x0>; |
| xlnx,all-outputs = <0x1>; |
| xlnx,all-outputs-2 = <0x0>; |
| xlnx,dout-default = <0x00000000>; |
| xlnx,dout-default-2 = <0x00000000>; |
| xlnx,gpio-width = <0x8>; |
| xlnx,gpio2-width = <0x20>; |
| xlnx,interrupt-present = <0x0>; |
| xlnx,is-dual = <0x0>; |
| xlnx,tri-default = <0xFFFFFFFF>; |
| xlnx,tri-default-2 = <0xFFFFFFFF>; |
| }; |
| linear_flash: flash@60000000 { |
| bank-width = <2>; |
| compatible = "cfi-flash"; |
| reg = <0x60000000 0x8000000>; |
| xlnx,axi-clk-period-ps = <0x1388>; |
| xlnx,include-datawidth-matching-0 = <0x1>; |
| xlnx,include-datawidth-matching-1 = <0x1>; |
| xlnx,include-datawidth-matching-2 = <0x1>; |
| xlnx,include-datawidth-matching-3 = <0x1>; |
| xlnx,include-negedge-ioregs = <0x0>; |
| xlnx,lflash-period-ps = <0x1388>; |
| xlnx,linear-flash-sync-burst = <0x0>; |
| xlnx,max-mem-width = <0x10>; |
| xlnx,mem-a-lsb = <0x0>; |
| xlnx,mem-a-msb = <0x1f>; |
| xlnx,mem0-type = <0x2>; |
| xlnx,mem0-width = <0x10>; |
| xlnx,mem1-type = <0x0>; |
| xlnx,mem1-width = <0x10>; |
| xlnx,mem2-type = <0x0>; |
| xlnx,mem2-width = <0x10>; |
| xlnx,mem3-type = <0x0>; |
| xlnx,mem3-width = <0x10>; |
| xlnx,num-banks-mem = <0x1>; |
| xlnx,page-size = <0x10>; |
| xlnx,parity-type-mem-0 = <0x0>; |
| xlnx,parity-type-mem-1 = <0x0>; |
| xlnx,parity-type-mem-2 = <0x0>; |
| xlnx,parity-type-mem-3 = <0x0>; |
| xlnx,port-diff = <0x0>; |
| xlnx,s-axi-en-reg = <0x0>; |
| xlnx,s-axi-mem-addr-width = <0x20>; |
| xlnx,s-axi-mem-data-width = <0x20>; |
| xlnx,s-axi-mem-id-width = <0x1>; |
| xlnx,s-axi-reg-addr-width = <0x5>; |
| xlnx,s-axi-reg-data-width = <0x20>; |
| xlnx,synch-pipedelay-0 = <0x1>; |
| xlnx,synch-pipedelay-1 = <0x1>; |
| xlnx,synch-pipedelay-2 = <0x1>; |
| xlnx,synch-pipedelay-3 = <0x1>; |
| xlnx,tavdv-ps-mem-0 = <0x1fbd0>; |
| xlnx,tavdv-ps-mem-1 = <0x3a98>; |
| xlnx,tavdv-ps-mem-2 = <0x3a98>; |
| xlnx,tavdv-ps-mem-3 = <0x3a98>; |
| xlnx,tcedv-ps-mem-0 = <0x1fbd0>; |
| xlnx,tcedv-ps-mem-1 = <0x3a98>; |
| xlnx,tcedv-ps-mem-2 = <0x3a98>; |
| xlnx,tcedv-ps-mem-3 = <0x3a98>; |
| xlnx,thzce-ps-mem-0 = <0x88b8>; |
| xlnx,thzce-ps-mem-1 = <0x1b58>; |
| xlnx,thzce-ps-mem-2 = <0x1b58>; |
| xlnx,thzce-ps-mem-3 = <0x1b58>; |
| xlnx,thzoe-ps-mem-0 = <0x1b58>; |
| xlnx,thzoe-ps-mem-1 = <0x1b58>; |
| xlnx,thzoe-ps-mem-2 = <0x1b58>; |
| xlnx,thzoe-ps-mem-3 = <0x1b58>; |
| xlnx,tlzwe-ps-mem-0 = <0xc350>; |
| xlnx,tlzwe-ps-mem-1 = <0x0>; |
| xlnx,tlzwe-ps-mem-2 = <0x0>; |
| xlnx,tlzwe-ps-mem-3 = <0x0>; |
| xlnx,tpacc-ps-flash-0 = <0x61a8>; |
| xlnx,tpacc-ps-flash-1 = <0x61a8>; |
| xlnx,tpacc-ps-flash-2 = <0x61a8>; |
| xlnx,tpacc-ps-flash-3 = <0x61a8>; |
| xlnx,twc-ps-mem-0 = <0x11170>; |
| xlnx,twc-ps-mem-1 = <0x3a98>; |
| xlnx,twc-ps-mem-2 = <0x3a98>; |
| xlnx,twc-ps-mem-3 = <0x3a98>; |
| xlnx,twp-ps-mem-0 = <0x13880>; |
| xlnx,twp-ps-mem-1 = <0x2ee0>; |
| xlnx,twp-ps-mem-2 = <0x2ee0>; |
| xlnx,twp-ps-mem-3 = <0x2ee0>; |
| xlnx,twph-ps-mem-0 = <0x13880>; |
| xlnx,twph-ps-mem-1 = <0x2ee0>; |
| xlnx,twph-ps-mem-2 = <0x2ee0>; |
| xlnx,twph-ps-mem-3 = <0x2ee0>; |
| xlnx,use-startup = <0x0>; |
| xlnx,use-startup-int = <0x0>; |
| xlnx,wr-rec-time-mem-0 = <0x186a0>; |
| xlnx,wr-rec-time-mem-1 = <0x6978>; |
| xlnx,wr-rec-time-mem-2 = <0x6978>; |
| xlnx,wr-rec-time-mem-3 = <0x6978>; |
| }; |
| microblaze_0_axi_intc: interrupt-controller@41200000 { |
| #interrupt-cells = <2>; |
| compatible = "xlnx,xps-intc-1.00.a"; |
| interrupt-controller ; |
| reg = <0x41200000 0x10000>; |
| xlnx,kind-of-intr = <0x0>; |
| xlnx,num-intr-inputs = <0x6>; |
| }; |
| push_buttons_5bits: gpio@40040000 { |
| #gpio-cells = <2>; |
| compatible = "xlnx,xps-gpio-1.00.a"; |
| gpio-controller ; |
| reg = <0x40040000 0x10000>; |
| xlnx,all-inputs = <0x1>; |
| xlnx,all-inputs-2 = <0x0>; |
| xlnx,all-outputs = <0x0>; |
| xlnx,all-outputs-2 = <0x0>; |
| xlnx,dout-default = <0x00000000>; |
| xlnx,dout-default-2 = <0x00000000>; |
| xlnx,gpio-width = <0x5>; |
| xlnx,gpio2-width = <0x20>; |
| xlnx,interrupt-present = <0x0>; |
| xlnx,is-dual = <0x0>; |
| xlnx,tri-default = <0xFFFFFFFF>; |
| xlnx,tri-default-2 = <0xFFFFFFFF>; |
| }; |
| reset_gpio: gpio@40000000 { |
| #gpio-cells = <2>; |
| compatible = "xlnx,xps-gpio-1.00.a"; |
| gpio-controller ; |
| reg = <0x40000000 0x10000>; |
| xlnx,all-inputs = <0x0>; |
| xlnx,all-inputs-2 = <0x0>; |
| xlnx,all-outputs = <0x1>; |
| xlnx,all-outputs-2 = <0x0>; |
| xlnx,dout-default = <0x00000000>; |
| xlnx,dout-default-2 = <0x00000000>; |
| xlnx,gpio-width = <0x1>; |
| xlnx,gpio2-width = <0x20>; |
| xlnx,interrupt-present = <0x0>; |
| xlnx,is-dual = <0x0>; |
| xlnx,tri-default = <0xFFFFFFFF>; |
| xlnx,tri-default-2 = <0xFFFFFFFF>; |
| }; |
| rs232_uart: serial@44a00000 { |
| clock-frequency = <200000000>; |
| clocks = <&clk_bus_0>; |
| compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a"; |
| current-speed = <115200>; |
| device_type = "serial"; |
| interrupt-parent = <µblaze_0_axi_intc>; |
| interrupts = <0 2>; |
| port-number = <0>; |
| reg = <0x44a00000 0x10000>; |
| reg-offset = <0x1000>; |
| reg-shift = <2>; |
| xlnx,external-xin-clk-hz = <0x17d7840>; |
| xlnx,external-xin-clk-hz-d = <0x19>; |
| xlnx,has-external-rclk = <0x0>; |
| xlnx,has-external-xin = <0x0>; |
| xlnx,is-a-16550 = <0x1>; |
| xlnx,s-axi-aclk-freq-hz-d = "200.0"; |
| xlnx,use-modem-ports = <0x1>; |
| xlnx,use-user-ports = <0x1>; |
| }; |
| }; |
| }; |