| Chanh Nguyen | 6610b2e | 2021-10-10 12:11:16 +0700 | [diff] [blame] | 1 | From 7947dbbfb21e10e8fb0f852a14485cedf5df1d36 Mon Sep 17 00:00:00 2001 |
| 2 | From: Chanh Nguyen <chanh@os.amperecomputing.com> |
| 3 | Date: Sun, 10 Oct 2021 11:57:20 +0700 |
| 4 | Subject: [PATCH] aspeed: Enable SPI master mode by default |
| 5 | |
| 6 | The ast2500 share the RGMII1 pin and the hw strap pins |
| 7 | for SPI interface mode selection ( pin[12:13] ). |
| 8 | In some systems, the RGMII/NCSI interface will use the pin. |
| 9 | It makes the SPI interface mode setting is not correct. |
| 10 | |
| 11 | This patch will enable the SPI master mode by default. |
| 12 | |
| 13 | Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> |
| 14 | --- |
| 15 | board/aspeed/ast-g5/ast-g5.c | 3 +++ |
| 16 | 1 file changed, 3 insertions(+) |
| 17 | |
| 18 | diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c |
| 19 | index e67a4bf8b2..82e9f81acc 100644 |
| 20 | --- a/board/aspeed/ast-g5/ast-g5.c |
| 21 | +++ b/board/aspeed/ast-g5/ast-g5.c |
| 22 | @@ -21,6 +21,9 @@ int board_init(void) |
| 23 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
| 24 | gd->flags = 0; |
| 25 | |
| 26 | + //pin switch by trap[13:12] -- [0:1] Enable SPI Master |
| 27 | + ast_scu_spi_master(1); /* enable SPI master */ |
| 28 | + |
| 29 | return 0; |
| 30 | } |
| 31 | |
| 32 | -- |
| 33 | 2.17.1 |
| 34 | |