| Patrick Williams | 8e7b46e | 2023-05-01 14:19:06 -0500 | [diff] [blame] | 1 | From e4b0fced6f3fd3c8ce5ab4d3aae97b880e7e07b0 Mon Sep 17 00:00:00 2001 |
| 2 | From: sahil <sahil@arm.com> |
| 3 | Date: Mon, 2 May 2022 17:43:17 +0530 |
| 4 | Subject: [PATCH] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region |
| 5 | |
| 6 | Enable SCP QSPI flash region access by adding it in the PlatformLibMem |
| 7 | |
| 8 | Upstream-Status: Pending |
| 9 | Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com> |
| 10 | Signed-off-by: sahil <sahil@arm.com> |
| 11 | Change-Id: I3ff832746ca94974ed72309eebe00e0024c47005 |
| 12 | --- |
| 13 | Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 4 ++++ |
| 14 | .../NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 8 +++++++- |
| 15 | 2 files changed, 11 insertions(+), 1 deletion(-) |
| 16 | |
| 17 | diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h |
| 18 | index 4966011e..c7219136 100644 |
| 19 | --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h |
| 20 | +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h |
| 21 | @@ -41,6 +41,10 @@ |
| 22 | #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000
|
| 23 | #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000
|
| 24 |
|
| 25 | +// SCP QSPI flash device
|
| 26 | +#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE 0x18000000
|
| 27 | +#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ 0x2000000
|
| 28 | +
|
| 29 | /*
|
| 30 | * Platform information structure stored in Non-secure SRAM. Platform
|
| 31 | * information are passed from the trusted firmware with the below structure
|
| 32 | diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c |
| 33 | index 5cacd437..8bb94074 100644 |
| 34 | --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c |
| 35 | +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c |
| 36 | @@ -15,7 +15,7 @@ |
| 37 | #include <NeoverseN1Soc.h>
|
| 38 |
|
| 39 | // The total number of descriptors, including the final "end-of-table" descriptor.
|
| 40 | -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
|
| 41 | +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20
|
| 42 |
|
| 43 | /** A helper function to locate the NtFwConfig PPI and get the base address of
|
| 44 | NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
|
| 45 | @@ -283,6 +283,12 @@ ArmPlatformGetVirtualMemoryMap ( |
| 46 | VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
|
| 47 | VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
| 48 |
|
| 49 | + // SCP QSPI flash device
|
| 50 | + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
|
| 51 | + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
|
| 52 | + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_SCP_QSPI_AHB_SZ;
|
| 53 | + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
| 54 | +
|
| 55 | if (PlatInfo->MultichipMode == 1) {
|
| 56 | //Remote DDR (2GB)
|
| 57 | VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) +
|