| Andrew Geissler | d159c7f | 2021-09-02 21:05:58 -0500 | [diff] [blame] | 1 | Add suppor for riscv64 and riscv32 musl targets |
| 2 | |
| 3 | Upstream-Status: Pending |
| 4 | Signed-off-by: Khem Raj <raj.khem@gmail.com> |
| 5 | |
| 6 | --- a/vendor/cc/src/lib.rs |
| 7 | +++ b/vendor/cc/src/lib.rs |
| 8 | @@ -2361,6 +2361,7 @@ impl Build { |
| 9 | "riscv-none-embed", |
| 10 | ]), |
| 11 | "riscv64gc-unknown-linux-gnu" => Some("riscv64-linux-gnu"), |
| 12 | + "riscv64gc-unknown-linux-musl" => Some("riscv64-linux-musl"), |
| 13 | "s390x-unknown-linux-gnu" => Some("s390x-linux-gnu"), |
| 14 | "sparc-unknown-linux-gnu" => Some("sparc-linux-gnu"), |
| 15 | "sparc64-unknown-linux-gnu" => Some("sparc64-linux-gnu"), |
| 16 | --- a/compiler/rustc_target/src/spec/mod.rs |
| 17 | +++ b/compiler/rustc_target/src/spec/mod.rs |
| 18 | @@ -641,9 +641,11 @@ supported_targets! { |
| 19 | ("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf), |
| 20 | ("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf), |
| 21 | ("riscv32gc-unknown-linux-gnu", riscv32gc_unknown_linux_gnu), |
| 22 | + ("riscv32gc-unknown-linux-musl", riscv32gc_unknown_linux_musl), |
| 23 | ("riscv64imac-unknown-none-elf", riscv64imac_unknown_none_elf), |
| 24 | ("riscv64gc-unknown-none-elf", riscv64gc_unknown_none_elf), |
| 25 | ("riscv64gc-unknown-linux-gnu", riscv64gc_unknown_linux_gnu), |
| 26 | + ("riscv64gc-unknown-linux-musl", riscv64gc_unknown_linux_musl), |
| 27 | |
| 28 | ("aarch64-unknown-none", aarch64_unknown_none), |
| 29 | ("aarch64-unknown-none-softfloat", aarch64_unknown_none_softfloat), |
| 30 | --- /dev/null |
| 31 | +++ b/compiler/rustc_target/src/spec/riscv32gc_unknown_linux_musl.rs |
| 32 | @@ -0,0 +1,19 @@ |
| 33 | +use crate::spec::{CodeModel, Target, TargetOptions}; |
| 34 | + |
| 35 | +pub fn target() -> Target { |
| 36 | + Target { |
| 37 | + llvm_target: "riscv32-unknown-linux-musl".to_string(), |
| 38 | + pointer_width: 32, |
| 39 | + data_layout: "e-m:e-p:32:32-i64:64-n32-S128".to_string(), |
| 40 | + arch: "riscv32".to_string(), |
| 41 | + options: TargetOptions { |
| 42 | + unsupported_abis: super::riscv_base::unsupported_abis(), |
| 43 | + code_model: Some(CodeModel::Medium), |
| 44 | + cpu: "generic-rv32".to_string(), |
| 45 | + features: "+m,+a,+f,+d,+c".to_string(), |
| 46 | + llvm_abiname: "ilp32d".to_string(), |
| 47 | + max_atomic_width: Some(32), |
| 48 | + ..super::linux_musl_base::opts() |
| 49 | + }, |
| 50 | + } |
| 51 | +} |
| 52 | --- /dev/null |
| 53 | +++ b/compiler/rustc_target/src/spec/riscv64gc_unknown_linux_musl.rs |
| 54 | @@ -0,0 +1,19 @@ |
| 55 | +use crate::spec::{CodeModel, Target, TargetOptions}; |
| 56 | + |
| 57 | +pub fn target() -> Target { |
| 58 | + Target { |
| 59 | + llvm_target: "riscv64-unknown-linux-musl".to_string(), |
| 60 | + pointer_width: 64, |
| 61 | + data_layout: "e-m:e-p:64:64-i64:64-i128:128-n64-S128".to_string(), |
| 62 | + arch: "riscv64".to_string(), |
| 63 | + options: TargetOptions { |
| 64 | + unsupported_abis: super::riscv_base::unsupported_abis(), |
| 65 | + code_model: Some(CodeModel::Medium), |
| 66 | + cpu: "generic-rv64".to_string(), |
| 67 | + features: "+m,+a,+f,+d,+c".to_string(), |
| 68 | + llvm_abiname: "lp64d".to_string(), |
| 69 | + max_atomic_width: Some(64), |
| 70 | + ..super::linux_musl_base::opts() |
| 71 | + }, |
| 72 | + } |
| 73 | +} |