| Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 1 | From be710c5657b03bc9a9ce18ecf7ce1956265bae47 Mon Sep 17 00:00:00 2001 |
| 2 | From: Adrian Herrera <adrian.herrera@arm.com> |
| 3 | Date: Thu, 10 Dec 2020 18:07:21 +0000 |
| 4 | Subject: [PATCH] dev-arm: SMMUv3, enable interrupt interface |
| 5 | |
| 6 | Users can set "irq_interface_enable" to allow software to program |
| 7 | SMMU_IRQ_CTRL and SMMU_IRQ_CTRLACK. This is required to boot Linux v5.4+ |
| 8 | in a reasonable time. Notice the model does not implement architectural |
| 9 | interrupt sources, so no assertions will happen. |
| 10 | |
| 11 | Change-Id: Ie138befdf5a204fe8fce961081c575c2166e22b9 |
| 12 | Signed-off-by: Adrian Herrera <adrian.herrera@arm.com> |
| 13 | Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38555 |
| 14 | Tested-by: kokoro <noreply+kokoro@google.com> |
| 15 | Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
| 16 | Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| 17 | |
| 18 | Upstream-Status: Accepted [https://gem5-review.googlesource.com/c/public/gem5/+/38555] |
| 19 | Expected version: v20.2 |
| 20 | --- |
| 21 | src/dev/arm/SMMUv3.py | 5 +++++ |
| 22 | src/dev/arm/smmu_v3.cc | 10 +++++++++- |
| 23 | src/dev/arm/smmu_v3.hh | 4 +++- |
| 24 | 3 files changed, 17 insertions(+), 2 deletions(-) |
| 25 | |
| 26 | diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py |
| 27 | index 29c15682bf..f57be896f9 100644 |
| 28 | --- a/src/dev/arm/SMMUv3.py |
| 29 | +++ b/src/dev/arm/SMMUv3.py |
| 30 | @@ -91,6 +91,11 @@ class SMMUv3(ClockedObject): |
| 31 | reg_map = Param.AddrRange('Address range for control registers') |
| 32 | system = Param.System(Parent.any, "System this device is part of") |
| 33 | |
| 34 | + irq_interface_enable = Param.Bool(False, |
| 35 | + "This flag enables software to program SMMU_IRQ_CTRL and " |
| 36 | + "SMMU_IRQ_CTRLACK as if the model implemented architectural " |
| 37 | + "interrupt sources") |
| 38 | + |
| 39 | device_interfaces = VectorParam.SMMUv3DeviceInterface([], |
| 40 | "Responder interfaces") |
| 41 | |
| 42 | diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc |
| 43 | index f9bdc277c6..d73f270170 100644 |
| 44 | --- a/src/dev/arm/smmu_v3.cc |
| 45 | +++ b/src/dev/arm/smmu_v3.cc |
| 46 | @@ -1,5 +1,5 @@ |
| 47 | /* |
| 48 | - * Copyright (c) 2013, 2018-2019 ARM Limited |
| 49 | + * Copyright (c) 2013, 2018-2020 ARM Limited |
| 50 | * All rights reserved |
| 51 | * |
| 52 | * The license below extends only to copyright in the software and shall |
| 53 | @@ -58,6 +58,7 @@ SMMUv3::SMMUv3(SMMUv3Params *params) : |
| 54 | requestPort(name() + ".request", *this), |
| 55 | tableWalkPort(name() + ".walker", *this), |
| 56 | controlPort(name() + ".control", *this, params->reg_map), |
| 57 | + irqInterfaceEnable(params->irq_interface_enable), |
| 58 | tlb(params->tlb_entries, params->tlb_assoc, params->tlb_policy), |
| 59 | configCache(params->cfg_entries, params->cfg_assoc, params->cfg_policy), |
| 60 | ipaCache(params->ipa_entries, params->ipa_assoc, params->ipa_policy), |
| 61 | @@ -626,6 +627,13 @@ SMMUv3::writeControl(PacketPtr pkt) |
| 62 | assert(pkt->getSize() == sizeof(uint32_t)); |
| 63 | regs.cr0 = regs.cr0ack = pkt->getLE<uint32_t>(); |
| 64 | break; |
| 65 | + case offsetof(SMMURegs, irq_ctrl): |
| 66 | + assert(pkt->getSize() == sizeof(uint32_t)); |
| 67 | + if (irqInterfaceEnable) { |
| 68 | + warn("SMMUv3::%s No support for interrupt sources", __func__); |
| 69 | + regs.irq_ctrl = regs.irq_ctrlack = pkt->getLE<uint32_t>(); |
| 70 | + } |
| 71 | + break; |
| 72 | |
| 73 | case offsetof(SMMURegs, cr1): |
| 74 | case offsetof(SMMURegs, cr2): |
| 75 | diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh |
| 76 | index 6b3f3982b8..a001d71178 100644 |
| 77 | --- a/src/dev/arm/smmu_v3.hh |
| 78 | +++ b/src/dev/arm/smmu_v3.hh |
| 79 | @@ -1,5 +1,5 @@ |
| 80 | /* |
| 81 | - * Copyright (c) 2013, 2018-2019 ARM Limited |
| 82 | + * Copyright (c) 2013, 2018-2020 ARM Limited |
| 83 | * All rights reserved |
| 84 | * |
| 85 | * The license below extends only to copyright in the software and shall |
| 86 | @@ -94,6 +94,8 @@ class SMMUv3 : public ClockedObject |
| 87 | SMMUTableWalkPort tableWalkPort; |
| 88 | SMMUControlPort controlPort; |
| 89 | |
| 90 | + const bool irqInterfaceEnable; |
| 91 | + |
| 92 | ARMArchTLB tlb; |
| 93 | ConfigCache configCache; |
| 94 | IPACache ipaCache; |
| 95 | -- |
| 96 | 2.17.1 |
| 97 | |