blob: 14095d8332456003ed005d4aa8ef3a7fdfda1bc2 [file] [log] [blame]
Andrew Geissler10fa1492020-12-11 16:25:29 -06001From a8c6c13cc322ecc300bb2cdf22e3d6f1680e56be Mon Sep 17 00:00:00 2001
Brad Bishop26bdd442019-08-16 17:08:17 -04002From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 18:07:24 +0530
Andrew Geissler10fa1492020-12-11 16:25:29 -06004Subject: [PATCH 18/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
5 insn definitions Change adddi3 to handle DI immediates as the second operand,
6 this requires modification to the output template however reduces the need to
7 specify seperate templates for 16-bit positive/negative immediate operands.
8 The use of 32-bit immediates for the addi and addic instructions is handled
9 by the assembler, which will emit the imm instructions when required. This
10 conveniently handles the optimizable cases where the immediate constant value
11 does not need the higher half words of the operands upper/lower words.
Brad Bishop286d45c2018-10-02 15:21:57 -040012
13Change the constraints of the subdi3 instruction definition such that it
14does not match the second operand as an immediate value. This is because
15there is no definition to handle this case nor is it possible to
16implement purely with instructions as microblaze does not provide an
17instruction to perform a forward arithmetic subtraction (it only
18provides reverse 'rD = IMM - rA').
19
20Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Brad Bishop286d45c2018-10-02 15:21:57 -040021---
22 gcc/config/microblaze/microblaze.md | 13 ++++++-------
23 1 file changed, 6 insertions(+), 7 deletions(-)
24
25diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
Andrew Geisslera9ff2b32020-10-16 10:11:54 -050026index 986d9c3aa25..efd2c34e0b7 100644
Brad Bishop286d45c2018-10-02 15:21:57 -040027--- a/gcc/config/microblaze/microblaze.md
28+++ b/gcc/config/microblaze/microblaze.md
Andrew Geissler84ad7c52020-06-27 00:00:16 -050029@@ -502,17 +502,16 @@
Brad Bishop286d45c2018-10-02 15:21:57 -040030 ;; Adding 2 DI operands in register or reg/imm
31
32 (define_insn "adddi3"
33- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
34- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
35- (match_operand:DI 2 "arith_operand32" "d,P,N")))]
36+ [(set (match_operand:DI 0 "register_operand" "=d,d")
37+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
38+ (match_operand:DI 2 "arith_operand" "d,i")))]
39 ""
40 "@
41 add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
42- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
43- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
44+ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
45 [(set_attr "type" "darith")
46 (set_attr "mode" "DI")
47- (set_attr "length" "8,8,12")])
48+ (set_attr "length" "8,8")])
49
50 ;;----------------------------------------------------------------
51 ;; Subtraction
Andrew Geissler84ad7c52020-06-27 00:00:16 -050052@@ -549,7 +548,7 @@
Brad Bishop286d45c2018-10-02 15:21:57 -040053 (define_insn "subdi3"
54 [(set (match_operand:DI 0 "register_operand" "=&d")
55 (minus:DI (match_operand:DI 1 "register_operand" "d")
56- (match_operand:DI 2 "arith_operand32" "d")))]
57+ (match_operand:DI 2 "register_operand" "d")))]
58 ""
59 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
60 [(set_attr "type" "darith")
61--
Andrew Geisslera9ff2b32020-10-16 10:11:54 -0500622.17.1
Brad Bishop286d45c2018-10-02 15:21:57 -040063