| Andrew Geissler | 7e0e3c0 | 2022-02-25 20:34:39 +0000 | [diff] [blame] | 1 | From 26a7f6b1e4c5f715c03e59a623f0d620498b92cf Mon Sep 17 00:00:00 2001 |
| 2 | From: Khem Raj <raj.khem@gmail.com> |
| 3 | Date: Sun, 13 Feb 2022 21:11:31 -0800 |
| 4 | Subject: [PATCH] riscv: fix build with binutils 2.38 |
| 5 | |
| 6 | From version 2.38, binutils default to ISA spec version 20191213. This |
| 7 | means that the csr read/write (csrr*/csrw*) instructions and fence.i |
| 8 | instruction has separated from the `I` extension, become two standalone |
| 9 | extensions: Zicsr and Zifencei. |
| 10 | |
| 11 | The fix is to specify those extensions explicitely in -march. However as |
| 12 | older binutils version do not support this, we first need to detect |
| 13 | that. |
| 14 | |
| 15 | Fixes |
| 16 | arch/riscv/lib/cache.c: Assembler messages: |
| 17 | arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i' |
| 18 | |
| 19 | Upstream-Status: Submitted [] |
| 20 | Signed-off-by: Khem Raj <raj.khem@gmail.com> |
| 21 | --- |
| 22 | arch/riscv/Makefile | 7 ++++++- |
| 23 | 1 file changed, 6 insertions(+), 1 deletion(-) |
| 24 | |
| 25 | --- a/arch/riscv/Makefile |
| 26 | +++ b/arch/riscv/Makefile |
| 27 | @@ -28,7 +28,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) |
| 28 | CMODEL = medany |
| 29 | endif |
| 30 | |
| 31 | -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) -mabi=$(ABI) \ |
| 32 | +# Newer binutils versions default to ISA spec version 20191213 which moves some |
| 33 | +# instructions from the I extension to the Zicsr and Zifencei extensions. |
| 34 | +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)_zicsr_zifencei) |
| 35 | +zicsr_zifencei-$(toolchain-need-zicsr-zifencei) := _zicsr_zifencei |
| 36 | + |
| 37 | +ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)$(zicsr_zifencei-y) -mabi=$(ABI) \ |
| 38 | -mcmodel=$(CMODEL) |
| 39 | |
| 40 | PLATFORM_CPPFLAGS += $(ARCH_FLAGS) |