| Delphine CC Chiu | 4f0996c | 2024-01-11 17:44:43 +0800 | [diff] [blame] | 1 | #!/bin/bash -e |
| 2 | # shellcheck source=meta-facebook/meta-yosemite4/recipes-yosemite4/plat-tool/files/yosemite4-common-functions |
| 3 | source /usr/libexec/yosemite4-common-functions |
| 4 | |
| 5 | # probe devices behind mux for management board cpld |
| MarshallZhan | a365e4b | 2024-07-18 18:13:19 +0800 | [diff] [blame] | 6 | mgm_stage=$(get_product_version Management_Board) |
| Delphine CC Chiu | 4f0996c | 2024-01-11 17:44:43 +0800 | [diff] [blame] | 7 | |
| MarshallZhan | a365e4b | 2024-07-18 18:13:19 +0800 | [diff] [blame] | 8 | if [ -z "$mgm_stage" ]; then |
| 9 | echo "Failed to check management board fru info, all CPLD I/O expender are keeping default setting" |
| 10 | elif [ "$mgm_stage" = "DVT" ] || [ "$mgm_stage" = "EVT" ]; then |
| 11 | echo pca9506 "0x20" > /sys/bus/i2c/devices/i2c-13/new_device |
| 12 | echo pca9506 "0x21" > /sys/bus/i2c/devices/i2c-13/new_device |
| 13 | echo pca9506 "0x22" > /sys/bus/i2c/devices/i2c-13/new_device |
| 14 | echo pca9506 "0x23" > /sys/bus/i2c/devices/i2c-13/new_device |
| 15 | fi |
| Delphine CC Chiu | 4f0996c | 2024-01-11 17:44:43 +0800 | [diff] [blame] | 16 | |
| 17 | # set initial value for pca9555 i/o pins on medusa board |
| MarshallZhan | a365e4b | 2024-07-18 18:13:19 +0800 | [diff] [blame] | 18 | medusa_stage=$(get_product_version Medusa_Board) |
| 19 | |
| 20 | if [ -z "$medusa_stage" ]; then |
| Delphine CC Chiu | 4f0996c | 2024-01-11 17:44:43 +0800 | [diff] [blame] | 21 | echo "Failed to check medusa board fru info, all I/O pins are keeping default input" |
| MarshallZhan | a365e4b | 2024-07-18 18:13:19 +0800 | [diff] [blame] | 22 | elif [ "$medusa_stage" = "POC" ]; then |
| Delphine CC Chiu | 4f0996c | 2024-01-11 17:44:43 +0800 | [diff] [blame] | 23 | set_gpio P48V_OCP_GPIO1 0 |
| 24 | set_gpio P48V_OCP_GPIO2 0 |
| 25 | set_gpio P48V_OCP_GPIO3 0 |
| 26 | set_gpio RST_MUX_R_N 1 |
| 27 | set_gpio RST_LED_CONTROL_FAN_BOARD_0_N 1 |
| 28 | set_gpio RST_LED_CONTROL_FAN_BOARD_1_N 1 |
| 29 | set_gpio RST_IOEXP_FAN_BOARD_0_N 1 |
| 30 | set_gpio RST_IOEXP_FAN_BOARD_1_N 1 |
| 31 | set_gpio HSC_OCP_SLOT_ODD_GPIO3 1 |
| 32 | set_gpio HSC_OCP_SLOT_EVEN_GPIO1 1 |
| 33 | set_gpio MEDUSA_BOARD_REV_0 0 |
| 34 | set_gpio MEDUSA_BOARD_REV_1 0 |
| 35 | set_gpio MEDUSA_BOARD_REV_2 0 |
| 36 | set_gpio MEDUSA_BOARD_TYPE 0 |
| 37 | set_gpio DELTA_MODULE_TYPE 0 |
| 38 | set_gpio P12V_HSC_TYPE 0 |
| 39 | else |
| 40 | set_gpio P48V_OCP_GPIO1 0 |
| 41 | set_gpio P48V_OCP_GPIO2 0 |
| 42 | set_gpio P48V_OCP_GPIO3 0 |
| 43 | set_gpio RST_MUX_R_N 1 |
| 44 | set_gpio RST_LED_CONTROL_FAN_BOARD_0_N 1 |
| 45 | set_gpio RST_LED_CONTROL_FAN_BOARD_1_N 1 |
| 46 | set_gpio RST_IOEXP_FAN_BOARD_0_N 1 |
| 47 | set_gpio RST_IOEXP_FAN_BOARD_1_N 1 |
| 48 | set_gpio HSC_OCP_SLOT_ODD_GPIO1 0 |
| 49 | set_gpio HSC_OCP_SLOT_ODD_GPIO2 0 |
| 50 | set_gpio HSC_OCP_SLOT_ODD_GPIO3 0 |
| 51 | set_gpio HSC_OCP_SLOT_EVEN_GPIO1 0 |
| 52 | set_gpio HSC_OCP_SLOT_EVEN_GPIO2 0 |
| 53 | set_gpio HSC_OCP_SLOT_EVEN_GPIO3 0 |
| 54 | fi |
| 55 | exit 0 |