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gerrit.openbmc.org / openbmc / bmcweb / b4a7bfad0a3ded7a813bdb44a46383316dc49b24 / . / include / regs-video.h
blob: 379fa9cacbb023623b6ce49a454f621cbe33beae [file] [log] [blame]
Ed Tanous1ccd57c2017-03-21 13:15:58 -0700[diff] [blame]1#pragma once
2
3
4#define PASS 0
5#define TRUE 0
6#define FALSE 1
7#define FAIL 1
8#define FIX 0
9#define STEP 1
10#define SEQ_ADDRESS_REGISTER 0x3C4
11#define SEQ_DATA_REGISTER 0x3C5
12#define CRTC_ADDRESS_REGISTER 0x3D4
13#define CRTC_DATA_REGISTER 0x3D5
14#define DAC_INDEX_REGISTER 0x3C8
15#define DAC_DATA_REGISTER 0x3C9
16
17#define VIDEOBASE_OFFSET 0x1E700000
18#define KEY_CONTROL 0x00 + VIDEOBASE_OFFSET
19#define VIDEOENGINE_SEQUENCE_CONTROL 0x04 + VIDEOBASE_OFFSET
20#define VIDEOENGINE_PASS1_CONTROL 0x08 + VIDEOBASE_OFFSET
21#define VIDEOENGINE_MODEDETECTIONSETTING_H 0x0C + VIDEOBASE_OFFSET
22#define VIDEOENGINE_MODEDETECTIONSETTING_V 0x10 + VIDEOBASE_OFFSET
23#define SCALE_FACTOR_REGISTER 0x14 + VIDEOBASE_OFFSET
24#define SCALING_FILTER_PARAMETERS_1 0x18 + VIDEOBASE_OFFSET
25#define SCALING_FILTER_PARAMETERS_2 0x1C + VIDEOBASE_OFFSET
26#define SCALING_FILTER_PARAMETERS_3 0x20 + VIDEOBASE_OFFSET
27#define SCALING_FILTER_PARAMETERS_4 0x24 + VIDEOBASE_OFFSET
28#define MODEDETECTION_STATUS_READBACK 0x98 + VIDEOBASE_OFFSET
29#define VIDEOPROCESSING_CONTROL 0x2C + VIDEOBASE_OFFSET
30#define VIDEO_CAPTURE_WINDOW_SETTING 0x30 + VIDEOBASE_OFFSET
31#define VIDEO_COMPRESS_WINDOW_SETTING 0x34 + VIDEOBASE_OFFSET
32#define VIDEO_COMPRESS_READ 0x3C + VIDEOBASE_OFFSET
33#define VIDEO_IN_BUFFER_BASEADDRESS 0x44 + VIDEOBASE_OFFSET
34#define VIDEO_IN_BUFFER_OFFSET 0x48 + VIDEOBASE_OFFSET
35#define VIDEOPROCESS_BUFFER_BASEADDRESS 0x4C + VIDEOBASE_OFFSET
36#define VIDEOCOMPRESS_SOURCE_BUFFER_BASEADDRESS 0x44 + VIDEOBASE_OFFSET
37#define VIDEOPROCESS_OFFSET 0x48 + VIDEOBASE_OFFSET
38#define VIDEOPROCESS_REFERENCE_BUFFER_BASEADDRESS 0x4C + VIDEOBASE_OFFSET
39#define FLAG_BUFFER_BASEADDRESS 0x50 + VIDEOBASE_OFFSET
40#define VIDEO_COMPRESS_DESTINATION_BASEADDRESS 0x54 + VIDEOBASE_OFFSET
41#define STREAM_BUFFER_SIZE_REGISTER 0x58 + VIDEOBASE_OFFSET
42#define VIDEO_CAPTURE_BOUND_REGISTER 0x5C + VIDEOBASE_OFFSET
43#define VIDEO_COMPRESS_CONTROL 0x60 + VIDEOBASE_OFFSET
44#define VIDEO_QUANTIZATION_TABLE_REGISTER 0x64 + VIDEOBASE_OFFSET
45#define BLOCK_SHARPNESS_DETECTION_CONTROL 0x6C + VIDEOBASE_OFFSET
46#define POST_WRITE_BUFFER_DRAM_THRESHOLD 0x68 + VIDEOBASE_OFFSET
47#define DETECTION_STATUS_REGISTER 0x98 + VIDEOBASE_OFFSET
48#define H_DETECTION_STATUS 0x90 + VIDEOBASE_OFFSET
49#define V_DETECTION_STATUS 0x94 + VIDEOBASE_OFFSET
50#define VIDEO_CONTROL_REGISTER 0x300 + VIDEOBASE_OFFSET
51#define VIDEO_INTERRUPT_CONTROL 0x304 + VIDEOBASE_OFFSET
52#define VIDEO_INTERRUPT_STATUS 0x308 + VIDEOBASE_OFFSET
53#define MODE_DETECTION_REGISTER 0x30C + VIDEOBASE_OFFSET
54
55#define FRONT_BOUND_REGISTER 0x310 + VIDEOBASE_OFFSET
56#define END_BOUND_REGISTER 0x314 + VIDEOBASE_OFFSET
57#define CRC_1_REGISTER 0x320 + VIDEOBASE_OFFSET
58#define CRC_2_REGISTER 0x324 + VIDEOBASE_OFFSET
59#define REDUCE_BIT_REGISTER 0x328 + VIDEOBASE_OFFSET
60#define BIOS_SCRATCH_REGISTER 0x34C + VIDEOBASE_OFFSET
61#define COMPRESS_DATA_COUNT_REGISTER 0x70 + VIDEOBASE_OFFSET
62#define COMPRESS_BLOCK_COUNT_REGISTER 0x74 + VIDEOBASE_OFFSET
63#define VIDEO_SCRATCH_REGISTER_34C 0x34C + VIDEOBASE_OFFSET
64#define VIDEO_SCRATCH_REGISTER_35C 0x35C + VIDEOBASE_OFFSET
65#define RC4KEYS_REGISTER 0x400 + VIDEOBASE_OFFSET
66#define VQHUFFMAN_TABLE_REGISTER 0x300 + VIDEOBASE_OFFSET
67
68// Parameters
69#define SAMPLE_RATE 24000000.0
70#define MODEDETECTION_VERTICAL_STABLE_MAXIMUM 0x6
71#define MODEDETECTION_HORIZONTAL_STABLE_MAXIMUM 0x6
72#define MODEDETECTION_VERTICAL_STABLE_THRESHOLD 0x2
73#define MODEDETECTION_HORIZONTAL_STABLE_THRESHOLD 0x2
74#define HORIZONTAL_SCALING_FILTER_PARAMETERS_LOW 0xFFFFFFFF
75#define HORIZONTAL_SCALING_FILTER_PARAMETERS_HIGH 0xFFFFFFFF
76#define VIDEO_WRITE_BACK_BUFFER_THRESHOLD_LOW 0x08
77#define VIDEO_WRITE_BACK_BUFFER_THRESHOLD_HIGH 0x04
78#define VQ_Y_LEVELS 0x10
79#define VQ_UV_LEVELS 0x05
80#define EXTERNAL_VIDEO_HSYNC_POLARITY 0x01
81#define EXTERNAL_VIDEO_VSYNC_POLARITY 0x01
82#define VIDEO_SOURCE_FROM 0x01
83#define EXTERNAL_ANALOG_SOURCE 0x01
84#define USE_intERNAL_TIMING_GENERATOR 0x01
85#define WRITE_DATA_FORMAT 0x00
86#define SET_BCD_TO_WHOLE_FRAME 0x01
87#define ENABLE_VERTICAL_DOWN_SCALING 0x01
88#define BCD_TOLERENCE 0xFF
89#define BCD_START_BLOCK_XY 0x0
90#define BCD_END_BLOCK_XY 0x3FFF
91#define COLOR_DEPTH 16
92#define BLOCK_SHARPNESS_DETECTION_HIGH_THRESHOLD 0xFF
93#define BLOCK_SHARPNESS_DETECTION_LOE_THRESHOLD 0xFF
94#define BLOCK_SHARPNESS_DETECTION_HIGH_COUNTS_THRESHOLD 0x3F
95#define BLOCK_SHARPNESS_DETECTION_LOW_COUNTS_THRESHOLD 0x1F
96#define VQTABLE_AUTO_GENERATE_BY_HARDWARE 0x0
97#define VQTABLE_SELECTION 0x0
98#define JPEG_COMPRESS_ONLY 0x0
99#define DUAL_MODE_COMPRESS 0x1
100#define BSD_H_AND_V 0x0
101#define ENABLE_RC4_ENCRYPTION 0x1
102#define BSD_ENABLE_HIGH_THRESHOLD_CHECK 0x0
103#define VIDEO_PROCESS_AUTO_TRIGGER 0x0
104#define VIDEO_COMPRESS_AUTO_TRIGGER 0x0
105#define DIGITAL_SIGNAL 0x0
106#define ANALOG_SIGNAL 0x1
107
108/* AST_VIDEO_SCRATCH_35C 0x35C Video Scratch Remap Read Back */
109#define SCRATCH_VGA_PWR_STS_HSYNC (1 << 31)
110#define SCRATCH_VGA_PWR_STS_VSYNC (1 << 30)
111#define SCRATCH_VGA_ATTRIBTE_INDEX_BIT5 (1 << 29)
112#define SCRATCH_VGA_MASK_REG (1 << 28)
113#define SCRATCH_VGA_CRT_RST (1 << 27)
114#define SCRATCH_VGA_SCREEN_OFF (1 << 26)
115#define SCRATCH_VGA_RESET (1 << 25)
116#define SCRATCH_VGA_ENABLE (1 << 24)
117
118typedef struct _VIDEO_MODE_INFO {
119 unsigned short X;
120 unsigned short Y;
121 unsigned short ColorDepth;
122 unsigned short RefreshRate;
123 unsigned char ModeIndex;
124} VIDEO_MODE_INFO, *PVIDEO_MODE_INFO;
125
126typedef struct _VQ_INFO {
127 unsigned char Y[16];
128 unsigned char U[32];
129 unsigned char V[32];
130 unsigned char NumberOfY;
131 unsigned char NumberOfUV;
132 unsigned char NumberOfInner;
133 unsigned char NumberOfOuter;
134} VQ_INFO, *PVQ_INFO;
135
136typedef struct _HUFFMAN_TABLE {
137 unsigned long HuffmanCode[32];
138} HUFFMAN_TABLE, *PHUFFMAN_TABLE;
139
140typedef struct _FRAME_HEADER {
141 unsigned long StartCode; // 0
142 unsigned long FrameNumber; /// 4
143 unsigned short HSize; // 8
144 unsigned short VSize;
145 unsigned long Reserved[2]; // 12 13 14
146 unsigned char DirectMode; // 15
147 unsigned char CompressionMode; // 15
148 unsigned char JPEGScaleFactor; // 16
149 unsigned char Y_JPEGTableSelector; // 18 [[[[
150 unsigned char JPEGYUVTableMapping;
151 unsigned char SharpModeSelection;
152 unsigned char AdvanceTableSelector;
153 unsigned char AdvanceScaleFactor;
154 unsigned long NumberOfMB;
155 unsigned char VQ_YLevel;
156 unsigned char VQ_UVLevel;
157 VQ_INFO VQVectors;
158 unsigned char Mode420;
159 unsigned char Visual_Lossless;
160} FRAME_HEADER, *PFRAME_HEADER;
161
162typedef struct _INF_DATA {
163 unsigned char AST2500;
164 unsigned char Input_Signale; // 0: internel vga, 1, ext digital, 2, ext analog
165 unsigned char Trigger_Mode; // 0: capture, 1, ext digital, 2, ext analog
166 unsigned char DownScalingEnable;
167 unsigned char DifferentialSetting;
168 unsigned short AnalogDifferentialThreshold;
169 unsigned short DigitalDifferentialThreshold;
170 unsigned char AutoMode;
171 unsigned char DirectMode; // 0: force sync mode 1: auto direct mode
172 unsigned short DelayControl;
173 unsigned char VQMode;
174 unsigned char JPEG_FILE;
175} INF_DATA, *PINF_DATA;
176
177typedef struct _COMPRESS_DATA {
178 unsigned long SourceFrameSize;
179 unsigned long CompressSize;
180 unsigned long HDebug;
181 unsigned long VDebug;
182} COMPRESS_DATA, *PCOMPRESS_DATA;
183
184// VIDEO Engine Info
185typedef struct _VIDEO_ENGINE_INFO {
186 INF_DATA INFData;
187 VIDEO_MODE_INFO SourceModeInfo;
188 VIDEO_MODE_INFO DestinationModeInfo;
189 VQ_INFO VQInfo;
190 FRAME_HEADER FrameHeader;
191 COMPRESS_DATA CompressData;
192 unsigned char ChipVersion;
193 unsigned char NoSignal;
194} VIDEO_ENGINE_INFO, *PVIDEO_ENGINE_INFO;
195
196typedef struct {
197 unsigned short HorizontalActive;
198 unsigned short VerticalActive;
199 unsigned short RefreshRate;
200 unsigned char ADCIndex1;
201 unsigned char ADCIndex2;
202 unsigned char ADCIndex3;
203 unsigned char ADCIndex5;
204 unsigned char ADCIndex6;
205 unsigned char ADCIndex7;
206 unsigned char ADCIndex8;
207 unsigned char ADCIndex9;
208 unsigned char ADCIndexA;
209 unsigned char ADCIndexF;
210 unsigned char ADCIndex15;
211 int HorizontalShift;
212 int VerticalShift;
213} ADC_MODE;
214
215typedef struct {
216 unsigned short HorizontalTotal;
217 unsigned short VerticalTotal;
218 unsigned short HorizontalActive;
219 unsigned short VerticalActive;
220 unsigned char RefreshRate;
221 double HorizontalFrequency;
222 unsigned short HSyncTime;
223 unsigned short HBackPorch;
224 unsigned short VSyncTime;
225 unsigned short VBackPorch;
226 unsigned short HLeftBorder;
227 unsigned short HRightBorder;
228 unsigned short VBottomBorder;
229 unsigned short VTopBorder;
230 ADC_MODE AdcMode;
231} VESA_MODE;
232
233
234
235typedef struct {
236 unsigned short HorizontalActive;
237 unsigned short VerticalActive;
238 unsigned short RefreshRateIndex;
239 double PixelClock;
240} INTERNAL_MODE;
241
242typedef struct _TRANSFER_HEADER {
243 unsigned long Data_Length;
244 unsigned long Blocks_Changed;
245 unsigned short User_Width;
246 unsigned short User_Height;
247 unsigned char Frist_frame; // 1: first frame
248 unsigned char Compress_type; // 0:aspeed mode, 1:jpeg mode
249 unsigned char Trigger_mode; // 0:capture, 1: compression, 2: buffer
250 unsigned char Data_format; // 0:DCT, 1:DCTwVQ2 color, 2:DCTwVQ4 color
251 unsigned char RC4_Enable;
252 unsigned char RC4_Reset; // no use
253 unsigned char Y_Table;
254 unsigned char UV_Table;
255 unsigned char Mode_420;
256 unsigned char Direct_Mode;
257 unsigned char VQ_Mode;
258 unsigned char Disable_VGA;
259 unsigned char Differential_Enable;
260 unsigned char Auto_Mode;
261 unsigned char VGA_Status;
262 unsigned char RC4State;
263 unsigned char Advance_Table;
264} TRANSFER_HEADER, *PTRANSFER_HEADER;