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gerrit.openbmc.org / openbmc / entity-manager / 621fdf92b5c600ae0f8e78b0717ec1842cd1c577 / . / configurations / meta / harma_mb.json
blob: 931d9f8cc489af2cc047627ee423198c79b9db82 [file] [log] [blame]
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1[
2 {
3 "Exposes": [
4 {
5 "BridgeGpio": [
6 {
7 "Name": "rtc-battery-voltage-read-enable",
8 "Polarity": "High",
9 "SetupTime": 1
10 }
11 ],
12 "Index": 7,
13 "Name": "MB_P3V_BAT_VOLT_V",
14 "ScaleFactor": 0.333333333,
15 "Thresholds": [
16 {
17 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]18 "Hysteresis": 0.04,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]19 "Name": "lower critical",
20 "Severity": 1,
21 "Value": 2.0
22 },
23 {
24 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]25 "Hysteresis": 0.068,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]26 "Name": "upper critical",
27 "Severity": 1,
28 "Value": 3.4
29 }
30 ],
31 "Type": "ADC"
32 },
33 {
34 "Address": "0x1d",
35 "Bus": 29,
36 "Labels": [
37 "in1",
38 "in2",
39 "in3",
40 "in4",
41 "in5"
42 ],
43 "Name": "MB_ADC0",
44 "Thresholds": [
45 {
46 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]47 "Hysteresis": 0.0209,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]48 "Label": "in1",
49 "Name": "lower critical",
50 "Severity": 1,
51 "Value": 1.045
52 },
53 {
54 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]55 "Hysteresis": 0.0231,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]56 "Label": "in1",
57 "Name": "upper critical",
58 "Severity": 1,
59 "Value": 1.155
60 },
61 {
62 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]63 "Hysteresis": 0.0627,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]64 "Label": "in2",
65 "Name": "lower critical",
66 "Severity": 1,
67 "Value": 3.135
68 },
69 {
70 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]71 "Hysteresis": 0.068,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]72 "Label": "in2",
73 "Name": "upper critical",
74 "Severity": 1,
75 "Value": 3.4
76 },
77 {
78 "Direction": "less than",
Daniel Hsu71e50072025-02-24 10:33:48 +0800[diff] [blame]79 "Hysteresis": 0,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]80 "Label": "in3",
81 "Name": "lower critical",
82 "Severity": 1,
83 "Value": 1.76
84 },
85 {
86 "Direction": "greater than",
Daniel Hsu71e50072025-02-24 10:33:48 +0800[diff] [blame]87 "Hysteresis": 0,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]88 "Label": "in3",
89 "Name": "upper critical",
90 "Severity": 1,
91 "Value": 1.84
92 },
93 {
94 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]95 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]96 "Label": "in4",
97 "Name": "lower critical",
98 "Severity": 1,
99 "Value": 10.8
100 },
101 {
102 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]103 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]104 "Label": "in4",
105 "Name": "upper critical",
106 "Severity": 1,
107 "Value": 13.2
108 },
109 {
110 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]111 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]112 "Label": "in5",
113 "Name": "lower critical",
114 "Severity": 1,
115 "Value": 10.8
116 },
117 {
118 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]119 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]120 "Label": "in5",
121 "Name": "upper critical",
122 "Severity": 1,
123 "Value": 13.2
124 }
125 ],
126 "Type": "ADC128D818",
127 "in1_Name": "MB_PVDD11_S3_VOLT_V",
128 "in1_PowerState": "On",
129 "in2_Name": "MB_P3V3_STBY_VOLT_V",
130 "in2_Scale": 500,
131 "in3_Name": "MB_PVDD18_S5_VOLT_V",
132 "in4_Name": "MB_P12V_AUX_VOLT_V",
133 "in4_Scale": 151.515151515,
134 "in5_Name": "MB_P12V_STBY_VOLT_V",
135 "in5_Scale": 151.515151515
136 },
137 {
138 "Address": "0x1f",
139 "Bus": 29,
140 "Labels": [
141 "in0",
142 "in1",
143 "in2",
144 "in3",
145 "in4",
146 "in5"
147 ],
148 "Name": "MB_ADC1",
149 "Thresholds": [
150 {
151 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]152 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]153 "Label": "in0",
154 "Name": "lower critical",
155 "Severity": 1,
156 "Value": 10.8
157 },
158 {
159 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]160 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]161 "Label": "in0",
162 "Name": "upper critical",
163 "Severity": 1,
164 "Value": 13.2
165 },
166 {
167 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]168 "Hysteresis": 0.095,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]169 "Label": "in1",
170 "Name": "lower critical",
171 "Severity": 1,
172 "Value": 4.75
173 },
174 {
175 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]176 "Hysteresis": 0.105,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]177 "Label": "in1",
178 "Name": "upper critical",
179 "Severity": 1,
180 "Value": 5.25
181 },
182 {
183 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]184 "Hysteresis": 0.0626,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]185 "Label": "in2",
186 "Name": "lower critical",
187 "Severity": 1,
188 "Value": 3.13
189 },
190 {
191 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]192 "Hysteresis": 0.0692,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]193 "Label": "in2",
194 "Name": "upper critical",
195 "Severity": 1,
196 "Value": 3.46
197 },
198 {
199 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]200 "Hysteresis": 0.0342,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]201 "Label": "in3",
202 "Name": "lower critical",
203 "Severity": 1,
204 "Value": 1.71
205 },
206 {
207 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]208 "Hysteresis": 0.0378,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]209 "Label": "in3",
210 "Name": "upper critical",
211 "Severity": 1,
212 "Value": 1.89
213 },
214 {
215 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]216 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]217 "Label": "in4",
218 "Name": "lower critical",
219 "Severity": 1,
220 "Value": 10.8
221 },
222 {
223 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]224 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]225 "Label": "in4",
226 "Name": "upper critical",
227 "Severity": 1,
228 "Value": 13.2
229 },
230 {
231 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]232 "Hysteresis": 0.0342,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]233 "Label": "in5",
234 "Name": "lower critical",
235 "Severity": 1,
236 "Value": 1.71
237 },
238 {
239 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]240 "Hysteresis": 0.0378,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]241 "Label": "in5",
242 "Name": "upper critical",
243 "Severity": 1,
244 "Value": 1.89
245 }
246 ],
247 "Type": "ADC128D818",
248 "in0_Name": "MB_P12V_MEM0_VOLT_V",
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]249 "in0_Scale": 151.515151515,
250 "in1_Name": "MB_P5V_STBY_VOLT_V",
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]251 "in1_Scale": 281.29395218,
252 "in2_Name": "MB_PVDD33_S5_VOLT_V",
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]253 "in2_Scale": 500,
254 "in3_Name": "MB_P1V8_STBY_VOLT_V",
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]255 "in4_Name": "MB_P12V_MEM1_VOLT_V",
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]256 "in4_Scale": 151.515151515,
257 "in5_Name": "MB_P1V8_CPU_RT_VOLT_V",
258 "in5_PowerState": "On"
259 },
260 {
261 "Address": "$address",
262 "Bus": "$bus",
263 "Name": "MB FRU",
264 "Type": "EEPROM"
265 },
266 {
267 "Address": "0x45",
268 "Bus": 23,
269 "Labels": [
270 "in1",
271 "curr1",
272 "power1"
273 ],
274 "Name": "MB_E1S0",
275 "PowerState": "On",
276 "Thresholds": [
277 {
278 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]279 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]280 "Label": "in1",
281 "Name": "lower critical",
282 "Severity": 1,
283 "Value": 10.8
284 },
285 {
286 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]287 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]288 "Label": "in1",
289 "Name": "upper critical",
290 "Severity": 1,
291 "Value": 13.2
292 },
293 {
294 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]295 "Hysteresis": 0.042,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]296 "Label": "curr1",
297 "Name": "upper critical",
298 "Severity": 1,
299 "Value": 2.1
300 },
301 {
302 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]303 "Hysteresis": 0.5,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]304 "Label": "power1",
305 "Name": "upper critical",
306 "Severity": 1,
307 "Value": 25.0
308 }
309 ],
310 "Type": "INA230",
311 "curr1_Name": "MB_E1S0_P12V_CURR_A",
312 "in1_Name": "MB_E1S0_P12V_VOLT_V",
313 "power1_Name": "MB_E1S0_P12V_PWR_W"
314 },
315 {
316 "Address": "0x45",
317 "Bus": 22,
318 "Labels": [
319 "in1",
320 "curr1",
321 "power1"
322 ],
323 "Name": "MB_E1S1",
324 "PowerState": "On",
325 "Thresholds": [
326 {
327 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]328 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]329 "Label": "in1",
330 "Name": "lower critical",
331 "Severity": 1,
332 "Value": 10.8
333 },
334 {
335 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]336 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]337 "Label": "in1",
338 "Name": "upper critical",
339 "Severity": 1,
340 "Value": 13.2
341 },
342 {
343 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]344 "Hysteresis": 0.042,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]345 "Label": "curr1",
346 "Name": "upper critical",
347 "Severity": 1,
348 "Value": 2.1
349 },
350 {
351 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]352 "Hysteresis": 0.5,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]353 "Label": "power1",
354 "Name": "upper critical",
355 "Severity": 1,
356 "Value": 25.0
357 }
358 ],
359 "Type": "INA230",
360 "curr1_Name": "MB_E1S1_P12V_CURR_A",
361 "in1_Name": "MB_E1S1_P12V_VOLT_V",
362 "power1_Name": "MB_E1S1_P12V_PWR_W"
363 },
364 {
365 "Address": "0x45",
366 "Bus": 29,
367 "Labels": [
368 "in1",
369 "curr1",
370 "power1"
371 ],
372 "Name": "NIC_MEZZ",
373 "Thresholds": [
374 {
375 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]376 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]377 "Label": "in1",
378 "Name": "lower critical",
379 "Severity": 1,
380 "Value": 10.8
381 },
382 {
383 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]384 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]385 "Label": "in1",
386 "Name": "upper critical",
387 "Severity": 1,
388 "Value": 13.2
389 },
390 {
391 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]392 "Hysteresis": 0.114,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]393 "Label": "curr1",
394 "Name": "upper critical",
395 "Severity": 1,
396 "Value": 5.7
397 },
398 {
399 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]400 "Hysteresis": 1.5,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]401 "Label": "power1",
402 "Name": "upper critical",
403 "Severity": 1,
404 "Value": 75.0
405 }
406 ],
407 "Type": "INA230",
408 "curr1_Name": "NIC_MEZZ_P12V_CURR_A",
409 "in1_Name": "NIC_MEZZ_P12V_VOLT_V",
410 "power1_Name": "NIC_MEZZ_P12V_PWR_W"
411 },
412 {
413 "Address": "0x63",
414 "Bus": 28,
415 "Labels": [
416 "iout1",
417 "vout1",
418 "pout1",
419 "temp1"
420 ],
421 "Name": "MB_VR_CPU_PVDD11",
422 "PowerState": "On",
423 "Thresholds": [
424 {
425 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]426 "Hysteresis": 1.18,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]427 "Label": "iout1",
428 "Name": "upper critical",
429 "Severity": 1,
430 "Value": 59.0
431 },
432 {
433 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]434 "Hysteresis": 0.0209,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]435 "Label": "vout1",
436 "Name": "lower critical",
437 "Severity": 1,
438 "Value": 1.045
439 },
440 {
441 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]442 "Hysteresis": 0.0231,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]443 "Label": "vout1",
444 "Name": "upper critical",
445 "Severity": 1,
446 "Value": 1.155
447 },
448 {
449 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]450 "Hysteresis": 1.3,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]451 "Label": "pout1",
452 "Name": "upper critical",
453 "Severity": 1,
454 "Value": 65.0
455 },
456 {
457 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]458 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]459 "Label": "temp1",
460 "Name": "lower critical",
461 "Severity": 1,
462 "Value": -1.0
463 },
464 {
465 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]466 "Hysteresis": 2.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]467 "Label": "temp1",
468 "Name": "upper critical",
469 "Severity": 1,
470 "Value": 105.0
471 }
472 ],
473 "Type": "ISL69260",
474 "iout1_Name": "MB_VR_CPU_PVDD11_CURR_A",
475 "pout1_Name": "MB_VR_CPU_PVDD11_PWR_W",
476 "temp1_Name": "MB_VR_CPU_PVDD11_TEMP_C",
477 "vout1_Name": "MB_VR_CPU_PVDD11_VOLT_V"
478 },
479 {
480 "Address": "0x61",
481 "Bus": 28,
482 "Labels": [
483 "iout1",
484 "iout2",
485 "vout1",
486 "vout2",
487 "pout1",
488 "pout2",
489 "temp1",
490 "temp2"
491 ],
492 "Name": "MB_VR_CPU_VCORE0_SOC",
493 "PowerState": "On",
494 "Thresholds": [
495 {
496 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]497 "Hysteresis": 6.36,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]498 "Label": "iout1",
499 "Name": "upper critical",
500 "Severity": 1,
501 "Value": 318.0
502 },
503 {
504 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]505 "Hysteresis": 4.2,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]506 "Label": "iout2",
507 "Name": "upper critical",
508 "Severity": 1,
509 "Value": 210.0
510 },
511 {
512 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]513 "Hysteresis": 0.0106,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]514 "Label": "vout1",
515 "Name": "lower critical",
516 "Severity": 1,
517 "Value": 0.53
518 },
519 {
520 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]521 "Hysteresis": 0.0304,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]522 "Label": "vout1",
523 "Name": "upper critical",
524 "Severity": 1,
525 "Value": 1.52
526 },
527 {
528 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]529 "Hysteresis": 0.0146,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]530 "Label": "vout2",
531 "Name": "lower critical",
532 "Severity": 1,
533 "Value": 0.73
534 },
535 {
536 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]537 "Hysteresis": 0.0244,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]538 "Label": "vout2",
539 "Name": "upper critical",
540 "Severity": 1,
541 "Value": 1.22
542 },
543 {
544 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]545 "Hysteresis": 3.5,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]546 "Label": "pout1",
547 "Name": "upper critical",
548 "Severity": 1,
549 "Value": 175.0
550 },
551 {
552 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]553 "Hysteresis": 2.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]554 "Label": "pout2",
555 "Name": "upper critical",
556 "Severity": 1,
557 "Value": 105.0
558 },
559 {
560 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]561 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]562 "Label": "temp1",
563 "Name": "lower critical",
564 "Severity": 1,
565 "Value": -1.0
566 },
567 {
568 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]569 "Hysteresis": 2.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]570 "Label": "temp1",
571 "Name": "upper critical",
572 "Severity": 1,
573 "Value": 105.0
574 },
575 {
576 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]577 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]578 "Label": "temp2",
579 "Name": "lower critical",
580 "Severity": 1,
581 "Value": -1.0
582 },
583 {
584 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]585 "Hysteresis": 2.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]586 "Label": "temp2",
587 "Name": "upper critical",
588 "Severity": 1,
589 "Value": 105.0
590 }
591 ],
592 "Type": "ISL69260",
593 "iout1_Name": "MB_VR_CPU_VCORE0_CURR_A",
594 "iout2_Name": "MB_VR_CPU_SOC_CURR_A",
595 "pout1_Name": "MB_VR_CPU_VCORE0_PWR_W",
596 "pout2_Name": "MB_VR_CPU_SOC_PWR_W",
597 "temp1_Name": "MB_VR_CPU_VCORE0_TEMP_C",
598 "temp2_Name": "MB_VR_CPU_SOC_TEMP_C",
599 "vout1_Name": "MB_VR_CPU_VCORE0_VOLT_V",
600 "vout2_Name": "MB_VR_CPU_SOC_VOLT_V"
601 },
602 {
603 "Address": "0x62",
604 "Bus": 28,
605 "Labels": [
606 "iout1",
607 "iout2",
608 "vout1",
609 "vout2",
610 "pout1",
611 "pout2",
612 "temp1",
613 "temp2"
614 ],
615 "Name": "MB_VR_CPU_VCORE1_PDDIO",
616 "PowerState": "On",
617 "Thresholds": [
618 {
619 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]620 "Hysteresis": 6.36,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]621 "Label": "iout1",
622 "Name": "upper critical",
623 "Severity": 1,
624 "Value": 318.0
625 },
626 {
627 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]628 "Hysteresis": 2.66,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]629 "Label": "iout2",
630 "Name": "upper critical",
631 "Severity": 1,
632 "Value": 133.0
633 },
634 {
635 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]636 "Hysteresis": 0.0106,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]637 "Label": "vout1",
638 "Name": "lower critical",
639 "Severity": 1,
640 "Value": 0.53
641 },
642 {
643 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]644 "Hysteresis": 0.0304,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]645 "Label": "vout1",
646 "Name": "upper critical",
647 "Severity": 1,
648 "Value": 1.52
649 },
650 {
651 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]652 "Hysteresis": 0.0176,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]653 "Label": "vout2",
654 "Name": "lower critical",
655 "Severity": 1,
656 "Value": 0.88
657 },
658 {
659 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]660 "Hysteresis": 0.0244,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]661 "Label": "vout2",
662 "Name": "upper critical",
663 "Severity": 1,
664 "Value": 1.22
665 },
666 {
667 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]668 "Hysteresis": 3.5,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]669 "Label": "pout1",
670 "Name": "upper critical",
671 "Severity": 1,
672 "Value": 175.0
673 },
674 {
675 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]676 "Hysteresis": 2.4,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]677 "Label": "pout2",
678 "Name": "upper critical",
679 "Severity": 1,
680 "Value": 120.0
681 },
682 {
683 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]684 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]685 "Label": "temp1",
686 "Name": "lower critical",
687 "Severity": 1,
688 "Value": -1.0
689 },
690 {
691 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]692 "Hysteresis": 2.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]693 "Label": "temp1",
694 "Name": "upper critical",
695 "Severity": 1,
696 "Value": 105.0
697 },
698 {
699 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]700 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]701 "Label": "temp2",
702 "Name": "lower critical",
703 "Severity": 1,
704 "Value": -1.0
705 },
706 {
707 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]708 "Hysteresis": 2.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]709 "Label": "temp2",
710 "Name": "upper critical",
711 "Severity": 1,
712 "Value": 105.0
713 }
714 ],
715 "Type": "ISL69260",
716 "iout1_Name": "MB_VR_CPU_VCORE1_CURR_A",
717 "iout2_Name": "MB_VR_CPU_PDDIO_CURR_A",
718 "pout1_Name": "MB_VR_CPU_VCORE1_PWR_W",
719 "pout2_Name": "MB_VR_CPU_PDDIO_PWR_W",
720 "temp1_Name": "MB_VR_CPU_VCORE1_TEMP_C",
721 "temp2_Name": "MB_VR_CPU_PDDIO_TEMP_C",
722 "vout1_Name": "MB_VR_CPU_VCORE1_VOLT_V",
723 "vout2_Name": "MB_VR_CPU_PDDIO_VOLT_V"
724 },
725 {
726 "Address": "0x20",
727 "Bus": 28,
728 "Labels": [
729 "iout1",
730 "vin",
731 "vout1",
732 "pin",
733 "temp1"
734 ],
735 "Name": "MB_HSC",
736 "Thresholds": [
737 {
738 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]739 "Hysteresis": 1.44,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]740 "Label": "iout1",
741 "Name": "upper critical",
742 "Severity": 1,
743 "Value": 72.0
744 },
745 {
746 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]747 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]748 "Label": "vin",
749 "Name": "lower critical",
750 "Severity": 1,
751 "Value": 10.8
752 },
753 {
754 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]755 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]756 "Label": "vin",
757 "Name": "upper critical",
758 "Severity": 1,
759 "Value": 13.2
760 },
761 {
762 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]763 "Hysteresis": 0.216,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]764 "Label": "vout1",
765 "Name": "lower critical",
766 "Severity": 1,
767 "Value": 10.8
768 },
769 {
770 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]771 "Hysteresis": 0.264,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]772 "Label": "vout1",
773 "Name": "upper critical",
774 "Severity": 1,
775 "Value": 13.2
776 },
777 {
778 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]779 "Hysteresis": 19.0,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]780 "Label": "pin",
781 "Name": "upper critical",
782 "Severity": 1,
783 "Value": 950.0
784 },
785 {
786 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]787 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]788 "Label": "temp1",
789 "Name": "upper critical",
790 "Severity": 1,
791 "Value": 80.0
792 }
793 ],
794 "Type": "MP5990",
795 "iout1_Name": "MB_HSC_CURR_A",
796 "pin_Name": "MB_HSC_PWR_W",
797 "temp1_Name": "MB_HSC_TEMP_C",
798 "vin_Name": "MB_HSC_VIN_VOLT_V",
799 "vout1_Name": "MB_HSC_VOUT_VOLT_V"
800 },
801 {
802 "Address": "0x6a",
803 "Bus": 23,
804 "Name": "MB_E1S0_TEMP_C",
805 "PowerState": "On",
806 "Thresholds": [
807 {
808 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]809 "Hysteresis": 0.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]810 "Name": "lower critical",
811 "Severity": 1,
812 "Value": 5.0
813 },
814 {
815 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]816 "Hysteresis": 1.4,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]817 "Name": "upper critical",
818 "Severity": 1,
819 "Value": 70.0
820 }
821 ],
822 "Type": "NVME1000"
823 },
824 {
825 "Address": "0x6a",
826 "Bus": 22,
827 "Name": "MB_E1S1_TEMP_C",
828 "PowerState": "On",
829 "Thresholds": [
830 {
831 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]832 "Hysteresis": 0.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]833 "Name": "lower critical",
834 "Severity": 1,
835 "Value": 5.0
836 },
837 {
838 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]839 "Hysteresis": 1.4,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]840 "Name": "upper critical",
841 "Severity": 1,
842 "Value": 70.0
843 }
844 ],
845 "Type": "NVME1000"
846 },
847 {
848 "Address": "0x24",
849 "Bus": 12,
850 "Name": "MB_RETIMER0_TEMP_C",
851 "PowerState": "On",
852 "Thresholds": [
853 {
854 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]855 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]856 "Name": "lower critical",
857 "Severity": 1,
858 "Value": -1.0
859 },
860 {
861 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]862 "Hysteresis": 2.0,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]863 "Name": "upper critical",
864 "Severity": 1,
865 "Value": 100.0
866 }
867 ],
868 "Type": "PT5161L"
869 },
870 {
871 "Address": "0x24",
872 "Bus": 21,
873 "Name": "MB_RETIMER1_TEMP_C",
874 "PowerState": "On",
875 "Thresholds": [
876 {
877 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]878 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]879 "Name": "lower critical",
880 "Severity": 1,
881 "Value": -1.0
882 },
883 {
884 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]885 "Hysteresis": 2.0,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]886 "Name": "upper critical",
887 "Severity": 1,
888 "Value": 100.0
889 }
890 ],
891 "Type": "PT5161L"
892 },
893 {
894 "Address": "0x3C",
895 "Bus": 7,
896 "Labels": [
897 "power1",
898 "power2",
899 "power3",
900 "power4",
901 "power5",
902 "power6",
903 "power7",
904 "power8",
905 "power9",
906 "temp1",
907 "temp2",
908 "temp3",
909 "temp4",
910 "temp5",
911 "temp6",
912 "temp7",
913 "temp8"
914 ],
915 "Name": "SBRMI",
916 "PowerState": "BiosPost",
917 "Thresholds": [
918 {
919 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]920 "Hysteresis": 12.8,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]921 "Label": "power1",
922 "Name": "upper critical",
923 "Severity": 1,
924 "Value": 640.0
925 },
926 {
927 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]928 "Hysteresis": 0.28,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]929 "Label": "power2",
930 "Name": "upper critical",
931 "Severity": 1,
932 "Value": 14.0
933 },
934 {
935 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]936 "Hysteresis": 0.28,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]937 "Label": "power3",
938 "Name": "upper critical",
939 "Severity": 1,
940 "Value": 14.0
941 },
942 {
943 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]944 "Hysteresis": 0.28,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]945 "Label": "power4",
946 "Name": "upper critical",
947 "Severity": 1,
948 "Value": 14.0
949 },
950 {
951 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]952 "Hysteresis": 0.28,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]953 "Label": "power5",
954 "Name": "upper critical",
955 "Severity": 1,
956 "Value": 14.0
957 },
958 {
959 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]960 "Hysteresis": 0.28,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]961 "Label": "power6",
962 "Name": "upper critical",
963 "Severity": 1,
964 "Value": 14.0
965 },
966 {
967 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]968 "Hysteresis": 0.28,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]969 "Label": "power7",
970 "Name": "upper critical",
971 "Severity": 1,
972 "Value": 14.0
973 },
974 {
975 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]976 "Hysteresis": 0.28,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]977 "Label": "power8",
978 "Name": "upper critical",
979 "Severity": 1,
980 "Value": 14.0
981 },
982 {
983 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]984 "Hysteresis": 0.28,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]985 "Label": "power9",
986 "Name": "upper critical",
987 "Severity": 1,
988 "Value": 14.0
989 },
990 {
991 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]992 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]993 "Label": "temp1",
994 "Name": "lower critical",
995 "Severity": 1,
996 "Value": -1.0
997 },
998 {
999 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1000 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1001 "Label": "temp1",
1002 "Name": "upper critical",
1003 "Severity": 1,
1004 "Value": 80.0
1005 },
1006 {
1007 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1008 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1009 "Label": "temp2",
1010 "Name": "lower critical",
1011 "Severity": 1,
1012 "Value": -1.0
1013 },
1014 {
1015 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1016 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1017 "Label": "temp2",
1018 "Name": "upper critical",
1019 "Severity": 1,
1020 "Value": 80.0
1021 },
1022 {
1023 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1024 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1025 "Label": "temp3",
1026 "Name": "lower critical",
1027 "Severity": 1,
1028 "Value": -1.0
1029 },
1030 {
1031 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1032 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1033 "Label": "temp3",
1034 "Name": "upper critical",
1035 "Severity": 1,
1036 "Value": 80.0
1037 },
1038 {
1039 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1040 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1041 "Label": "temp4",
1042 "Name": "lower critical",
1043 "Severity": 1,
1044 "Value": -1.0
1045 },
1046 {
1047 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1048 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1049 "Label": "temp4",
1050 "Name": "upper critical",
1051 "Severity": 1,
1052 "Value": 80.0
1053 },
1054 {
1055 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1056 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1057 "Label": "temp5",
1058 "Name": "lower critical",
1059 "Severity": 1,
1060 "Value": -1.0
1061 },
1062 {
1063 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1064 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1065 "Label": "temp5",
1066 "Name": "upper critical",
1067 "Severity": 1,
1068 "Value": 80.0
1069 },
1070 {
1071 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1072 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1073 "Label": "temp6",
1074 "Name": "lower critical",
1075 "Severity": 1,
1076 "Value": -1.0
1077 },
1078 {
1079 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1080 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1081 "Label": "temp6",
1082 "Name": "upper critical",
1083 "Severity": 1,
1084 "Value": 80.0
1085 },
1086 {
1087 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1088 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1089 "Label": "temp7",
1090 "Name": "lower critical",
1091 "Severity": 1,
1092 "Value": -1.0
1093 },
1094 {
1095 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1096 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1097 "Label": "temp7",
1098 "Name": "upper critical",
1099 "Severity": 1,
1100 "Value": 80.0
1101 },
1102 {
1103 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1104 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1105 "Label": "temp8",
1106 "Name": "lower critical",
1107 "Severity": 1,
1108 "Value": -1.0
1109 },
1110 {
1111 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1112 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1113 "Label": "temp8",
1114 "Name": "upper critical",
1115 "Severity": 1,
1116 "Value": 80.0
1117 }
1118 ],
1119 "Type": "SBRMI",
1120 "power1_Name": "MB_CPU_PKG_PWR_W",
1121 "power2_Name": "MB_DIMM_A0_PWR_W",
1122 "power3_Name": "MB_DIMM_A1_PWR_W",
1123 "power4_Name": "MB_DIMM_A2_PWR_W",
1124 "power5_Name": "MB_DIMM_A4_PWR_W",
1125 "power6_Name": "MB_DIMM_A6_PWR_W",
1126 "power7_Name": "MB_DIMM_A7_PWR_W",
1127 "power8_Name": "MB_DIMM_A8_PWR_W",
1128 "power9_Name": "MB_DIMM_A10_PWR_W",
1129 "temp1_Name": "MB_DIMM_A0_TEMP_C",
1130 "temp2_Name": "MB_DIMM_A1_TEMP_C",
1131 "temp3_Name": "MB_DIMM_A2_TEMP_C",
1132 "temp4_Name": "MB_DIMM_A4_TEMP_C",
1133 "temp5_Name": "MB_DIMM_A6_TEMP_C",
1134 "temp6_Name": "MB_DIMM_A7_TEMP_C",
1135 "temp7_Name": "MB_DIMM_A8_TEMP_C",
1136 "temp8_Name": "MB_DIMM_A10_TEMP_C"
1137 },
1138 {
1139 "Address": "0x4C",
1140 "Bus": 7,
1141 "Name": "MB_CPU_TEMP_C",
1142 "PowerState": "BiosPost",
1143 "Thresholds": [
1144 {
1145 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1146 "Hysteresis": 0.02,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1147 "Name": "lower critical",
1148 "Severity": 1,
1149 "Value": -1.0
1150 },
1151 {
1152 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1153 "Hysteresis": 1.9,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1154 "Name": "upper critical",
1155 "Severity": 1,
1156 "Value": 95.0
1157 }
1158 ],
1159 "Type": "SBTSI"
1160 },
1161 {
1162 "Address": "0x49",
1163 "Bus": 29,
1164 "Name": "MB_OUTLET_TEMP_C",
1165 "Thresholds": [
1166 {
1167 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1168 "Hysteresis": 0.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1169 "Name": "lower critical",
1170 "Severity": 1,
1171 "Value": 5.0
1172 },
1173 {
1174 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1175 "Hysteresis": 1.6,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1176 "Name": "upper critical",
1177 "Severity": 1,
1178 "Value": 80.0
1179 }
1180 ],
1181 "Type": "TMP75"
1182 },
1183 {
1184 "Address": "0x4A",
1185 "Bus": 29,
1186 "Name": "MB_INLET_TEMP_C",
1187 "Thresholds": [
1188 {
1189 "Direction": "less than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1190 "Hysteresis": 0.1,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1191 "Name": "lower critical",
1192 "Severity": 1,
1193 "Value": 5.0
1194 },
1195 {
1196 "Direction": "greater than",
Daniel Hsu79cd8b12024-12-12 14:49:04 +0800[diff] [blame]1197 "Hysteresis": 1.2,
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1198 "Name": "upper critical",
1199 "Severity": 1,
1200 "Value": 60.0
1201 }
1202 ],
1203 "Type": "TMP75"
1204 }
1205 ],
1206 "Name": "Harma MB",
1207 "Probe": [
1208 "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'Harma MB EVT', 'BOARD_PART_NUMBER': '3BF0MMA0040'})",
1209 "OR",
1210 "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'Harma MB EVT', 'BOARD_PART_NUMBER': '3BF0MMA0080'})",
1211 "OR",
1212 "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'Harma MB ', 'BOARD_INFO_AM4': 'vr-isl'})"
1213 ],
1214 "Type": "Board",
1215 "xyz.openbmc_project.Inventory.Decorator.Asset": {
1216 "BuildDate": "$BOARD_MANUFACTURE_DATE",
1217 "Manufacturer": "$BOARD_MANUFACTURER",
1218 "Model": "$BOARD_PRODUCT_NAME",
1219 "PartNumber": "$BOARD_PART_NUMBER",
1220 "SerialNumber": "$BOARD_SERIAL_NUMBER",
1221 "SparePartNumber": "$BOARD_INFO_AM1"
Potin Lai16152b52023-10-31 18:48:02 +0800[diff] [blame]1222 },
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1223 "xyz.openbmc_project.Inventory.Decorator.AssetTag": {
1224 "AssetTag": "$PRODUCT_ASSET_TAG"
Potin Lai16152b52023-10-31 18:48:02 +0800[diff] [blame]1225 },
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1226 "xyz.openbmc_project.Inventory.Item.Board.Motherboard": {
1227 "ProductId": 1
Potin Lai16152b52023-10-31 18:48:02 +0800[diff] [blame]1228 }
Peter Yin91c92902024-05-15 16:17:12 +0800[diff] [blame]1229 },
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1230 {
Daniel Hsu621fdf92025-01-22 11:07:55 +0800[diff] [blame^]1231 "Exposes": [
1232 {
1233 "Class": "fan",
1234 "FFGainCoefficient": 1.0,
1235 "FFOffCoefficient": 0.0,
1236 "ICoefficient": 0.0,
1237 "ILimitMax": 0.0,
1238 "ILimitMin": 0.0,
1239 "Inputs": [
1240 "FAN_BP1_FAN1_TACH_IL_SPEED_RPM",
1241 "FAN_BP1_FAN1_TACH_OL_SPEED_RPM",
1242 "FAN_BP1_FAN2_TACH_IL_SPEED_RPM",
1243 "FAN_BP1_FAN2_TACH_OL_SPEED_RPM",
1244 "FAN_BP1_FAN3_TACH_IL_SPEED_RPM",
1245 "FAN_BP1_FAN3_TACH_OL_SPEED_RPM",
1246 "FAN_BP1_FAN4_TACH_IL_SPEED_RPM",
1247 "FAN_BP1_FAN4_TACH_OL_SPEED_RPM",
1248 "FAN_BP2_FAN1_TACH_IL_SPEED_RPM",
1249 "FAN_BP2_FAN1_TACH_OL_SPEED_RPM",
1250 "FAN_BP2_FAN2_TACH_IL_SPEED_RPM",
1251 "FAN_BP2_FAN2_TACH_OL_SPEED_RPM",
1252 "FAN_BP2_FAN3_TACH_IL_SPEED_RPM",
1253 "FAN_BP2_FAN3_TACH_OL_SPEED_RPM",
1254 "FAN_BP2_FAN4_TACH_IL_SPEED_RPM",
1255 "FAN_BP2_FAN4_TACH_OL_SPEED_RPM"
1256 ],
1257 "Name": "All Fan",
1258 "OutLimitMax": 100.0,
1259 "OutLimitMin": 0.0,
1260 "Outputs": [
1261 "FAN_BP1_FAN_PWM",
1262 "FAN_BP1_FAN_PWM",
1263 "FAN_BP1_FAN_PWM",
1264 "FAN_BP1_FAN_PWM",
1265 "FAN_BP1_FAN_PWM",
1266 "FAN_BP1_FAN_PWM",
1267 "FAN_BP1_FAN_PWM",
1268 "FAN_BP1_FAN_PWM",
1269 "FAN_BP2_FAN_PWM",
1270 "FAN_BP2_FAN_PWM",
1271 "FAN_BP2_FAN_PWM",
1272 "FAN_BP2_FAN_PWM",
1273 "FAN_BP2_FAN_PWM",
1274 "FAN_BP2_FAN_PWM",
1275 "FAN_BP2_FAN_PWM",
1276 "FAN_BP2_FAN_PWM"
1277 ],
1278 "PCoefficient": 0.0,
1279 "SlewNeg": 0.0,
1280 "SlewPos": 0.0,
1281 "Type": "Pid",
1282 "Zones": [
1283 "Zone 0"
1284 ]
1285 },
1286 {
1287 "CheckHysteresisWithSetpoint": true,
1288 "Class": "temp",
1289 "DCoefficient": 0.0,
1290 "FFGainCoefficient": 0.0,
1291 "FFOffCoefficient": 0.0,
1292 "ICoefficient": -0.0035,
1293 "ILimitMax": 100,
1294 "ILimitMin": -50,
1295 "InputUnavailableAsFailed": false,
1296 "Inputs": [
1297 "MB_CPU_TEMP_C"
1298 ],
1299 "Name": "PID_MB_CPU",
1300 "NegativeHysteresis": 2.0,
1301 "OutLimitMax": 100,
1302 "OutLimitMin": 0,
1303 "PCoefficient": -1.0,
1304 "PositiveHysteresis": 0.0,
1305 "SetPoint": 79.0,
1306 "SlewNeg": 0.0,
1307 "SlewPos": 0.0,
1308 "Type": "Pid",
1309 "Zones": [
1310 "Zone 0"
1311 ]
1312 },
1313 {
1314 "CheckHysteresisWithSetpoint": true,
1315 "Class": "temp",
1316 "DCoefficient": 0.0,
1317 "FFGainCoefficient": 0.0,
1318 "FFOffCoefficient": 0.0,
1319 "ICoefficient": -0.0035,
1320 "ILimitMax": 100,
1321 "ILimitMin": -50,
1322 "InputUnavailableAsFailed": false,
1323 "Inputs": [
1324 "MB_DIMM_A0_TEMP_C",
1325 "MB_DIMM_A1_TEMP_C",
1326 "MB_DIMM_A2_TEMP_C",
1327 "MB_DIMM_A4_TEMP_C",
1328 "MB_DIMM_A6_TEMP_C",
1329 "MB_DIMM_A7_TEMP_C",
1330 "MB_DIMM_A8_TEMP_C",
1331 "MB_DIMM_A10_TEMP_C"
1332 ],
1333 "Name": "PID_MB_DIMM",
1334 "NegativeHysteresis": 2.0,
1335 "OutLimitMax": 100,
1336 "OutLimitMin": 0,
1337 "PCoefficient": -3.0,
1338 "PositiveHysteresis": 0.0,
1339 "SetPoint": 79.0,
1340 "SlewNeg": 0.0,
1341 "SlewPos": 0.0,
1342 "Type": "Pid",
1343 "Zones": [
1344 "Zone 0"
1345 ]
1346 },
1347 {
1348 "AccumulateSetPoint": true,
1349 "CycleIntervalTimeMS": 1000,
1350 "FailSafePercent": 85.0,
1351 "MinThermalOutput": 0.0,
1352 "Name": "Zone 0",
1353 "Type": "Pid.Zone",
1354 "UpdateThermalsTimeMS": 1000
1355 },
1356 {
1357 "Class": "temp",
1358 "InputUnavailableAsFailed": false,
1359 "Inputs": [
1360 "SCM_INLET_TEMP_C"
1361 ],
1362 "Name": "Stepwise_SCM_INLET",
1363 "NegativeHysteresis": 2.0,
1364 "Output": [
1365 20.0,
1366 22.0,
1367 25.0,
1368 90.0
1369 ],
1370 "PositiveHysteresis": 0.0,
1371 "Reading": [
1372 25.0,
1373 30.0,
1374 35.0,
1375 40.0
1376 ],
1377 "Type": "Stepwise",
1378 "Zones": [
1379 "Zone 0"
1380 ]
1381 },
1382 {
1383 "Class": "temp",
1384 "InputUnavailableAsFailed": false,
1385 "Inputs": [
1386 "MB_CPU_TEMP_C"
1387 ],
1388 "Name": "Stepwise_MB_CPU",
1389 "NegativeHysteresis": 2.0,
1390 "Output": [
1391 20.0,
1392 23.0,
1393 25.0,
1394 27.0,
1395 30.0
1396 ],
1397 "PositiveHysteresis": 0.0,
1398 "Reading": [
1399 55.0,
1400 60.0,
1401 65.0,
1402 70.0,
1403 75.0
1404 ],
1405 "Type": "Stepwise",
1406 "Zones": [
1407 "Zone 0"
1408 ]
1409 },
1410 {
1411 "Class": "temp",
1412 "InputUnavailableAsFailed": false,
1413 "Inputs": [
1414 "MB_DIMM_A0_TEMP_C",
1415 "MB_DIMM_A1_TEMP_C",
1416 "MB_DIMM_A2_TEMP_C",
1417 "MB_DIMM_A4_TEMP_C",
1418 "MB_DIMM_A6_TEMP_C",
1419 "MB_DIMM_A7_TEMP_C",
1420 "MB_DIMM_A8_TEMP_C",
1421 "MB_DIMM_A10_TEMP_C"
1422 ],
1423 "Name": "Stepwise_MB_DIMM",
1424 "NegativeHysteresis": 2.0,
1425 "Output": [
1426 20.0,
1427 25.0,
1428 30.0
1429 ],
1430 "PositiveHysteresis": 0.0,
1431 "Reading": [
1432 60.0,
1433 70.0,
1434 75.0
1435 ],
1436 "Type": "Stepwise",
1437 "Zones": [
1438 "Zone 0"
1439 ]
1440 },
1441 {
1442 "Class": "temp",
1443 "InputUnavailableAsFailed": false,
1444 "Inputs": [
1445 "MB_VR_CPU_VCORE0_TEMP_C",
1446 "MB_VR_CPU_VCORE1_TEMP_C",
1447 "MB_VR_CPU_PVDD11_TEMP_C",
1448 "MB_VR_CPU_PDDIO_TEMP_C",
1449 "MB_VR_CPU_SOC_TEMP_C"
1450 ],
1451 "Name": "Stepwise_MB_VR",
1452 "NegativeHysteresis": 2.0,
1453 "Output": [
1454 20.0,
1455 25.0,
1456 90.0
1457 ],
1458 "PositiveHysteresis": 0.0,
1459 "Reading": [
1460 80.0,
1461 90.0,
1462 100.0
1463 ],
1464 "Type": "Stepwise",
1465 "Zones": [
1466 "Zone 0"
1467 ]
1468 },
1469 {
1470 "Class": "temp",
1471 "InputUnavailableAsFailed": false,
1472 "Inputs": [
1473 "MB_RETIMER0_TEMP_C",
1474 "MB_RETIMER1_TEMP_C"
1475 ],
1476 "Name": "Stepwise_MB_RETIMER",
1477 "NegativeHysteresis": 2.0,
1478 "Output": [
1479 20.0,
1480 25.0,
1481 90.0
1482 ],
1483 "PositiveHysteresis": 0.0,
1484 "Reading": [
1485 80.0,
1486 90.0,
1487 100.0
1488 ],
1489 "Type": "Stepwise",
1490 "Zones": [
1491 "Zone 0"
1492 ]
1493 },
1494 {
1495 "Class": "temp",
1496 "InputUnavailableAsFailed": false,
1497 "Inputs": [
1498 "NIC_Temp_1"
1499 ],
1500 "Name": "Stepwise_NIC",
1501 "NegativeHysteresis": 2.0,
1502 "Output": [
1503 20.0,
1504 25.0,
1505 90.0
1506 ],
1507 "PositiveHysteresis": 0.0,
1508 "Reading": [
1509 80.0,
1510 90.0,
1511 100.0
1512 ],
1513 "Type": "Stepwise",
1514 "Zones": [
1515 "Zone 0"
1516 ]
1517 },
1518 {
1519 "Class": "temp",
1520 "InputUnavailableAsFailed": false,
1521 "Inputs": [
1522 "MB_E1S0_TEMP_C",
1523 "MB_E1S1_TEMP_C"
1524 ],
1525 "Name": "Stepwise_E1S",
1526 "NegativeHysteresis": 2.0,
1527 "Output": [
1528 20.0,
1529 25.0,
1530 90.0
1531 ],
1532 "PositiveHysteresis": 0.0,
1533 "Reading": [
1534 60.0,
1535 65.0,
1536 70.0
1537 ],
1538 "Type": "Stepwise",
1539 "Zones": [
1540 "Zone 0"
1541 ]
1542 },
1543 {
1544 "Class": "temp",
1545 "InputUnavailableAsFailed": false,
1546 "Inputs": [
1547 "PDB_BRICK_TEMP_C"
1548 ],
1549 "Name": "Stepwise_Brick",
1550 "NegativeHysteresis": 2.0,
1551 "Output": [
1552 20.0,
1553 25.0,
1554 90.0
1555 ],
1556 "PositiveHysteresis": 0.0,
1557 "Reading": [
1558 80.0,
1559 90.0,
1560 100.0
1561 ],
1562 "Type": "Stepwise",
1563 "Zones": [
1564 "Zone 0"
1565 ]
1566 }
1567 ],
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1568 "Name": "Harma Chassis",
1569 "Probe": [
1570 "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'Harma MB EVT', 'BOARD_PART_NUMBER': '3BF0MMA0040'})",
1571 "OR",
1572 "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'Harma MB EVT', 'BOARD_PART_NUMBER': '3BF0MMA0080'})",
1573 "OR",
1574 "xyz.openbmc_project.FruDevice({'BOARD_PRODUCT_NAME': 'Harma MB ', 'BOARD_INFO_AM4': 'vr-isl'})"
1575 ],
1576 "Type": "Chassis",
1577 "xyz.openbmc_project.Inventory.Decorator.Asset": {
1578 "Manufacturer": "$PRODUCT_MANUFACTURER",
1579 "Model": "$PRODUCT_PRODUCT_NAME",
1580 "PartNumber": "$PRODUCT_PART_NUMBER",
1581 "SerialNumber": "$PRODUCT_INFO_AM2",
1582 "SparePartNumber": "$PRODUCT_FRU_VERSION_ID"
1583 },
1584 "xyz.openbmc_project.Inventory.Decorator.AssetTag": {
1585 "AssetTag": "$PRODUCT_INFO_AM3"
1586 }
Potin Lai16152b52023-10-31 18:48:02 +0800[diff] [blame]1587 }
Peter Yin0740b172024-10-21 14:37:42 +0800[diff] [blame]1588]