| { |
| "$schema": "https://json-schema.org/draft/2020-12/schema", |
| "type": "object", |
| "description": "PCI Express Error Section", |
| "required": [], |
| "additionalProperties": false, |
| "properties": { |
| "portType": { |
| "type": "object", |
| "description": "PCIe Device/Port Type as defined in the PCI Express capabilities register.", |
| "$ref": "./common/cper-json-nvp.json" |
| }, |
| "version": { |
| "type": "object", |
| "description": "PCIe Spec. version supported by the platform", |
| "required": ["major", "minor"], |
| "properties": { |
| "major": { |
| "type": "integer" |
| }, |
| "minor": { |
| "type": "integer" |
| } |
| } |
| }, |
| "commandStatus": { |
| "type": "object", |
| "required": ["commandRegister", "statusRegister"], |
| "properties": { |
| "commandRegister": { |
| "type": "integer", |
| "description": "PCI Command Register" |
| }, |
| "statusRegister": { |
| "type": "integer", |
| "description": "PCI Status Register" |
| } |
| } |
| }, |
| "deviceID": { |
| "type": "object", |
| "description": "PCIe Root Port PCI/bridge PCI compatible device number and bus number information to uniquely identify the root port or bridge.", |
| "required": [ |
| "vendorID", |
| "deviceID", |
| "deviceIDHex", |
| "classCode", |
| "functionNumber", |
| "deviceNumber", |
| "segmentNumber", |
| "primaryOrDeviceBusNumber", |
| "secondaryBusNumber", |
| "slotNumber" |
| ], |
| "properties": { |
| "vendorID": { |
| "type": "integer" |
| }, |
| "deviceID": { |
| "type": "integer" |
| }, |
| "deviceIDHex": { |
| "type": "string" |
| }, |
| "classCode": { |
| "type": "integer" |
| }, |
| "functionNumber": { |
| "type": "integer" |
| }, |
| "deviceNumber": { |
| "type": "integer" |
| }, |
| "segmentNumber": { |
| "type": "integer" |
| }, |
| "primaryOrDeviceBusNumber": { |
| "type": "integer" |
| }, |
| "secondaryBusNumber": { |
| "type": "integer" |
| }, |
| "slotNumber": { |
| "type": "integer" |
| } |
| } |
| }, |
| "deviceSerialNumber": { |
| "type": "integer", |
| "description": "PCIe Device Serial Number" |
| }, |
| "bridgeControlStatus": { |
| "type": "object", |
| "required": ["secondaryStatusRegister", "controlRegister"], |
| "properties": { |
| "secondaryStatusRegister": { |
| "type": "integer", |
| "description": "Bridge Secondary Status Register" |
| }, |
| "controlRegister": { |
| "type": "integer", |
| "description": "Bridge Control Register" |
| } |
| } |
| }, |
| "capabilityStructure": { |
| "type": "object", |
| "description": "This feild reports either the PCIe 2.0 Capability structure", |
| "required": ["data"], |
| "properties": { |
| "data": { |
| "type": "string" |
| } |
| } |
| }, |
| "aerInfo": { |
| "type": "object", |
| "description": "PCIe Advanced Error Reporting Extended Capability Structure.", |
| "required": ["data"], |
| "properties": { |
| "data": { |
| "type": "string" |
| }, |
| "capability_header": { |
| "type": "integer" |
| }, |
| "uncorrectable_error_status": { |
| "type": "integer" |
| }, |
| "uncorrectable_error_status_hex": { |
| "type": "string" |
| }, |
| "uncorrectable_error_mask": { |
| "type": "integer" |
| }, |
| "uncorrectable_error_severity": { |
| "type": "integer" |
| }, |
| "correctable_error_status": { |
| "type": "integer" |
| }, |
| "correctable_error_status_hex": { |
| "type": "string" |
| }, |
| "correctable_error_mask": { |
| "type": "integer" |
| }, |
| "capabilites_control": { |
| "type": "integer" |
| }, |
| "tlp_header_0": { |
| "type": "integer" |
| }, |
| "tlp_header_1": { |
| "type": "integer" |
| }, |
| "tlp_header_2": { |
| "type": "integer" |
| }, |
| "tlp_header_3": { |
| "type": "integer" |
| } |
| } |
| } |
| } |
| } |