Lawrence Tang | 4dbe3d7 | 2022-07-06 13:51:01 +0100 | [diff] [blame] | 1 | #ifndef CPER_SECTION_PCIE_H |
| 2 | #define CPER_SECTION_PCIE_H |
| 3 | |
Karthik Rajagopalan | 255bd81 | 2024-09-06 14:36:34 -0700 | [diff] [blame] | 4 | #ifdef __cplusplus |
| 5 | extern "C" { |
| 6 | #endif |
| 7 | |
Lawrence Tang | 5202bbb | 2022-08-12 14:54:36 +0100 | [diff] [blame] | 8 | #include <json.h> |
Lawrence Tang | 4dbe3d7 | 2022-07-06 13:51:01 +0100 | [diff] [blame] | 9 | #include "../edk/Cper.h" |
| 10 | |
John Chung | f8fc705 | 2024-05-03 20:05:29 +0800 | [diff] [blame] | 11 | #define PCIE_ERROR_VALID_BITFIELD_NAMES \ |
| 12 | (const char *[]) \ |
| 13 | { \ |
| 14 | "portTypeValid", "versionValid", "commandStatusValid", \ |
| 15 | "deviceIDValid", "deviceSerialNumberValid", \ |
| 16 | "bridgeControlStatusValid", \ |
| 17 | "capabilityStructureStatusValid", "aerInfoValid" \ |
| 18 | } |
| 19 | #define PCIE_ERROR_PORT_TYPES_KEYS \ |
| 20 | (int[]) \ |
| 21 | { \ |
| 22 | 0, 1, 4, 5, 6, 7, 8, 9, 10 \ |
| 23 | } |
| 24 | #define PCIE_ERROR_PORT_TYPES_VALUES \ |
| 25 | (const char *[]) \ |
| 26 | { \ |
| 27 | "PCI Express End Point", "Legacy PCI End Point Device", \ |
| 28 | "Root Port", "Upstream Switch Port", \ |
| 29 | "Downstream Switch Port", \ |
| 30 | "PCI Express to PCI/PCI-X Bridge", \ |
| 31 | "PCI/PCI-X Bridge to PCI Express Bridge", \ |
| 32 | "Root Complex Integrated Endpoint Device", \ |
| 33 | "Root Complex Event Collector" \ |
| 34 | } |
Lawrence Tang | 4dbe3d7 | 2022-07-06 13:51:01 +0100 | [diff] [blame] | 35 | |
John Chung | f8fc705 | 2024-05-03 20:05:29 +0800 | [diff] [blame] | 36 | json_object *cper_section_pcie_to_ir(void *section); |
| 37 | void ir_section_pcie_to_cper(json_object *section, FILE *out); |
Lawrence Tang | 4dbe3d7 | 2022-07-06 13:51:01 +0100 | [diff] [blame] | 38 | |
Karthik Rajagopalan | 255bd81 | 2024-09-06 14:36:34 -0700 | [diff] [blame] | 39 | #ifdef __cplusplus |
| 40 | } |
| 41 | #endif |
| 42 | |
John Chung | f8fc705 | 2024-05-03 20:05:29 +0800 | [diff] [blame] | 43 | #endif |