Lawrence Tang | 4dbe3d7 | 2022-07-06 13:51:01 +0100 | [diff] [blame^] | 1 | /** |
| 2 | * Describes functions for converting PCIe CPER sections from binary and JSON format |
| 3 | * into an intermediate format. |
| 4 | * |
| 5 | * Author: Lawrence.Tang@arm.com |
| 6 | **/ |
| 7 | #include <stdio.h> |
| 8 | #include "json.h" |
| 9 | #include "../edk/Cper.h" |
| 10 | #include "../cper-utils.h" |
| 11 | #include "cper-section-pcie.h" |
| 12 | |
| 13 | //Converts a single PCIe CPER section into JSON IR. |
| 14 | json_object* cper_section_pcie_to_ir(void* section, EFI_ERROR_SECTION_DESCRIPTOR* descriptor) |
| 15 | { |
| 16 | EFI_PCIE_ERROR_DATA* pcie_error = (EFI_PCIE_ERROR_DATA*)section; |
| 17 | json_object* section_ir = json_object_new_object(); |
| 18 | |
| 19 | //Validation bits. |
| 20 | json_object* validation = bitfield_to_ir(pcie_error->ValidFields, 8, PCIE_ERROR_VALID_BITFIELD_NAMES); |
| 21 | json_object_object_add(section_ir, "validationBits", validation); |
| 22 | |
| 23 | //Port type. |
| 24 | json_object* port_type = integer_to_readable_pair(pcie_error->PortType, 9, |
| 25 | PCIE_ERROR_PORT_TYPES_KEYS, |
| 26 | PCIE_ERROR_PORT_TYPES_VALUES, |
| 27 | "Unknown"); |
| 28 | json_object_object_add(section_ir, "portType", port_type); |
| 29 | |
| 30 | //Version, provided each half in BCD. |
| 31 | json_object* version = json_object_new_object(); |
| 32 | json_object_object_add(version, "minor", json_object_new_int(bcd_to_int(pcie_error->Version & 0xFF))); |
| 33 | json_object_object_add(version, "major", json_object_new_int(bcd_to_int(pcie_error->Version >> 8))); |
| 34 | json_object_object_add(section_ir, "version", version); |
| 35 | |
| 36 | //Command & status. |
| 37 | json_object* command_status = json_object_new_object(); |
| 38 | json_object_object_add(command_status, "commandRegister", json_object_new_uint64(pcie_error->CommandStatus & 0xFFFF)); |
| 39 | json_object_object_add(command_status, "statusRegister", json_object_new_uint64(pcie_error->CommandStatus >> 16)); |
| 40 | json_object_object_add(section_ir, "commandStatus", command_status); |
| 41 | |
| 42 | //PCIe Device ID. |
| 43 | json_object* device_id = json_object_new_object(); |
| 44 | UINT64 class_id = pcie_error->DevBridge.ClassCode[0] + |
| 45 | (pcie_error->DevBridge.ClassCode[1] << 8) + |
| 46 | (pcie_error->DevBridge.ClassCode[2] << 16); |
| 47 | json_object_object_add(device_id, "vendorID", json_object_new_uint64(pcie_error->DevBridge.VendorId)); |
| 48 | json_object_object_add(device_id, "deviceID", json_object_new_uint64(pcie_error->DevBridge.DeviceId)); |
| 49 | json_object_object_add(device_id, "classCode", json_object_new_uint64(class_id)); |
| 50 | json_object_object_add(device_id, "functionNumber", json_object_new_uint64(pcie_error->DevBridge.Function)); |
| 51 | json_object_object_add(device_id, "deviceNumber", json_object_new_uint64(pcie_error->DevBridge.Device)); |
| 52 | json_object_object_add(device_id, "segmentNumber", json_object_new_uint64(pcie_error->DevBridge.Segment)); |
| 53 | json_object_object_add(device_id, "primaryOrDeviceBusNumber", json_object_new_uint64(pcie_error->DevBridge.PrimaryOrDeviceBus)); |
| 54 | json_object_object_add(device_id, "secondaryBusNumber", json_object_new_uint64(pcie_error->DevBridge.SecondaryBus)); |
| 55 | json_object_object_add(device_id, "slotNumber", json_object_new_uint64(pcie_error->DevBridge.Slot.Number)); |
| 56 | json_object_object_add(section_ir, "deviceID", device_id); |
| 57 | |
| 58 | //Device serial number. |
| 59 | json_object_object_add(section_ir, "deviceSerialNumber", json_object_new_uint64(pcie_error->SerialNo)); |
| 60 | |
| 61 | //Bridge control status. |
| 62 | json_object* bridge_control_status = json_object_new_object(); |
| 63 | json_object_object_add(bridge_control_status, "secondaryStatusRegister", |
| 64 | json_object_new_uint64(pcie_error->BridgeControlStatus & 0xFFFF)); |
| 65 | json_object_object_add(bridge_control_status, "controlRegister", |
| 66 | json_object_new_uint64(pcie_error->BridgeControlStatus >> 16)); |
| 67 | json_object_object_add(section_ir, "bridgeControlStatus", bridge_control_status); |
| 68 | |
| 69 | //Capability structure. |
| 70 | //todo: See Figure 6-9 of the PCIe 2.0 Base Specification to implement this |
| 71 | |
| 72 | //AER information. |
| 73 | //todo: See the PCIe 2.0 Base Specification to implement this. |
| 74 | |
| 75 | return section_ir; |
| 76 | } |