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Lawrence Tang580423f2022-08-24 09:37:53 +01001/**
2 * Describes available sections to the CPER parser.
3 *
4 * Author: Lawrence.Tang@arm.com
5 **/
6#include "../edk/Cper.h"
7#include "cper-section.h"
8#include "cper-section-arm.h"
9#include "cper-section-generic.h"
10#include "cper-section-ia32x64.h"
11#include "cper-section-ipf.h"
12#include "cper-section-memory.h"
13#include "cper-section-pcie.h"
14#include "cper-section-firmware.h"
15#include "cper-section-pci-bus.h"
16#include "cper-section-pci-dev.h"
17#include "cper-section-dmar-generic.h"
18#include "cper-section-dmar-vtd.h"
19#include "cper-section-dmar-iommu.h"
20#include "cper-section-ccix-per.h"
21#include "cper-section-cxl-protocol.h"
22#include "cper-section-cxl-component.h"
23
24//Definitions of all sections available to the CPER parser.
25CPER_SECTION_DEFINITION section_definitions[] = {
26 {&gEfiProcessorGenericErrorSectionGuid, "Processor Generic", cper_section_generic_to_ir, ir_section_generic_to_cper},
27 {&gEfiIa32X64ProcessorErrorSectionGuid, "IA32/X64", cper_section_ia32x64_to_ir, ir_section_ia32x64_to_cper},
28 {&gEfiIpfProcessorErrorSectionGuid, "IPF", NULL, NULL},
29 {&gEfiArmProcessorErrorSectionGuid, "ARM", cper_section_arm_to_ir, ir_section_arm_to_cper},
30 {&gEfiPlatformMemoryErrorSectionGuid, "Platform Memory", cper_section_platform_memory_to_ir, ir_section_memory_to_cper},
31 {&gEfiPlatformMemoryError2SectionGuid, "Platform Memory 2", cper_section_platform_memory2_to_ir, ir_section_memory2_to_cper},
32 {&gEfiPcieErrorSectionGuid, "PCIe", cper_section_pcie_to_ir, ir_section_pcie_to_cper},
33 {&gEfiFirmwareErrorSectionGuid, "Firmware Error Record Reference", cper_section_firmware_to_ir, ir_section_firmware_to_cper},
34 {&gEfiPciBusErrorSectionGuid, "PCI/PCI-X Bus", cper_section_pci_bus_to_ir, ir_section_pci_bus_to_cper},
35 {&gEfiPciDevErrorSectionGuid, "PCI Component/Device", cper_section_pci_dev_to_ir, ir_section_pci_dev_to_cper},
36 {&gEfiDMArGenericErrorSectionGuid, "DMAr Generic", cper_section_dmar_generic_to_ir, ir_section_dmar_generic_to_cper},
37 {&gEfiDirectedIoDMArErrorSectionGuid, "Intel VT for Directed I/O Specific DMAr", cper_section_dmar_vtd_to_ir, ir_section_dmar_vtd_to_cper},
38 {&gEfiIommuDMArErrorSectionGuid, "IOMMU Specific DMAr", cper_section_dmar_iommu_to_ir, ir_section_dmar_iommu_to_cper},
39 {&gEfiCcixPerLogErrorSectionGuid, "CCIX PER Log Error", cper_section_ccix_per_to_ir, ir_section_ccix_per_to_cper},
40 {&gEfiCxlProtocolErrorSectionGuid, "CXL Protocol Error", cper_section_cxl_protocol_to_ir, ir_section_cxl_protocol_to_cper},
41 {&gEfiCxlGeneralMediaErrorSectionGuid, "CXL General Media Component Error", cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper},
42 {&gEfiCxlDramEventErrorSectionGuid, "CXL DRAM Component Error", cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper},
43 {&gEfiCxlMemoryModuleErrorSectionGuid, "CXL Memory Module Component Error", cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper},
44 {&gEfiCxlPhysicalSwitchErrorSectionGuid, "CXL Physical Switch Component Error", cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper},
45 {&gEfiCxlVirtualSwitchErrorSectionGuid, "CXL Virtual Switch Component Error", cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper},
46 {&gEfiCxlMldPortErrorSectionGuid, "CXL MLD Port Component Error", cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper},
47};
48const size_t section_definitions_len = sizeof(section_definitions) / sizeof(CPER_SECTION_DEFINITION);