blob: f34ef220181afde6f162e94364263b0abf0fc427 [file] [log] [blame]
Brad Bishop89451ae2015-10-22 15:38:02 -05001diff --git a/arch/arm/cpu/arm926ejs/aspeed/IO.c b/arch/arm/cpu/arm926ejs/aspeed/IO.c
2index 86e9918..b06fdba 100644
3--- a/arch/arm/cpu/arm926ejs/aspeed/IO.c
4+++ b/arch/arm/cpu/arm926ejs/aspeed/IO.c
5@@ -31,7 +31,7 @@ static const char ThisFile[] = "IO.c";
6 #include <post.h>
7 #include <malloc.h>
8 #include <net.h>
9- #include <COMMINF.H>
10+ #include "COMMINF.H"
11 #endif
12 #ifdef SLT_DOS
13 #include <stdlib.h>
14@@ -353,4 +353,3 @@ ULONG ReadSOC_DD(ULONG addr)
15 #endif
16 return 0;
17 }
18-
19diff --git a/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c
20index 498d4fd..fdabd45 100644
21--- a/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c
22+++ b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c
23@@ -13,9 +13,9 @@ static const char ThisFile[] = "LAN9303.c";
24
25 #include "SWFUNC.H"
26 #ifdef SLT_UBOOT
27- #include <COMMINF.H>
28- #include <MAC.H>
29- #include <IO.H>
30+ #include "COMMINF.H"
31+ #include "MAC.H"
32+ #include "IO.H"
33 #endif
34
35 #ifdef SLT_DOS
36diff --git a/arch/arm/cpu/arm926ejs/aspeed/MAC.c b/arch/arm/cpu/arm926ejs/aspeed/MAC.c
37index 829da92..b4182f5 100644
38--- a/arch/arm/cpu/arm926ejs/aspeed/MAC.c
39+++ b/arch/arm/cpu/arm926ejs/aspeed/MAC.c
40@@ -16,7 +16,7 @@ static const char ThisFile[] = "MAC.c";
41 #ifdef SLT_UBOOT
42 #include <common.h>
43 #include <command.h>
44- #include <COMMINF.H>
45+ #include "COMMINF.H"
46 #include "STDUBOOT.H"
47 #endif
48 #ifdef SLT_DOS
49@@ -2081,5 +2081,3 @@ char TestingLoop (ULONG loop_checknum) {
50
51 return(0);
52 } // End char TestingLoop (ULONG loop_checknum)
53-
54-
55diff --git a/arch/arm/cpu/arm926ejs/aspeed/Makefile b/arch/arm/cpu/arm926ejs/aspeed/Makefile
56index 378745e..4c4e239 100644
57--- a/arch/arm/cpu/arm926ejs/aspeed/Makefile
58+++ b/arch/arm/cpu/arm926ejs/aspeed/Makefile
59@@ -16,7 +16,7 @@
60
61 include $(TOPDIR)/config.mk
62
63-LIB = $(obj)lib$(SOC).a
64+LIB = $(obj)lib$(SOC).o
65
66 COBJS = timer.o
67 COBJS += reset.o
68@@ -41,7 +41,7 @@ START := $(addprefix $(obj),$(START))
69 all: $(obj).depend $(LIB)
70
71 $(LIB): $(OBJS)
72- $(AR) $(ARFLAGS) $@ $(OBJS)
73+ $(call cmd_link_o_target, $(OBJS))
74
75 #########################################################################
76
77diff --git a/arch/arm/cpu/arm926ejs/aspeed/NCSI.c b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c
78index 7de06c3..7e86fb6 100644
79--- a/arch/arm/cpu/arm926ejs/aspeed/NCSI.c
80+++ b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c
81@@ -16,9 +16,9 @@ static const char ThisFile[] = "NCSI.c";
82 #ifdef SLT_UBOOT
83 #include <common.h>
84 #include <command.h>
85- #include <COMMINF.H>
86- #include <NCSI.H>
87- #include <IO.H>
88+ #include "COMMINF.H"
89+ #include "NCSI.H"
90+ #include "IO.H"
91 #endif
92 #ifdef SLT_DOS
93 #include <stdio.h>
94diff --git a/arch/arm/cpu/arm926ejs/aspeed/PHY.c b/arch/arm/cpu/arm926ejs/aspeed/PHY.c
95index 6afed9d..db73a70 100644
96--- a/arch/arm/cpu/arm926ejs/aspeed/PHY.c
97+++ b/arch/arm/cpu/arm926ejs/aspeed/PHY.c
98@@ -16,7 +16,7 @@ static const char ThisFile[] = "PHY.c";
99 #ifdef SLT_UBOOT
100 #include <common.h>
101 #include <command.h>
102- #include <COMMINF.H>
103+ #include "COMMINF.H"
104 #include "STDUBOOT.H"
105 #endif
106 #ifdef SLT_DOS
107diff --git a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c
108index 95958b0..2414d57 100644
109--- a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c
110+++ b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c
111@@ -13,11 +13,11 @@ static const char ThisFile[] = "PLLTEST.c";
112
113 #include "SWFUNC.H"
114
115-#include <COMMINF.H>
116-#include <STDUBOOT.H>
117-#include <TYPEDEF.H>
118-#include <IO.H>
119-#include <PLLTESTU.H>
120+#include "COMMINF.H"
121+#include "STDUBOOT.H"
122+#include "TYPEDEF.H"
123+#include "IO.H"
124+#include "PLLTESTU.H"
125
126 /*
127 * static
128@@ -407,5 +407,3 @@ int pll_function(int argc, char *argv[])
129 return (ERR_FATAL);
130 }
131 }
132-
133-
134diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H
135index 7fbf590..4e0adf6 100644
136--- a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H
137+++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H
138@@ -13,6 +13,5 @@
139
140 unsigned long int strtoul(char *string, char **endPtr, int base);
141 int atoi( char s[] );
142-int rand(void);
143
144 #endif // End STDUBOOT_H
145diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c
146index 90e2997..4b1f439 100644
147--- a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c
148+++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c
149@@ -19,11 +19,11 @@ int isspace ( char c )
150 {
151 if ( ( c == ' ' ) || ( c == 9 ) || ( c == 13 ) )
152 return 1;
153-
154+
155 return 0;
156 }
157
158-/*
159+/*
160 * strtoul.c --
161 *
162 * Source code for the "strtoul" library procedure.
163@@ -111,7 +111,7 @@ strtoul(char *string, char **endPtr, int base)
164 * If no base was provided, pick one from the leading characters
165 * of the string.
166 */
167-
168+
169 if (base == 0)
170 {
171 if (*p == '0') {
172@@ -219,17 +219,6 @@ int atoi( char s[] )
173 ans = ( 10 * ans ) + ( s[i] - '0' );
174
175 return ans;
176-}
177-
178-// -----------------------------------------------------------------------------
179-/* rand:return pseudo-random integer on 0...32767 */
180-int rand(void)
181-{
182- static unsigned long int next = 1;
183-
184- next = next * 1103515245 + 12345;
185-
186- return (unsigned int) ( next / 65536 ) % 32768;
187 }
188
189 #endif // End SLT_UBOOT
190diff --git a/arch/arm/cpu/arm926ejs/aspeed/STRESS.c b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c
191index dffd64f..e86685e 100644
192--- a/arch/arm/cpu/arm926ejs/aspeed/STRESS.c
193+++ b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c
194@@ -12,8 +12,8 @@
195 static const char ThisFile[] = "STRESS.c";
196
197 #include "SWFUNC.H"
198-#include <COMMINF.H>
199-#include <IO.H>
200+#include "COMMINF.H"
201+#include "IO.H"
202
203 #define TIMEOUT_DRAM 5000000
204
205@@ -142,4 +142,3 @@ int dram_stress_function(int argc, char *argv[])
206
207 return( ret );
208 }
209-
210diff --git a/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c
211index 72936c0..24ec0c5 100644
212--- a/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c
213+++ b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c
214@@ -13,9 +13,9 @@ static const char ThisFile[] = "PLLTEST.c";
215
216 #include "SWFUNC.H"
217
218-#include <COMMINF.H>
219-#include <TYPEDEF.H>
220-#include <IO.H>
221+#include "COMMINF.H"
222+#include "TYPEDEF.H"
223+#include "IO.H"
224
225 #define ASTCHIP_2400 0
226 #define ASTCHIP_2300 1
227diff --git a/arch/arm/cpu/arm926ejs/aspeed/mactest.c b/arch/arm/cpu/arm926ejs/aspeed/mactest.c
228index 95bd560..62a696d 100644
229--- a/arch/arm/cpu/arm926ejs/aspeed/mactest.c
230+++ b/arch/arm/cpu/arm926ejs/aspeed/mactest.c
231@@ -19,9 +19,9 @@ static const char ThisFile[] = "MACTEST.c";
232 #include <post.h>
233 #include <malloc.h>
234 #include <net.h>
235- #include <COMMINF.H>
236- #include <STDUBOOT.H>
237- #include <IO.H>
238+ #include "COMMINF.H"
239+ #include "STDUBOOT.H"
240+ #include "IO.H"
241 #else
242 #include <stdlib.h>
243 #include <string.h>
244@@ -1212,4 +1212,3 @@ Find_Err_IOMargin:;
245 return(Finish_Check(0));
246
247 }
248-
249diff --git a/arch/arm/cpu/arm926ejs/aspeed/reset.c b/arch/arm/cpu/arm926ejs/aspeed/reset.c
250index e0a57f9..ce8dba1 100644
251--- a/arch/arm/cpu/arm926ejs/aspeed/reset.c
252+++ b/arch/arm/cpu/arm926ejs/aspeed/reset.c
253@@ -17,7 +17,7 @@ void reset_cpu(ulong addr)
254 {
255 __raw_writel(0x10 , AST_WDT_BASE+0x04);
256 __raw_writel(0x4755, AST_WDT_BASE+0x08);
257- __raw_writel(0x3, AST_WDT_BASE+0x0c);
258+ __raw_writel(0x23, AST_WDT_BASE+0x0c); /* reset the full chip */
259
260 while (1)
261 /*nothing*/;
262diff --git a/arch/arm/cpu/arm926ejs/aspeed/timer.c b/arch/arm/cpu/arm926ejs/aspeed/timer.c
263index 4bba5c5..add4c0e 100644
264--- a/arch/arm/cpu/arm926ejs/aspeed/timer.c
265+++ b/arch/arm/cpu/arm926ejs/aspeed/timer.c
266@@ -16,12 +16,17 @@
267 */
268
269 #include <common.h>
270-#include <arm926ejs.h>
271+
272+#if CONFIG_ASPEED_TIMER_CLK < CONFIG_SYS_HZ
273+#error "CONFIG_ASPEED_TIMER_CLK must be as large as CONFIG_SYS_HZ"
274+#endif
275
276 #define TIMER_LOAD_VAL 0xffffffff
277+#define CLK_PER_HZ (CONFIG_ASPEED_TIMER_CLK / CONFIG_SYS_HZ)
278
279 /* macro to read the 32 bit timer */
280-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+0))
281+#define READ_CLK (*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0))
282+#define READ_TIMER (READ_CLK / CLK_PER_HZ)
283
284 static ulong timestamp;
285 static ulong lastdec;
286@@ -57,27 +62,25 @@ void set_timer (ulong t)
287 }
288
289 /* delay x useconds AND perserve advance timstamp value */
290-void udelay (unsigned long usec)
291+void __udelay (unsigned long usec)
292 {
293- ulong tmo, tmp;
294-
295- if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
296- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
297- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
298- tmo /= 1000; /* finish normalize. */
299- }else{ /* else small number, don't kill it prior to HZ multiply */
300- tmo = usec * CONFIG_SYS_HZ;
301- tmo /= (1000*1000);
302- }
303-
304- tmp = get_timer (0); /* get current timestamp */
305- if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
306- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
307- else
308- tmo += tmp; /* else, set advancing stamp wake up time */
309-
310- while (get_timer_masked () < tmo)/* loop till event */
311- /*NOP*/;
312+ ulong last = READ_CLK;
313+ ulong clks;
314+ ulong elapsed = 0;
315+
316+ /* translate usec to clocks */
317+ clks = (usec / 1000) * CLK_PER_HZ;
318+ clks += (usec % 1000) * CLK_PER_HZ / 1000;
319+
320+ while (clks > elapsed) {
321+ ulong now = READ_CLK;
322+ if (now <= last) {
323+ elapsed += last - now;
324+ } else {
325+ elapsed += TIMER_LOAD_VAL - (now - last);
326+ }
327+ last = now;
328+ }
329 }
330
331 void reset_timer_masked (void)
332@@ -100,7 +103,7 @@ ulong get_timer_masked (void)
333 * (TLV-now) amount of time after passing though -1
334 * nts = new "advancing time stamp"...it could also roll and cause problems.
335 */
336- timestamp += lastdec + TIMER_LOAD_VAL - now;
337+ timestamp += lastdec + (TIMER_LOAD_VAL / CLK_PER_HZ) - now;
338 }
339 lastdec = now;
340
341@@ -110,25 +113,7 @@ ulong get_timer_masked (void)
342 /* waits specified delay value and resets timestamp */
343 void udelay_masked (unsigned long usec)
344 {
345- ulong tmo;
346- ulong endtime;
347- signed long diff;
348-
349- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
350- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
351- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
352- tmo /= 1000; /* finish normalize. */
353- } else { /* else small number, don't kill it prior to HZ multiply */
354- tmo = usec * CONFIG_SYS_HZ;
355- tmo /= (1000*1000);
356- }
357-
358- endtime = get_timer_masked () + tmo;
359-
360- do {
361- ulong now = get_timer_masked ();
362- diff = endtime - now;
363- } while (diff >= 0);
364+ __udelay(usec);
365 }
366
367 /*
368@@ -146,8 +131,5 @@ unsigned long long get_ticks(void)
369 */
370 ulong get_tbclk (void)
371 {
372- ulong tbclk;
373-
374- tbclk = CONFIG_SYS_HZ;
375- return tbclk;
376+ return CONFIG_SYS_HZ;
377 }
378diff --git a/board/aspeed/ast2400/Makefile b/board/aspeed/ast2400/Makefile
379index 1970ea1..fb77fc9 100644
380--- a/board/aspeed/ast2400/Makefile
381+++ b/board/aspeed/ast2400/Makefile
382@@ -11,7 +11,7 @@
383
384 include $(TOPDIR)/config.mk
385
386-LIB = $(obj)lib$(BOARD).a
387+LIB = $(obj)lib$(BOARD).o
388
389 COBJS := ast2400.o flash.o flash_spi.o pci.o crc32.o slt.o regtest.o vfun.o vhace.o crt.o videotest.o mactest.o hactest.o mictest.o
390
391@@ -28,17 +28,13 @@ OBJS := $(addprefix $(obj),$(COBJS))
392 SOBJS := $(addprefix $(obj),$(SOBJS))
393
394 $(LIB): $(obj).depend $(OBJS) $(SOBJS)
395- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
396+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
397
398-clean:
399- rm -f $(SOBJS) $(OBJS)
400-
401-distclean: clean
402- rm -f $(LIB) core *.bak $(obj).depend
403+#########################################################################
404
405 # defines $(obj).depend target
406 include $(SRCTREE)/rules.mk
407
408-sinclude .depend
409+sinclude $(obj).depend
410
411 #########################################################################
412diff --git a/board/aspeed/ast2400/ast2400.c b/board/aspeed/ast2400/ast2400.c
413index 65bccbe..55ed6b7 100644
414--- a/board/aspeed/ast2400/ast2400.c
415+++ b/board/aspeed/ast2400/ast2400.c
416@@ -10,6 +10,7 @@
417 */
418
419 #include <common.h>
420+#include <asm/io.h>
421 #include <command.h>
422 #include <pci.h>
423
424@@ -105,8 +106,8 @@ int dram_init (void)
425 {
426 DECLARE_GLOBAL_DATA_PTR;
427
428- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
429- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
430+ /* dram_init must store complete ramsize in gd->ram_size */
431+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
432
433 return 0;
434 }
435@@ -190,6 +191,22 @@ int ast1070_calibration()
436 return 0;
437 }
438
439+static void watchdog_init()
440+{
441+#ifdef CONFIG_ASPEED_ENABLE_WATCHDOG
442+#define AST_WDT_BASE 0x1e785000
443+#define AST_WDT_CLK (1*1000*1000) /* 1M clock source */
444+ u32 reload = AST_WDT_CLK * CONFIG_ASPEED_WATCHDOG_TIMEOUT;
445+ /* set the reload value */
446+ __raw_writel(reload, AST_WDT_BASE + 0x04);
447+ /* magic word to reload */
448+ __raw_writel(0x4755, AST_WDT_BASE + 0x08);
449+ /* start the watchdog with 1M clk src and reset whole chip */
450+ __raw_writel(0x33, AST_WDT_BASE + 0x0c);
451+ printf("Watchdog: %us\n", CONFIG_ASPEED_WATCHDOG_TIMEOUT);
452+#endif
453+}
454+
455 int misc_init_r(void)
456 {
457 unsigned int reg, reg1, revision, chip_id, lpc_plus;
458@@ -290,6 +307,8 @@ int misc_init_r(void)
459 if (getenv ("eeprom") == NULL) {
460 setenv ("eeprom", "y");
461 }
462+
463+ watchdog_init();
464 }
465
466 #ifdef CONFIG_PCI
467@@ -302,3 +321,15 @@ void pci_init_board(void)
468 aspeed_init_pci(&hose);
469 }
470 #endif
471+
472+int board_eth_init(bd_t *bis)
473+{
474+ int ret = -1;
475+#if defined(CONFIG_ASPEEDNIC)
476+ ret = aspeednic_initialize(bis);
477+#else
478+ printf("No ETH, ");
479+#endif
480+
481+ return ret;
482+}
483diff --git a/board/aspeed/ast2400/config.mk b/board/aspeed/ast2400/config.mk
484index 24ca09b..eddc3bf 100755
485--- a/board/aspeed/ast2400/config.mk
486+++ b/board/aspeed/ast2400/config.mk
487@@ -9,10 +9,5 @@
488 # MA 02111-1307 USA
489 #
490
491-# ROM version
492-#TEXT_BASE = 0xBFC00000
493-
494-# RAM version
495-TEXT_BASE = 0x40500000
496-#TEXT_BASE = 0x00000000
497-#TEXT_BASE = 0x00400000
498+# SPI flash is mapped to 0x00000000 initially
499+CONFIG_SYS_TEXT_BASE = 0x00000000
500diff --git a/board/aspeed/ast2400/flash_spi.c b/board/aspeed/ast2400/flash_spi.c
501index ad89254..339e531 100755
502--- a/board/aspeed/ast2400/flash_spi.c
503+++ b/board/aspeed/ast2400/flash_spi.c
504@@ -23,7 +23,7 @@
505 */
506
507 /* The DEBUG define must be before common to enable debugging */
508-/* #define DEBUG */
509+/* #define DEBUG */
510
511 #include <common.h>
512 #include <asm/processor.h>
513@@ -68,6 +68,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
514 /* Support Flash ID */
515 #define STM25P64 0x172020
516 #define STM25P128 0x182020
517+#define N25Q128 0x18ba20
518 #define N25Q256 0x19ba20
519 #define N25Q512 0x20ba20
520 #define S25FL064A 0x160201
521@@ -581,7 +582,7 @@ static ulong flash_get_size (ulong base, int banknum)
522 ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ;
523 info->flash_id = ulID;
524
525- //printf("SPI Flash ID: %x \n", ulID);
526+ printf("SPI Flash ID: %x \n", ulID);
527
528 /* init default */
529 info->iomode = IOMODEx1;
530@@ -617,6 +618,19 @@ static ulong flash_get_size (ulong base, int banknum)
531 ReadClk = 50;
532 break;
533
534+ case N25Q128:
535+ info->sector_count = 256;
536+ info->size = 0x1000000;
537+ erase_region_size = 0x10000;
538+ info->readcmd = 0x0b;
539+ info->dualport = 0;
540+ info->dummybyte = 1;
541+ info->buffersize = 256;
542+ WriteClk = 50;
543+ EraseClk = 20;
544+ ReadClk = 50;
545+ break;
546+
547 case N25Q256:
548 info->sector_count = 256;
549 info->size = 0x1000000;
550@@ -1051,8 +1065,7 @@ AST2300 A0 SPI can't run faster than 50Mhz
551 } /* JDEC */
552 }
553
554- debug ("erase_region_count = %d erase_region_size = %d\n",
555- erase_region_count, erase_region_size);
556+ debug ("erase_region_size = %d\n", erase_region_size);
557
558 sector = base;
559 for (j = 0; j < info->sector_count; j++) {
560diff --git a/board/aspeed/ast2400/platform.S b/board/aspeed/ast2400/platform.S
561index 27e8f26..dd94da0 100644
562--- a/board/aspeed/ast2400/platform.S
563+++ b/board/aspeed/ast2400/platform.S
564@@ -334,7 +334,11 @@ set_MPLL:
565 str r1, [r0]
566
567 /* Debug - UART console message */
568- ldr r0, =0x1e78400c
569+ ldr r0, =0x1e6e2080
570+ ldr r1, =0xFFFF0000 @ enable UART3 and UART4
571+ str r1, [r0]
572+
573+ ldr r0, =CONFIG_ASPEED_COM_LCR
574 mov r1, #0x83
575 str r1, [r0]
576
577@@ -342,28 +346,38 @@ set_MPLL:
578 ldr r2, [r0]
579 mov r2, r2, lsr #12
580 tst r2, #0x01
581- ldr r0, =0x1e784000
582+ ldr r0, =CONFIG_ASPEED_COM
583+#if CONFIG_BAUDRATE == 115200
584 moveq r1, #0x0D @ Baudrate 115200
585 movne r1, #0x01 @ Baudrate 115200, div13
586-#if defined(CONFIG_DRAM_UART_38400)
587+#endif
588+#if CONFIG_BAUDRATE == 57600
589+ moveq r1, #0x1A @ Baudrate 57600
590+ movne r1, #0x02 @ Baudrate 57600, div13
591+#endif
592+#if CONFIG_BAUDRATE == 38400
593 moveq r1, #0x27 @ Baudrate 38400
594 movne r1, #0x03 @ Baudrate 38400 , div13
595 #endif
596+#if CONFIG_BAUDRATE == 9600
597+ moveq r1, #0x9c @ Baudrate 9600
598+ movne r1, #0x0C @ Baudrate 9600 , div13
599+#endif
600 str r1, [r0]
601
602- ldr r0, =0x1e784004
603+ ldr r0, =CONFIG_ASPEED_COM_IER
604 mov r1, #0x00
605 str r1, [r0]
606
607- ldr r0, =0x1e78400c
608+ ldr r0, =CONFIG_ASPEED_COM_LCR
609 mov r1, #0x03
610 str r1, [r0]
611
612- ldr r0, =0x1e784008
613+ ldr r0, =CONFIG_ASPEED_COM_IIR
614 mov r1, #0x07
615 str r1, [r0]
616
617- ldr r0, =0x1e784000
618+ ldr r0, =CONFIG_ASPEED_COM
619 mov r1, #0x0D @ '\r'
620 str r1, [r0]
621 mov r1, #0x0A @ '\n'
622@@ -575,7 +589,7 @@ delay_2:
623 ******************************************************************************/
624 ddr3_init:
625 /* Debug - UART console message */
626- ldr r0, =0x1e784000
627+ ldr r0, =CONFIG_ASPEED_COM
628 mov r1, #0x33 @ '3'
629 str r1, [r0]
630 mov r1, #0x0D @ '\r'
631@@ -764,7 +778,7 @@ delay3_4:
632 ******************************************************************************/
633 ddr2_init:
634 /* Debug - UART console message */
635- ldr r0, =0x1e784000
636+ ldr r0, =CONFIG_ASPEED_COM
637 mov r1, #0x32 @ '2'
638 str r1, [r0]
639 mov r1, #0x0D @ '\r'
640@@ -1416,7 +1430,7 @@ init_sram_start3:
641 *****************************************************************************/
642 CBR0_START:
643 /* Debug - UART console message */
644- ldr r0, =0x1e784000
645+ ldr r0, =CONFIG_ASPEED_COM
646 mov r1, #0x43 @ 'C'
647 str r1, [r0]
648 mov r1, #0x42 @ 'B'
649@@ -1454,7 +1468,7 @@ cbr0_next_dqidly:
650 bgt CBR0_END
651
652 /* Debug - UART console message */
653- ldr r0, =0x1e784000
654+ ldr r0, =CONFIG_ASPEED_COM
655 and r1, r8, #0x07
656 add r1, r1, #0x30 @ '0-7'
657 str r1, [r0]
658@@ -1776,7 +1790,7 @@ delay_5:
659 *****************************************************************************/
660 CBR1_START:
661 /* Debug - UART console message */
662- ldr r0, =0x1e784000
663+ ldr r0, =CONFIG_ASPEED_COM
664 mov r1, #0x0D @ '\r'
665 str r1, [r0]
666 mov r1, #0x0A @ '\n'
667@@ -2057,7 +2071,7 @@ cbr1_set_result_end:
668
669 CBR3_START:
670 /* Debug - UART console message */
671- ldr r0, =0x1e784000
672+ ldr r0, =CONFIG_ASPEED_COM
673 mov r1, #0x33 @ '3'
674 str r1, [r0]
675 /* Debug - UART console message */
676@@ -2276,7 +2290,7 @@ CBR3_END:
677 *****************************************************************************/
678 CBR4_START:
679 /* Debug - UART console message */
680- ldr r0, =0x1e784000
681+ ldr r0, =CONFIG_ASPEED_COM
682 mov r1, #0x34 @ '4'
683 str r1, [r0]
684 /* Debug - UART console message */
685@@ -2556,7 +2570,7 @@ set_scratch:
686 str r1, [r0]
687
688 /* Debug - UART console message */
689- ldr r0, =0x1e784000
690+ ldr r0, =CONFIG_ASPEED_COM
691 mov r1, #0x44 @ 'D'
692 str r1, [r0]
693 mov r1, #0x6F @ 'o'
694@@ -2724,11 +2738,13 @@ ECC_Init_Flag:
695 orr r1, r1, #0x08
696 str r1, [r0]
697
698+#ifndef CONFIG_ASPEED_ENABLE_JTAG
699 ldr r0, =0x1e6e2004
700 ldr r1, [r0]
701 ldr r2, =0xFFBFFFFF @ Enable JTAG Master, solve ARM stucked by JTAG issue
702 and r1, r1, r2
703 str r1, [r0]
704+#endif
705
706 ldr r0, =0x1e6e2048 @ Set MAC interface delay timing
707 ldr r1, =0x2255
708diff --git a/board/aspeed/ast2400/u-boot.lds b/board/aspeed/ast2400/u-boot.lds
709deleted file mode 100755
710index ff0fe22..0000000
711--- a/board/aspeed/ast2400/u-boot.lds
712+++ /dev/null
713@@ -1,56 +0,0 @@
714-/*
715- * (C) Copyright 2004
716- * Wolfgang Denk, DENX Software Engineering, <wg@denx.de>
717- *
718- * See file CREDITS for list of people who contributed to this
719- * project.
720- *
721- * This program is free software; you can redistribute it and/or
722- * modify it under the terms of the GNU General Public License as
723- * published by the Free Software Foundation; either version 2 of
724- * the License, or (at your option) any later version.
725- *
726- * This program is distributed in the hope that it will be useful,
727- * but WITHOUT ANY WARRANTY; without even the implied warranty of
728- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
729- * GNU General Public License for more details.
730- *
731- * You should have received a copy of the GNU General Public License
732- * along with this program; if not, write to the Free Software
733- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
734- * MA 02111-1307 USA
735- */
736-
737-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
738-/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
739-OUTPUT_ARCH(arm)
740-ENTRY(_start)
741-SECTIONS
742-{
743- . = 0x00000000;
744-
745- . = ALIGN(4);
746- .text :
747- {
748- cpu/arm926ejs/start.o (.text)
749- *(.text)
750- }
751-
752- . = ALIGN(4);
753- .rodata : { *(.rodata) }
754-
755- . = ALIGN(4);
756- .data : { *(.data) }
757-
758- . = ALIGN(4);
759- .got : { *(.got) }
760-
761- __u_boot_cmd_start = .;
762- .u_boot_cmd : { *(.u_boot_cmd) }
763- __u_boot_cmd_end = .;
764-
765- . = ALIGN(4);
766- __bss_start = .;
767- .bss : { *(.bss) }
768- _end = .;
769-}
770diff --git a/boards.cfg b/boards.cfg
771index 674896b..ce6bff1 100644
772--- a/boards.cfg
773+++ b/boards.cfg
774@@ -72,7 +72,8 @@ mini2440 arm arm920t mini2440 friendl
775 VCMA9 arm arm920t vcma9 mpl s3c24x0
776 smdk2410 arm arm920t - samsung s3c24x0
777 omap1510inn arm arm925t - ti
778-ast2400 arm arm926ejs ast2400 aspeed aspeed
779+wedge arm arm926ejs ast2400 aspeed aspeed
780+palmetto arm arm926ejs ast2400 aspeed aspeed
781 integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_S
782 integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S
783 aspenite arm arm926ejs - Marvell armada100
784diff --git a/common/cmd_slt.c b/common/cmd_slt.c
785index 9763692..6296416 100644
786--- a/common/cmd_slt.c
787+++ b/common/cmd_slt.c
788@@ -9,6 +9,7 @@
789 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
790 */
791
792+#include <common.h>
793 #include <command.h>
794
795 extern int pll_function(int argc, char *argv[]);
796diff --git a/common/env_common.c b/common/env_common.c
797index 906b41f..f5af537 100644
798--- a/common/env_common.c
799+++ b/common/env_common.c
800@@ -203,6 +203,9 @@ void env_relocate(void)
801 #else
802 bootstage_error(BOOTSTAGE_ID_NET_CHECKSUM);
803 set_default_env("!bad CRC");
804+#ifdef CONFIG_ASPEED_WRITE_DEFAULT_ENV
805+ saveenv();
806+#endif
807 #endif
808 } else {
809 env_relocate_spec();
810diff --git a/common/image.c b/common/image.c
811index f5ad097..2fc071b 100644
812--- a/common/image.c
813+++ b/common/image.c
814@@ -902,6 +902,11 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
815 rd_data = image_get_data(rd_hdr);
816 rd_len = image_get_data_size(rd_hdr);
817 rd_load = image_get_load(rd_hdr);
818+#ifdef CONFIG_ASPEED
819+ /* Need to copy the initrd into RAM */
820+ memmove_wd((void *)rd_load, (void *)rd_data, rd_len, CHUNKSZ);
821+ rd_data = rd_load;
822+#endif
823 break;
824 #if defined(CONFIG_FIT)
825 case IMAGE_FORMAT_FIT:
826diff --git a/drivers/net/aspeednic.c b/drivers/net/aspeednic.c
827index 6b1ce05..d75ef67 100644
828--- a/drivers/net/aspeednic.c
829+++ b/drivers/net/aspeednic.c
830@@ -16,6 +16,7 @@
831 #include <malloc.h>
832 #include <net.h>
833 #include <pci.h>
834+#include <linux/mii.h>
835
836
837 /*
838@@ -53,7 +54,6 @@
839 #define MAC1_MDC (1 << 30)
840 #define MAC1_PHY_LINK (1 << 0)
841 #define MAC2_MDC_MDIO (1 << 2)
842-#define MAC1_PHY_LINK (1 << 0)
843 #define MAC2_PHY_LINK (1 << 1)
844 #else
845 #define MAC2_MDC_MDIO (1 << 20)
846@@ -69,6 +69,9 @@ unsigned int aspeednic_iobase[CONFIG_ASPEED_MAC_NUMBER] = {
847 0x1E660000, 0x1E680000};
848 #endif
849
850+/* PHY address */
851+static u8 g_phy_addr = 0;
852+
853 #undef DEBUG_SROM
854 #undef DEBUG_SROM2
855
856@@ -249,6 +252,7 @@ struct de4x5_desc {
857 #define PHYID_RTL8201EL 0x001cc810
858 #define PHYID_RTL8211 0x001cc910
859 #define PHYID_BCM54612E 0x03625E6A
860+#define PHYID_BCM54616S 0x03625D12
861
862 //NCSI define & structure
863 //NC-SI Command Packet
864@@ -410,6 +414,12 @@ static void aspeednic_halt(struct eth_device* dev);
865 static void set_mac_address (struct eth_device* dev, bd_t* bis);
866 static void phy_write_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address, u16 PHY_Data);
867 static u16 phy_read_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address);
868+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
869+static int faraday_mdio_read(const char *devname, uint8_t addr, uint8_t reg,
870+ uint16_t *value);
871+static int faraday_mdio_write(const char *devname, uint8_t addr, uint8_t reg,
872+ uint16_t value);
873+#endif
874 static void set_mac_control_register(struct eth_device* dev);
875
876 #if defined(CONFIG_E500)
877@@ -456,7 +466,7 @@ void NCSI_Struct_Initialize(void)
878
879 int aspeednic_initialize(bd_t *bis)
880 {
881- int card_number = 0;
882+ int card_number = CONFIG_ASPEED_MAC_CONFIG - 1;
883 unsigned int iobase, SCURegister;
884 struct eth_device* dev;
885
886@@ -538,7 +548,7 @@ int aspeednic_initialize(bd_t *bis)
887
888 dev->iobase = iobase;
889
890- if (CONFIG_MAC1_PHY_SETTING >= 1) {
891+ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) {
892 //NCSI Struct Initialize
893 NCSI_Struct_Initialize();
894 }
895@@ -556,20 +566,22 @@ int aspeednic_initialize(bd_t *bis)
896 dev->recv = aspeednic_recv;
897
898 /* Ensure we're not sleeping. */
899- if (CONFIG_MAC1_PHY_SETTING >= 1) {
900+ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) {
901 udelay(2000000); //2.0 sec
902 }
903 else {
904 udelay(10 * 1000);
905 }
906
907-
908 dev->init(dev, bis);
909
910 eth_register(dev);
911
912+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
913+ miiphy_register(dev->name, faraday_mdio_read, faraday_mdio_write);
914+#endif
915
916- return card_number;
917+ return 1;
918 }
919
920 void Calculate_Checksum(unsigned char *buffer_base, int Length)
921@@ -1114,11 +1126,37 @@ void Set_Link (struct eth_device* dev)
922 Retry = 0;
923 }
924
925+static void aspeednic_probe_phy(struct eth_device *dev)
926+{
927+ u8 phy_addr;
928+ u16 phy_id;
929+
930+ /* assume it as 0 */
931+ g_phy_addr = 0;
932+
933+ /* Check if the PHY is up to snuff..., max phy addr is 0x1f */
934+ for (phy_addr = 0; phy_addr <= 0x1f; phy_addr++) {
935+ phy_id = phy_read_register(dev, MII_PHYSID1, phy_addr);
936+ /*
937+ * When it is unable to found PHY,
938+ * the interface usually return 0xffff or 0x0000
939+ */
940+ if (phy_id != 0xffff && phy_id != 0x0) {
941+ g_phy_addr = phy_addr;
942+ break;
943+ }
944+ }
945+ printf("%s: PHY at 0x%02x\n", dev->name, phy_addr);
946+}
947+
948 static int aspeednic_init(struct eth_device* dev, bd_t* bis)
949 {
950 unsigned long i, Package_Found = 0, Channel_Found = 0, Re_Send = 0, Link_Status;
951
952 RESET_DE4X5(dev);
953+
954+ aspeednic_probe_phy(dev);
955+
956 set_mac_address (dev, bis);
957 set_mac_control_register (dev);
958
959@@ -1149,7 +1187,7 @@ static int aspeednic_init(struct eth_device* dev, bd_t* bis)
960 tx_new = 0;
961 rx_new = 0;
962
963- if (CONFIG_MAC1_PHY_SETTING >= 1) {
964+ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) {
965 //NCSI Start
966 //DeSelect Package/ Select Package
967 for (i = 0; i < 4; i++) {
968@@ -1313,58 +1351,23 @@ static void aspeednic_halt(struct eth_device* dev)
969
970 static void set_mac_address (struct eth_device* dev, bd_t* bis)
971 {
972- unsigned char mac_address[6]; // 6 bytes mac address
973- unsigned char ethaddress[20]; // string for setenv function
974- char *s;
975- int i, env; // env variable 0: eeprom, 1: environment parameters
976-
977- s = getenv ("eeprom");
978- env = (s && (*s == 'y')) ? 0 : 1;
979-
980- if (env == 0) {
981- env = 1;
982- eeprom_init ();
983- eeprom_read (0xA0, 0, mac_address, 6);
984-
985- for (i = 0; i < 6; i++) {
986- if (mac_address[i] != 0xFF) {
987- env = 0; //Suppose not all 0xFF is valid
988- }
989- }
990+ if (!eth_getenv_enetaddr_by_index("eth", 0, dev->enetaddr)) {
991+ eth_random_enetaddr(dev->enetaddr);
992 }
993
994- if (env == 0) { // EEPROM
995- sprintf (ethaddress, "%02X:%02X:%02X:%02X:%02X:%02X", mac_address[0], mac_address[1], mac_address[2], mac_address[3], mac_address[4], mac_address[5]);
996- setenv ("ethaddr", ethaddress);
997- OUTL(dev, ((mac_address[2] << 24) | (mac_address[3] << 16) | (mac_address[4] << 8) | mac_address[5]), MAC_LADR_REG);
998- OUTL(dev, ((mac_address[0] << 8) | mac_address[1]), MAC_MADR_REG);
999- if (CONFIG_MAC1_PHY_SETTING >= 1) {
1000- for (i = 0; i < 6; i++) {
1001- NCSI_Request.SA[i] = mac_address[i];
1002- }
1003- }
1004- }
1005- else { // Environment Parameters
1006- OUTL(dev, ((bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5]), MAC_LADR_REG);
1007- OUTL(dev, ((bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]), MAC_MADR_REG);
1008- if (CONFIG_MAC1_PHY_SETTING >= 1) {
1009- for (i = 0; i < 6; i++) {
1010- NCSI_Request.SA[i] = bis->bi_enetaddr[i];
1011- }
1012- }
1013+ OUTL(dev, ((dev->enetaddr[2] << 24) | (dev->enetaddr[3] << 16)
1014+ | (dev->enetaddr[4] << 8) | dev->enetaddr[5]), MAC_LADR_REG);
1015+ OUTL(dev, ((dev->enetaddr[0] << 8) | dev->enetaddr[1]), MAC_MADR_REG);
1016+ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) {
1017+ memcpy(NCSI_Request.SA, dev->enetaddr, 6);
1018 }
1019-
1020 }
1021
1022-
1023 static u16 phy_read_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address)
1024 {
1025 u32 Data, Status = 0, Loop_Count = 0, PHY_Ready = 1;
1026 u16 Return_Data;
1027
1028-#ifdef REALTEK_PHY_SUPPORT
1029- PHY_Address = 0x01;
1030-#endif
1031 //20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
1032 OUTL(dev, (PHY_Register << 21) + (PHY_Address << 16) + MIIRD + MDC_CYCTHR, PHYCR_REG);
1033 do {
1034@@ -1378,7 +1381,6 @@ static u16 phy_read_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Ad
1035 } while (Status == MIIRD);
1036
1037 if (PHY_Ready == 0) {
1038- printf ("PHY NOT REDAY ");
1039 return 0;
1040 }
1041 Data = INL (dev, PHYDATA_REG);
1042@@ -1392,9 +1394,6 @@ static void phy_write_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_
1043 {
1044 u32 Status = 0, Loop_Count = 0, PHY_Ready = 1;
1045
1046-#ifdef REALTEK_PHY_SUPPORT
1047- PHY_Address = 0x01;
1048-#endif
1049 //20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
1050 OUTL(dev, PHY_Data, PHYDATA_REG);
1051 OUTL(dev, (PHY_Register << 21) + (PHY_Address << 16) + MIIWR + MDC_CYCTHR, PHYCR_REG);
1052@@ -1407,31 +1406,66 @@ static void phy_write_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_
1053 break;
1054 }
1055 } while (Status == MIIWR);
1056- if (PHY_Ready == 0) {
1057- printf ("PHY NOT REDAY ");
1058+}
1059+
1060+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1061+
1062+static int faraday_mdio_read(
1063+ const char *devname, uint8_t addr, uint8_t reg, uint16_t *value)
1064+{
1065+ int ret = 0;
1066+ struct eth_device *dev;
1067+
1068+ dev = eth_get_dev_by_name(devname);
1069+ if (dev == NULL) {
1070+ printf("%s: no such device\n", devname);
1071+ ret = -1;
1072+ } else {
1073+ *value = phy_read_register(dev, reg, addr);
1074+ }
1075+
1076+ return ret;
1077+}
1078+
1079+static int faraday_mdio_write(
1080+ const char *devname, uint8_t addr, uint8_t reg, uint16_t value)
1081+{
1082+ int ret = 0;
1083+ struct eth_device *dev;
1084+
1085+ dev = eth_get_dev_by_name(devname);
1086+ if (dev == NULL) {
1087+ printf("%s: no such device\n", devname);
1088+ ret = -1;
1089+ } else {
1090+ phy_write_register(dev, reg, addr, value);
1091 }
1092+
1093+ return ret;
1094 }
1095
1096+#endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
1097+
1098 static void set_mac_control_register (struct eth_device* dev)
1099 {
1100 unsigned long MAC_CR_Register = 0;
1101- unsigned long Loop_Count = 0, PHY_Ready = 1, Chip_ID;
1102+ unsigned int Loop_Count = 0, PHY_Ready = 1, Chip_ID;
1103 u16 PHY_Status, PHY_Speed, PHY_Duplex, Resolved_Status = 0, Advertise, Link_Partner;
1104
1105- if (CONFIG_MAC1_PHY_SETTING >= 1) {
1106+ if (CONFIG_ASPEED_MAC_PHY_SETTING >= 1) {
1107 MAC_CR_Register = SPEED_100M_MODE_bit | RX_BROADPKT_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit;
1108 }
1109 else {
1110 MAC_CR_Register = SPEED_100M_MODE_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit;
1111 }
1112
1113- if (CONFIG_MAC1_PHY_SETTING != 2) {
1114- Chip_ID = ((phy_read_register (dev, 0x02, 0)) << 16);
1115- Chip_ID |= (phy_read_register (dev, 0x03, 0) & 0xffff);
1116+ if (CONFIG_ASPEED_MAC_PHY_SETTING != 2) {
1117+ Chip_ID = ((phy_read_register (dev, 0x02, g_phy_addr)) << 16);
1118+ Chip_ID |= (phy_read_register (dev, 0x03, g_phy_addr) & 0xffff);
1119 if (((Chip_ID & PHYID_VENDOR_MASK) == PHYID_VENDOR_BROADCOM) ||
1120 ((Chip_ID & PHYID_VENDOR_MODEL_MASK) == PHYID_RTL8201EL)) {
1121- Advertise = phy_read_register (dev, 0x04, 0);
1122- Link_Partner = phy_read_register (dev, 0x05, 0);
1123+ Advertise = phy_read_register (dev, 0x04, g_phy_addr);
1124+ Link_Partner = phy_read_register (dev, 0x05, g_phy_addr);
1125 Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK);
1126 Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK);
1127 if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) {
1128@@ -1456,7 +1490,8 @@ static void set_mac_control_register (struct eth_device* dev)
1129 //Max waiting time = (20 + 2)ms * 250(PHY_LOOP) = 5.5s
1130 do {
1131 udelay (20000);
1132- Resolved_Status = (phy_read_register (dev, 0x11, 0) & RESOLVED_BIT);
1133+ Resolved_Status = (phy_read_register (dev, 0x11, g_phy_addr)
1134+ & RESOLVED_BIT);
1135 Loop_Count++;
1136 if (Loop_Count >= PHY_LOOP) {
1137 PHY_Ready = 0;
1138@@ -1466,7 +1501,7 @@ static void set_mac_control_register (struct eth_device* dev)
1139 } while (Resolved_Status != RESOLVED_BIT);
1140
1141 if (PHY_Ready == 1) {
1142- PHY_Status = phy_read_register (dev, 0x11, 0);
1143+ PHY_Status = phy_read_register (dev, 0x11, g_phy_addr);
1144 PHY_Speed = (PHY_Status & PHY_SPEED_MASK) >> 14;
1145 PHY_Duplex = (PHY_Status & PHY_DUPLEX_MASK) >> 13;
1146
1147@@ -1485,40 +1520,54 @@ static void set_mac_control_register (struct eth_device* dev)
1148 }
1149 //LED Control
1150 // if (Chip_ID == 0x1C) {
1151-// PHY_Status = phy_read_register (dev, 0x18, 0);
1152-// phy_write_register (dev, 0x18, 0, (PHY_Status | 0x09));
1153+// PHY_Status = phy_read_register (dev, 0x18, g_phy_addr);
1154+// phy_write_register (dev, 0x18, g_phy_addr, (PHY_Status | 0x09));
1155 // }
1156 //LED Control D[0], D[6]
1157 // if (Chip_ID == 0x141) {
1158-// PHY_Status = phy_read_register (dev, 0x18, 0);
1159-// phy_write_register (dev, 0x18, 0, ((PHY_Status & ~(0x41)) | 0x01));
1160+// PHY_Status = phy_read_register (dev, 0x18, g_phy_addr);
1161+// phy_write_register (dev, 0x18, g_phy_addr, ((PHY_Status & ~(0x41)) | 0x01));
1162 // }
1163 }
1164- else if (Chip_ID == PHYID_BCM54612E ) {
1165- phy_write_register ( dev, 0x1C, 1, 0x8C00 ); // Disable GTXCLK Clock Delay Enable
1166- phy_write_register ( dev, 0x18, 1, 0xF0E7 ); // Disable RGMII RXD to RXC Skew
1167-
1168- Advertise = phy_read_register (dev, 0x04, 1);
1169- Link_Partner = phy_read_register (dev, 0x05, 1);
1170- Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK);
1171- Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK);
1172- if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) {
1173- MAC_CR_Register |= SPEED_100M_MODE_bit;
1174- MAC_CR_Register |= FULLDUP_bit;
1175+ else if (Chip_ID == PHYID_BCM54612E || Chip_ID == PHYID_BCM54616S) {
1176+ // Disable GTXCLK Clock Delay Enable
1177+ phy_write_register( dev, 0x1C, g_phy_addr, 0x8C00);
1178+ // Disable RGMII RXD to RXC Skew
1179+ phy_write_register( dev, 0x18, g_phy_addr, 0xF0E7);
1180+ // First Switch shadow register selector
1181+ phy_write_register(dev, 0x1C, g_phy_addr, 0x2000);
1182+ PHY_Status = phy_read_register(dev, 0x1C, g_phy_addr);
1183+ PHY_Duplex = (PHY_Status & 0x0080);
1184+ switch (PHY_Status & 0x0018) {
1185+ case 0x0000:
1186+ PHY_Speed = SPEED_1000M;
1187+ break;
1188+ case 0x0008:
1189+ PHY_Speed = SPEED_100M;
1190+ break;
1191+ case 0x0010:
1192+ PHY_Speed = SPEED_10M;
1193+ break;
1194+ default:
1195+ PHY_Speed = SPEED_100M;
1196+ break;
1197 }
1198- else if ((Advertise & Link_Partner) & PHY_100M_HALF) {
1199- MAC_CR_Register |= SPEED_100M_MODE_bit;
1200- MAC_CR_Register &= ~FULLDUP_bit;
1201+ if (PHY_Speed == SPEED_1000M) {
1202+ MAC_CR_Register |= GMAC_MODE_bit;
1203+ } else {
1204+ MAC_CR_Register &= ~GMAC_MODE_bit;
1205+ if (PHY_Speed == SPEED_100M) {
1206+ MAC_CR_Register |= SPEED_100M_MODE_bit;
1207+ } else {
1208+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
1209+ }
1210 }
1211- else if ((Advertise & Link_Partner) & PHY_10M_DUPLEX) {
1212- MAC_CR_Register &= ~SPEED_100M_MODE_bit;
1213+ if (PHY_Duplex) {
1214 MAC_CR_Register |= FULLDUP_bit;
1215- }
1216- else if ((Advertise & Link_Partner) & PHY_10M_HALF) {
1217- MAC_CR_Register &= ~SPEED_100M_MODE_bit;
1218+ } else {
1219 MAC_CR_Register &= ~FULLDUP_bit;
1220 }
1221- }else {
1222+ } else {
1223 printf("Unknow Chip_ID %x\n",Chip_ID);
1224 }
1225 }
1226diff --git a/include/configs/wedge.h b/include/configs/wedge.h
1227new file mode 100644
1228index 0000000..6bb7639
1229--- /dev/null
1230+++ b/include/configs/wedge.h
1231@@ -0,0 +1,350 @@
1232+/*
1233+ * Copyright 2004-present Facebook. All Rights Reserved.
1234+ *
1235+ * This program is free software; you can redistribute it and/or
1236+ * modify it under the terms of the GNU General Public License as
1237+ * published by the Free Software Foundation; either version 2 of
1238+ * the License, or (at your option) any later version.
1239+ *
1240+ * This program is distributed in the hope that it will be useful,
1241+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1242+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1243+ * GNU General Public License for more details.
1244+ *
1245+ * You should have received a copy of the GNU General Public License
1246+ * along with this program; if not, write to the Free Software
1247+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1248+ * MA 02111-1307 USA
1249+ */
1250+
1251+#ifndef __CONFIG_H
1252+#define __CONFIG_H
1253+
1254+/* Uncommit the following line to enable JTAG in u-boot */
1255+//#define CONFIG_ASPEED_ENABLE_JTAG
1256+
1257+/*
1258+ * High Level Configuration Options
1259+ * (easy to change)
1260+ */
1261+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
1262+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
1263+//#define CONFIG_FPGA_ASPEED 1
1264+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
1265+#define CONFIG_ASPEED 1
1266+#define CONFIG_AST2400 1
1267+//#define CONFIG_AST1070 1
1268+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
1269+#define CONFIG_FLASH_SPI
1270+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
1271+#undef CONFIG_2SPIFLASH
1272+#undef CONFIG_ASPEED_SLT
1273+#define CONFIG_FLASH_AST2300
1274+//#define CONFIG_FLASH_AST2300_DMA
1275+//#define CONFIG_FLASH_SPIx2_Dummy
1276+//#define CONFIG_FLASH_SPIx4_Dummy
1277+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
1278+
1279+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
1280+#define CONFIG_MISC_INIT_R
1281+
1282+/*
1283+ * DRAM Config
1284+ *
1285+ * 1. DRAM Size //
1286+ * CONFIG_DRAM_512MBIT // 512M bit
1287+ * CONFIG_DRAM_1GBIT // 1G bit (default)
1288+ * CONFIG_DRAM_2GBIT // 2G bit
1289+ * CONFIG_DRAM_4GBIT // 4G bit
1290+ * 2. DRAM Speed //
1291+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
1292+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
1293+ * 3. VGA Mode
1294+ * CONFIG_CRT_DISPLAY // define to disable VGA function
1295+ * 4. ECC Function enable
1296+ * CONFIG_DRAM_ECC // define to enable ECC function
1297+ * 5. UART Debug Message
1298+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
1299+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
1300+ */
1301+
1302+//1. DRAM Size
1303+//#define CONFIG_DRAM_512MBIT
1304+#define CONFIG_DRAM_1GBIT
1305+//#define CONFIG_DRAM_2GBIT
1306+//#define CONFIG_DRAM_4GBIT
1307+//2. DRAM Speed
1308+//#define CONFIG_DRAM_336
1309+#define CONFIG_DRAM_408
1310+//3. VGA Mode
1311+//#define CONFIG_CRT_DISPLAY
1312+//4. ECC Function enable
1313+//#define CONFIG_DRAM_ECC
1314+//5. UART Debug Message
1315+#define CONFIG_DRAM_UART_OUT
1316+//#define CONFIG_DRAM_UART_38400
1317+
1318+
1319+
1320+/*
1321+ * Environment Config
1322+ */
1323+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
1324+#define CONFIG_SETUP_MEMORY_TAGS 1
1325+#define CONFIG_INITRD_TAG 1
1326+#define CONFIG_BOOTARGS "debug console=ttyS2,9600n8 root=/dev/ram rw"
1327+#define CONFIG_UPDATE "tftp 40800000 ast2400.scr; so 40800000'"
1328+
1329+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
1330+#define CONFIG_AUTOBOOT_KEYED
1331+#define CONFIG_AUTOBOOT_PROMPT \
1332+ "autoboot in %d seconds (stop with 'Delete' key)...\n", bootdelay
1333+#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x5b\x33\x7e" /* 'Delete', ESC[3~ */
1334+#define CONFIG_ZERO_BOOTDELAY_CHECK
1335+
1336+#ifdef CONFIG_FLASH_AST2300
1337+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
1338+#else
1339+#ifdef CONFIG_SYS_FLASH_CFI
1340+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
1341+#else
1342+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
1343+#endif
1344+#endif
1345+#define CONFIG_BOOTFILE "all.bin"
1346+#define CONFIG_ENV_OVERWRITE
1347+
1348+/*
1349+ * Command line configuration.
1350+ */
1351+#include <config_cmd_default.h>
1352+
1353+#define CONFIG_CMD_DFL
1354+#define CONFIG_CMD_ENV
1355+#define CONFIG_CMD_FLASH
1356+#define CONFIG_CMD_MII
1357+#define CONFIG_CMD_NET
1358+#define CONFIG_CMD_PING
1359+#define CONFIG_CMD_I2C
1360+#define CONFIG_CMD_EEPROM
1361+#define CONFIG_CMD_NETTEST
1362+#define CONFIG_CMD_SLT
1363+
1364+/*
1365+ * CPU Setting
1366+ */
1367+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
1368+
1369+/*
1370+ * Size of malloc() pool
1371+ */
1372+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
1373+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
1374+
1375+/*
1376+ * Stack sizes, The stack sizes are set up in start.S using the settings below
1377+ */
1378+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
1379+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
1380+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
1381+
1382+/*
1383+ * Memory Configuration
1384+ */
1385+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
1386+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
1387+#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
1388+
1389+#define CONFIG_SYS_SDRAM_BASE 0x40000000
1390+
1391+/*
1392+ * FLASH Configuration
1393+ */
1394+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
1395+
1396+#ifdef CONFIG_FLASH_AST2300
1397+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
1398+#else
1399+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
1400+#endif
1401+
1402+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
1403+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
1404+
1405+#define CONFIG_SYS_MAX_FLASH_BANKS 1
1406+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
1407+
1408+#define CONFIG_ENV_IS_IN_FLASH 1
1409+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
1410+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
1411+
1412+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
1413+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
1414+
1415+#else /* SPI Flash */
1416+
1417+#ifdef CONFIG_FLASH_AST2300
1418+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
1419+#else
1420+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
1421+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
1422+#define PHYS_FLASH_2_BASE 0x10000000
1423+#endif
1424+
1425+#ifdef CONFIG_2SPIFLASH
1426+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
1427+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
1428+#define CONFIG_SYS_MAX_FLASH_BANKS 2
1429+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
1430+
1431+#define CONFIG_ENV_IS_IN_FLASH 1
1432+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
1433+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
1434+#else
1435+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
1436+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
1437+#define CONFIG_SYS_MAX_FLASH_BANKS 1
1438+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
1439+
1440+#define CONFIG_ENV_IS_IN_FLASH 1
1441+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
1442+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
1443+#define CONFIG_ASPEED_WRITE_DEFAULT_ENV
1444+#endif
1445+
1446+#endif
1447+
1448+#define __LITTLE_ENDIAN 1
1449+
1450+#define CONFIG_MONITOR_BASE TEXT_BASE
1451+#define CONFIG_MONITOR_LEN (192 << 10)
1452+
1453+/* timeout values are in ticks */
1454+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
1455+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
1456+
1457+/*
1458+ * Miscellaneous configurable options
1459+ */
1460+#define CONFIG_SYS_LONGHELP /* undef to save memory */
1461+
1462+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
1463+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1464+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
1465+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
1466+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1467+
1468+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
1469+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
1470+
1471+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
1472+
1473+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
1474+#define CONFIG_SYS_HZ 1000
1475+#define CONFIG_ASPEED_TIMER_CLK (1*1000*1000) /* use external clk (1M) */
1476+
1477+/*
1478+ * Serial Configuration
1479+ */
1480+#define CONFIG_SYS_NS16550
1481+#define CONFIG_SYS_NS16550_SERIAL
1482+#define CONFIG_SYS_NS16550_MEM32
1483+#define CONFIG_SYS_NS16550_REG_SIZE -4
1484+#define CONFIG_SYS_NS16550_CLK 24000000
1485+#define CONFIG_SYS_NS16550_COM1 0x1e783000
1486+#define CONFIG_SYS_NS16550_COM2 0x1e784000
1487+#define CONFIG_SYS_NS16550_COM3 0x1e78e000
1488+#define CONFIG_SYS_LOADS_BAUD_CHANGE
1489+#define CONFIG_CONS_INDEX 2
1490+#define CONFIG_BAUDRATE 9600
1491+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
1492+#define CONFIG_ASPEED_COM 0x1e78e000 // COM3
1493+#define CONFIG_ASPEED_COM_IER (CONFIG_ASPEED_COM + 0x4)
1494+#define CONFIG_ASPEED_COM_IIR (CONFIG_ASPEED_COM + 0x8)
1495+#define CONFIG_ASPEED_COM_LCR (CONFIG_ASPEED_COM + 0xc)
1496+
1497+/*
1498+ * USB device configuration
1499+ */
1500+/*
1501+#define CONFIG_USB_DEVICE 1
1502+#define CONFIG_USB_TTY 1
1503+
1504+#define CONFIG_USBD_VENDORID 0x1234
1505+#define CONFIG_USBD_PRODUCTID 0x5678
1506+#define CONFIG_USBD_MANUFACTURER "Siemens"
1507+#define CONFIG_USBD_PRODUCT_NAME "SX1"
1508+*/
1509+
1510+/*
1511+ * I2C configuration
1512+ */
1513+#define CONFIG_HARD_I2C
1514+#define CONFIG_SYS_I2C_SPEED 100000
1515+#define CONFIG_SYS_I2C_SLAVE 1
1516+#define CONFIG_DRIVER_ASPEED_I2C
1517+
1518+/*
1519+* EEPROM configuration
1520+*/
1521+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
1522+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
1523+
1524+#define __BYTE_ORDER __LITTLE_ENDIAN
1525+#define __LITTLE_ENDIAN_BITFIELD
1526+
1527+/*
1528+ * NIC configuration
1529+ */
1530+#define CONFIG_ASPEEDNIC
1531+#define CONFIG_NET_MULTI
1532+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
1533+#define CONFIG_MAC2_ENABLE
1534+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
1535+/*
1536+*-------------------------------------------------------------------------------
1537+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
1538+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
1539+* inform kernel driver.
1540+* The meanings of the 2 bits are:
1541+* 00(0): Dedicated PHY
1542+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
1543+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
1544+* 11: Reserved
1545+*
1546+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
1547+* 0: Dedicated PHY
1548+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
1549+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
1550+* 3: Reserved
1551+*-------------------------------------------------------------------------------
1552+*/
1553+#define CONFIG_MAC1_PHY_SETTING 0
1554+#define CONFIG_MAC2_PHY_SETTING 0
1555+#define CONFIG_ASPEED_MAC_NUMBER 2
1556+#define CONFIG_ASPEED_MAC_CONFIG 2 // config MAC2
1557+#define _PHY_SETTING_CONCAT(mac) CONFIG_MAC##mac##_PHY_SETTING
1558+#define _GET_MAC_PHY_SETTING(mac) _PHY_SETTING_CONCAT(mac)
1559+#define CONFIG_ASPEED_MAC_PHY_SETTING \
1560+ _GET_MAC_PHY_SETTING(CONFIG_ASPEED_MAC_CONFIG)
1561+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
1562+#define CONFIG_RANDOM_MACADDR
1563+//#define CONFIG_GATEWAYIP 192.168.0.1
1564+//#define CONFIG_NETMASK 255.255.255.0
1565+//#define CONFIG_IPADDR 192.168.0.45
1566+//#define CONFIG_SERVERIP 192.168.0.81
1567+
1568+/*
1569+ * SLT
1570+ */
1571+/*
1572+#define CONFIG_SLT
1573+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
1574+*/
1575+
1576+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
1577+
1578+#define CONFIG_ASPEED_ENABLE_WATCHDOG
1579+#define CONFIG_ASPEED_WATCHDOG_TIMEOUT (5*60) // 5m
1580+
1581+#endif /* __CONFIG_H */
1582diff --git a/include/configs/palmetto.h b/include/configs/palmetto.h
1583new file mode 100644
1584index 0000000..6bb7639
1585--- /dev/null
1586+++ b/include/configs/palmetto.h
1587@@ -0,0 +1,350 @@
1588+/*
1589+ * Copyright 2004-present Facebook. All Rights Reserved.
1590+ *
1591+ * This program is free software; you can redistribute it and/or
1592+ * modify it under the terms of the GNU General Public License as
1593+ * published by the Free Software Foundation; either version 2 of
1594+ * the License, or (at your option) any later version.
1595+ *
1596+ * This program is distributed in the hope that it will be useful,
1597+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1598+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1599+ * GNU General Public License for more details.
1600+ *
1601+ * You should have received a copy of the GNU General Public License
1602+ * along with this program; if not, write to the Free Software
1603+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1604+ * MA 02111-1307 USA
1605+ */
1606+
1607+#ifndef __CONFIG_H
1608+#define __CONFIG_H
1609+
1610+/* Uncommit the following line to enable JTAG in u-boot */
1611+//#define CONFIG_ASPEED_ENABLE_JTAG
1612+
1613+/*
1614+ * High Level Configuration Options
1615+ * (easy to change)
1616+ */
1617+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
1618+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
1619+//#define CONFIG_FPGA_ASPEED 1
1620+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
1621+#define CONFIG_ASPEED 1
1622+#define CONFIG_AST2400 1
1623+//#define CONFIG_AST1070 1
1624+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
1625+#define CONFIG_FLASH_SPI
1626+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
1627+#undef CONFIG_2SPIFLASH
1628+#undef CONFIG_ASPEED_SLT
1629+#define CONFIG_FLASH_AST2300
1630+//#define CONFIG_FLASH_AST2300_DMA
1631+//#define CONFIG_FLASH_SPIx2_Dummy
1632+//#define CONFIG_FLASH_SPIx4_Dummy
1633+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
1634+
1635+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
1636+#define CONFIG_MISC_INIT_R
1637+
1638+/*
1639+ * DRAM Config
1640+ *
1641+ * 1. DRAM Size //
1642+ * CONFIG_DRAM_512MBIT // 512M bit
1643+ * CONFIG_DRAM_1GBIT // 1G bit (default)
1644+ * CONFIG_DRAM_2GBIT // 2G bit
1645+ * CONFIG_DRAM_4GBIT // 4G bit
1646+ * 2. DRAM Speed //
1647+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
1648+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
1649+ * 3. VGA Mode
1650+ * CONFIG_CRT_DISPLAY // define to disable VGA function
1651+ * 4. ECC Function enable
1652+ * CONFIG_DRAM_ECC // define to enable ECC function
1653+ * 5. UART Debug Message
1654+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
1655+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
1656+ */
1657+
1658+//1. DRAM Size
1659+//#define CONFIG_DRAM_512MBIT
1660+#define CONFIG_DRAM_1GBIT
1661+//#define CONFIG_DRAM_2GBIT
1662+//#define CONFIG_DRAM_4GBIT
1663+//2. DRAM Speed
1664+//#define CONFIG_DRAM_336
1665+#define CONFIG_DRAM_408
1666+//3. VGA Mode
1667+//#define CONFIG_CRT_DISPLAY
1668+//4. ECC Function enable
1669+//#define CONFIG_DRAM_ECC
1670+//5. UART Debug Message
1671+#define CONFIG_DRAM_UART_OUT
1672+//#define CONFIG_DRAM_UART_38400
1673+
1674+
1675+
1676+/*
1677+ * Environment Config
1678+ */
1679+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
1680+#define CONFIG_SETUP_MEMORY_TAGS 1
1681+#define CONFIG_INITRD_TAG 1
Brad Bishop9c023572015-10-29 13:58:59 -05001682+#define CONFIG_BOOTARGS "console=ttyS4,38400n8 root=/dev/ram rw"
Brad Bishop89451ae2015-10-22 15:38:02 -05001683+#define CONFIG_UPDATE "tftp 40800000 ast2400.scr; so 40800000'"
1684+
1685+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
1686+#define CONFIG_AUTOBOOT_KEYED
1687+#define CONFIG_AUTOBOOT_PROMPT \
1688+ "autoboot in %d seconds (stop with 'Delete' key)...\n", bootdelay
1689+#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x5b\x33\x7e" /* 'Delete', ESC[3~ */
1690+#define CONFIG_ZERO_BOOTDELAY_CHECK
1691+
1692+#ifdef CONFIG_FLASH_AST2300
1693+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
1694+#else
1695+#ifdef CONFIG_SYS_FLASH_CFI
1696+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
1697+#else
1698+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
1699+#endif
1700+#endif
1701+#define CONFIG_BOOTFILE "all.bin"
1702+#define CONFIG_ENV_OVERWRITE
1703+
1704+/*
1705+ * Command line configuration.
1706+ */
1707+#include <config_cmd_default.h>
1708+
1709+#define CONFIG_CMD_DFL
1710+#define CONFIG_CMD_ENV
1711+#define CONFIG_CMD_FLASH
1712+#define CONFIG_CMD_MII
1713+#define CONFIG_CMD_NET
1714+#define CONFIG_CMD_PING
1715+#define CONFIG_CMD_I2C
1716+#define CONFIG_CMD_EEPROM
1717+#define CONFIG_CMD_NETTEST
1718+#define CONFIG_CMD_SLT
1719+
1720+/*
1721+ * CPU Setting
1722+ */
1723+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
1724+
1725+/*
1726+ * Size of malloc() pool
1727+ */
1728+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
1729+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
1730+
1731+/*
1732+ * Stack sizes, The stack sizes are set up in start.S using the settings below
1733+ */
1734+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
1735+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
1736+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
1737+
1738+/*
1739+ * Memory Configuration
1740+ */
1741+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
1742+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
1743+#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
1744+
1745+#define CONFIG_SYS_SDRAM_BASE 0x40000000
1746+
1747+/*
1748+ * FLASH Configuration
1749+ */
1750+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
1751+
1752+#ifdef CONFIG_FLASH_AST2300
1753+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
1754+#else
1755+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
1756+#endif
1757+
1758+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
1759+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
1760+
1761+#define CONFIG_SYS_MAX_FLASH_BANKS 1
1762+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
1763+
1764+#define CONFIG_ENV_IS_IN_FLASH 1
1765+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
1766+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
1767+
1768+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
1769+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
1770+
1771+#else /* SPI Flash */
1772+
1773+#ifdef CONFIG_FLASH_AST2300
1774+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
1775+#else
1776+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
1777+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
1778+#define PHYS_FLASH_2_BASE 0x10000000
1779+#endif
1780+
1781+#ifdef CONFIG_2SPIFLASH
1782+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
1783+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
1784+#define CONFIG_SYS_MAX_FLASH_BANKS 2
1785+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
1786+
1787+#define CONFIG_ENV_IS_IN_FLASH 1
1788+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
1789+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
1790+#else
1791+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
1792+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
1793+#define CONFIG_SYS_MAX_FLASH_BANKS 1
1794+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
1795+
1796+#define CONFIG_ENV_IS_IN_FLASH 1
1797+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
1798+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
1799+#define CONFIG_ASPEED_WRITE_DEFAULT_ENV
1800+#endif
1801+
1802+#endif
1803+
1804+#define __LITTLE_ENDIAN 1
1805+
1806+#define CONFIG_MONITOR_BASE TEXT_BASE
1807+#define CONFIG_MONITOR_LEN (192 << 10)
1808+
1809+/* timeout values are in ticks */
1810+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
1811+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
1812+
1813+/*
1814+ * Miscellaneous configurable options
1815+ */
1816+#define CONFIG_SYS_LONGHELP /* undef to save memory */
1817+
1818+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
1819+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1820+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
1821+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
1822+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1823+
1824+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
1825+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
1826+
1827+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
1828+
1829+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
1830+#define CONFIG_SYS_HZ 1000
1831+#define CONFIG_ASPEED_TIMER_CLK (1*1000*1000) /* use external clk (1M) */
1832+
1833+/*
1834+ * Serial Configuration
1835+ */
1836+#define CONFIG_SYS_NS16550
1837+#define CONFIG_SYS_NS16550_SERIAL
1838+#define CONFIG_SYS_NS16550_MEM32
1839+#define CONFIG_SYS_NS16550_REG_SIZE -4
1840+#define CONFIG_SYS_NS16550_CLK 24000000
1841+#define CONFIG_SYS_NS16550_COM1 0x1e783000
1842+#define CONFIG_SYS_NS16550_COM2 0x1e784000
1843+#define CONFIG_SYS_NS16550_COM3 0x1e78e000
1844+#define CONFIG_SYS_LOADS_BAUD_CHANGE
1845+#define CONFIG_CONS_INDEX 2
1846+#define CONFIG_BAUDRATE 38400
1847+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
1848+#define CONFIG_ASPEED_COM 0x1e784000 // UART5
1849+#define CONFIG_ASPEED_COM_IER (CONFIG_ASPEED_COM + 0x4)
1850+#define CONFIG_ASPEED_COM_IIR (CONFIG_ASPEED_COM + 0x8)
1851+#define CONFIG_ASPEED_COM_LCR (CONFIG_ASPEED_COM + 0xc)
1852+
1853+/*
1854+ * USB device configuration
1855+ */
1856+/*
1857+#define CONFIG_USB_DEVICE 1
1858+#define CONFIG_USB_TTY 1
1859+
1860+#define CONFIG_USBD_VENDORID 0x1234
1861+#define CONFIG_USBD_PRODUCTID 0x5678
1862+#define CONFIG_USBD_MANUFACTURER "Siemens"
1863+#define CONFIG_USBD_PRODUCT_NAME "SX1"
1864+*/
1865+
1866+/*
1867+ * I2C configuration
1868+ */
1869+#define CONFIG_HARD_I2C
1870+#define CONFIG_SYS_I2C_SPEED 100000
1871+#define CONFIG_SYS_I2C_SLAVE 1
1872+#define CONFIG_DRIVER_ASPEED_I2C
1873+
1874+/*
1875+* EEPROM configuration
1876+*/
1877+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
1878+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
1879+
1880+#define __BYTE_ORDER __LITTLE_ENDIAN
1881+#define __LITTLE_ENDIAN_BITFIELD
1882+
1883+/*
1884+ * NIC configuration
1885+ */
1886+#define CONFIG_ASPEEDNIC
1887+#define CONFIG_NET_MULTI
1888+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
1889+#define CONFIG_MAC2_ENABLE
1890+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
1891+/*
1892+*-------------------------------------------------------------------------------
1893+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
1894+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
1895+* inform kernel driver.
1896+* The meanings of the 2 bits are:
1897+* 00(0): Dedicated PHY
1898+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
1899+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
1900+* 11: Reserved
1901+*
1902+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
1903+* 0: Dedicated PHY
1904+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
1905+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
1906+* 3: Reserved
1907+*-------------------------------------------------------------------------------
1908+*/
1909+#define CONFIG_MAC1_PHY_SETTING 2
1910+#define CONFIG_MAC2_PHY_SETTING 0
1911+#define CONFIG_ASPEED_MAC_NUMBER 1
1912+#define CONFIG_ASPEED_MAC_CONFIG 1 // config MAC1
1913+#define _PHY_SETTING_CONCAT(mac) CONFIG_MAC##mac##_PHY_SETTING
1914+#define _GET_MAC_PHY_SETTING(mac) _PHY_SETTING_CONCAT(mac)
1915+#define CONFIG_ASPEED_MAC_PHY_SETTING \
1916+ _GET_MAC_PHY_SETTING(CONFIG_ASPEED_MAC_CONFIG)
1917+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
1918+#define CONFIG_RANDOM_MACADDR
1919+//#define CONFIG_GATEWAYIP 192.168.0.1
1920+//#define CONFIG_NETMASK 255.255.255.0
1921+//#define CONFIG_IPADDR 192.168.0.45
1922+//#define CONFIG_SERVERIP 192.168.0.81
1923+
1924+/*
1925+ * SLT
1926+ */
1927+/*
1928+#define CONFIG_SLT
1929+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
1930+*/
1931+
1932+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
1933+
1934+#define CONFIG_ASPEED_ENABLE_WATCHDOG
1935+#define CONFIG_ASPEED_WATCHDOG_TIMEOUT (5*60) // 5m
1936+
1937+#endif /* __CONFIG_H */