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gerrit.openbmc.org / openbmc / meta-ibm / f7293c7c03028c1a457722dc3f59b24fd0c0747c / . / meta-palmetto / recipes-bsp / u-boot / files / patch-2013.07 / 0000-u-boot-aspeed-064.patch
blob: 7d8c805c46c1d85eafd7b53bb5d81cfa97380793 [file] [log] [blame]
Brad Bishop1fcc6132015-10-08 15:20:57 -0400[diff] [blame]1diff --git a/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H b/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H
2new file mode 100644
3index 0000000..44b7540
4--- /dev/null
5+++ b/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H
6@@ -0,0 +1,641 @@
7+/*
8+ * This program is distributed in the hope that it will be useful,
9+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
10+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11+ * GNU General Public License for more details.
12+ *
13+ * You should have received a copy of the GNU General Public License
14+ * along with this program; if not, write to the Free Software
15+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16+ */
17+#ifndef COMMINF_H
18+#define COMMINF_H
19+
20+#include "SWFUNC.H"
21+
22+#if defined(LinuxAP)
23+#endif
24+#ifdef SLT_UBOOT
25+#endif
26+#ifdef SLT_DOS
27+ #include <stdio.h>
28+ #include <time.h>
29+ #include <dos.h> // For delay()
30+#endif
31+
32+#include "TYPEDEF.H"
33+#include "LIB.H"
34+
35+//---------------------------------------------------------
36+// Print Message
37+//---------------------------------------------------------
38+// for function
39+#define FP_LOG 0
40+#define FP_IO 1
41+#define STD_OUT 2
42+
43+#ifdef SLT_UBOOT
44+ #define PRINT printf
45+ #define OUT_OBJ
46+ #define FILE_VAR
47+
48+ #define GET_OBJ( i ) \
49+ do { \
50+ if ( i != STD_OUT ) \
51+ return; \
52+ } while ( 0 );
53+
54+#else
55+ #define PRINT fprintf
56+ #define OUT_OBJ fp,
57+ #define FILE_VAR FILE *fp;
58+
59+ #define GET_OBJ( i ) \
60+ switch( i ) { \
61+ case FP_LOG: \
62+ fp = fp_log; \
63+ break; \
64+ case FP_IO: \
65+ fp = fp_io; \
66+ break; \
67+ case STD_OUT: \
68+ fp = stdout; \
69+ break; \
70+ default : break; \
71+ }
72+#endif
73+
74+//---------------------------------------------------------
75+// Function
76+//---------------------------------------------------------
77+#ifdef SLT_UBOOT
78+ #define DELAY( x ) udelay( x * 1000 ) // For Uboot, the unit of udelay() is us.
79+ #define GET_CAHR getc
80+#endif
81+#ifdef SLT_DOS
82+ #define DELAY( x ) delay( x ) // For DOS, the unit of delay() is ms.
83+ #define GET_CAHR getchar
84+#endif
85+
86+//---------------------------------------------------------
87+// Default argument
88+//---------------------------------------------------------
89+#define DEF_USER_DEF_PACKET_VAL 0x66666666 //0xff00ff00, 0xf0f0f0f0, 0xcccccccc, 0x55aa55aa, 0x5a5a5a5a, 0x66666666
90+#define DEF_IOTIMINGBUND 5 //0/1/3/5/7
91+#define DEF_PHY_ADR 0
92+#define DEF_TESTMODE 0 //[0]0: no burst mode, 1: 0xff, 2: 0x55, 3: random, 4: ARP, 5: ARP, 6: IO timing, 7: IO timing+IO Strength
93+#define DEF_LOOP_MAX 1
94+#define DEF_MAC_LOOP_BACK 0 //GCtrl bit6
95+#define DEF_SKIP_CHECK_PHY 0 //GCtrl bit4
96+#define DEF_INIT_PHY 1 //GCtrl bit3
97+
98+#define SET_1GBPS 0 // 1G bps
99+#define SET_100MBPS 1 // 100M bps
100+#define SET_10MBPS 2 // 10M bps
101+#define SET_1G_100M_10MBPS 3 // 1G and 100M and 10M bps
102+#define DEF_SPEED SET_1G_100M_10MBPS
103+#define DEF_ARPNUMCNT 0
104+
105+//---------------------------------------------------------
106+// MAC information
107+//---------------------------------------------------------
108+#if ( AST1010_IOMAP == 1 )
109+ // AST1010 only has a MAC
110+ #define MAC_BASE1 AST_MAC1_BASE
111+ #define MAC_BASE2 AST_MAC1_BASE
112+ #define MAC_BASE3 AST_MAC1_BASE
113+ #define MAC_BASE4 AST_MAC1_BASE
114+#endif
115+
116+#if ( AST1010_IOMAP == 2 )
117+ // AST1010 only has a MAC
118+ #define MAC_BASE1 0x0830000
119+ #define MAC_BASE2 0x0830000
120+ #define MAC_BASE3 0x0830000
121+ #define MAC_BASE4 0x0830000
122+#endif
123+
124+#ifndef AST1010_IOMAP
125+ #define MAC_BASE1 0x1e660000
126+ #define MAC_BASE2 0x1e680000
127+ #define MAC_BASE3 0x1e670000
128+ #define MAC_BASE4 0x1e690000
129+#endif
130+
131+#define MDC_Thres 0x3f
132+#define MAC_PHYWr 0x08000000
133+#define MAC_PHYRd 0x04000000
134+
135+#define MAC_PHYWr_New 0x00009400
136+#define MAC_PHYRd_New 0x00009800
137+#define MAC_PHYBusy_New 0x00008000
138+
139+//#define MAC_30h 0x00001010
140+//#define MAC_34h 0x00000000
141+//#define MAC_38h 0x00d22f00 //default 0x22f00
142+//#define MAC_38h 0x00022f00 //default 0x22f00
143+
144+#define MAC_40h 0x40000000
145+
146+#ifdef Enable_BufMerge
147+ #define MAC_48h 0x007702F1 //default 0xf1
148+#else
149+ #ifdef AST1010_IOMAP
150+ #define MAC_48h 0x000002F1 //default 0xf1
151+ #else
152+ #define MAC_48h 0x000001F1 //default 0xf1
153+ #endif
154+#endif
155+
156+//---------------------------------------------------------
157+// Data information
158+//---------------------------------------------------------
159+#ifdef SelectSimpleBoundary
160+ #define ZeroCopy_OFFSET 0
161+#else
162+ #define ZeroCopy_OFFSET ( (BurstEnable) ? 0 : 2 )
163+#endif
164+
165+// --------------------------------- DRAM_MapAdr = TDES_BASE1
166+// | TX descriptor ring #1 |
167+// ------------------------- DRAM_MapAdr + 0x040000 = RDES_BASE1
168+// | RX descriptor ring #1 |
169+// ------------------------- DRAM_MapAdr + 0x080000 = TDES_BASE2
170+// | TX descriptor ring #2 |
171+// ------------------------- DRAM_MapAdr + 0x0C0000 = RDES_BASE2
172+// | RX descriptor ring #2 |
173+// --------------------------------- DRAM_MapAdr + 0x100000 = DMA_BASE -------------------------
174+// | #1 | \ | #1 Tx |
175+// DMA buffer | | DMA_BufSize | LOOP = 0 |
176+// ( Tx/Rx ) ------------------------- / --------------------------------------------------
177+// | #2 | | #2 Rx | #2 Tx |
178+// | | | LOOP = 0 | LOOP = 1 |
179+// ------------------------- --------------------------------------------------
180+// | #3 | | #3 Rx |
181+// | | | LOOP = 1 |
182+// ------------------------- -------------------------
183+// | #4 | ..........
184+// | |
185+// -------------------------
186+// | #5 |
187+// | |
188+// -------------------------
189+// | #6 |
190+// | |
191+// -------------------------
192+// .
193+// .
194+// -------------------------
195+// | #n, n = DMA_BufNum |
196+// | |
197+// ---------------------------------
198+
199+#if ( AST1010_IOMAP == 1 )
200+ #define DRAM_MapAdr ( CONFIG_DRAM_SWAP_BASE + 0x00200000 ) // We use 0xA00000 to 0xEFFFFF
201+ #define CPU_BUS_ADDR_SDRAM_OFFSET 0x01000000 // In ReMapping function, MAC engine need Bus address
202+ // But Coldfire need CPU address, so need to do offset
203+#endif
204+
205+#if ( AST1010_IOMAP == 2 )
206+ #define DRAM_MapAdr 0x0A00000 // We use 0xA00000 to 0xEFFFFF
207+ #define CPU_BUS_ADDR_SDRAM_OFFSET 0
208+#endif
209+
210+#ifndef AST1010_IOMAP
211+ #ifdef AST3200_IOMAP
212+ #define DRAM_MapAdr 0x80000000
213+ #else
214+ #define DRAM_MapAdr 0x44000000
215+ #endif
216+
217+ #define CPU_BUS_ADDR_SDRAM_OFFSET 0
218+#endif
219+
220+ #define TDES_BASE1 ( 0x00000000 + DRAM_MapAdr )
221+ #define RDES_BASE1 ( 0x00040000 + DRAM_MapAdr )
222+ #define TDES_BASE2 ( 0x00080000 + DRAM_MapAdr )
223+ #define RDES_BASE2 ( 0x000C0000 + DRAM_MapAdr )
224+
225+ #define TDES_IniVal ( 0xb0000000 + FRAME_LEN_Cur )
226+ #define RDES_IniVal ( 0x00000fff )
227+ #define EOR_IniVal ( 0x40008000 )
228+ #define HWOwnTx(dat) ( (dat) & 0x80000000 )
229+ #define HWOwnRx(dat) ( !((dat) & 0x80000000) )
230+ #define HWEOR(dat) ( dat & 0x40000000 )
231+
232+//---------------------------------------------------------
233+// Error Flag Bits
234+//---------------------------------------------------------
235+#define Err_MACMode ( 1 << 0 ) // MAC interface mode mismatch
236+#define Err_PHY_Type ( 1 << 1 ) // Unidentifiable PHY
237+#define Err_MALLOC_FrmSize ( 1 << 2 ) // Malloc fail at frame size buffer
238+#define Err_MALLOC_LastWP ( 1 << 3 ) // Malloc fail at last WP buffer
239+#define Err_Check_Buf_Data ( 1 << 4 ) // Received data mismatch
240+#define Err_Check_Des ( 1 << 5 ) // Descriptor error
241+#define Err_NCSI_LinkFail ( 1 << 6 ) // NCSI packet retry number over flows
242+#define Err_NCSI_Check_TxOwnTimeOut ( 1 << 7 ) // Time out of checking Tx owner bit in NCSI packet
243+#define Err_NCSI_Check_RxOwnTimeOut ( 1 << 8 ) // Time out of checking Rx owner bit in NCSI packet
244+#define Err_NCSI_Check_ARPOwnTimeOut ( 1 << 9 ) // Time out of checking ARP owner bit in NCSI packet
245+#define Err_NCSI_No_PHY ( 1 << 10 ) // Can not find NCSI PHY
246+#define Err_NCSI_Channel_Num ( 1 << 11 ) // NCSI Channel Number Mismatch
247+#define Err_NCSI_Package_Num ( 1 << 12 ) // NCSI Package Number Mismatch
248+#define Err_PHY_TimeOut ( 1 << 13 ) // Time out of read/write/reset PHY register
249+#define Err_RXBUF_UNAVA ( 1 << 14 ) // MAC00h[2]:Receiving buffer unavailable
250+#define Err_RPKT_LOST ( 1 << 15 ) // MAC00h[3]:Received packet lost due to RX FIFO full
251+#define Err_NPTXBUF_UNAVA ( 1 << 16 ) // MAC00h[6]:Normal priority transmit buffer unavailable
252+#define Err_TPKT_LOST ( 1 << 17 ) // MAC00h[7]:Packets transmitted to Ethernet lost
253+#define Err_DMABufNum ( 1 << 18 ) // DMA Buffer is not enough
254+#define Err_IOMargin ( 1 << 19 ) // IO timing margin is not enough
255+#define Err_IOMarginOUF ( 1 << 20 ) // IO timing testing out of boundary
256+#define Err_MHCLK_Ratio ( 1 << 21 ) // Error setting of MAC AHB bus clock (SCU08[18:16])
257+
258+#define Check_Des_TxOwnTimeOut ( 1 << 0 ) // Time out of checking Tx owner bit
259+#define Check_Des_RxOwnTimeOut ( 1 << 1 ) // Time out of checking Rx owner bit
260+#define Check_Des_RxErr ( 1 << 2 ) // Input signal RxErr
261+#define Check_Des_OddNibble ( 1 << 3 ) // Nibble bit happen
262+#define Check_Des_CRC ( 1 << 4 ) // CRC error of frame
263+#define Check_Des_RxFIFOFull ( 1 << 5 ) // Rx FIFO full
264+#define Check_Des_FrameLen ( 1 << 6 ) // Frame length mismatch
265+
266+#define NCSI_LinkFail_Get_Version_ID ( 1 << 0 ) // Time out when Get Version ID
267+#define NCSI_LinkFail_Get_Capabilities ( 1 << 1 ) // Time out when Get Capabilities
268+#define NCSI_LinkFail_Select_Active_Package ( 1 << 2 ) // Time out when Select Active Package
269+#define NCSI_LinkFail_Enable_Set_MAC_Address ( 1 << 3 ) // Time out when Enable Set MAC Address
270+#define NCSI_LinkFail_Enable_Broadcast_Filter ( 1 << 4 ) // Time out when Enable Broadcast Filter
271+#define NCSI_LinkFail_Enable_Network_TX ( 1 << 5 ) // Time out when Enable Network TX
272+#define NCSI_LinkFail_Enable_Channel ( 1 << 6 ) // Time out when Enable Channel
273+#define NCSI_LinkFail_Disable_Network_TX ( 1 << 7 ) // Time out when Disable Network TX
274+#define NCSI_LinkFail_Disable_Channel ( 1 << 8 ) // Time out when Disable Channel
275+
276+//---------------------------------------------------------
277+// SCU information
278+//---------------------------------------------------------
279+#if ( AST1010_IOMAP == 1 )
280+ #define SCU_BASE AST_SCU_BASE
281+#endif
282+#if ( AST1010_IOMAP == 2 )
283+ #define SCU_BASE 0x0841000
284+#endif
285+
286+#ifndef AST1010_IOMAP
287+ #define SCU_BASE 0x1e6e2000
288+#endif
289+
290+#define SCU_48h_AST1010 0x00000200
291+#define SCU_48h_AST2300 0x00222255
292+
293+//#ifdef SLT_DOS
294+// #define SCU_80h 0x00000000
295+// #define SCU_88h 0x00000000
296+// #define SCU_90h 0x00000000
297+// #define SCU_74h 0x00000000
298+//#else
299+// #define SCU_80h 0x0000000f //AST2300[3:0]MAC1~4 PHYLINK
300+// #define SCU_88h 0xc0000000 //AST2300[31]MAC1 MDIO, [30]MAC1 MDC
301+// #define SCU_90h 0x00000004 //AST2300[2 ]MAC2 MDC/MDIO
302+// #define SCU_74h 0x06300000 //AST3000[20]MAC2 MDC/MDIO, [21]MAC2 MII, [25]MAC1 PHYLINK, [26]MAC2 PHYLINK
303+//#endif
304+
305+//---------------------------------------------------------
306+// DMA Buffer information
307+//---------------------------------------------------------
308+#ifdef FPGA
309+ #define DRAM_KByteSize ( 56 * 1024 )
310+#else
311+ #ifdef AST1010_IOMAP
312+ #define DRAM_KByteSize ( 3 * 1024 ) // DATA buffer only use 0xB00000 to 0xE00000
313+ #else
314+ #define DRAM_KByteSize ( 18 * 1024 )
315+ #endif
316+#endif
317+
318+#define DMA_BASE ( 0x00100000 + DRAM_MapAdr )
319+
320+#ifdef Enable_Jumbo
321+ #define DMA_PakSize ( 10 * 1024 )
322+#else
323+ #define DMA_PakSize ( 2 * 1024 ) // The size of one LAN packet
324+#endif
325+
326+#ifdef SelectSimpleBoundary
327+ #define DMA_BufSize ( ( ( ( ( DES_NUMBER + 15 ) * DMA_PakSize ) >> 2 ) << 2 ) ) //vary by DES_NUMBER
328+#else
329+ #define DMA_BufSize (4 + ( ( ( ( DES_NUMBER + 15 ) * DMA_PakSize ) >> 2 ) << 2 ) ) //vary by DES_NUMBER
330+#endif
331+
332+#define DMA_BufNum ( ( DRAM_KByteSize * 1024 ) / ( DMA_BufSize ) ) //vary by DES_NUMBER
333+#define GET_DMA_BASE_SETUP ( DMA_BASE )
334+#define GET_DMA_BASE(x) ( DMA_BASE + ( ( ( ( x ) % DMA_BufNum ) + 1 ) * DMA_BufSize ) )//vary by DES_NUMBER
335+
336+#define SEED_START 8
337+#define DATA_SEED(seed) ( ( seed ) | (( seed + 1 ) << 16 ) )
338+#define DATA_IncVal 0x00020001
339+//#define DATA_IncVal 0x01000001 //fail
340+//#define DATA_IncVal 0x10000001 //fail
341+//#define DATA_IncVal 0x10000000 //fail
342+//#define DATA_IncVal 0x80000000 //fail
343+//#define DATA_IncVal 0x00000001 //ok
344+//#define DATA_IncVal 0x01000100 //ok
345+//#define DATA_IncVal 0x01010000 //ok
346+//#define DATA_IncVal 0x01010101 //ok
347+//#define DATA_IncVal 0x00000101 //ok
348+//#define DATA_IncVal 0x00001111 //fail
349+//#define DATA_IncVal 0x00000011 //fail
350+//#define DATA_IncVal 0x10100101 //fail
351+//#define DATA_IncVal 0xfeff0201
352+//#define DATA_IncVal 0x00010001
353+#define PktByteSize ( ( ( ( ZeroCopy_OFFSET + FRAME_LEN_Cur - 1 ) >> 2 ) + 1) << 2 )
354+
355+//---------------------------------------------------------
356+// Delay (ms)
357+//---------------------------------------------------------
358+//#define Delay_DesGap 1000 //off
359+//#define Delay_DesGap 700 //off
360+
361+//#define Delay_ChkRxOwn 10
362+//#define Delay_ChkTxOwn 10
363+#define Delay_CntMax 100000000
364+//#define Delay_CntMax 1000
365+//#define Delay_CntMax 8465
366+//#define Delay_CntMaxIncVal 50000
367+#define Delay_CntMaxIncVal 47500
368+
369+#define Delay_PHYRst 100
370+#define Delay_PHYRd 5
371+
372+#define Delay_SCU 11
373+#define Delay_MACRst 1
374+#define Delay_MACDump 100
375+
376+//#define Delay_DES 1
377+
378+//---------------------------------------------------------
379+// Time Out
380+//---------------------------------------------------------
381+#define TIME_OUT_Des 10000
382+#define TIME_OUT_PHY_RW 10000
383+#define TIME_OUT_PHY_Rst 10000
384+
385+//#define TIME_OUT_NCSI 300000
386+#define TIME_OUT_NCSI 30000
387+
388+
389+
390+//---------------------------------------------------------
391+// Chip memory MAP
392+//---------------------------------------------------------
393+#define LITTLE_ENDIAN_ADDRESS 0
394+#define BIG_ENDIAN_ADDRESS 1
395+
396+typedef struct {
397+ ULONG StartAddr;
398+ ULONG EndAddr;
399+} LittleEndian_Area;
400+
401+#if ( AST1010_IOMAP == 1 )
402+ static const LittleEndian_Area LittleEndianArea[] = {
403+ { AST_IO_BASE, (AST_IO_BASE + 0x000FFFFF) },
404+ { 0xFFFFFFFF, 0xFFFFFFFF } // End
405+ };
406+#else
407+ static const LittleEndian_Area LittleEndianArea[] = {
408+ { 0xFFFFFFFF, 0xFFFFFFFF } // End
409+ };
410+#endif
411+
412+// ========================================================
413+// For ncsi.c
414+
415+#define DEF_PACKAGE2NUM 1 // Default value
416+#define DEF_CHANNEL2NUM 2 // Default value
417+
418+typedef struct {
419+ unsigned char Package_ID;
420+ unsigned char Channel_ID;
421+ unsigned long Capabilities_Flags;
422+ unsigned long Broadcast_Packet_Filter_Capabilities;
423+ unsigned long Multicast_Packet_Filter_Capabilities;
424+ unsigned long Buffering_Capabilities;
425+ unsigned long AEN_Control_Support;
426+ unsigned long PCI_DID_VID;
427+ unsigned long ManufacturerID;
428+} NCSI_Capability;
429+
430+#undef GLOBAL
431+#ifdef NCSI_C
432+#define GLOBAL
433+#else
434+#define GLOBAL extern
435+#endif
436+
437+GLOBAL NCSI_Capability NCSI_Cap_SLT;
438+GLOBAL BYTE number_chl;
439+
440+GLOBAL char phy_ncsi (void);
441+
442+// ========================================================
443+// For mactest
444+
445+#undef GLOBAL
446+#ifdef MACTEST_C
447+#define GLOBAL
448+#else
449+#define GLOBAL extern
450+#endif
451+
452+GLOBAL ULONG NCSI_DiSChannel;
453+
454+//
455+#ifdef SLT_UBOOT
456+#else
457+// SLT_DOS
458+GLOBAL FILE *fp_log;
459+GLOBAL FILE *fp_io;
460+#endif
461+
462+GLOBAL CHAR dlymap[16][16];
463+GLOBAL CHAR PrintNCSIEn;
464+GLOBAL ULONG ARPNumCnt;
465+GLOBAL CHAR FileNameMain[256];
466+GLOBAL CHAR FileName[256];
467+GLOBAL CHAR ASTChipName[256];
468+GLOBAL CHAR LOOP_Str[256];
469+GLOBAL BYTE IOTimingBund;
470+GLOBAL BYTE ChannelTolNum;
471+GLOBAL BYTE PackageTolNum;
472+GLOBAL ULONG IOdly_out_reg;
473+GLOBAL BYTE IOdly_out_reg_idx;
474+GLOBAL ULONG Dat_ULONG;
475+GLOBAL ULONG IOdly_incval;
476+GLOBAL ULONG IOdly_in_reg;
477+GLOBAL BYTE IOdly_in_reg_idx;
478+GLOBAL ULONG *wp_lst;
479+GLOBAL ULONG *FRAME_LEN;
480+GLOBAL ULONG DES_NUMBER;
481+GLOBAL ULONG DES_NUMBER_Org;
482+GLOBAL int LOOP_MAX;
483+GLOBAL ULONG LOOP_CheckNum;
484+GLOBAL int Loop;
485+GLOBAL ULONG CheckBuf_MBSize;
486+GLOBAL ULONG Err_Flag;
487+GLOBAL ULONG SCU_f0h_old;
488+#ifdef AST1010_IOMAP
489+ GLOBAL ULONG SCU_11Ch_old;
490+#endif
491+GLOBAL ULONG SCU_04h;
492+GLOBAL ULONG SCU_90h_old;
493+GLOBAL ULONG SCU_7ch_old;
494+GLOBAL ULONG MAC_50h;
495+GLOBAL ULONG SCU_ach_old;
496+GLOBAL ULONG SCU_70h_old;
497+GLOBAL ULONG MAC_50h_Speed;
498+GLOBAL ULONG SCU_48h_old;
499+GLOBAL ULONG SCU_48h_mix;
500+GLOBAL ULONG MAC_08h_old;
501+GLOBAL ULONG MAC_0ch_old;
502+GLOBAL ULONG MAC_40h_old;
503+GLOBAL ULONG SCU_08h_old;
504+GLOBAL ULONG MAC_PHYBASE;
505+GLOBAL ULONG LOOP_MAX_arg;
506+GLOBAL BYTE GRun_Mode;
507+GLOBAL ULONG GSpeed_idx;
508+GLOBAL CHAR GSpeed_sel[3];
509+GLOBAL CHAR PHY_ADR;
510+GLOBAL CHAR PHY_ADR_arg;
511+GLOBAL CHAR PHYName[256];
512+GLOBAL ULONG PHY_ID3;
513+GLOBAL ULONG PHY_ID2;
514+GLOBAL BYTE number_pak;
515+GLOBAL BYTE TestMode;
516+GLOBAL ULONG IOStr_i;
517+GLOBAL BYTE IOTimingBund_arg;
518+GLOBAL BYTE GSpeed;
519+GLOBAL BYTE GCtrl;
520+GLOBAL ULONG UserDVal;
521+GLOBAL ULONG H_MAC_BASE;
522+GLOBAL ULONG H_TDES_BASE;
523+GLOBAL ULONG H_RDES_BASE;
524+GLOBAL CHAR Loop_rl[3];
525+GLOBAL CHAR IOTiming;
526+GLOBAL CHAR LOOP_INFINI;
527+GLOBAL CHAR SelectMAC;
528+GLOBAL CHAR Enable_SkipChkPHY;
529+GLOBAL CHAR Enable_MAC34;
530+GLOBAL CHAR IOStrength;
531+GLOBAL CHAR DataDelay;
532+GLOBAL CHAR SA[6];
533+GLOBAL CHAR RxDataEnable;
534+GLOBAL CHAR IEEETesting;
535+GLOBAL CHAR BurstEnable;
536+GLOBAL CHAR MAC_Mode;
537+GLOBAL CHAR Enable_MACLoopback;
538+GLOBAL CHAR Enable_InitPHY;
539+GLOBAL CHAR MAC1_1GEn;
540+GLOBAL CHAR MAC2_RMII;
541+GLOBAL CHAR Enable_RMII;
542+GLOBAL CHAR MAC2_1GEn;
543+GLOBAL CHAR TxDataEnable;
544+GLOBAL CHAR AST2300_NewMDIO;
545+GLOBAL CHAR ASTChipType;
546+GLOBAL CHAR Err_Flag_PrintEn;
547+GLOBAL CHAR AST2400;
548+GLOBAL CHAR AST2300;
549+GLOBAL CHAR AST1100;//Different in phy & dram initiation & dram size & RMII
550+GLOBAL CHAR AST3200;
551+GLOBAL CHAR AST1010;
552+GLOBAL SCHAR IOdly_i_min;
553+GLOBAL SCHAR IOdly_j_min;
554+GLOBAL SCHAR IOdly_i_max;
555+GLOBAL SCHAR IOdly_j_max;
556+GLOBAL BYTE IOdly_i;
557+GLOBAL BYTE IOdly_j;
558+GLOBAL BYTE IOdly_in;
559+GLOBAL BYTE IOdly_out;
560+GLOBAL SCHAR IOdly_in_str;
561+GLOBAL BYTE IOdly_in_end;
562+GLOBAL BYTE IOdly_out_end;
563+GLOBAL BYTE IOdly_out_shf;
564+GLOBAL BYTE IOdly_in_shf;
565+GLOBAL SCHAR IOdly_out_str;
566+GLOBAL BYTE valary[16];
567+
568+#define MODE_DEDICATED 0x01
569+#define MODE_NSCI 0x02
570+GLOBAL CHAR ModeSwitch;
571+
572+#ifdef SLT_UBOOT
573+#else
574+ GLOBAL time_t timestart;
575+#endif
576+
577+#ifdef SPI_BUS
578+ GLOBAL ULONG mmiobase;
579+#else
580+ // ( USE_P2A | USE_LPC )
581+ GLOBAL UCHAR *mmiobase;
582+ GLOBAL ULONG ulPCIBaseAddress;
583+ GLOBAL ULONG ulMMIOBaseAddress;
584+#endif
585+
586+
587+// ========================================================
588+// For mac.c
589+#undef GLOBAL
590+#ifdef MAC_C
591+#define GLOBAL
592+#else
593+#define GLOBAL extern
594+#endif
595+
596+GLOBAL ULONG ARP_data[16];
597+GLOBAL ULONG NCSI_LinkFail_Val;
598+static const char version_name[] = VER_NAME;
599+
600+GLOBAL void Debug_delay (void);
601+GLOBAL void read_scu (void);
602+GLOBAL void Setting_scu (void);
603+GLOBAL void PrintMode (void);
604+GLOBAL void PrintPakNUm (void);
605+GLOBAL void PrintChlNUm (void);
606+GLOBAL void PrintTest (void);
607+GLOBAL void PrintIOTimingBund (void);
608+GLOBAL void PrintSpeed (void);
609+GLOBAL void PrintCtrl (void);
610+GLOBAL void PrintLoop (void);
611+GLOBAL void PrintPHYAdr (void);
612+GLOBAL void Finish_Close (void);
613+GLOBAL void Calculate_LOOP_CheckNum (void);
614+GLOBAL char Finish_Check (int value);
615+GLOBAL void init_scu1 (void);
616+GLOBAL void init_scu_macrst (void);
617+GLOBAL void setup_arp (void);
618+GLOBAL void TestingSetup (void);
619+GLOBAL void init_scu2 (void);
620+GLOBAL void init_scu3 (void);
621+GLOBAL void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase);
622+GLOBAL char TestingLoop (ULONG loop_checknum);
623+GLOBAL void PrintIO_Line_LOG (void);
624+GLOBAL void init_phy (int loop_phy);
625+GLOBAL void recov_phy (int loop_phy);
626+GLOBAL int FindErr (int value);
627+GLOBAL int FindErr_Des (int value);
628+GLOBAL void PrintIO_Header (BYTE option);
629+GLOBAL void Print_Header (BYTE option);
630+GLOBAL void PrintIO_LineS (BYTE option);
631+GLOBAL void PrintIO_Line (BYTE option);
632+GLOBAL void FPri_ErrFlag (BYTE option);
633+
634+#ifdef SUPPORT_PHY_LAN9303
635+// ========================================================
636+// For LAN9303.c
637+#undef GLOBAL
638+#ifdef LAN9303_C
639+#define GLOBAL
640+#else
641+#define GLOBAL extern
642+#endif
643+
644+GLOBAL void LAN9303(int num, int phy_adr, int speed, int int_loopback);
645+#endif // SUPPORT_PHY_LAN9303
646+#endif // End COMMINF_H
647+
648diff --git a/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H b/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H
649new file mode 100644
650index 0000000..02353e7
651--- /dev/null
652+++ b/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H
653@@ -0,0 +1,35 @@
654+/*
655+ * This program is distributed in the hope that it will be useful,
656+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
657+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
658+ * GNU General Public License for more details.
659+ *
660+ * You should have received a copy of the GNU General Public License
661+ * along with this program; if not, write to the Free Software
662+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
663+ */
664+#ifndef DEF_SPI_H
665+#define DEF_SPI_H
666+
667+#include "TYPEDEF.H"
668+#include "SWFUNC.H"
669+
670+typedef struct _DEVICE_PCI_INFO
671+{
672+ USHORT usVendorID;
673+ USHORT usDeviceID;
674+ ULONG ulPCIConfigurationBaseAddress;
675+ ULONG ulPhysicalBaseAddress;
676+ ULONG ulMMIOBaseAddress;
677+ USHORT usRelocateIO;
678+} DEVICE_PCI_INFO;
679+
680+//VIDEO Engine Info
681+typedef struct _VIDEO_ENGINE_INFO {
682+ USHORT iEngVersion;
683+ DEVICE_PCI_INFO VGAPCIInfo;
684+} VIDEO_ENGINE_INFO;
685+
686+BOOLEAN GetDevicePCIInfo (VIDEO_ENGINE_INFO *VideoEngineInfo);
687+
688+#endif // DEF_SPI_H
689diff --git a/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c b/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c
690new file mode 100644
691index 0000000..fe2b5cf
692--- /dev/null
693+++ b/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c
694@@ -0,0 +1,78 @@
695+/*
696+ * This program is distributed in the hope that it will be useful,
697+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
698+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
699+ * GNU General Public License for more details.
700+ *
701+ * You should have received a copy of the GNU General Public License
702+ * along with this program; if not, write to the Free Software
703+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
704+ */
705+#define DRAM_SPI_C
706+static const char ThisFile[] = "DRAM_SPI.c";
707+
708+#include "SWFUNC.H"
709+
710+#ifdef SPI_BUS
711+#include <stdio.h>
712+#include "DEF_SPI.H"
713+#include "LIB_SPI.H"
714+
715+VOID Set_MMIO_Base(ULONG PCI_BASE, ULONG addr)
716+{
717+ static ULONG MMIO_BASE = -1;
718+
719+ if(MMIO_BASE != (addr & 0xffff0000)){
720+ if(MMIO_BASE == -1){
721+ *(ULONG *)(PCI_BASE + 0xF000) = 1;
722+ }
723+ *(ULONG *)(PCI_BASE + 0xF004) = addr;
724+ MMIO_BASE = addr & 0xffff0000;
725+ }
726+}
727+
728+VOID MOutbm(ULONG PCI_BASE, ULONG Offset, BYTE Data)
729+{
730+ Set_MMIO_Base(PCI_BASE, Offset);
731+ *(BYTE *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
732+}
733+
734+VOID MOutwm(ULONG PCI_BASE, ULONG Offset, USHORT Data)
735+{
736+ Set_MMIO_Base(PCI_BASE, Offset);
737+ *(USHORT *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
738+}
739+
740+VOID MOutdwm(ULONG PCI_BASE, ULONG Offset, ULONG Data)
741+{
742+ Set_MMIO_Base(PCI_BASE, Offset);
743+ *(ULONG *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
744+}
745+
746+BYTE MInbm(ULONG PCI_BASE, ULONG Offset)
747+{
748+ BYTE jData;
749+
750+ Set_MMIO_Base(PCI_BASE, Offset);
751+ jData = *(BYTE *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
752+ return(jData);
753+}
754+
755+USHORT MInwm(ULONG PCI_BASE, ULONG Offset)
756+{
757+ USHORT usData;
758+
759+ Set_MMIO_Base(PCI_BASE, Offset);
760+ usData = *(USHORT *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
761+ return(usData);
762+}
763+
764+ULONG MIndwm(ULONG PCI_BASE, ULONG Offset)
765+{
766+ ULONG ulData;
767+
768+ Set_MMIO_Base(PCI_BASE, Offset);
769+ ulData = *(ULONG *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
770+ return(ulData);
771+}
772+#endif // End SPI_BUS
773diff --git a/arch/arm/cpu/arm926ejs/aspeed/IO.H b/arch/arm/cpu/arm926ejs/aspeed/IO.H
774new file mode 100644
775index 0000000..5fe03f0
776--- /dev/null
777+++ b/arch/arm/cpu/arm926ejs/aspeed/IO.H
778@@ -0,0 +1,36 @@
779+/*
780+ * This program is distributed in the hope that it will be useful,
781+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
782+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
783+ * GNU General Public License for more details.
784+ *
785+ * You should have received a copy of the GNU General Public License
786+ * along with this program; if not, write to the Free Software
787+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
788+ */
789+#ifndef IO_H
790+#define IO_H
791+
792+#include "SWFUNC.H"
793+
794+//
795+// Macro
796+//
797+#if defined(LinuxAP)
798+ #define delay(val) usleep(val*1000)
799+ #define ob(p,d) outb(d,p)
800+ #define ib(p) inb(p)
801+#else
802+ #define ob(p,d) outp(p,d)
803+ #define ib(p) inp(p)
804+#endif
805+
806+#ifdef USE_LPC
807+void open_aspeed_sio_password(void);
808+void enable_aspeed_LDU(BYTE jldu_number);
809+int findlpcport(BYTE jldu_number);
810+#endif
811+
812+void WriteSOC_DD(ULONG addr, ULONG data);
813+ULONG ReadSOC_DD(ULONG addr);
814+#endif
815diff --git a/arch/arm/cpu/arm926ejs/aspeed/IO.c b/arch/arm/cpu/arm926ejs/aspeed/IO.c
816new file mode 100644
817index 0000000..86e9918
818--- /dev/null
819+++ b/arch/arm/cpu/arm926ejs/aspeed/IO.c
820@@ -0,0 +1,356 @@
821+/*
822+ * This program is distributed in the hope that it will be useful,
823+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
824+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
825+ * GNU General Public License for more details.
826+ *
827+ * You should have received a copy of the GNU General Public License
828+ * along with this program; if not, write to the Free Software
829+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
830+ */
831+#define IO_C
832+static const char ThisFile[] = "IO.c";
833+
834+#include "SWFUNC.H"
835+
836+#if defined(LinuxAP)
837+ #include <stdio.h>
838+ #include <string.h>
839+ #include <stdlib.h>
840+ #include <stdarg.h>
841+ #include <unistd.h>
842+ #include <string.h>
843+ #include <fcntl.h>
844+ #include <pthread.h>
845+ #include <sys/mman.h>
846+ #include <sys/io.h>
847+#endif
848+#ifdef SLT_UBOOT
849+ #include <common.h>
850+ #include <command.h>
851+ #include <post.h>
852+ #include <malloc.h>
853+ #include <net.h>
854+ #include <COMMINF.H>
855+#endif
856+#ifdef SLT_DOS
857+ #include <stdlib.h>
858+ #include <stdio.h>
859+ #include <time.h>
860+ #include <conio.h>
861+ #include <dos.h>
862+ #include <mem.h>
863+ #include "TYPEDEF.H"
864+ #include "LIB.H"
865+ #include "COMMINF.H"
866+#endif
867+
868+#include "TYPEDEF.H"
869+#include "IO.H"
870+#include "LIB_SPI.H"
871+
872+#ifdef SPI_BUS
873+#endif
874+#ifdef USE_LPC
875+ USHORT usLPCPort;
876+#endif
877+#ifdef USE_P2A
878+#endif
879+
880+#ifdef USE_LPC
881+//------------------------------------------------------------
882+// LPC access
883+//------------------------------------------------------------
884+void open_aspeed_sio_password(void)
885+{
886+ ob (usLPCPort, 0xaa);
887+
888+ ob (usLPCPort, 0xa5);
889+ ob (usLPCPort, 0xa5);
890+}
891+
892+//------------------------------------------------------------
893+void close_aspeed_sio_password(void)
894+{
895+ ob (usLPCPort, 0xaa);
896+}
897+
898+//------------------------------------------------------------
899+void enable_aspeed_LDU(BYTE jldu_number)
900+{
901+ ob (usLPCPort, 0x07);
902+ ob ((usLPCPort + 1), jldu_number);
903+ ob (usLPCPort, 0x30);
904+ ob ((usLPCPort + 1), 0x01);
905+}
906+
907+//------------------------------------------------------------
908+void disable_aspeed_LDU(BYTE jldu_number)
909+{
910+ ob (usLPCPort, 0x07);
911+ ob ((usLPCPort + 1), jldu_number);
912+ ob (usLPCPort, 0x30);
913+ ob ((usLPCPort + 1), 0x00);
914+}
915+
916+//------------------------------------------------------------
917+/*
918+ulAddress = AHB address
919+jmode = 0: byte mode
920+ 1: word mode
921+ 2: dword mode
922+*/
923+static ULONG lpc_read (ULONG ulAddress, BYTE jmode)
924+{
925+ ULONG uldata = 0;
926+ ULONG ultemp = 0;
927+ BYTE jtemp;
928+
929+ //Write Address
930+ ob ( usLPCPort, 0xf0);
931+ ob ( (usLPCPort + 1 ), ((ulAddress & 0xff000000) >> 24));
932+ ob ( usLPCPort, 0xf1);
933+ ob ( (usLPCPort + 1) , ((ulAddress & 0x00ff0000) >> 16));
934+ ob ( usLPCPort, 0xf2);
935+ ob ( (usLPCPort + 1), ((ulAddress & 0x0000ff00) >> 8));
936+ ob ( usLPCPort, 0xf3);
937+ ob ( (usLPCPort + 1), ulAddress & 0xff);
938+
939+ //Write Mode
940+ ob (usLPCPort, 0xf8);
941+ jtemp = ib ((usLPCPort + 1));
942+ ob ((usLPCPort + 1), ((jtemp & 0xfc) | jmode));
943+
944+ //Fire
945+ ob (usLPCPort, 0xfe);
946+ jtemp = ib ((usLPCPort + 1));
947+
948+ //Get Data
949+ switch ( jmode )
950+ {
951+ case 0:
952+ ob (usLPCPort, 0xf7);
953+ ultemp = ib ((usLPCPort + 1));
954+ uldata |= (ultemp);
955+ break;
956+
957+ case 1:
958+ ob (usLPCPort, 0xf6);
959+ ultemp = ib ((usLPCPort + 1));
960+ uldata |= (ultemp << 8);
961+ ob (usLPCPort, 0xf7);
962+ ultemp = ib ((usLPCPort + 1));
963+ uldata |= (ultemp << 0);
964+ break;
965+
966+ case 2:
967+ ob (usLPCPort, 0xf4);
968+ ultemp = ib ((usLPCPort + 1));
969+ uldata |= (ultemp << 24);
970+ ob (usLPCPort, 0xf5);
971+ ultemp = ib ((usLPCPort + 1));
972+ uldata |= (ultemp << 16);
973+ ob (usLPCPort, 0xf6);
974+ ultemp = ib ((usLPCPort + 1));
975+ uldata |= (ultemp << 8);
976+ ob (usLPCPort, 0xf7);
977+ ultemp = ib ((usLPCPort + 1));
978+ uldata |= ultemp;
979+ break;
980+ } // End switch ( jmode )
981+
982+ return uldata;
983+} // End static ULONG lpc_read (ULONG ulAddress, BYTE jmode)
984+
985+//------------------------------------------------------------
986+static void lpc_write (ULONG ulAddress, ULONG uldata, BYTE jmode)
987+{
988+ BYTE jtemp;
989+
990+ //Write Address
991+ ob ( usLPCPort, 0xf0);
992+ ob ((usLPCPort + 1), ((ulAddress & 0xff000000) >> 24));
993+ ob ( usLPCPort, 0xf1);
994+ ob ((usLPCPort + 1), ((ulAddress & 0x00ff0000) >> 16));
995+ ob ( usLPCPort, 0xf2);
996+ ob ((usLPCPort + 1), ((ulAddress & 0x0000ff00) >> 8));
997+ ob ( usLPCPort, 0xf3);
998+ ob ((usLPCPort + 1), ulAddress & 0xff);
999+
1000+ //Write Data
1001+ switch ( jmode )
1002+ {
1003+ case 0:
1004+ ob ( usLPCPort, 0xf7);
1005+ ob ((usLPCPort + 1), (uldata & 0xff));
1006+ break;
1007+ case 1:
1008+ ob ( usLPCPort, 0xf6);
1009+ ob ((usLPCPort + 1), ((uldata & 0xff00) >> 8));
1010+ ob ( usLPCPort, 0xf7);
1011+ ob ((usLPCPort + 1), (uldata & 0x00ff));
1012+ break;
1013+ case 2:
1014+ ob ( usLPCPort, 0xf4);
1015+ ob ((usLPCPort + 1), ((uldata & 0xff000000) >> 24));
1016+ ob ( usLPCPort, 0xf5);
1017+ ob ((usLPCPort + 1), ((uldata & 0x00ff0000) >> 16));
1018+ ob ( usLPCPort, 0xf6);
1019+ ob ((usLPCPort + 1), ((uldata & 0x0000ff00) >> 8));
1020+ ob ( usLPCPort, 0xf7);
1021+ ob ((usLPCPort + 1), uldata & 0xff);
1022+ break;
1023+ } // End switch ( jmode )
1024+
1025+ //Write Mode
1026+ ob (usLPCPort, 0xf8);
1027+ jtemp = ib ((usLPCPort + 1));
1028+ ob ((usLPCPort + 1), ((jtemp & 0xfc) | jmode));
1029+
1030+ //Fire
1031+ ob (usLPCPort, 0xfe);
1032+ ob ((usLPCPort + 1), 0xcf);
1033+
1034+} // End static void lpc_write (ULONG ulAddress, ULONG uldata, BYTE jmode)
1035+
1036+//------------------------------------------------------------
1037+static USHORT usLPCPortList[] = {0x2e, 0x4e, 0xff};
1038+int findlpcport(BYTE jldu_number)
1039+{
1040+ USHORT *jLPCPortPtr;
1041+ ULONG ulData;
1042+
1043+ jLPCPortPtr = usLPCPortList;
1044+ while (*(USHORT *)(jLPCPortPtr) != 0xff )
1045+ {
1046+ usLPCPort = *(USHORT *)(jLPCPortPtr++);
1047+
1048+ open_aspeed_sio_password();
1049+ enable_aspeed_LDU(0x0d);
1050+
1051+ ulData = lpc_read(0x1e6e207c, 2);
1052+
1053+ if ( (ulData != 0x00000000) &&
1054+ (ulData != 0xFFFFFFFF) )
1055+ {
1056+ printf("Find LPC IO port at 0x%2x \n", usLPCPort);
1057+ return 1;
1058+ }
1059+
1060+ disable_aspeed_LDU(0x0d);
1061+ close_aspeed_sio_password();
1062+ }
1063+
1064+ //printf("[Error] Fail to find proper LPC IO Port \n");
1065+ return 0;
1066+}
1067+#endif // End ifdef USE_LPC
1068+
1069+#ifdef USE_P2A
1070+//------------------------------------------------------------
1071+// A2P Access
1072+//------------------------------------------------------------
1073+void mm_write (ULONG addr, ULONG data, BYTE jmode)
1074+{
1075+ *(ULONG *) (mmiobase + 0xF004) = (ULONG) ((addr) & 0xFFFF0000);
1076+ *(ULONG *) (mmiobase + 0xF000) = (ULONG) 0x00000001;
1077+
1078+ switch ( jmode )
1079+ {
1080+ case 0:
1081+ *(BYTE *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = (BYTE) data;
1082+ break;
1083+ case 1:
1084+ *(USHORT *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = (USHORT) data;
1085+ break;
1086+ case 2:
1087+ default:
1088+ *(ULONG *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = data;
1089+ break;
1090+ } //switch
1091+}
1092+
1093+//------------------------------------------------------------
1094+ULONG mm_read (ULONG addr, BYTE jmode)
1095+{
1096+ *(ULONG *) (mmiobase + 0xF004) = (ULONG) ((addr) & 0xFFFF0000);
1097+ *(ULONG *) (mmiobase + 0xF000) = (ULONG) 0x00000001;
1098+ switch (jmode)
1099+ {
1100+ case 0:
1101+ return ( *(BYTE *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
1102+ break;
1103+ case 1:
1104+ return ( *(USHORT *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
1105+ break;
1106+ default:
1107+ case 2:
1108+ return ( *(ULONG *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
1109+ break;
1110+ } //switch
1111+
1112+ return 0;
1113+}
1114+#endif // End ifdef USE_P2A
1115+
1116+//------------------------------------------------------------
1117+// General Access API
1118+//------------------------------------------------------------
1119+#ifdef SLT_UBOOT
1120+BYTE Check_BEorLN ( ULONG chkaddr )
1121+{
1122+ BYTE ret = BIG_ENDIAN_ADDRESS;
1123+ BYTE i = 0;
1124+
1125+ do {
1126+ if ( LittleEndianArea[i].StartAddr == LittleEndianArea[i].EndAddr )
1127+ break;
1128+
1129+ if ( ( LittleEndianArea[i].StartAddr <= chkaddr ) &&
1130+ ( LittleEndianArea[i].EndAddr >= chkaddr ) ) {
1131+ ret = LITTLE_ENDIAN_ADDRESS;
1132+ break;
1133+ }
1134+ i++;
1135+ } while ( 1 );
1136+
1137+ return ret;
1138+}
1139+#endif
1140+
1141+void WriteSOC_DD(ULONG addr, ULONG data)
1142+{
1143+#ifdef SLT_UBOOT
1144+ if ( Check_BEorLN( addr ) == BIG_ENDIAN_ADDRESS )
1145+ *(volatile unsigned long *)(addr) = cpu_to_le32(data);
1146+ else
1147+ *(volatile unsigned long *)(addr) = data;
1148+#else
1149+ #ifdef USE_LPC
1150+ lpc_write(addr, data, 2);
1151+ #endif
1152+ #ifdef USE_P2A
1153+ mm_write(addr, data, 2);
1154+ #endif
1155+#endif
1156+}
1157+
1158+//------------------------------------------------------------
1159+ULONG ReadSOC_DD(ULONG addr)
1160+{
1161+#ifdef SLT_UBOOT
1162+ if ( Check_BEorLN( addr ) == BIG_ENDIAN_ADDRESS )
1163+ return le32_to_cpu(*(volatile unsigned long *) (addr));
1164+ else
1165+ return (*(volatile unsigned long *) (addr));
1166+#else
1167+ #ifdef USE_LPC
1168+ return (lpc_read(addr, 2));
1169+ #endif
1170+ #ifdef USE_P2A
1171+ return (mm_read(addr, 2));
1172+ #endif
1173+#endif
1174+ return 0;
1175+}
1176+
1177diff --git a/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c
1178new file mode 100644
1179index 0000000..498d4fd
1180--- /dev/null
1181+++ b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c
1182@@ -0,0 +1,525 @@
1183+/*
1184+ * This program is distributed in the hope that it will be useful,
1185+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1186+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1187+ * GNU General Public License for more details.
1188+ *
1189+ * You should have received a copy of the GNU General Public License
1190+ * along with this program; if not, write to the Free Software
1191+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1192+ */
1193+#define LAN9303_C
1194+static const char ThisFile[] = "LAN9303.c";
1195+
1196+#include "SWFUNC.H"
1197+#ifdef SLT_UBOOT
1198+ #include <COMMINF.H>
1199+ #include <MAC.H>
1200+ #include <IO.H>
1201+#endif
1202+
1203+#ifdef SLT_DOS
1204+ #include "COMMINF.H"
1205+ #include <stdlib.h>
1206+ #include "IO.H"
1207+#endif
1208+
1209+#ifdef SUPPORT_PHY_LAN9303
1210+//#define LAN9303M
1211+#define I2C_Debug 0
1212+#define Print_DWRW 0
1213+#define Print_PHYRW 0
1214+#define I2C_TIMEOUT 10000000
1215+
1216+ULONG devbase;
1217+ULONG busnum;
1218+ULONG byte;
1219+ULONG data_rd;
1220+
1221+//------------------------------------------------------------
1222+// Basic
1223+//------------------------------------------------------------
1224+void actime(ULONG ac1, ULONG ac2, ULONG *fact, ULONG *ckh, ULONG *ckl)
1225+{
1226+ static int divcnt;
1227+
1228+ ac1 = ac1 * 50 + 1;
1229+ ac2 = ac2 * 50 + 1;
1230+
1231+ divcnt = 0;
1232+ while (ac1 > 8 || ac2 > 8) {
1233+ divcnt++;
1234+ ac1 >>= 1;
1235+ ac2 >>= 1;
1236+ }
1237+
1238+ if (ac1 < 2 ) ac1 = 2;
1239+ if (ac2 < 2 ) ac2 = 2;
1240+ if (ac1 > ac2) ac2 = 1;
1241+ else ac1 += 1;
1242+
1243+#ifdef PRINT_MSG
1244+ printf("Divcnt = %d, ckdiv = %d, ckh = %d, ckl = %d\n",(1<<divcnt)*(ac1+ac2),divcnt,ac1-1,ac2-1);
1245+ printf("CKH = %d us, CKL = %d us\n",(1<<divcnt)*ac1/50,(1<<divcnt)*ac2/50);
1246+#endif
1247+
1248+ *fact = divcnt;
1249+ *ckh = ac1 - 1;
1250+ *ckl = ac2 - 1;
1251+}
1252+
1253+//------------------------------------------------------------
1254+ULONG PollStatus()
1255+{
1256+ static ULONG status;
1257+ static ULONG cnt = 0;
1258+
1259+ do {
1260+ status = ReadSOC_DD( devbase + 0x14 ) & 0xff;
1261+
1262+ if ( ++cnt > I2C_TIMEOUT ) {
1263+ printf("\nWait1 Timeout at bus %d!\n", busnum);
1264+ printf("Status 14 = %08x\n", ReadSOC_DD(devbase + 0x14));
1265+ exit(0);
1266+ }
1267+ } while (status != 0);
1268+
1269+ cnt = 0;
1270+ do {
1271+ status = ReadSOC_DD( devbase + 0x10 );
1272+ if ( ++cnt > I2C_TIMEOUT ) {
1273+ printf("\nWait2 Timeout at bus %d!\n", busnum);
1274+ printf("Status 14 = %08x\n", ReadSOC_DD(devbase + 0x14));
1275+ exit(0);
1276+ }
1277+ } while (status == 0);
1278+
1279+ WriteSOC_DD( devbase + 0x10, status );
1280+
1281+ return(status);
1282+}
1283+
1284+
1285+//------------------------------------------------------------
1286+ULONG writeb(ULONG start, ULONG data, ULONG stop)
1287+{
1288+ WriteSOC_DD( devbase + 0x20, data);
1289+ WriteSOC_DD( devbase + 0x14, 0x02 | start | (stop << 5) );
1290+ return(PollStatus());
1291+}
1292+
1293+//------------------------------------------------------------
1294+ULONG readb(ULONG last, ULONG stop)
1295+{
1296+ static ULONG data;
1297+
1298+ WriteSOC_DD( devbase + 0x14, 0x08 | (last << 4) | (stop << 5) );
1299+ data = PollStatus();
1300+
1301+ if (data & 0x4) {
1302+ data = ReadSOC_DD( devbase + 0x20 );
1303+ return(data >> 8);
1304+ }
1305+ else {
1306+ return(-1);
1307+ }
1308+}
1309+
1310+//------------------------------------------------------------
1311+void Initial(ULONG base, ULONG ckh, ULONG ckl)
1312+{
1313+ static ULONG ackh;
1314+ static ULONG ackl;
1315+ static ULONG divx;
1316+
1317+ actime(ckh, ckl, &divx, &ackh, &ackl);
1318+ WriteSOC_DD(base + 0x00, 0x1);
1319+ if (ReadSOC_DD(base + 0x00) != 0x1) {
1320+ printf("Controller initial fail : %x\n",base);
1321+ exit(0);
1322+ }
1323+ WriteSOC_DD(base + 0x04, 0x77700360 | (ackh << 16) | (ackl << 12) | divx);
1324+ WriteSOC_DD(base + 0x08, 0x0);
1325+ WriteSOC_DD(base + 0x0c, 0x0);
1326+ WriteSOC_DD(base + 0x10, 0xffffffff);
1327+ WriteSOC_DD(base + 0x14, 0x00);
1328+ WriteSOC_DD(base + 0x1C, 0xff0000);
1329+ WriteSOC_DD(base + 0x20, 0x00);
1330+}
1331+
1332+//------------------------------------------------------------
1333+void print_status(ULONG status)
1334+{
1335+ if ( status & 0x02 ) printf( "Device NAK\n" );
1336+ if ( status & 0x08 ) printf( "Arbitration Loss\n" );
1337+ if ( status & 0x10 ) printf( "STOP\n" );
1338+ if ( status & 0x20 ) printf( "Abnormal STOP\n" );
1339+ if ( status & 0x40 ) printf( "SCL Low timeout\n" );
1340+}
1341+
1342+//------------------------------------------------------------
1343+void readme()
1344+{
1345+ printf("\nVersion:%s\n", version_name);
1346+#ifdef LAN9303M
1347+ printf("LAN9303M [bus] [vir_PHY_adr] [speed] [func]\n");
1348+#else
1349+ printf("LAN9303 [bus] [vir_PHY_adr] [speed] [func]\n" );
1350+#endif
1351+ printf("[bus] | 1~14: I2C bus number\n" );
1352+ printf("[vir_PHY_adr] | 0~1: virtual PHY address\n" );
1353+ printf("[speed] | 1: 100M\n" );
1354+ printf(" | 2: 10 M\n" );
1355+ printf("[func] | 0: external loopback\n" );
1356+ printf(" | 1: internal loopback\n" );
1357+}
1358+
1359+//------------------------------------------------------------
1360+void quit()
1361+{
1362+ WriteSOC_DD( devbase + 0x14, 0x20 );
1363+ PollStatus();
1364+ readme();
1365+}
1366+
1367+//------------------------------------------------------------
1368+// Double-Word Read/Write
1369+//------------------------------------------------------------
1370+ULONG I2C_DWRead(ULONG adr)
1371+{
1372+ static ULONG status;
1373+ int i;
1374+
1375+ Initial(devbase, 10, 10);
1376+
1377+ if ( Print_DWRW )
1378+ printf("RAdr %02x: ", adr);
1379+
1380+ status = writeb( 1, LAN9303_I2C_ADR, 0 );
1381+ if ( I2C_Debug )
1382+ printf("R1W[%02x]%02x ", status, LAN9303_I2C_ADR);
1383+
1384+ if ( status != 0x1 ) {
1385+ print_status(status);
1386+ quit();
1387+ exit(0);
1388+ }
1389+
1390+ status = writeb(0, adr, 0);
1391+ if ( I2C_Debug )
1392+ printf("R2W[%02x]%02x ", status, adr);
1393+ if ( !(status & 0x1) ) {
1394+ print_status(status);
1395+ quit();
1396+ exit(0);
1397+ }
1398+
1399+ status = writeb(1, LAN9303_I2C_ADR | 0x1, 0);
1400+ if ( I2C_Debug )
1401+ printf("R3W[%02x]%02x ", status, LAN9303_I2C_ADR | 0x1);
1402+ if ( status != 0x1 ) {
1403+ print_status(status);
1404+ quit();
1405+ exit(0);
1406+ }
1407+
1408+ if ( I2C_Debug )
1409+ printf("R4");
1410+
1411+ data_rd = 0;
1412+ for (i = 24; i >= 0; i-=8) {
1413+ if (i == 0) byte = readb(1, 1);
1414+ else byte = readb(0, 0);
1415+
1416+ if ( I2C_Debug )
1417+ printf("%02x ", byte);
1418+ data_rd = data_rd | (byte << i);
1419+ }
1420+
1421+ if ( Print_DWRW )
1422+ printf("%08x\n", data_rd);
1423+
1424+ return (data_rd);
1425+} // End ULONG I2C_DWRead(ULONG adr)
1426+
1427+//------------------------------------------------------------
1428+void I2C_DWWrite(ULONG adr, ULONG dwdata)
1429+{
1430+ static ULONG status;
1431+ int i;
1432+ ULONG endx;
1433+
1434+ Initial(devbase, 10, 10);
1435+ if (Print_DWRW)
1436+ printf("WAdr %02x: ", adr);
1437+
1438+ status = writeb(1, LAN9303_I2C_ADR, 0);
1439+ if ( I2C_Debug )
1440+ printf("W1[%02x]%02x ", status, LAN9303_I2C_ADR);
1441+ if ( status != 0x1 ) {
1442+ print_status(status);
1443+ quit();
1444+ exit(0);
1445+ }
1446+ status = writeb(0, adr, 0);
1447+ if ( I2C_Debug )
1448+ printf("W2[%02x]%02x ", status, adr);
1449+ if ( !(status & 0x1) ) {
1450+ print_status(status);
1451+ quit();
1452+ exit(0);
1453+ }
1454+
1455+ if (I2C_Debug)
1456+ printf("W3");
1457+ endx = 0;
1458+ for (i = 24; i >= 0; i-=8) {
1459+ if (i == 0)
1460+ endx = 1;
1461+ byte = (dwdata >> i) & 0xff;
1462+ status = writeb(0, byte, endx);
1463+
1464+ if (I2C_Debug)
1465+ printf("[%02x]%02x ", status, byte);
1466+ if (!(status & 0x1)) {
1467+ print_status(status);
1468+ quit();
1469+ exit(0);
1470+ }
1471+ }
1472+
1473+ if (Print_DWRW) printf("%08x\n", dwdata);
1474+} // End void I2C_DWWrite(ULONG adr, ULONG dwdata)
1475+
1476+//------------------------------------------------------------
1477+// PHY Read/Write
1478+//------------------------------------------------------------
1479+ULONG LAN9303_PHY_Read(ULONG phy_adr, ULONG reg_adr)
1480+{
1481+ static ULONG data_rd;
1482+
1483+ I2C_DWWrite(0x2a, ((phy_adr & 0x1f) << 11) | ((reg_adr & 0x1f) << 6));//[0A8h]PMI_ACCESS
1484+ do {
1485+ data_rd = I2C_DWRead (0x2a);
1486+ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
1487+
1488+ data_rd = I2C_DWRead (0x29);//[0A4h]PMI_DATA
1489+ if (Print_PHYRW)
1490+ printf("PHY:%2d, Reg:%2d, Data:%08x\n", phy_adr, reg_adr, data_rd);
1491+
1492+ return(data_rd);
1493+}
1494+
1495+//------------------------------------------------------------
1496+void LAN9303_PHY_Write(ULONG phy_adr, ULONG reg_adr, ULONG data_wr)
1497+{
1498+ static ULONG data_rd;
1499+
1500+ I2C_DWWrite(0x29, data_wr);//[0A4h]PMI_DATA
1501+
1502+ I2C_DWWrite(0x2a, ((phy_adr & 0x1f) << 11) | ((reg_adr & 0x1f) << 6) | 0x2);//[0A8h]PMI_ACCESS
1503+ do {
1504+ data_rd = I2C_DWRead (0x2a);
1505+ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
1506+}
1507+
1508+//------------------------------------------------------------
1509+ULONG LAN9303_PHY_Read_WD(ULONG data_ctl)
1510+{
1511+ static ULONG data_rd;
1512+
1513+ I2C_DWWrite(0x2a, data_ctl);//[0A8h]PMI_ACCESS
1514+ do {
1515+ data_rd = I2C_DWRead (0x2a);
1516+ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
1517+
1518+ data_rd = I2C_DWRead (0x29);//[0A4h]PMI_DATA
1519+ if (Print_PHYRW)
1520+ printf("WD Data:%08x\n", data_ctl);
1521+
1522+ return(data_rd);
1523+}
1524+
1525+//------------------------------------------------------------
1526+void LAN9303_PHY_Write_WD(ULONG data_ctl, ULONG data_wr)
1527+{
1528+ static ULONG data_rd;
1529+
1530+ I2C_DWWrite( 0x29, data_wr ); //[0A4h]PMI_DATA
1531+ I2C_DWWrite( 0x2a, data_ctl ); //[0A8h]PMI_ACCESS
1532+ do {
1533+ data_rd = I2C_DWRead (0x2a);
1534+ } while(data_rd & 0x00000001); //[0A8h]PMI_ACCESS
1535+}
1536+
1537+//------------------------------------------------------------
1538+// Virtual PHY Read/Write
1539+//------------------------------------------------------------
1540+ULONG LAN9303_VirPHY_Read(ULONG reg_adr)
1541+{
1542+ static ULONG data_rd;
1543+
1544+ data_rd = I2C_DWRead (0x70+reg_adr);//[1C0h]
1545+ if ( Print_PHYRW )
1546+ printf("VirPHY Reg:%2d, Data:%08x\n", reg_adr, data_rd);
1547+
1548+ return(data_rd);
1549+}
1550+
1551+//------------------------------------------------------------
1552+void LAN9303_VirPHY_Write(ULONG reg_adr, ULONG data_wr)
1553+{
1554+ I2C_DWWrite(0x70+reg_adr, data_wr);//[1C0h]
1555+}
1556+
1557+//------------------------------------------------------------
1558+void LAN9303_VirPHY_RW(ULONG reg_adr, ULONG data_clr, ULONG data_set)
1559+{
1560+ I2C_DWWrite(0x70+reg_adr, (LAN9303_VirPHY_Read(reg_adr) & (~data_clr)) | data_set);//[1C0h]
1561+}
1562+
1563+//------------------------------------------------------------
1564+// PHY Read/Write
1565+//------------------------------------------------------------
1566+ULONG LAN9303_Read(ULONG adr)
1567+{
1568+ static ULONG data_rd;
1569+
1570+ I2C_DWWrite(0x6c, 0xc00f0000 | adr & 0xffff);//[1B0h]SWITCH_CSR_CMD
1571+ do {
1572+ data_rd = I2C_DWRead (0x6c);
1573+ } while(data_rd & 0x80000000);//[1B0h]SWITCH_CSR_CMD
1574+
1575+ return(I2C_DWRead (0x6b));//[1ACh]SWITCH_CSR_DATA
1576+}
1577+
1578+//------------------------------------------------------------
1579+void LAN9303_Write(ULONG adr, ULONG data)
1580+{
1581+ static ULONG data_rd;
1582+
1583+ I2C_DWWrite(0x6b, data);//[1ACh]SWITCH_CSR_DATA
1584+ I2C_DWWrite(0x6c, 0x800f0000 | adr & 0xffff);//[1B0h]SWITCH_CSR_CMD
1585+
1586+ do {
1587+ data_rd = I2C_DWRead (0x6c);
1588+ } while(data_rd & 0x80000000);//[1B0h]SWITCH_CSR_CMD
1589+}
1590+
1591+//------------------------------------------------------------
1592+void LAN9303(int num, int phy_adr, int speed, int int_loopback)
1593+{
1594+ static ULONG data_rd;
1595+
1596+ //------------------------------------------------------------
1597+ // I2C Initial
1598+ //------------------------------------------------------------
1599+ busnum = num;
1600+ if (busnum <= 7) devbase = 0x1E78A000 + ( busnum * 0x40);
1601+ else devbase = 0x1E78A300 + ((busnum-8) * 0x40);
1602+ Initial(devbase, 10, 10);
1603+
1604+ //------------------------------------------------------------
1605+ // LAN9303 Register Setting
1606+ //------------------------------------------------------------
1607+ printf("----> Start\n");
1608+ if (int_loopback == 0) {
1609+ //Force Speed & external loopback
1610+ if (speed == 1) { //100M
1611+ LAN9303_VirPHY_RW( 0, 0xffff, 0x2300 ); //adr clr set //VPHY_BASIC_CTRL
1612+ LAN9303_VirPHY_RW( 11, 0xffff, 0x2300 ); //adr clr set //P1_MII_BASIC_CONTROL
1613+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x2300 );
1614+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x2300 );
1615+ }
1616+ else {
1617+ LAN9303_VirPHY_RW( 0, 0xffff, 0x0100 ); //adr clr set //VPHY_BASIC_CTRL
1618+ LAN9303_VirPHY_RW( 11, 0xffff, 0x0100 ); //adr clr set //P1_MII_BASIC_CONTROL
1619+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x0100);
1620+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x0100);
1621+ }
1622+
1623+ LAN9303_Write( 0x180c, 0x00000001 ); // SWE_VLAN_WR_DATA
1624+ LAN9303_Write( 0x180b, 0x00000010 ); // SWE_VLAN_CMD
1625+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1626+
1627+ LAN9303_Write( 0x180c, 0x00000002 ); // SWE_VLAN_WR_DATA
1628+ LAN9303_Write( 0x180b, 0x00000011 ); // SWE_VLAN_CMD
1629+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1630+
1631+ LAN9303_Write( 0x180c, 0x00000003 ); // SWE_VLAN_WR_DATA
1632+ LAN9303_Write( 0x180b, 0x00000012 ); // SWE_VLAN_CMD
1633+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1634+
1635+#ifdef LAN9303M
1636+ LAN9303_Write( 0x180c, 0x00022001 ); // SWE_VLAN_WR_DATA
1637+ LAN9303_Write( 0x180b, 0x00000000 ); // SWE_VLAN_CMD
1638+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1639+
1640+ LAN9303_Write( 0x180c, 0x00024002 ); // SWE_VLAN_WR_DATA
1641+ LAN9303_Write( 0x180b, 0x00000001 ); // SWE_VLAN_CMD
1642+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1643+
1644+ LAN9303_Write( 0x180c, 0x0002a003 ); // SWE_VLAN_WR_DATA
1645+ LAN9303_Write( 0x180b, 0x00000002 ); // SWE_VLAN_CMD
1646+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1647+#else
1648+ LAN9303_Write( 0x180c, 0x0002a001 ); // SWE_VLAN_WR_DATA
1649+ LAN9303_Write( 0x180b, 0x00000000 ); // SWE_VLAN_CMD
1650+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1651+
1652+ LAN9303_Write( 0x180c, 0x0000a002 ); // SWE_VLAN_WR_DATA
1653+ LAN9303_Write( 0x180b, 0x00000001 ); // SWE_VLAN_CMD
1654+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1655+
1656+ LAN9303_Write( 0x180c, 0x00022003 ); // SWE_VLAN_WR_DATA
1657+ LAN9303_Write( 0x180b, 0x00000002 ); // SWE_VLAN_CMD
1658+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
1659+#endif
1660+ LAN9303_Write( 0x1840, 0x00000007);
1661+ }
1662+ else if ( int_loopback == 1 ) {
1663+ //Force Speed & internal loopback
1664+ if ( speed == 1 ) {
1665+ //100M
1666+ LAN9303_VirPHY_RW( 0, 0xffff, 0x6300 ); // adr clr set //VPHY_BASIC_CTRL
1667+ LAN9303_VirPHY_RW( 11, 0xffff, 0x6300 ); // adr clr set //P1_MII_BASIC_CONTROL
1668+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x6300 );
1669+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x6300 );
1670+ }
1671+ else {
1672+ LAN9303_VirPHY_RW( 0, 0xffff, 0x4100 ); // adr clr set //VPHY_BASIC_CTRL
1673+ LAN9303_VirPHY_RW( 11, 0xffff, 0x4100 ); // adr clr set //P1_MII_BASIC_CONTROL
1674+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x4100 );
1675+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x4100 );
1676+ }
1677+ }
1678+ else {
1679+ //Force Speed
1680+ if (speed == 1) {
1681+ //100M
1682+ LAN9303_VirPHY_RW( 0, 0xffff, 0x2300 ); // adr clr set //VPHY_BASIC_CTRL
1683+ LAN9303_VirPHY_RW( 11, 0xffff, 0x2300 ); // adr clr set //P1_MII_BASIC_CONTROL
1684+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x2300 );
1685+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x2300 );
1686+ }
1687+ else {
1688+ LAN9303_VirPHY_RW( 0, 0xffff, 0x0100 ); // adr clr set //VPHY_BASIC_CTRL
1689+ LAN9303_VirPHY_RW( 11, 0xffff, 0x0100 ); // adr clr set //P1_MII_BASIC_CONTROL
1690+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x0100 );
1691+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x0100 );
1692+ }
1693+#ifdef LAN9303M
1694+#else
1695+ if (int_loopback == 3) {
1696+ //[LAN9303]IEEE measurement
1697+ data_rd = LAN9303_PHY_Read(phy_adr+1, 27);//PHY_SPECIAL_CONTROL_STAT_IND_x
1698+ LAN9303_PHY_Write(phy_adr+1, 27, (data_rd & 0x9fff) | 0x8000);//PHY_SPECIAL_CONTROL_STAT_IND_x
1699+
1700+ data_rd = LAN9303_PHY_Read(phy_adr+2, 27);//PHY_SPECIAL_CONTROL_STAT_IND_x
1701+ LAN9303_PHY_Write(phy_adr+2, 27, (data_rd & 0x9fff) | 0x8000);//PHY_SPECIAL_CONTROL_STAT_IND_x
1702+ }
1703+#endif
1704+ } // End if (int_loopback == 0)
1705+} // End void LAN9303(int num, int phy_adr, int speed, int int_loopback)
1706+#endif // SUPPORT_PHY_LAN9303
1707+
1708diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB.H b/arch/arm/cpu/arm926ejs/aspeed/LIB.H
1709new file mode 100644
1710index 0000000..a7c61dd
1711--- /dev/null
1712+++ b/arch/arm/cpu/arm926ejs/aspeed/LIB.H
1713@@ -0,0 +1,37 @@
1714+/*
1715+ * This program is distributed in the hope that it will be useful,
1716+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1717+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1718+ * GNU General Public License for more details.
1719+ *
1720+ * You should have received a copy of the GNU General Public License
1721+ * along with this program; if not, write to the Free Software
1722+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1723+ */
1724+#ifndef LIB_H
1725+#define LIB_H
1726+
1727+#include "TYPEDEF.H"
1728+
1729+//
1730+// Macro
1731+//
1732+#define INTFUNC int386
1733+
1734+#define OUTDWPORT outpd
1735+#define INDWPORT inpd
1736+#define OUTPUT outp
1737+#define INPUT inp
1738+
1739+//
1740+// PCI
1741+//
1742+ULONG ReadPCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask);
1743+ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType);
1744+VOID WritePCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask, ULONG ulData);
1745+
1746+//
1747+// Map Resource
1748+//
1749+ULONG MapPhysicalToLinear (ULONG ulBaseAddress, ULONG ulSize);
1750+#endif
1751diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB.c b/arch/arm/cpu/arm926ejs/aspeed/LIB.c
1752new file mode 100644
1753index 0000000..f2a0c54
1754--- /dev/null
1755+++ b/arch/arm/cpu/arm926ejs/aspeed/LIB.c
1756@@ -0,0 +1,184 @@
1757+/*
1758+ * This program is distributed in the hope that it will be useful,
1759+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1760+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1761+ * GNU General Public License for more details.
1762+ *
1763+ * You should have received a copy of the GNU General Public License
1764+ * along with this program; if not, write to the Free Software
1765+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1766+ */
1767+#define LIB_C
1768+static const char ThisFile[] = "LIB.c";
1769+
1770+#include "SWFUNC.H"
1771+
1772+#ifdef SLT_UBOOT
1773+ #include <common.h>
1774+ #include <command.h>
1775+#endif
1776+#ifdef SLT_DOS
1777+#include <stdlib.h>
1778+#include <stdio.h>
1779+#include <time.h>
1780+#include <conio.h>
1781+#include <dos.h>
1782+#include <mem.h>
1783+#endif
1784+
1785+#include "LIB.H"
1786+#include "TYPEDEF.H"
1787+
1788+#ifdef USE_P2A
1789+//------------------------------------------------------------
1790+// PCI
1791+//------------------------------------------------------------
1792+ULONG ReadPCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask)
1793+{
1794+#ifndef Windows
1795+ OUTDWPORT(0xcf8, ulPCIConfigAddress + jOffest);
1796+
1797+ return (((ULONG)INDWPORT(0xcfc)) & ulMask);
1798+#else
1799+ WRITE_PORT_ULONG((PULONG)0xcf8, ulPCIConfigAddress + jOffest);
1800+
1801+ return (READ_PORT_ULONG((PULONG)0xcfc) & ulMask);
1802+#endif
1803+}
1804+
1805+//------------------------------------------------------------
1806+VOID WritePCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask, ULONG ulData)
1807+{
1808+#ifndef Windows
1809+ OUTDWPORT(0xcf8, ulPCIConfigAddress + jOffest);
1810+ OUTDWPORT(0xcfc, (INDWPORT(0xcfc) & ulMask | ulData));
1811+#else
1812+ WRITE_PORT_ULONG((PULONG)0xcf8, ulPCIConfigAddress + jOffest);
1813+ WRITE_PORT_ULONG((PULONG)0xcfc, (READ_PORT_ULONG((PULONG)0xcfc) & ulMask | ulData));
1814+#endif
1815+}
1816+
1817+//------------------------------------------------------------
1818+ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType)
1819+{
1820+//Return: ulPCIConfigAddress
1821+//usBusType: ACTIVE/PCI/AGP/PCI-E
1822+
1823+ ULONG Base[256];
1824+ ULONG ebx;
1825+ USHORT i;
1826+ USHORT j;
1827+
1828+ for (i = 0; i < 256; i++) {
1829+ Base[i] = 0x80000000 + 0x10000 * i;
1830+ }
1831+
1832+ if (usBusType == PCI)
1833+ {
1834+ ebx = 0x80000000;
1835+ }
1836+ else if (usBusType == PCIE)
1837+ {
1838+ ebx = 0x80020000;
1839+ }
1840+ else // AGP and ACTIVE
1841+ {
1842+ ebx = 0x80010000;
1843+ }
1844+
1845+ if ( usBusType != ACTIVE ) //AGP, PCI, PCIE
1846+ {
1847+ for (i = 0; i < 32; i++)
1848+ {
1849+ ebx = ebx + (0x800);
1850+ if (((USHORT)ReadPCIReg(ebx, 0, 0xffff) == usVendorID) && ((USHORT)(ReadPCIReg(ebx, 0, 0xffff0000) >> 16) == usDeviceID))
1851+ {
1852+ return ebx;
1853+ }
1854+ }
1855+ return 0;
1856+ }
1857+ else //ACTIVE
1858+ {
1859+ for (j = 0; j < 256; j++)
1860+ {
1861+ ebx = Base[j];
1862+ for (i = 0; i < 32; i++)
1863+ {
1864+ ebx = ebx + (0x800);
1865+ if (((USHORT)ReadPCIReg(ebx, 0, 0xffff) == usVendorID) && ((USHORT)(ReadPCIReg(ebx, 0, 0xffff0000) >> 16) == usDeviceID))
1866+ {
1867+ return ebx;
1868+ }
1869+ }
1870+ }
1871+ return 0;
1872+ }
1873+} // End ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType)
1874+#endif
1875+//------------------------------------------------------------
1876+// Allocate Resource
1877+//------------------------------------------------------------
1878+#ifdef SLT_DOS
1879+ULONG InitDOS32()
1880+{
1881+ union REGS regs ;
1882+
1883+ regs.w.ax = 0xee00;
1884+ INTFUNC(0x31, &regs, &regs) ;
1885+
1886+ if(regs.w.ax >= 0x301) // DOS32 version >= 3.01 ?
1887+ return 1;
1888+ else
1889+ return 0;
1890+}
1891+
1892+//------------------------------------------------------------
1893+USHORT CheckDOS()
1894+{
1895+ union REGS regs;
1896+
1897+ regs.w.ax = 0xeeff;
1898+ int386(0x31, &regs, &regs);
1899+ if (regs.x.eax == 0x504d4457)
1900+ {
1901+ return 0;
1902+ } else {
1903+ printf("PMODEW Init. fail\n");
1904+ return 1;
1905+ }
1906+}
1907+
1908+//------------------------------------------------------------
1909+ULONG MapPhysicalToLinear (ULONG ulBaseAddress, ULONG ulSize)
1910+{
1911+ union REGS regs;
1912+
1913+ regs.w.ax = 0x0800; // map physcial memory
1914+ regs.w.bx = ulBaseAddress >> 16; // bx:cx = physical address
1915+ regs.w.cx = ulBaseAddress;
1916+ regs.w.si = ulSize >> 16; // si:di = mapped memory block size
1917+ regs.w.di = ulSize;
1918+ INTFUNC(0x31, &regs, &regs); // int386(0x31, &regs, &regs);
1919+ if (regs.w.cflag == 0)
1920+ return (ULONG) (regs.w.bx << 16 + regs.w.cx); // Linear Addr = bx:cx
1921+ else
1922+ return 0;
1923+}
1924+
1925+//------------------------------------------------------------
1926+USHORT FreePhysicalMapping(ULONG udwLinAddress)
1927+{
1928+ union REGS regs;
1929+
1930+ regs.w.ax = 0x0801;
1931+ regs.w.bx = udwLinAddress >> 16;
1932+ regs.w.cx = udwLinAddress & 0xFFFF;
1933+ int386(0x31, &regs, &regs);
1934+
1935+ if (regs.x.cflag)
1936+ return ((USHORT) 0);
1937+ else return ((USHORT) 1);
1938+}
1939+#endif
1940+
1941diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H b/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H
1942new file mode 100644
1943index 0000000..78c8f1e
1944--- /dev/null
1945+++ b/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H
1946@@ -0,0 +1,23 @@
1947+/*
1948+ * This program is distributed in the hope that it will be useful,
1949+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1950+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1951+ * GNU General Public License for more details.
1952+ *
1953+ * You should have received a copy of the GNU General Public License
1954+ * along with this program; if not, write to the Free Software
1955+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1956+ */
1957+#ifndef LIB_SPI_H
1958+#define LIB_SPI_H
1959+
1960+#ifdef SPI_BUS
1961+ // MMIO Functions
1962+ VOID MOutwm (ULONG, ULONG, USHORT);
1963+ VOID MOutdwm (ULONG, ULONG, ULONG);
1964+ ULONG MIndwm (ULONG, ULONG);
1965+
1966+ void spim_init(int cs);
1967+#endif
1968+
1969+#endif // LIB_SPI_H
1970diff --git a/arch/arm/cpu/arm926ejs/aspeed/MAC.H b/arch/arm/cpu/arm926ejs/aspeed/MAC.H
1971new file mode 100644
1972index 0000000..6732117
1973--- /dev/null
1974+++ b/arch/arm/cpu/arm926ejs/aspeed/MAC.H
1975@@ -0,0 +1,157 @@
1976+/*
1977+ * This program is distributed in the hope that it will be useful,
1978+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1979+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1980+ * GNU General Public License for more details.
1981+ *
1982+ * You should have received a copy of the GNU General Public License
1983+ * along with this program; if not, write to the Free Software
1984+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1985+ */
1986+#ifndef MAC_H
1987+#define MAC_H
1988+
1989+#ifdef SPI_BUS
1990+ #include <stdio.h>
1991+ #include <stdlib.h>
1992+ #include <time.h>
1993+ #define SPI_CS 1
1994+#endif
1995+// ( USE_P2A | USE_LPC )
1996+
1997+#if defined(LinuxAP)
1998+ #include <stdio.h>
1999+ #include <stdlib.h>
2000+ #include <string.h>
2001+ #include <stdarg.h>
2002+ #include <unistd.h>
2003+ #include <string.h>
2004+ #include <fcntl.h>
2005+ #include <pthread.h>
2006+ #include <sys/mman.h>
2007+ #include <sys/io.h>
2008+#endif
2009+#ifdef SLT_UBOOT
2010+ #include <common.h>
2011+ #include <command.h>
2012+#endif
2013+#ifdef SLT_DOS
2014+ #include <stdio.h>
2015+ #include <stdlib.h>
2016+ #include <time.h>
2017+ #include <conio.h>
2018+ #include <dos.h>
2019+ #include <mem.h>
2020+#endif
2021+
2022+#include "NCSI.H"
2023+#include "IO.H"
2024+
2025+// --------------------------------------------------------------
2026+// Define
2027+// --------------------------------------------------------------
2028+
2029+//#define Force_Enable_MAC34 //[ON][SLT:off] (Force enable mac34)
2030+//#define Force_Enable_NewMDIO //[off][SLT:off] (Force enable new MDC/MDIO)
2031+//#define Enable_Fast_SCU //[off]
2032+//#define Enable_Old_Style //[off]
2033+#define ENABLE_DASA //[ON]
2034+//#define Enable_AST2300_Int125MHz //[off]
2035+//#define ENABLE_ARP_2_WOL //[off]
2036+//#define Enable_MAC_SWRst //[off]
2037+
2038+#define Enable_Runt
2039+//#define Enable_Jumbo
2040+//#define Enable_BufMerge
2041+//#define Disable_VGA
2042+
2043+//#define SelectSimpleBoundary //[off] Using in debug
2044+//#define SelectSimpleData //[off] Using in debug
2045+//#define SelectSimpleLength 1512 //[off] 60(0x3c) ~ 1514(0x5ea); 1512(0x5e8)
2046+//#define SelectDesNumber 8 //[off] 1 ~
2047+//#define SelectSimpleDA //[off] Using in debug
2048+//#define SelectSimpleDes //[off]
2049+//#define SelectLengthInc //[off] Using in debug
2050+
2051+#define SimpleData_Fix //[ON] Using in debug
2052+#define SimpleData_FixNum 12
2053+#define SimpleData_FixVal00 0x00000000 //[0]no SelectSimpleDA: (60: 0412 8908)(1512: e20d e9da)
2054+#define SimpleData_FixVal01 0xffffffff //[0]no SelectSimpleDA: (60: f48c f14d)(1512: af05 260c)
2055+#define SimpleData_FixVal02 0x55555555 //[0]no SelectSimpleDA: (60: 5467 5ecb)(1512: d90a 5368)
2056+#define SimpleData_FixVal03 0xaaaaaaaa //[0]no SelectSimpleDA: (60: a4f9 268e)(1512: 9402 9cbe)
2057+#define SimpleData_FixVal04 0x5a5a5a5a //[1]no SelectSimpleDA: (60: 7f01 e22d)(1512: 4fd3 8012)
2058+#define SimpleData_FixVal05 0xc3c3c3c3 //[1]no SelectSimpleDA: (60: 5916 02d5)(1512: 99f1 6127)
2059+#define SimpleData_FixVal06 0x96969696 //[1]no SelectSimpleDA: (60: 0963 d516)(1512: a2f6 db95)
2060+#define SimpleData_FixVal07 0xf0f0f0f0 //[1]no SelectSimpleDA: (60: dfea 4dab)(1512: 39dc f576)
2061+#define SimpleData_FixVal08 0x5555aaaa //[2]no SelectSimpleDA: (60: b61b 5777)(1512: 4652 ddb0)
2062+#define SimpleData_FixVal09 0xffff0000 //[2]no SelectSimpleDA: (60: 16f0 f8f1)(1512: 305d a8d4)
2063+#define SimpleData_FixVal10 0x5a5aa5a5 //[2]no SelectSimpleDA: (60: 9d7d eb91)(1512: d08b 0eca)
2064+#define SimpleData_FixVal11 0xc3c33c3c //[2]no SelectSimpleDA: (60: bb6a 0b69)(1512: 06a9 efff)
2065+
2066+#define SelectSimpleDA_Dat0 0x67052301
2067+#define SelectSimpleDA_Dat1 0xe0cda089
2068+#define SelectSimpleDA_Dat2 0x98badcfe
2069+
2070+#define SelectWOLDA_DatH 0x206a
2071+#define SelectWOLDA_DatL 0x8a374d9b
2072+
2073+#define MOVE_DATA_MB_SEC 800 // MByte per second to move data
2074+
2075+//---------------------------------------------------------
2076+// Frame size
2077+//---------------------------------------------------------
2078+#define ENABLE_RAND_SIZE 0
2079+#define Rand_Sed 0xffccd
2080+#define FRAME_Rand_Simple 0
2081+#define MIN_FRAME_RAND_SIZE 60
2082+#define MAX_FRAME_RAND_SIZE 1514
2083+
2084+#define FRAME_SELH_PERD 7
2085+#ifdef Enable_Jumbo
2086+// #define FRAME_LENH 9212 //max:9212
2087+// #define FRAME_LENL 9211 //max:9212
2088+ #define FRAME_LENH 9212 //max:9212
2089+ #define FRAME_LENL 9212 //max:9212
2090+// #define FRAME_LENH 8120
2091+// #define FRAME_LENL 8119
2092+// #define FRAME_LENH 7000
2093+// #define FRAME_LENL 6999
2094+// #define FRAME_LENH 4095
2095+// #define FRAME_LENL 4094
2096+// #define FRAME_LENH 2040
2097+// #define FRAME_LENL 2039
2098+#else
2099+ #ifdef SelectSimpleLength
2100+// #define FRAME_LENH ( SelectSimpleLength + 1 )
2101+// #define FRAME_LENL ( SelectSimpleLength )
2102+ #define FRAME_LENH SelectSimpleLength
2103+ #define FRAME_LENL SelectSimpleLength
2104+ #else
2105+// #define FRAME_LENH 1514 //max:1514
2106+// #define FRAME_LENL 1513 //max:1514
2107+ #define FRAME_LENH 1514 //max:1514
2108+ #define FRAME_LENL 1514 //max:1514
2109+ #endif
2110+#endif
2111+
2112+const ULONG ARP_org_data[16] = {
2113+ 0xffffffff,
2114+ 0x0000ffff, // SA:00 00
2115+ 0x12345678, // SA:12 34 56 78
2116+ 0x01000608, // ARP(0x0806)
2117+ 0x04060008,
2118+ 0x00000100, // sender MAC Address: 00 00
2119+ 0x12345678, // sender MAC Address: 12 34 56 78
2120+ 0xeb00a8c0, // sender IP Address: 192.168.0.235
2121+ 0x00000000, // target MAC Address: 00 00 00 00
2122+ 0xa8c00000, // target MAC Address: 00 00, sender IP Address:192.168
2123+ 0x00000100, // sender IP Address: 0.1
2124+// 0x0000de00, // sender IP Address: 0.222
2125+ 0x00000000,
2126+ 0x00000000,
2127+ 0x00000000,
2128+ 0x00000000,
2129+ 0xc68e2bd5
2130+};
2131+
2132+#endif // MAC_H
2133diff --git a/arch/arm/cpu/arm926ejs/aspeed/MAC.c b/arch/arm/cpu/arm926ejs/aspeed/MAC.c
2134new file mode 100644
2135index 0000000..829da92
2136--- /dev/null
2137+++ b/arch/arm/cpu/arm926ejs/aspeed/MAC.c
2138@@ -0,0 +1,2085 @@
2139+/*
2140+ * This program is distributed in the hope that it will be useful,
2141+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2142+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2143+ * GNU General Public License for more details.
2144+ *
2145+ * You should have received a copy of the GNU General Public License
2146+ * along with this program; if not, write to the Free Software
2147+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2148+ */
2149+#define MAC_C
2150+static const char ThisFile[] = "MAC.c";
2151+
2152+#include "SWFUNC.H"
2153+
2154+#ifdef SLT_UBOOT
2155+ #include <common.h>
2156+ #include <command.h>
2157+ #include <COMMINF.H>
2158+ #include "STDUBOOT.H"
2159+#endif
2160+#ifdef SLT_DOS
2161+ #include <stdio.h>
2162+ #include <stdlib.h>
2163+ #include <conio.h>
2164+ #include <string.h>
2165+ #include "COMMINF.H"
2166+#endif
2167+
2168+#include "MAC.H"
2169+
2170+double Avg_frame_len;
2171+ULONG Check_Des_Val;
2172+ULONG wp_fir;
2173+ULONG wp;
2174+ULONG FRAME_LEN_Cur;
2175+ULONG gdata;
2176+ULONG CheckDesFail_DesNum;
2177+ULONG VGAMode;
2178+ULONG SCU_1ch_old;
2179+ULONG SCU_0ch_old;
2180+ULONG SCU_48h_default;
2181+ULONG SCU_2ch_old;
2182+ULONG SCU_80h_old;
2183+ULONG SCU_74h_old;
2184+ULONG SCU_a4h_old;
2185+ULONG SCU_88h_old;
2186+ULONG WDT_0ch_old;
2187+ULONG SCU_04h_mix;
2188+ULONG SCU_04h_old;
2189+ULONG WDT_2ch_old;
2190+char SCU_oldvld = 0;
2191+
2192+#ifdef SLT_UBOOT
2193+#else
2194+ static double timeused;
2195+#endif
2196+// -------------------------------------------------------------
2197+
2198+void Debug_delay (void) {
2199+ #ifdef DbgPrn_Enable_Debug_delay
2200+ GET_CAHR();
2201+ #endif
2202+}
2203+
2204+
2205+
2206+
2207+void dump_mac_ROreg (void) {
2208+ DELAY(Delay_MACDump);
2209+ printf("\n");
2210+ printf("[MAC-H] ROReg A0h~ACh: %08lx %08lx %08lx %08lx\n", ReadSOC_DD(H_MAC_BASE+0xA0), ReadSOC_DD(H_MAC_BASE+0xA4), ReadSOC_DD(H_MAC_BASE+0xA8), ReadSOC_DD(H_MAC_BASE+0xAC));
2211+ printf("[MAC-H] ROReg B0h~BCh: %08lx %08lx %08lx %08lx\n", ReadSOC_DD(H_MAC_BASE+0xB0), ReadSOC_DD(H_MAC_BASE+0xB4), ReadSOC_DD(H_MAC_BASE+0xB8), ReadSOC_DD(H_MAC_BASE+0xBC));
2212+ printf("[MAC-H] ROReg C0h~C8h: %08lx %08lx %08lx \n", ReadSOC_DD(H_MAC_BASE+0xC0), ReadSOC_DD(H_MAC_BASE+0xC4), ReadSOC_DD(H_MAC_BASE+0xC8));
2213+}
2214+
2215+//------------------------------------------------------------
2216+// SCU
2217+//------------------------------------------------------------
2218+void recov_scu (void) {
2219+ #ifdef DbgPrn_FuncHeader
2220+ printf ("recov_scu\n");
2221+ Debug_delay();
2222+ #endif
2223+
2224+ //MAC
2225+ WriteSOC_DD( H_MAC_BASE + 0x08, MAC_08h_old );
2226+ WriteSOC_DD( H_MAC_BASE + 0x0c, MAC_0ch_old );
2227+ WriteSOC_DD( H_MAC_BASE + 0x40, MAC_40h_old );
2228+
2229+ //SCU
2230+ WriteSOC_DD( SCU_BASE + 0x04, SCU_04h_old );
2231+ WriteSOC_DD( SCU_BASE + 0x08, SCU_08h_old );
2232+ WriteSOC_DD( SCU_BASE + 0x0c, SCU_0ch_old );
2233+ WriteSOC_DD( SCU_BASE + 0x1c, SCU_1ch_old );
2234+ WriteSOC_DD( SCU_BASE + 0x2c, SCU_2ch_old );
2235+ WriteSOC_DD( SCU_BASE + 0x48, SCU_48h_old );
2236+// WriteSOC_DD( SCU_BASE + 0x70, SCU_70h_old );
2237+ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old );
2238+ WriteSOC_DD( SCU_BASE + 0x7c, SCU_7ch_old );
2239+ WriteSOC_DD( SCU_BASE + 0x80, SCU_80h_old );
2240+ WriteSOC_DD( SCU_BASE + 0x88, SCU_88h_old );
2241+ WriteSOC_DD( SCU_BASE + 0x90, SCU_90h_old );
2242+ WriteSOC_DD( SCU_BASE + 0xa4, SCU_a4h_old );
2243+ WriteSOC_DD( SCU_BASE + 0xac, SCU_ach_old );
2244+ #ifdef AST1010_IOMAP
2245+ WriteSOC_DD( SCU_BASE + 0x11C, SCU_11Ch_old );
2246+ #endif
2247+
2248+ //WDT
2249+ #ifdef AST1010_IOMAP
2250+ #else
2251+ // WriteSOC_DD(0x1e78500c, WDT_0ch_old);
2252+ // WriteSOC_DD(0x1e78502c, WDT_2ch_old);
2253+ #endif
2254+
2255+ if ( ASTChipType == 3 ) {
2256+ if ( SCU_f0h_old & 0x01 ) WriteSOC_DD( SCU_BASE + 0xf0, 0xAEED0001 ); //Enable MAC34
2257+ if ( SCU_f0h_old & 0x02 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x2000DEEA ); //Enable Decode
2258+ if ( SCU_f0h_old & 0x04 ) WriteSOC_DD( SCU_BASE + 0xf0, 0xA0E0E0D3 ); //Enable I2S
2259+ if ( SCU_f0h_old & 0x08 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x4D0E0E0A ); //Enable PCI Host
2260+ if ( SCU_f0h_old & 0x10 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x10ADDEED ); //Enable IR
2261+ if ( SCU_f0h_old & 0x20 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x66559959 ); //Enabel Buffer Merge
2262+ if ( SCU_f0h_old & 0x40 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x68961A33 ); //Enable PS2 IO
2263+ if ( SCU_f0h_old & 0x80 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x68971A33 ); //Enable PS2 IO
2264+ }
2265+} // End void recov_scu (void)
2266+
2267+void read_scu (void) {
2268+ #ifdef DbgPrn_FuncHeader
2269+ printf ("read_scu\n");
2270+ Debug_delay();
2271+ #endif
2272+
2273+ if (!SCU_oldvld) {
2274+ //SCU
2275+ SCU_04h_old = ReadSOC_DD( SCU_BASE + 0x04 );
2276+ SCU_08h_old = ReadSOC_DD( SCU_BASE + 0x08 );
2277+ SCU_0ch_old = ReadSOC_DD( SCU_BASE + 0x0c );
2278+ SCU_1ch_old = ReadSOC_DD( SCU_BASE + 0x1c );
2279+ SCU_2ch_old = ReadSOC_DD( SCU_BASE + 0x2c );
2280+ SCU_48h_old = ReadSOC_DD( SCU_BASE + 0x48 );
2281+ SCU_70h_old = ReadSOC_DD( SCU_BASE + 0x70 );
2282+ SCU_74h_old = ReadSOC_DD( SCU_BASE + 0x74 );
2283+ SCU_7ch_old = ReadSOC_DD( SCU_BASE + 0x7c );
2284+ SCU_80h_old = ReadSOC_DD( SCU_BASE + 0x80 );
2285+ SCU_88h_old = ReadSOC_DD( SCU_BASE + 0x88 );
2286+ SCU_90h_old = ReadSOC_DD( SCU_BASE + 0x90 );
2287+ SCU_a4h_old = ReadSOC_DD( SCU_BASE + 0xa4 );
2288+ SCU_ach_old = ReadSOC_DD( SCU_BASE + 0xac );
2289+ SCU_f0h_old = ReadSOC_DD( SCU_BASE + 0xf0 );
2290+ #ifdef AST1010_IOMAP
2291+ SCU_11Ch_old = ReadSOC_DD( SCU_BASE + 0x11C );
2292+ #endif
2293+
2294+ //WDT
2295+ #ifdef AST1010_IOMAP
2296+ #else
2297+ WDT_0ch_old = ReadSOC_DD( 0x1e78500c );
2298+ WDT_2ch_old = ReadSOC_DD( 0x1e78502c );
2299+ #endif
2300+
2301+ SCU_oldvld = 1;
2302+ } // End if (!SCU_oldvld)
2303+} // End read_scu()
2304+
2305+void Setting_scu (void)
2306+{
2307+ //SCU
2308+ if (AST1010) {
2309+ do {
2310+ WriteSOC_DD( SCU_BASE + 0x00 , 0x1688a8a8);
2311+ #ifndef SLT_UBOOT
2312+ WriteSOC_DD( SCU_BASE + 0x70 , SCU_70h_old & 0xfffffffe); // Disable CPU
2313+ #endif
2314+ } while ( ReadSOC_DD( SCU_BASE + 0x00 ) != 0x1 );
2315+
2316+ #if( AST1010_IOMAP == 1)
2317+ WriteSOC_DD( SCU_BASE + 0x11C, 0x00000000); // Disable Cache functionn
2318+ #endif
2319+ }
2320+ else {
2321+ do {
2322+ WriteSOC_DD( SCU_BASE + 0x00, 0x1688a8a8);
2323+ #ifndef SLT_UBOOT
2324+ WriteSOC_DD( SCU_BASE + 0x70, SCU_70h_old | 0x3 ); // Disable CPU
2325+ #endif
2326+ } while ( ReadSOC_DD( SCU_BASE + 0x00 ) != 0x1 );
2327+ } // End if (AST1010)
2328+
2329+ //WDT
2330+ #ifdef AST1010_IOMAP
2331+ #else
2332+ WriteSOC_DD( 0x1e78500c, WDT_0ch_old & 0xfffffffc );
2333+ WriteSOC_DD( 0x1e78502c, WDT_2ch_old & 0xfffffffc );
2334+ #endif
2335+}
2336+
2337+//------------------------------------------------------------
2338+void init_scu1 (void) {
2339+ #ifdef DbgPrn_FuncHeader
2340+ printf ("init_scu1\n");
2341+ Debug_delay();
2342+ #endif
2343+
2344+ if (AST3200) {
2345+ WriteSOC_DD( SCU_BASE + 0x0c, (SCU_0ch_old & 0xffefffff) );//Clock Stop Control
2346+ }
2347+ else if (AST1010) {
2348+ WriteSOC_DD( SCU_BASE + 0x0c, ( SCU_0ch_old & 0xffffffbf ) );//Clock Stop Control
2349+ WriteSOC_DD( SCU_BASE + 0x88, ((SCU_88h_old & 0x003fffff ) | 0xffc00000) );//Multi-function Pin Control
2350+ }
2351+ else if (AST2300) {
2352+#ifdef Enable_BufMerge
2353+ WriteSOC_DD( SCU_BASE + 0xf0, 0x66559959 );//MAC buffer merge
2354+#endif
2355+
2356+#ifdef Enable_AST2300_Int125MHz
2357+ SCU_48h_mix = (SCU_48h_old & 0xf0000000) | 0x80000000;
2358+// WriteSOC_DD( SCU_BASE + 0xf0, 0xa0e0e0d3 );//Enable I2S
2359+// WriteSOC_DD( SCU_BASE + 0x04, SCU_04h_old & 0xfffdffff );//Rst(Enable I2S)
2360+//
2361+//// WriteSOC_DD( 0x1e6e5020, ReadSOC_DD(0x1e6e5020) | 0x00010000 );//P_I2SPLLAdjEnable
2362+// WriteSOC_DD( 0x1e6e5020, ReadSOC_DD(0x1e6e5020) | 0x00000000 );//P_I2SPLLAdjEnable
2363+// WriteSOC_DD( 0x1e6e5024, 0x00000175 );//P_I2SPLLAdjCnt
2364+
2365+// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000a51a );//124800000(24MHz)
2366+// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000a92f );//125333333(24MHz)
2367+// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000587d );//125000000(24MHz)
2368+ WriteSOC_DD( SCU_BASE + 0x1c, 0x00006c7d );//125000000(24MHz)
2369+ WriteSOC_DD( SCU_BASE + 0x2c, 0x00300000 | (SCU_2ch_old & 0xffcfffef) );//D-PLL assigned to VGA, D2-PLL assigned to I2S.
2370+ WriteSOC_DD( SCU_BASE + 0x48, 0x80000000 | SCU_48h_old );//125MHz come from I2SPLL
2371+#else
2372+ SCU_48h_mix = (SCU_48h_old & 0xf0000000);
2373+#endif
2374+ switch (SelectMAC) {
2375+ case 0 :
2376+ WriteSOC_DD( SCU_BASE + 0x88, (SCU_88h_old & 0x3fffffff) | 0xc0000000 );//[31]MAC1 MDIO, [30]MAC1 MDC
2377+ break;
2378+ case 1 :
2379+ WriteSOC_DD( SCU_BASE + 0x90, (SCU_90h_old & 0xfffffffb) | 0x00000004 );//[2 ]MAC2 MDC/MDIO
2380+ break;
2381+ case 2 :
2382+ case 3 :
2383+ default : break;
2384+ }
2385+
2386+ WriteSOC_DD(SCU_BASE+0x0c, (SCU_0ch_old & 0xff0fffff) );//Clock Stop Control
2387+// WriteSOC_DD(SCU_BASE+0x80, (SCU_80h_old & 0xfffffff0) | 0x0000000f);//MAC1LINK/MAC2LINK
2388+ }
2389+ else {
2390+ switch (SelectMAC) {
2391+ case 0 :
2392+// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfdffffff) | 0x02000000);//[25]MAC1 PHYLINK
2393+ break;
2394+ case 1 :
2395+ if (MAC2_RMII) {
2396+// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfbefffff) | 0x04100000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
2397+ WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xffefffff) | 0x00100000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
2398+ } else {
2399+// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfbcfffff) | 0x04300000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
2400+ WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xffcfffff) | 0x00300000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
2401+ }
2402+ break;
2403+ default : break;
2404+ } // End switch (SelectMAC)
2405+ } // End if (AST3200)
2406+} // End void init_scu1 (void)
2407+
2408+//------------------------------------------------------------
2409+void init_scu_macrst (void) {
2410+
2411+#ifdef Enable_AST2300_Int125MHz
2412+ if (ASTChipType == 3) {
2413+ SCU_04h_mix = SCU_04h_old & 0xfffdffff;
2414+ } else {
2415+ SCU_04h_mix = SCU_04h_old;
2416+ }
2417+#else
2418+ SCU_04h_mix = SCU_04h_old;
2419+#endif
2420+
2421+ WriteSOC_DD ( SCU_BASE + 0x04, (SCU_04h_mix & ~SCU_04h) | SCU_04h);//Rst
2422+ DELAY(Delay_SCU);
2423+ WriteSOC_DD ( SCU_BASE + 0x04, (SCU_04h_mix & ~SCU_04h) );//Enable Engine
2424+// DELAY(Delay_SCU);
2425+} // End void init_scu_macrst (void)
2426+
2427+//------------------------------------------------------------
2428+void init_scu2 (void) {
2429+
2430+#ifdef SCU_74h
2431+ #ifdef DbgPrn_FuncHeader
2432+ printf ("init_scu2\n");
2433+ Debug_delay();
2434+ #endif
2435+
2436+ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old | SCU_74h );//PinMux
2437+ delay(Delay_SCU);
2438+#endif
2439+
2440+} // End void init_scu2 (void)
2441+
2442+//------------------------------------------------------------
2443+void init_scu3 (void) {
2444+
2445+#ifdef SCU_74h
2446+ #ifdef DbgPrn_FuncHeader
2447+ printf ("init_scu3\n");
2448+ Debug_delay();
2449+ #endif
2450+
2451+ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old | (SCU_74h & 0xffefffff) );//PinMux
2452+ delay(Delay_SCU);
2453+#endif
2454+
2455+} // End void init_scu3 (void)
2456+
2457+//------------------------------------------------------------
2458+// MAC
2459+//------------------------------------------------------------
2460+void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase) {
2461+ #ifdef DbgPrn_FuncHeader
2462+ printf ("init_mac\n");
2463+ Debug_delay();
2464+ #endif
2465+
2466+#ifdef Enable_MAC_SWRst
2467+ WriteSOC_DD( base + 0x50, 0x80000000 | MAC_50h | MAC_50h_Speed);
2468+// WriteSOC_DD( base + 0x50, 0x80000000);
2469+
2470+ while (0x80000000 & ReadSOC_DD(base+0x50)) {
2471+//printf(".");
2472+ DELAY(Delay_MACRst);
2473+ }
2474+ DELAY(Delay_MACRst);
2475+#endif
2476+
2477+ WriteSOC_DD( base + 0x20, (tdexbase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
2478+ WriteSOC_DD( base + 0x24, (rdexbase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
2479+
2480+#ifdef MAC_30h
2481+ WriteSOC_DD( base + 0x30, MAC_30h);//Int Thr/Cnt
2482+#endif
2483+
2484+#ifdef MAC_34h
2485+ WriteSOC_DD( base + 0x34, MAC_34h);//Poll Cnt
2486+#endif
2487+
2488+#ifdef MAC_38h
2489+ WriteSOC_DD( base + 0x38, MAC_38h);
2490+#endif
2491+
2492+#ifdef MAC_40h
2493+ if (Enable_MACLoopback) {
2494+ if (AST2300_NewMDIO) WriteSOC_DD( base + 0x40, MAC_40h | 0x80000000);
2495+ else WriteSOC_DD( base + 0x40, MAC_40h);
2496+ }
2497+#endif
2498+
2499+#ifdef MAC_48h
2500+ WriteSOC_DD( base + 0x48, MAC_48h);
2501+#endif
2502+
2503+ if ( ModeSwitch == MODE_NSCI )
2504+ WriteSOC_DD( base + 0x4c, NCSI_RxDMA_PakSize);
2505+ else
2506+ WriteSOC_DD( base + 0x4c, DMA_PakSize);
2507+
2508+ WriteSOC_DD( base + 0x50, MAC_50h | MAC_50h_Speed | 0xf);
2509+ DELAY(Delay_MACRst);
2510+} // End void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase)
2511+
2512+//------------------------------------------------------------
2513+// Basic
2514+//------------------------------------------------------------
2515+void FPri_RegValue (BYTE option) {
2516+
2517+#ifdef SLT_UBOOT
2518+#else
2519+ time_t timecur;
2520+#endif
2521+
2522+ FILE_VAR
2523+
2524+ GET_OBJ( option )
2525+
2526+ PRINT(OUT_OBJ "[SCU] 04:%08lx 08:%08lx 0c:%08lx 48:%08lx\n", SCU_04h_old, SCU_08h_old, SCU_0ch_old, SCU_48h_old);
2527+ PRINT(OUT_OBJ "[SCU] 70:%08lx 74:%08lx 7c:%08lx\n", SCU_70h_old, SCU_74h_old, SCU_7ch_old);
2528+ PRINT(OUT_OBJ "[SCU] 80:%08lx 88:%08lx 90:%08lx f0:%08lx\n", SCU_80h_old, SCU_88h_old, SCU_90h_old, SCU_f0h_old);
2529+ PRINT(OUT_OBJ "[SCU] a4:%08lx ac:%08lx\n", SCU_a4h_old, SCU_ach_old);
2530+ PRINT(OUT_OBJ "[WDT] 0c:%08lx 2c:%08lx\n", WDT_0ch_old, WDT_2ch_old);
2531+ PRINT(OUT_OBJ "[MAC] 08:%08lx 0c:%08lx\n", MAC_08h_old, MAC_0ch_old);
2532+ PRINT(OUT_OBJ "[MAC] A0|%08lx %08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xa0), ReadSOC_DD( MAC_PHYBASE + 0xa4 ), ReadSOC_DD( MAC_PHYBASE + 0xa8 ), ReadSOC_DD(MAC_PHYBASE + 0xac ) );
2533+ PRINT(OUT_OBJ "[MAC] B0|%08lx %08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xb0), ReadSOC_DD( MAC_PHYBASE + 0xb4 ), ReadSOC_DD( MAC_PHYBASE + 0xb8 ), ReadSOC_DD(MAC_PHYBASE + 0xbc ) );
2534+ PRINT(OUT_OBJ "[MAC] C0|%08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xc0), ReadSOC_DD( MAC_PHYBASE + 0xc4 ), ReadSOC_DD( MAC_PHYBASE + 0xc8 ));
2535+
2536+#ifdef SLT_UBOOT
2537+#else
2538+ fprintf(fp, "Time: %s", ctime(&timestart));
2539+ time(&timecur);
2540+ fprintf(fp, "----> %s", ctime(&timecur));
2541+#endif
2542+} // End void FPri_RegValue (BYTE *fp)
2543+
2544+//------------------------------------------------------------
2545+void FPri_End (BYTE option) {
2546+
2547+ FILE_VAR
2548+
2549+ GET_OBJ( option )
2550+
2551+ if ( !RxDataEnable ) {
2552+ }
2553+ else if ( Err_Flag ) {
2554+ PRINT(OUT_OBJ " \n----> fail !!!\n");
2555+ } else {
2556+ PRINT(OUT_OBJ " \n----> All Pass !!!\n");
2557+ }
2558+
2559+ if ( ModeSwitch == MODE_DEDICATED ) {
2560+ if (PHY_ADR_arg != PHY_ADR)
2561+ PRINT(OUT_OBJ "\n[Warning] PHY Address change from %d to %d !!!\n", PHY_ADR_arg, PHY_ADR);
2562+ }
2563+
2564+ if ( AST1010 ) {
2565+ Dat_ULONG = (SCU_ach_old >> 12) & 0xf;
2566+ if (Dat_ULONG) {
2567+ PRINT(OUT_OBJ "\n[Warning] SCUAC[15:12] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
2568+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
2569+ }
2570+
2571+ SCU_48h_default = SCU_48h_AST1010 & 0x01000f00;
2572+ if ((SCU_48h_old != SCU_48h_default)) {
2573+ PRINT(OUT_OBJ "\n[Warning] SCU48 == 0x%08lx is not the suggestion value 0x%08lx.\n", SCU_48h_old, SCU_48h_default);
2574+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
2575+ }
2576+ }
2577+ else if ( AST2300 ) {
2578+ if ( AST2400 ) {
2579+ Dat_ULONG = (SCU_90h_old >> 8) & 0xf;
2580+ if (Dat_ULONG) {
2581+ PRINT(OUT_OBJ "\n[Warning] SCU90[11: 8] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
2582+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
2583+ }
2584+ }
2585+ else {
2586+ Dat_ULONG = (SCU_90h_old >> 8) & 0xff;
2587+ if (Dat_ULONG) {
2588+ PRINT(OUT_OBJ "\n[Warning] SCU90[15: 8] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
2589+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
2590+ }
2591+ }
2592+
2593+ if (Enable_MAC34) SCU_48h_default = SCU_48h_AST2300;
2594+ else SCU_48h_default = SCU_48h_AST2300 & 0x0300ffff;
2595+
2596+ if ((SCU_48h_old != SCU_48h_default)) {
2597+ PRINT(OUT_OBJ "\n[Warning] SCU48 == 0x%08lx is not the suggestion value 0x%08lx.\n", SCU_48h_old, SCU_48h_default);
2598+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
2599+ }
2600+ } // End if ( AST1010 )
2601+
2602+ if ( ModeSwitch == MODE_NSCI ) {
2603+ PRINT(OUT_OBJ "\n[Arg] %d %d %d %d %d %ld (%s)\n", GRun_Mode, PackageTolNum, ChannelTolNum, TestMode, IOTimingBund, (ARPNumCnt| (ULONG)PrintNCSIEn), ASTChipName);
2604+
2605+ switch (NCSI_Cap_SLT.PCI_DID_VID) {
2606+ case PCI_DID_VID_Intel_82574L : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82574L \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2607+ case PCI_DID_VID_Intel_82575_10d6 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2608+ case PCI_DID_VID_Intel_82575_10a7 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2609+ case PCI_DID_VID_Intel_82575_10a9 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2610+ case PCI_DID_VID_Intel_82576_10c9 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2611+ case PCI_DID_VID_Intel_82576_10e6 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2612+ case PCI_DID_VID_Intel_82576_10e7 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2613+ case PCI_DID_VID_Intel_82576_10e8 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2614+ case PCI_DID_VID_Intel_82576_1518 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2615+ case PCI_DID_VID_Intel_82576_1526 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2616+ case PCI_DID_VID_Intel_82576_150a : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2617+ case PCI_DID_VID_Intel_82576_150d : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2618+ case PCI_DID_VID_Intel_82599_10fb : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82599 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2619+ case PCI_DID_VID_Intel_82599_1557 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82599 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2620+ case PCI_DID_VID_Intel_I350_1521 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I350 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2621+ case PCI_DID_VID_Intel_I350_1523 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I350 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2622+ case PCI_DID_VID_Intel_I210 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I210 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2623+ case PCI_DID_VID_Intel_X540 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel X540 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2624+ case PCI_DID_VID_Broadcom_BCM5718 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5718 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2625+ case PCI_DID_VID_Broadcom_BCM5720 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5720 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2626+ case PCI_DID_VID_Broadcom_BCM5725 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5725 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2627+// case PCI_DID_VID_Broadcom_BCM57810 : PRINT( OUT_OBJ "[NC]%08x %08x: Broadcom BCM57810 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2628+ case PCI_DID_VID_Mellanox_ConnectX_3 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Mellanox ConnectX-3\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2629+ default :
2630+ switch (NCSI_Cap_SLT.ManufacturerID) {
2631+ case ManufacturerID_Intel : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2632+ case ManufacturerID_Broadcom : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2633+ case ManufacturerID_Mellanox : PRINT( OUT_OBJ "[NC]%08lx %08lx: Mellanox\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
2634+ default : PRINT(OUT_OBJ "[NC]%08lx %08lx \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID); break;
2635+ } // End switch (NCSI_Cap_SLT.ManufacturerID)
2636+ } // End switch (NCSI_Cap_SLT.PCI_DID_VID)
2637+ }
2638+ else {
2639+ if (LOOP_INFINI) PRINT(OUT_OBJ "\n[Arg] %d %d %d # %d %d %d %lx (%s)[%d %d %d]\n" , GRun_Mode, GSpeed, GCtrl, TestMode, PHY_ADR_arg, IOTimingBund, UserDVal, ASTChipName, Loop_rl[0], Loop_rl[1], Loop_rl[2]);
2640+ else PRINT(OUT_OBJ "\n[Arg] %d %d %d %ld %d %d %d %lx (%s)[%d %d %d]\n", GRun_Mode, GSpeed, GCtrl, LOOP_MAX_arg, TestMode, PHY_ADR_arg, IOTimingBund, UserDVal, ASTChipName, Loop_rl[0], Loop_rl[1], Loop_rl[2]);
2641+
2642+ PRINT(OUT_OBJ "[PHY] Adr:%d ID2:%04lx ID3:%04lx (%s)\n", PHY_ADR, PHY_ID2, PHY_ID3, PHYName);
2643+ } // End if ( ModeSwitch == MODE_NSCI )
2644+
2645+#ifdef SUPPORT_PHY_LAN9303
2646+ PRINT(OUT_OBJ "[Ver II] %s (for LAN9303 with I2C%d)\n", version_name, LAN9303_I2C_BUSNUM);
2647+#else
2648+ PRINT(OUT_OBJ "[Ver II] %s\n", version_name);
2649+#endif
2650+} // End void FPri_End (BYTE option)
2651+
2652+//------------------------------------------------------------
2653+void FPri_ErrFlag (BYTE option) {
2654+
2655+ FILE_VAR
2656+
2657+ GET_OBJ( option )
2658+
2659+ if (Err_Flag && Err_Flag_PrintEn) {
2660+ PRINT(OUT_OBJ "\n\n");
2661+//fprintf(fp, "Err_Flag: %x\n\n", Err_Flag);
2662+
2663+ if ( Err_Flag & Err_PHY_Type ) PRINT( OUT_OBJ "[Err] Unidentifiable PHY \n" );
2664+ if ( Err_Flag & Err_MALLOC_FrmSize ) PRINT( OUT_OBJ "[Err] Malloc fail at frame size buffer \n" );
2665+ if ( Err_Flag & Err_MALLOC_LastWP ) PRINT( OUT_OBJ "[Err] Malloc fail at last WP buffer \n" );
2666+ if ( Err_Flag & Err_Check_Buf_Data ) PRINT( OUT_OBJ "[Err] Received data mismatch \n" );
2667+ if ( Err_Flag & Err_NCSI_Check_TxOwnTimeOut ) PRINT( OUT_OBJ "[Err] Time out of checking Tx owner bit in NCSI packet \n" );
2668+ if ( Err_Flag & Err_NCSI_Check_RxOwnTimeOut ) PRINT( OUT_OBJ "[Err] Time out of checking Rx owner bit in NCSI packet \n" );
2669+ if ( Err_Flag & Err_NCSI_Check_ARPOwnTimeOut) PRINT( OUT_OBJ "[Err] Time out of checking ARP owner bit in NCSI packet \n" );
2670+ if ( Err_Flag & Err_NCSI_No_PHY ) PRINT( OUT_OBJ "[Err] Can not find NCSI PHY \n" );
2671+ if ( Err_Flag & Err_NCSI_Channel_Num ) PRINT( OUT_OBJ "[Err] NCSI Channel Number Mismatch \n" );
2672+ if ( Err_Flag & Err_NCSI_Package_Num ) PRINT( OUT_OBJ "[Err] NCSI Package Number Mismatch \n" );
2673+ if ( Err_Flag & Err_PHY_TimeOut ) PRINT( OUT_OBJ "[Err] Time out of read/write/reset PHY register \n" );
2674+ if ( Err_Flag & Err_RXBUF_UNAVA ) PRINT( OUT_OBJ "[Err] MAC00h[2]:Receiving buffer unavailable \n" );
2675+ if ( Err_Flag & Err_RPKT_LOST ) PRINT( OUT_OBJ "[Err] MAC00h[3]:Received packet lost due to RX FIFO full \n" );
2676+ if ( Err_Flag & Err_NPTXBUF_UNAVA ) PRINT( OUT_OBJ "[Err] MAC00h[6]:Normal priority transmit buffer unavailable \n" );
2677+ if ( Err_Flag & Err_TPKT_LOST ) PRINT( OUT_OBJ "[Err] MAC00h[7]:Packets transmitted to Ethernet lost \n" );
2678+ if ( Err_Flag & Err_DMABufNum ) PRINT( OUT_OBJ "[Err] DMA Buffer is not enough \n" );
2679+ if ( Err_Flag & Err_IOMargin ) PRINT( OUT_OBJ "[Err] IO timing margin is not enough \n" );
2680+
2681+ if ( Err_Flag & Err_MHCLK_Ratio ) {
2682+ if ( AST1010 ) {
2683+ PRINT(OUT_OBJ "[Err] Error setting of MAC AHB bus clock (SCU08[13:12]) \n");
2684+ Dat_ULONG = (SCU_08h_old >> 12) & 0x3;
2685+ PRINT(OUT_OBJ " SCU08[13:12] == 0x%01lx is not the suggestion value 0.\n", Dat_ULONG);
2686+ }
2687+ else {
2688+ PRINT(OUT_OBJ "[Err] Error setting of MAC AHB bus clock (SCU08[18:16]) \n");
2689+ Dat_ULONG = (SCU_08h_old >> 16) & 0x7;
2690+
2691+ if (MAC1_1GEn | MAC2_1GEn) {
2692+ PRINT(OUT_OBJ " SCU08[18:16] == 0x%01lx is not the suggestion value 2.\n", Dat_ULONG);
2693+ }
2694+ else {
2695+ PRINT(OUT_OBJ " SCU08[18:16] == 0x%01lx is not the suggestion value 4.\n", Dat_ULONG);
2696+ }
2697+ } // end if ( AST1010 )
2698+ } // End if ( Err_Flag & Err_MHCLK_Ratio )
2699+
2700+ if (Err_Flag & Err_IOMarginOUF ) {
2701+ PRINT(OUT_OBJ "[Err] IO timing testing range out of boundary\n");
2702+ if (Enable_RMII) {
2703+#ifdef Enable_Old_Style
2704+ PRINT(OUT_OBJ " (%d,%d): 1x%d [%d]x[%d:%d]\n", IOdly_out_reg_idx, IOdly_in_reg_idx, IOTimingBund, IOdly_out_reg_idx, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1));
2705+#else
2706+ PRINT(OUT_OBJ " (%d,%d): %dx1 [%d:%d]x[%d]\n", IOdly_in_reg_idx, IOdly_out_reg_idx, IOTimingBund, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1), IOdly_out_reg_idx);
2707+#endif
2708+ } else {
2709+#ifdef Enable_Old_Style
2710+ PRINT(OUT_OBJ " (%d,%d): %dx%d [%d:%d]x[%d:%d]\n", IOdly_out_reg_idx, IOdly_in_reg_idx, IOTimingBund, IOTimingBund, IOdly_out_reg_idx - (IOTimingBund>>1), IOdly_out_reg_idx + (IOTimingBund>>1), IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1));
2711+#else
2712+ PRINT(OUT_OBJ " (%d,%d): %dx%d [%d:%d]x[%d:%d]\n", IOdly_in_reg_idx, IOdly_out_reg_idx, IOTimingBund, IOTimingBund, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1), IOdly_out_reg_idx - (IOTimingBund>>1), IOdly_out_reg_idx + (IOTimingBund>>1));
2713+#endif
2714+ }
2715+ } // End if (Err_Flag & Err_IOMarginOUF )
2716+
2717+ if (Err_Flag & Err_Check_Des ) {
2718+ PRINT(OUT_OBJ "[Err] Descriptor error\n");
2719+ if ( Check_Des_Val & Check_Des_TxOwnTimeOut ) PRINT( OUT_OBJ "[Des] Time out of checking Tx owner bit\n" );
2720+ if ( Check_Des_Val & Check_Des_RxOwnTimeOut ) PRINT( OUT_OBJ "[Des] Time out of checking Rx owner bit\n" );
2721+ if ( Check_Des_Val & Check_Des_RxErr ) PRINT( OUT_OBJ "[Des] Input signal RxErr \n" );
2722+ if ( Check_Des_Val & Check_Des_OddNibble ) PRINT( OUT_OBJ "[Des] Nibble bit happen \n" );
2723+ if ( Check_Des_Val & Check_Des_CRC ) PRINT( OUT_OBJ "[Des] CRC error of frame \n" );
2724+ if ( Check_Des_Val & Check_Des_RxFIFOFull ) PRINT( OUT_OBJ "[Des] Rx FIFO full \n" );
2725+ if ( Check_Des_Val & Check_Des_FrameLen ) PRINT( OUT_OBJ "[Des] Frame length mismatch \n" );
2726+ } // End if (Err_Flag & Err_Check_Des )
2727+
2728+ if (Err_Flag & Err_MACMode ) {
2729+ PRINT(OUT_OBJ "[Err] MAC interface mode mismatch\n");
2730+ if ( AST1010 ) {
2731+ }
2732+ else if (AST2300) {
2733+ switch (MAC_Mode) {
2734+ case 0 : PRINT( OUT_OBJ " SCU70h[7:6] == 0: [MAC#1] RMII [MAC#2] RMII \n" ); break;
2735+ case 1 : PRINT( OUT_OBJ " SCU70h[7:6] == 1: [MAC#1] RGMII [MAC#2] RMII \n" ); break;
2736+ case 2 : PRINT( OUT_OBJ " SCU70h[7:6] == 2: [MAC#1] RMII [MAC#2] RGMII\n" ); break;
2737+ case 3 : PRINT( OUT_OBJ " SCU70h[7:6] == 3: [MAC#1] RGMII [MAC#2] RGMII\n" ); break;
2738+ }
2739+ }
2740+ else {
2741+ switch (MAC_Mode) {
2742+ case 0 : PRINT( OUT_OBJ " SCU70h[8:6] == 000: [MAC#1] GMII \n" ); break;
2743+ case 1 : PRINT( OUT_OBJ " SCU70h[8:6] == 001: [MAC#1] MII [MAC#2] MII \n" ); break;
2744+ case 2 : PRINT( OUT_OBJ " SCU70h[8:6] == 010: [MAC#1] RMII [MAC#2] MII \n" ); break;
2745+ case 3 : PRINT( OUT_OBJ " SCU70h[8:6] == 011: [MAC#1] MII \n" ); break;
2746+ case 4 : PRINT( OUT_OBJ " SCU70h[8:6] == 100: [MAC#1] RMII \n" ); break;
2747+ case 5 : PRINT( OUT_OBJ " SCU70h[8:6] == 101: Reserved \n" ); break;
2748+ case 6 : PRINT( OUT_OBJ " SCU70h[8:6] == 110: [MAC#1] RMII [MAC#2] RMII\n" ); break;
2749+ case 7 : PRINT( OUT_OBJ " SCU70h[8:6] == 111: Disable MAC \n" ); break;
2750+ }
2751+ } // End if ( AST1010 )
2752+ } // End if (Err_Flag & Err_MACMode )
2753+
2754+ if ( ModeSwitch == MODE_NSCI ) {
2755+ if (Err_Flag & Err_NCSI_LinkFail ) {
2756+ PRINT(OUT_OBJ "[Err] NCSI packet retry number over flows when find channel\n");
2757+
2758+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Get_Version_ID ) PRINT(OUT_OBJ "[NCSI] Time out when Get Version ID \n");
2759+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Get_Capabilities ) PRINT(OUT_OBJ "[NCSI] Time out when Get Capabilities \n");
2760+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Select_Active_Package ) PRINT(OUT_OBJ "[NCSI] Time out when Select Active Package \n");
2761+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Set_MAC_Address ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Set MAC Address \n");
2762+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Broadcast_Filter) PRINT(OUT_OBJ "[NCSI] Time out when Enable Broadcast Filter\n");
2763+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Network_TX ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Network TX \n");
2764+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Channel ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Channel \n");
2765+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Disable_Network_TX ) PRINT(OUT_OBJ "[NCSI] Time out when Disable Network TX \n");
2766+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Disable_Channel ) PRINT(OUT_OBJ "[NCSI] Time out when Disable Channel \n");
2767+ }
2768+
2769+ if (Err_Flag & Err_NCSI_Channel_Num ) PRINT(OUT_OBJ "[NCSI] Channel number expected: %d, real: %d\n", ChannelTolNum, number_chl);
2770+ if (Err_Flag & Err_NCSI_Package_Num ) PRINT(OUT_OBJ "[NCSI] Peckage number expected: %d, real: %d\n", PackageTolNum, number_pak);
2771+ } // End if ( ModeSwitch == MODE_NSCI )
2772+ } // End if (Err_Flag && Err_Flag_PrintEn)
2773+} // End void FPri_ErrFlag (BYTE option)
2774+
2775+//------------------------------------------------------------
2776+void Finish_Close (void) {
2777+
2778+ if (SCU_oldvld)
2779+ recov_scu();
2780+
2781+#ifdef SLT_DOS
2782+ if (fp_io && IOTiming)
2783+ fclose(fp_io);
2784+
2785+ if (fp_log)
2786+ fclose(fp_log);
2787+#endif
2788+} // End void Finish_Close (void)
2789+
2790+//------------------------------------------------------------
2791+char Finish_Check (int value) {
2792+ ULONG temp;
2793+ CHAR i = 0;
2794+
2795+#ifdef Disable_VGA
2796+ if (VGAModeVld) {
2797+ outp(0x3d4, 0x17);
2798+ outp(0x3d5, VGAMode);
2799+ }
2800+#endif
2801+ #ifdef DbgPrn_FuncHeader
2802+ printf ("Finish_Check\n");
2803+ Debug_delay();
2804+ #endif
2805+
2806+ if ( FRAME_LEN )
2807+ free(FRAME_LEN);
2808+
2809+ if ( wp_lst )
2810+ free(wp_lst );
2811+
2812+ Err_Flag = Err_Flag | value;
2813+
2814+ if ( DbgPrn_ErrFlg )
2815+ printf ("\nErr_Flag: [%08lx]\n", Err_Flag);
2816+
2817+ if ( !BurstEnable )
2818+ FPri_ErrFlag( FP_LOG );
2819+
2820+ if ( IOTiming )
2821+ FPri_ErrFlag( FP_IO );
2822+
2823+ FPri_ErrFlag( STD_OUT );
2824+
2825+ if ( !BurstEnable )
2826+ FPri_End( FP_LOG );
2827+
2828+ if ( IOTiming )
2829+ FPri_End( FP_IO );
2830+
2831+ FPri_End( STD_OUT );
2832+
2833+
2834+ if ( !BurstEnable ) FPri_RegValue( FP_LOG );
2835+ if ( IOTiming ) FPri_RegValue( FP_IO );
2836+
2837+ Finish_Close();
2838+
2839+ // 20140325
2840+ temp = ReadSOC_DD( 0x1e6e2040 );
2841+ if ( ModeSwitch == MODE_NSCI )
2842+ {
2843+ if ( SelectMAC == 0 )
2844+ i = 17;
2845+ else
2846+ i = 16;
2847+ }
2848+ else
2849+ {
2850+ if ( SelectMAC == 0 )
2851+ i = 19;
2852+ else
2853+ i = 18;
2854+ }
2855+ WriteSOC_DD( 0x1e6e2040, (temp | (1 << i)) );
2856+
2857+
2858+ if ( Err_Flag )
2859+ {
2860+ // Fail
2861+ return( 1 );
2862+ }
2863+ else
2864+ {
2865+ // Pass
2866+ return( 0 );
2867+ }
2868+} // End char Finish_Check (int value)
2869+
2870+//------------------------------------------------------------
2871+int FindErr (int value) {
2872+ Err_Flag = Err_Flag | value;
2873+
2874+ if ( DbgPrn_ErrFlg )
2875+ printf ("\nErr_Flag: [%08lx]\n", Err_Flag);
2876+
2877+ return(1);
2878+}
2879+
2880+//------------------------------------------------------------
2881+int FindErr_Des (int value) {
2882+ Check_Des_Val = Check_Des_Val | value;
2883+ Err_Flag = Err_Flag | Err_Check_Des;
2884+ if ( DbgPrn_ErrFlg )
2885+ printf ("\nErr_Flag: [%08lx] Check_Des_Val: [%08lx]\n", Err_Flag, Check_Des_Val);
2886+
2887+ return(1);
2888+}
2889+
2890+//------------------------------------------------------------
2891+// Get and Check status of Interrupt
2892+//------------------------------------------------------------
2893+int check_int ( char *type ) {
2894+ #ifdef DbgPrn_FuncHeader
2895+ printf ("check_int : %d\n", Loop);
2896+ Debug_delay();
2897+ #endif
2898+
2899+ Dat_ULONG = ReadSOC_DD( H_MAC_BASE + 0x00 );//Interrupt Status
2900+#ifdef SLT_DOS
2901+#ifdef CheckRxbufUNAVA
2902+ if ( Dat_ULONG & 0x00000004 ) {
2903+ fprintf(fp_log, "[%sIntStatus] Receiving buffer unavailable : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
2904+ FindErr( Err_RXBUF_UNAVA );
2905+ }
2906+#endif
2907+
2908+#ifdef CheckRPktLost
2909+ if ( Dat_ULONG & 0x00000008 ) {
2910+ fprintf(fp_log, "[%sIntStatus] Received packet lost due to RX FIFO full : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
2911+ FindErr( Err_RPKT_LOST );
2912+ }
2913+#endif
2914+
2915+#ifdef CheckNPTxbufUNAVA
2916+ if ( Dat_ULONG & 0x00000040 ) {
2917+ fprintf(fp_log, "[%sIntStatus] Normal priority transmit buffer unavailable: %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
2918+ FindErr( Err_NPTXBUF_UNAVA );
2919+ }
2920+#endif
2921+
2922+#ifdef CheckTPktLost
2923+ if ( Dat_ULONG & 0x00000080 ) {
2924+ fprintf(fp_log, "[%sIntStatus] Packets transmitted to Ethernet lost : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
2925+ FindErr( Err_TPKT_LOST );
2926+ }
2927+#endif
2928+#endif
2929+ if (Err_Flag)
2930+ return(1);
2931+ else
2932+ return(0);
2933+} // End int check_int (char *type)
2934+
2935+
2936+//------------------------------------------------------------
2937+// Buffer
2938+//------------------------------------------------------------
2939+void setup_framesize (void) {
2940+ int i;
2941+
2942+ #ifdef DbgPrn_FuncHeader
2943+ printf ("setup_framesize\n");
2944+ Debug_delay();
2945+ #endif
2946+
2947+ //------------------------------------------------------------
2948+ // Fill Frame Size out descriptor area
2949+ //------------------------------------------------------------
2950+ #ifdef SLT_UBOOT
2951+ if (0)
2952+ #else
2953+ if ( ENABLE_RAND_SIZE )
2954+ #endif
2955+ {
2956+ for (i = 0; i < DES_NUMBER; i++) {
2957+ if ( FRAME_Rand_Simple ) {
2958+ switch(rand() % 5) {
2959+ case 0 : FRAME_LEN[i] = 0x4e ; break;
2960+ case 1 : FRAME_LEN[i] = 0x4ba; break;
2961+ default: FRAME_LEN[i] = 0x5ea; break;
2962+ }
2963+ }
2964+ else {
2965+ FRAME_LEN_Cur = rand() % (MAX_FRAME_RAND_SIZE + 1);
2966+
2967+ if (FRAME_LEN_Cur < MIN_FRAME_RAND_SIZE)
2968+ FRAME_LEN_Cur = MIN_FRAME_RAND_SIZE;
2969+
2970+ FRAME_LEN[i] = FRAME_LEN_Cur;
2971+ }
2972+#ifdef SLT_DOS
2973+ if (DbgPrn_FRAME_LEN)
2974+ fprintf(fp_log, "[setup_framesize] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN[i], i, Loop);
2975+#endif
2976+ }
2977+ }
2978+ else {
2979+ for (i = 0; i < DES_NUMBER; i++) {
2980+ #ifdef SelectSimpleLength
2981+ if (i % FRAME_SELH_PERD)
2982+ FRAME_LEN[i] = FRAME_LENH;
2983+ else
2984+ FRAME_LEN[i] = FRAME_LENL;
2985+ #else
2986+ if ( BurstEnable ) {
2987+ if (IEEETesting) {
2988+ FRAME_LEN[i] = 1514;
2989+ }
2990+ else {
2991+ #ifdef ENABLE_ARP_2_WOL
2992+ FRAME_LEN[i] = 164;
2993+ #else
2994+ FRAME_LEN[i] = 60;
2995+ #endif
2996+ }
2997+ }
2998+ else {
2999+ #ifdef SelectLengthInc
3000+// FRAME_LEN[i] = (i%1455)+60;
3001+ FRAME_LEN[i] = 1514-( i % 1455 );
3002+ #else
3003+ if (i % FRAME_SELH_PERD)
3004+ FRAME_LEN[i] = FRAME_LENH;
3005+ else
3006+ FRAME_LEN[i] = FRAME_LENL;
3007+ #endif
3008+ } // End if (BurstEnable)
3009+ #endif
3010+/*
3011+ switch(i % 20) {
3012+ case 0 : FRAME_LEN[i] = FRAME_LENH; break;
3013+ case 1 : FRAME_LEN[i] = FRAME_LENH; break;
3014+ case 2 : FRAME_LEN[i] = FRAME_LENH; break;
3015+ default: FRAME_LEN[i] = FRAME_LENL; break;
3016+ }
3017+*/
3018+#ifdef SLT_DOS
3019+ if (DbgPrn_FRAME_LEN)
3020+ fprintf(fp_log, "[setup_framesize] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN[i], i, Loop);
3021+#endif
3022+ } // End for (i = 0; i < DES_NUMBER; i++)
3023+ } // End if ( ENABLE_RAND_SIZE )
3024+
3025+ // Calculate average of frame size
3026+ Avg_frame_len = 0;
3027+
3028+ for ( i = 0; i < DES_NUMBER; i++ ) {
3029+ Avg_frame_len += FRAME_LEN[i];
3030+ }
3031+
3032+ Avg_frame_len = Avg_frame_len / (double)DES_NUMBER;
3033+
3034+ //------------------------------------------------------------
3035+ // Write Plane
3036+ //------------------------------------------------------------
3037+ switch( ZeroCopy_OFFSET & 0x3 ) {
3038+ case 0: wp_fir = 0xffffffff; break;
3039+ case 1: wp_fir = 0xffffff00; break;
3040+ case 2: wp_fir = 0xffff0000; break;
3041+ case 3: wp_fir = 0xff000000; break;
3042+ }
3043+
3044+ for ( i = 0; i < DES_NUMBER; i++ ) {
3045+ switch( ( ZeroCopy_OFFSET + FRAME_LEN[i] - 1 ) & 0x3 ) {
3046+ case 0: wp_lst[i] = 0x000000ff; break;
3047+ case 1: wp_lst[i] = 0x0000ffff; break;
3048+ case 2: wp_lst[i] = 0x00ffffff; break;
3049+ case 3: wp_lst[i] = 0xffffffff; break;
3050+ }
3051+ } // End for ( i = 0; i < DES_NUMBER; i++ )
3052+} // End void setup_framesize (void)
3053+
3054+//------------------------------------------------------------
3055+void setup_arp (void) {
3056+ int i;
3057+ for (i = 0; i < 16; i++ )
3058+ ARP_data[i] = ARP_org_data[i];
3059+
3060+ ARP_data[1] = 0x0000ffff | ( SA[0] << 16 )
3061+ | ( SA[1] << 24 );
3062+
3063+ ARP_data[2] = ( SA[2] )
3064+ | ( SA[3] << 8 )
3065+ | ( SA[4] << 16 )
3066+ | ( SA[5] << 24 );
3067+
3068+ ARP_data[5] = 0x00000100 | ( SA[0] << 16 )
3069+ | ( SA[1] << 24 );
3070+
3071+ ARP_data[6] = ( SA[2] )
3072+ | ( SA[3] << 8 )
3073+ | ( SA[4] << 16 )
3074+ | ( SA[5] << 24 );
3075+} // End void setup_arp (void)
3076+
3077+//------------------------------------------------------------
3078+void setup_buf (void) {
3079+ int i;
3080+ int j;
3081+ ULONG adr;
3082+ ULONG adr_srt;
3083+ ULONG adr_end;
3084+ ULONG len;
3085+ #ifdef SelectSimpleDA
3086+ int cnt;
3087+ ULONG Current_framelen;
3088+ #endif
3089+
3090+ #ifdef ENABLE_ARP_2_WOL
3091+ int DA[3];
3092+
3093+ DA[0] = ( ( SelectWOLDA_DatH >> 8 ) & 0x00ff ) |
3094+ ( ( SelectWOLDA_DatH << 8 ) & 0xff00 );
3095+
3096+ DA[1] = ( ( SelectWOLDA_DatL >> 24 ) & 0x00ff ) |
3097+ ( ( SelectWOLDA_DatL >> 8 ) & 0xff00 );
3098+
3099+ DA[2] = ( ( SelectWOLDA_DatL >> 8 ) & 0x00ff ) |
3100+ ( ( SelectWOLDA_DatL << 8 ) & 0xff00 );
3101+ #endif
3102+
3103+ #ifdef DbgPrn_FuncHeader
3104+ printf ("setup_buf : %d\n", Loop);
3105+ Debug_delay();
3106+ #endif
3107+
3108+ // It need be multiple of 4
3109+ adr_srt = GET_DMA_BASE_SETUP & 0xfffffffc;
3110+
3111+ for (j = 0; j < DES_NUMBER; j++) {
3112+ if ( DbgPrn_BufAdr )
3113+ printf("[loop:%4d][des:%4d][setup_buf ] %08lx\n", Loop, j, adr_srt);
3114+
3115+ if ( BurstEnable ) {
3116+ if ( IEEETesting ) {
3117+ #ifdef ENABLE_DASA
3118+ WriteSOC_DD( adr_srt , 0xffffffff );
3119+ WriteSOC_DD( adr_srt + 4, ARP_data[1] );
3120+ WriteSOC_DD( adr_srt + 8, ARP_data[2] );
3121+
3122+ for (adr = (adr_srt + 12); adr < (adr_srt + DMA_PakSize); adr += 4 )
3123+ #else
3124+ for (adr = adr_srt; adr < (adr_srt + DMA_PakSize); adr += 4 )
3125+ #endif
3126+ {
3127+ switch( TestMode ) {
3128+ case 1: gdata = 0xffffffff; break;
3129+ case 2: gdata = 0x55555555; break;
3130+ case 3: gdata = rand() | (rand() << 16); break;
3131+ case 5: gdata = UserDVal; break;
3132+ }
3133+ WriteSOC_DD(adr, gdata);
3134+ } // End for()
3135+ }
3136+ else {
3137+ for (i = 0; i < 16; i++) {
3138+ WriteSOC_DD( adr_srt + ( i << 2 ), ARP_data[i] );
3139+ }
3140+
3141+ #ifdef ENABLE_ARP_2_WOL
3142+ for (i = 16; i < 40; i += 3) {
3143+ WriteSOC_DD( adr_srt + ( i << 2 ), ( DA[1] << 16 ) | DA[0] );
3144+ WriteSOC_DD( adr_srt + ( i << 2 ) + 4, ( DA[0] << 16 ) | DA[2] );
3145+ WriteSOC_DD( adr_srt + ( i << 2 ) + 8, ( DA[2] << 16 ) | DA[1] );
3146+ }
3147+ #endif
3148+ } // End if ( IEEETesting )
3149+ }
3150+ else {
3151+ // --------------------------------------------
3152+ #ifdef SelectSimpleData
3153+ #ifdef SimpleData_Fix
3154+ switch( j % SimpleData_FixNum ) {
3155+ case 0 : gdata = SimpleData_FixVal00; break;
3156+ case 1 : gdata = SimpleData_FixVal01; break;
3157+ case 2 : gdata = SimpleData_FixVal02; break;
3158+ case 3 : gdata = SimpleData_FixVal03; break;
3159+ case 4 : gdata = SimpleData_FixVal04; break;
3160+ case 5 : gdata = SimpleData_FixVal05; break;
3161+ case 6 : gdata = SimpleData_FixVal06; break;
3162+ case 7 : gdata = SimpleData_FixVal07; break;
3163+ case 8 : gdata = SimpleData_FixVal08; break;
3164+ case 9 : gdata = SimpleData_FixVal09; break;
3165+ case 10 : gdata = SimpleData_FixVal10; break;
3166+ default : gdata = SimpleData_FixVal11; break;
3167+ }
3168+ #else
3169+ gdata = 0x11111111 * ((j + SEED_START) % 256);
3170+ #endif
3171+
3172+ adr_end = adr_srt + DMA_PakSize;
3173+ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
3174+ WriteSOC_DD( adr, gdata );
3175+ }
3176+ // --------------------------------------------
3177+ #elif SelectSimpleDA
3178+
3179+ gdata = DATA_SEED(j + SEED_START);
3180+ Current_framelen = FRAME_LEN[j];
3181+
3182+ if ( DbgPrn_FRAME_LEN )
3183+ fprintf(fp_log, "[setup_buf ] Current_framelen:%08lx[Des:%d][loop:%d]\n", Current_framelen, j, Loop);
3184+
3185+ cnt = 0;
3186+ len = ( ( ( Current_framelen - 14 ) & 0xff ) << 8) |
3187+ ( ( Current_framelen - 14 ) >> 8 );
3188+
3189+ adr_end = adr_srt + DMA_PakSize;
3190+ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
3191+ cnt++;
3192+ if (cnt == 1 ) WriteSOC_DD( adr, SelectSimpleDA_Dat0 );
3193+ else if (cnt == 2 ) WriteSOC_DD( adr, SelectSimpleDA_Dat1 );
3194+ else if (cnt == 3 ) WriteSOC_DD( adr, SelectSimpleDA_Dat2 );
3195+ else if (cnt == 4 ) WriteSOC_DD( adr, len | (len << 16) );
3196+ else
3197+ WriteSOC_DD( adr, gdata );
3198+
3199+ gdata += DATA_IncVal;
3200+ }
3201+ // --------------------------------------------
3202+ #else
3203+
3204+ gdata = DATA_SEED(j + SEED_START);
3205+ adr_end = adr_srt + DMA_PakSize;
3206+ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
3207+ WriteSOC_DD( adr, gdata );
3208+
3209+ gdata += DATA_IncVal;
3210+ }
3211+
3212+ #endif
3213+
3214+ } // End if ( BurstEnable )
3215+
3216+ adr_srt += DMA_PakSize;
3217+ } // End for (j = 0; j < DES_NUMBER; j++)
3218+} // End void setup_buf (void)
3219+
3220+//------------------------------------------------------------
3221+// Check data of one packet
3222+//------------------------------------------------------------
3223+char check_Data (ULONG desadr, LONG number) {
3224+ int index;
3225+ int cnt;
3226+ ULONG rdata;
3227+ ULONG wp_lst_cur;
3228+ ULONG adr_las;
3229+ ULONG adr;
3230+ ULONG adr_srt;
3231+ ULONG adr_end;
3232+ ULONG len;
3233+ #ifdef SelectSimpleDA
3234+ ULONG gdata_bak;
3235+ #endif
3236+
3237+ #ifdef DbgPrn_FuncHeader
3238+ printf ("check_Data : %d\n", Loop);
3239+ Debug_delay();
3240+ #endif
3241+ //printf("[Des:%d][loop:%d]Desadr:%08x\n", number, Loop, desadr);
3242+
3243+ wp_lst_cur = wp_lst[number];
3244+ FRAME_LEN_Cur = FRAME_LEN[number];
3245+#ifdef SLT_DOS
3246+ if ( DbgPrn_FRAME_LEN )
3247+ fprintf(fp_log, "[check_Data ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN_Cur, number, Loop);
3248+#endif
3249+ adr_srt = ReadSOC_DD(desadr) & 0xfffffffc;
3250+ adr_end = adr_srt + PktByteSize;
3251+
3252+ #ifdef SelectSimpleData
3253+ #ifdef SimpleData_Fix
3254+ switch( number % SimpleData_FixNum ) {
3255+ case 0 : gdata = SimpleData_FixVal00; break;
3256+ case 1 : gdata = SimpleData_FixVal01; break;
3257+ case 2 : gdata = SimpleData_FixVal02; break;
3258+ case 3 : gdata = SimpleData_FixVal03; break;
3259+ case 4 : gdata = SimpleData_FixVal04; break;
3260+ case 5 : gdata = SimpleData_FixVal05; break;
3261+ case 6 : gdata = SimpleData_FixVal06; break;
3262+ case 7 : gdata = SimpleData_FixVal07; break;
3263+ case 8 : gdata = SimpleData_FixVal08; break;
3264+ case 9 : gdata = SimpleData_FixVal09; break;
3265+ case 10 : gdata = SimpleData_FixVal10; break;
3266+ default : gdata = SimpleData_FixVal11; break;
3267+ }
3268+ #else
3269+ gdata = 0x11111111 * ((number + SEED_START) % 256);
3270+ #endif
3271+ #else
3272+ gdata = DATA_SEED(number + SEED_START);
3273+ #endif
3274+
3275+ wp = wp_fir;
3276+ adr_las = adr_end - 4;
3277+
3278+ cnt = 0;
3279+ len = (((FRAME_LEN_Cur-14) & 0xff) << 8) | ((FRAME_LEN_Cur-14) >> 8);
3280+#ifdef SLT_DOS
3281+ if (DbgPrn_Bufdat)
3282+ fprintf(fp_log, " Inf:%08lx ~ %08lx(%08lx) %08lx [Des:%d][loop:%d]\n", adr_srt, adr_end, adr_las, gdata, number, Loop);
3283+#endif
3284+ for (adr = adr_srt; adr < adr_end; adr+=4) {
3285+
3286+ #ifdef SelectSimpleDA
3287+ cnt++;
3288+ if ( cnt == 1 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat0; }
3289+ else if ( cnt == 2 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat1; }
3290+ else if ( cnt == 3 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat2; }
3291+ else if ( cnt == 4 ) { gdata_bak = gdata; gdata = len | (len << 16); }
3292+ #endif
3293+ rdata = ReadSOC_DD(adr);
3294+ if (adr == adr_las)
3295+ wp = wp & wp_lst_cur;
3296+
3297+ if ( (rdata & wp) != (gdata & wp) ) {
3298+#ifdef SLT_DOS
3299+ fprintf(fp_log, "\nError: Adr:%08lx[%3d] (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, (adr - adr_srt) / 4, rdata, gdata, wp, number, Loop);
3300+#endif
3301+ for (index = 0; index < 6; index++) {
3302+ rdata = ReadSOC_DD(adr);
3303+#ifdef SLT_DOS
3304+ fprintf(fp_log, "Rep : Adr:%08lx (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, rdata, gdata, wp, number, Loop);
3305+#endif
3306+ }
3307+
3308+ if ( DbgPrn_DumpMACCnt )
3309+ dump_mac_ROreg();
3310+
3311+ return( FindErr( Err_Check_Buf_Data ) );
3312+ } // End if ( (rdata & wp) != (gdata & wp) )
3313+#ifdef SLT_DOS
3314+ if ( DbgPrn_BufdatDetail )
3315+ fprintf(fp_log, " Adr:%08lx[%3d] (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, (adr - adr_srt) / 4, rdata, gdata, wp, number, Loop);
3316+#endif
3317+ #ifdef SelectSimpleDA
3318+ if ( cnt <= 4 )
3319+ gdata = gdata_bak;
3320+ #endif
3321+
3322+ #ifdef SelectSimpleData
3323+ #else
3324+ gdata += DATA_IncVal;
3325+ #endif
3326+
3327+ wp = 0xffffffff;
3328+ }
3329+ return(0);
3330+} // End char check_Data (ULONG desadr, LONG number)
3331+
3332+//------------------------------------------------------------
3333+char check_buf (int loopcnt) {
3334+ int count;
3335+ ULONG desadr;
3336+
3337+ #ifdef DbgPrn_FuncHeader
3338+ printf ("check_buf : %d\n", Loop);
3339+ Debug_delay();
3340+ #endif
3341+
3342+ for ( count = DES_NUMBER - 1; count >= 0; count-- ) {
3343+ desadr = H_RDES_BASE + ( 16 * count ) + 12;
3344+ //printf("%d:%08x\n", count, desadr);
3345+ if (check_Data(desadr, count)) {
3346+ check_int ("");
3347+
3348+ return(1);
3349+ }
3350+ }
3351+ if ( check_int ("") )
3352+ return(1);
3353+
3354+ return(0);
3355+} // End char check_buf (int loopcnt)
3356+
3357+//------------------------------------------------------------
3358+// Descriptor
3359+//------------------------------------------------------------
3360+void setup_txdes (ULONG desadr, ULONG bufbase) {
3361+ ULONG bufadr;
3362+ ULONG desval;
3363+ int count;
3364+
3365+ #ifdef DbgPrn_FuncHeader
3366+ printf ("setup_txdes: %d\n", Loop);
3367+ Debug_delay();
3368+ #endif
3369+
3370+ bufadr = bufbase + ZeroCopy_OFFSET;
3371+
3372+ if (TxDataEnable) {
3373+ for (count = 0; count < DES_NUMBER; count++) {
3374+ FRAME_LEN_Cur = FRAME_LEN[count];
3375+ desval = TDES_IniVal;
3376+ #ifdef SLT_DOS
3377+ if (DbgPrn_FRAME_LEN)
3378+ fprintf(fp_log, "[setup_txdes ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN_Cur, count, Loop);
3379+ #endif
3380+ if (DbgPrn_BufAdr)
3381+ printf("[loop:%4d][des:%4d][setup_txdes] %08lx\n", Loop, count, bufadr);
3382+
3383+ WriteSOC_DD( desadr + 0x04, 0 );
3384+ WriteSOC_DD( desadr + 0x08, 0 );
3385+ WriteSOC_DD( desadr + 0x0C, (bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
3386+ if ( count == ( DES_NUMBER - 1 ) )
3387+ WriteSOC_DD( desadr , desval | EOR_IniVal);
3388+ else
3389+ WriteSOC_DD( desadr , desval );
3390+
3391+ bufadr += DMA_PakSize;
3392+ desadr += 16;
3393+ }
3394+ }
3395+ else {
3396+ WriteSOC_DD( desadr , 0);
3397+ }
3398+} // End void setup_txdes (ULONG desadr, ULONG bufbase)
3399+
3400+//------------------------------------------------------------
3401+void setup_rxdes (ULONG desadr, ULONG bufbase) {
3402+ ULONG bufadr;
3403+ ULONG desval;
3404+ int count;
3405+
3406+ #ifdef DbgPrn_FuncHeader
3407+ printf ("setup_rxdes: %d\n", Loop);
3408+ Debug_delay();
3409+ #endif
3410+
3411+ bufadr = bufbase+ZeroCopy_OFFSET;
3412+ desval = RDES_IniVal;
3413+
3414+ if ( RxDataEnable ) {
3415+ for (count = 0; count < DES_NUMBER; count++) {
3416+ if (DbgPrn_BufAdr)
3417+ printf("[loop:%4d][des:%4d][setup_rxdes] %08lx\n", Loop, count, bufadr);
3418+ WriteSOC_DD( desadr + 0x04, 0 );
3419+ WriteSOC_DD( desadr + 0x08, 0 );
3420+ WriteSOC_DD( desadr + 0x0C, ( bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
3421+ if ( count == ( DES_NUMBER - 1 ) )
3422+ WriteSOC_DD( desadr , desval | EOR_IniVal );
3423+ else
3424+ WriteSOC_DD( desadr , desval );
3425+
3426+ desadr += 16;
3427+ bufadr += DMA_PakSize;
3428+ }
3429+ }
3430+ else {
3431+ WriteSOC_DD( desadr , 0x80000000 );
3432+ } // End if ( RxDataEnable )
3433+} // End void setup_rxdes (ULONG desadr, ULONG bufbase)
3434+
3435+//------------------------------------------------------------
3436+// First setting TX and RX information
3437+//------------------------------------------------------------
3438+void setup_des (ULONG bufnum) {
3439+
3440+ if ( DbgPrn_BufAdr ) {
3441+ printf ("setup_rxdes: %ld\n", bufnum);
3442+ Debug_delay();
3443+ }
3444+
3445+ setup_txdes( H_TDES_BASE, GET_DMA_BASE_SETUP );
3446+ setup_rxdes( H_RDES_BASE, GET_DMA_BASE(0) );
3447+
3448+} // End void setup_des (ULONG bufnum)
3449+
3450+//------------------------------------------------------------
3451+// Move buffer point of TX and RX descriptor to next DMA buffer
3452+//------------------------------------------------------------
3453+void setup_des_loop (ULONG bufnum) {
3454+ int count;
3455+ ULONG H_rx_desadr;
3456+ ULONG H_tx_desadr;
3457+ ULONG H_tx_bufadr;
3458+ ULONG H_rx_bufadr;
3459+
3460+ if ( DbgPrn_BufAdr ) {
3461+ printf ("setup_rxdes_loop: %ld\n", bufnum);
3462+ Debug_delay();
3463+ }
3464+
3465+ if (RxDataEnable) {
3466+ H_rx_bufadr = GET_DMA_BASE( bufnum + 1 ) + ZeroCopy_OFFSET;
3467+ H_rx_desadr = H_RDES_BASE;
3468+//printf (" =====>setup_rxdes_loop: %ld [%lX]\n", bufnum, H_rx_bufadr);
3469+ for (count = 0; count < DES_NUMBER; count++) {
3470+ WriteSOC_DD(H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
3471+
3472+ if (count == (DES_NUMBER - 1)) {
3473+ WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
3474+ }
3475+ else {
3476+ WriteSOC_DD( H_rx_desadr, RDES_IniVal );
3477+ }
3478+ H_rx_bufadr += DMA_PakSize;
3479+ H_rx_desadr += 16;
3480+ }
3481+ }
3482+
3483+ if (TxDataEnable) {
3484+ if (RxDataEnable) {
3485+ H_tx_bufadr = GET_DMA_BASE( bufnum ) + ZeroCopy_OFFSET;
3486+ }
3487+ else {
3488+ H_tx_bufadr = GET_DMA_BASE( 0 ) + ZeroCopy_OFFSET;
3489+ }
3490+ H_tx_desadr = H_TDES_BASE;
3491+//printf (" =====>setup_Txdes_loop: %ld [%lX]\n", bufnum, H_tx_bufadr);
3492+ for (count = 0; count < DES_NUMBER; count++) {
3493+ FRAME_LEN_Cur = FRAME_LEN[count];
3494+ WriteSOC_DD( H_tx_desadr + 0x0C, ( H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
3495+ if (count == (DES_NUMBER - 1)) {
3496+ WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
3497+ }
3498+ else {
3499+ WriteSOC_DD( H_tx_desadr, TDES_IniVal );
3500+ }
3501+ H_tx_bufadr += DMA_PakSize;
3502+ H_tx_desadr += 16;
3503+ }
3504+ }
3505+
3506+ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 ); // Tx Poll
3507+ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 ); // Rx Poll
3508+} // End void setup_des_loop (ULONG bufnum)
3509+
3510+//------------------------------------------------------------
3511+char check_des_header_Tx (char *type, ULONG adr, LONG desnum) {
3512+ int timeout = 0;
3513+ ULONG dat;
3514+
3515+ dat = ReadSOC_DD(adr);
3516+
3517+ while ( HWOwnTx(dat) ) {
3518+ // we will run again, if transfer has not been completed.
3519+ if ( RxDataEnable && (++timeout > TIME_OUT_Des) ) {
3520+ #ifdef SLT_DOS
3521+ fprintf(fp_log, "[%sTxDesOwn] Address %08lx = %08lx [Des:%d][loop:%d]\n", type, adr, dat, desnum, Loop);
3522+ #endif
3523+ return(FindErr_Des(Check_Des_TxOwnTimeOut));
3524+ }
3525+ WriteSOC_DD(H_MAC_BASE + 0x18, 0x00000000);//Tx Poll
3526+ WriteSOC_DD(H_MAC_BASE + 0x1c, 0x00000000);//Rx Poll
3527+
3528+ #ifdef Delay_ChkTxOwn
3529+ delay(Delay_ChkTxOwn);
3530+ #endif
3531+ dat = ReadSOC_DD(adr);
3532+ }
3533+
3534+ return(0);
3535+} // End char check_des_header_Tx (char *type, ULONG adr, LONG desnum)
3536+
3537+//------------------------------------------------------------
3538+char check_des_header_Rx (char *type, ULONG adr, LONG desnum) {
3539+ #ifdef CheckRxOwn
3540+ int timeout = 0;
3541+ ULONG dat;
3542+
3543+ dat = ReadSOC_DD(adr);
3544+
3545+ while ( HWOwnRx( dat ) ) {
3546+ // we will run again, if transfer has not been completed.
3547+ if (TxDataEnable && (++timeout > TIME_OUT_Des)) {
3548+ #ifdef SLT_DOS
3549+ fprintf(fp_log, "[%sRxDesOwn] Address %08lx = %08lx [Des:%d][loop:%d]\n", type, adr, dat, desnum, Loop);
3550+ #endif
3551+ return(FindErr_Des(Check_Des_RxOwnTimeOut));
3552+ }
3553+
3554+ WriteSOC_DD(H_MAC_BASE + 0x18, 0x00000000);//Tx Poll
3555+ WriteSOC_DD(H_MAC_BASE + 0x1c, 0x00000000);//Rx Poll
3556+
3557+ #ifdef Delay_ChkRxOwn
3558+ delay(Delay_ChkRxOwn);
3559+ #endif
3560+ dat = ReadSOC_DD(adr);
3561+ };
3562+
3563+ Dat_ULONG = ReadSOC_DD( adr + 12 );
3564+
3565+ #ifdef CheckRxLen
3566+ #ifdef SLT_DOS
3567+ if ( DbgPrn_FRAME_LEN )
3568+ fprintf(fp_log, "[%sRxDes ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", type, (FRAME_LEN_Cur + 4), desnum, Loop);
3569+ #endif
3570+
3571+ if ((dat & 0x3fff) != (FRAME_LEN_Cur + 4)) {
3572+ #ifdef SLT_DOS
3573+ fprintf(fp_log, "[%sRxDes] Error Frame Length %08lx:%08lx %08lx(%4d/%4d) [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, (dat & 0x3fff), (FRAME_LEN_Cur + 4), desnum, Loop);
3574+ #endif
3575+ FindErr_Des(Check_Des_FrameLen);
3576+ }
3577+ #endif // End CheckRxLen
3578+
3579+ #ifdef CheckRxErr
3580+ if (dat & 0x00040000) {
3581+ #ifdef SLT_DOS
3582+ fprintf(fp_log, "[%sRxDes] Error RxErr %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
3583+ #endif
3584+ FindErr_Des(Check_Des_RxErr);
3585+ }
3586+ #endif // End CheckRxErr
3587+
3588+ #ifdef CheckOddNibble
3589+ if (dat & 0x00400000) {
3590+ #ifdef SLT_DOS
3591+ fprintf(fp_log, "[%sRxDes] Odd Nibble %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
3592+ #endif
3593+ FindErr_Des(Check_Des_OddNibble);
3594+ }
3595+ #endif // End CheckOddNibble
3596+
3597+ #ifdef CheckCRC
3598+ if (dat & 0x00080000) {
3599+ #ifdef SLT_DOS
3600+ fprintf(fp_log, "[%sRxDes] Error CRC %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
3601+ #endif
3602+ FindErr_Des(Check_Des_CRC);
3603+ }
3604+ #endif // End CheckCRC
3605+
3606+ #ifdef CheckRxFIFOFull
3607+ if (dat & 0x00800000) {
3608+ #ifdef SLT_DOS
3609+ fprintf(fp_log, "[%sRxDes] Error Rx FIFO Full %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
3610+ #endif
3611+ FindErr_Des(Check_Des_RxFIFOFull);
3612+ }
3613+ #endif // End CheckRxFIFOFull
3614+
3615+ // if (check_int ("")) {return(1);}
3616+ #endif // End CheckRxOwn
3617+
3618+ if (Err_Flag)
3619+ return(1);
3620+ else
3621+ return(0);
3622+} // End char check_des_header_Rx (char *type, ULONG adr, LONG desnum)
3623+
3624+//------------------------------------------------------------
3625+char check_des (ULONG bufnum, int checkpoint) {
3626+ int desnum;
3627+ ULONG H_rx_desadr;
3628+ ULONG H_tx_desadr;
3629+ ULONG H_tx_bufadr;
3630+ ULONG H_rx_bufadr;
3631+
3632+ #ifdef Delay_DesGap
3633+ ULONG dly_cnt = 0;
3634+ ULONG dly_max = Delay_CntMaxIncVal;
3635+ #endif
3636+
3637+ #ifdef DbgPrn_FuncHeader
3638+ printf ("check_des : %d(%d)\n", Loop, checkpoint);
3639+ Debug_delay();
3640+ #endif
3641+
3642+ // Fire the engine to send and recvice
3643+ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll
3644+ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 );//Rx Poll
3645+
3646+ #ifdef SelectSimpleDes
3647+ #else
3648+ if ( IEEETesting == 1 ) {
3649+ // IEEE test mode, there is the same data in every lan packet
3650+ H_tx_bufadr = GET_DMA_BASE_SETUP;
3651+ H_rx_bufadr = GET_DMA_BASE(0);
3652+ }
3653+ else {
3654+ H_rx_bufadr = GET_DMA_BASE( bufnum + 1 ) + ZeroCopy_OFFSET;
3655+
3656+ if (RxDataEnable) {
3657+ H_tx_bufadr = GET_DMA_BASE(bufnum ) + ZeroCopy_OFFSET;
3658+ }
3659+ else {
3660+ H_tx_bufadr = GET_DMA_BASE( 0 ) + ZeroCopy_OFFSET;
3661+ }
3662+ }
3663+ #endif
3664+
3665+ H_rx_desadr = H_RDES_BASE;
3666+ H_tx_desadr = H_TDES_BASE;
3667+
3668+ #ifdef Delay_DES
3669+ delay(Delay_DES);
3670+ #endif
3671+
3672+ for (desnum = 0; desnum < DES_NUMBER; desnum++) {
3673+ if ( DbgPrn_BufAdr )
3674+ printf( "[loop:%4d][des:%4d][check_des ] %08lx %08lx [%08lx] [%08lx]\n", Loop, desnum, ( H_tx_desadr ), ( H_rx_desadr ), ReadSOC_DD( H_tx_desadr + 12 ), ReadSOC_DD( H_rx_desadr + 12 ) );
3675+
3676+ //[Delay]--------------------
3677+ #ifdef Delay_DesGap
3678+ if ( dly_cnt++ > 3 ) {
3679+ switch ( rand() % 12 ) {
3680+ case 1 : dly_max = 00000; break;
3681+ case 3 : dly_max = 20000; break;
3682+ case 5 : dly_max = 40000; break;
3683+ case 7 : dly_max = 60000; break;
3684+ defaule: dly_max = 70000; break;
3685+ }
3686+
3687+ dly_max += ( rand() % 4 ) * 14321;
3688+
3689+ while (dly_cnt < dly_max) {
3690+ dly_cnt++;
3691+ }
3692+
3693+ dly_cnt = 0;
3694+ }
3695+ else {
3696+// timeout = 0;
3697+// while (timeout < 50000) {timeout++;};
3698+ }
3699+ #endif // End Delay_DesGap
3700+
3701+ //[Check Owner Bit]--------------------
3702+ FRAME_LEN_Cur = FRAME_LEN[desnum];
3703+#ifdef SLT_DOS
3704+ if ( DbgPrn_FRAME_LEN )
3705+ fprintf(fp_log, "[check_des ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]%d\n", FRAME_LEN_Cur, desnum, Loop, checkpoint);
3706+#endif
3707+// if (BurstEnable) {
3708+// if (check_des_header_Tx("", H_tx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
3709+// } else {
3710+// if (check_des_header_Rx("", H_rx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
3711+// if (check_des_header_Tx("", H_tx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
3712+// }
3713+
3714+ // Check the description of Tx and Rx
3715+ if ( RxDataEnable && check_des_header_Rx("", H_rx_desadr, desnum) ) {
3716+ CheckDesFail_DesNum = desnum;
3717+
3718+ return(1);
3719+ }
3720+ if ( TxDataEnable && check_des_header_Tx("", H_tx_desadr, desnum) ) {
3721+ CheckDesFail_DesNum = desnum;
3722+
3723+ return(1);
3724+ }
3725+// else {
3726+// printf(" %d \r", desnum);
3727+// }
3728+
3729+ #ifdef SelectSimpleDes
3730+ #else
3731+ if ( !checkpoint ) {
3732+ // Setting buffer address to description of Tx and Rx on next stage
3733+
3734+// if (!BurstEnable) {
3735+// WriteSOC_DD( H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) );
3736+// WriteSOC_DD( H_tx_desadr + 0x0C, (H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) );
3737+// }
3738+//
3739+// if ( desnum == (DES_NUMBER - 1) ) {
3740+// WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
3741+// WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
3742+// }
3743+// else {
3744+// WriteSOC_DD( H_rx_desadr, RDES_IniVal );
3745+// WriteSOC_DD( H_tx_desadr, TDES_IniVal );
3746+// }
3747+// WriteSOC_DD( H_MAC_BASE+0x18, 0x00000000 ); //Tx Poll
3748+// WriteSOC_DD( H_MAC_BASE+0x1c, 0x00000000 ); //Rx Poll
3749+
3750+ if ( RxDataEnable ) {
3751+ WriteSOC_DD( H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
3752+
3753+ if ( desnum == (DES_NUMBER - 1) ) {
3754+ WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
3755+ } else {
3756+ WriteSOC_DD( H_rx_desadr, RDES_IniVal );
3757+ }
3758+ }
3759+ if ( TxDataEnable ) {
3760+ WriteSOC_DD( H_tx_desadr + 0x0C, (H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
3761+ if ( desnum == (DES_NUMBER - 1) ) {
3762+ WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
3763+ }
3764+ else {
3765+ WriteSOC_DD( H_tx_desadr, TDES_IniVal );
3766+ }
3767+ }
3768+ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 ); //Tx Poll
3769+ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 ); //Rx Poll
3770+ }
3771+ H_rx_bufadr += DMA_PakSize;
3772+ H_tx_bufadr += DMA_PakSize;
3773+ #endif // End SelectSimpleDes
3774+
3775+ H_rx_desadr += 16;
3776+ H_tx_desadr += 16;
3777+ } // End for (desnum = 0; desnum < DES_NUMBER; desnum++)
3778+
3779+ return(0);
3780+} // End char check_des (ULONG bufnum, int checkpoint)
3781+//#endif
3782+
3783+//------------------------------------------------------------
3784+// Print
3785+//------------------------------------------------------------
3786+void PrintMode (void) {
3787+ if (Enable_MAC34) printf ("run_mode[dec] | 0->MAC1 1->MAC2 2->MAC3 3->MAC4\n");
3788+ else printf ("run_mode[dec] | 0->MAC1 1->MAC2\n");
3789+}
3790+
3791+//------------------------------------------------------------
3792+void PrintSpeed (void) {
3793+ printf ("speed[dec] | 0->1G 1->100M 2->10M 3->all speed (default:%3d)\n", DEF_SPEED);
3794+}
3795+
3796+//------------------------------------------------------------
3797+void PrintCtrl (void) {
3798+ printf ("ctrl[dec] | bit0~2: Reserved\n");
3799+ printf ("(default:%3d) | bit3 : 1->Enable PHY init 0->Disable PHY init\n", GCtrl);
3800+ printf (" | bit4 : 1->Enable PHY int-loop 0->Disable PHY int-loop\n");
3801+ printf (" | bit5 : 1->Ignore PHY ID 0->Check PHY ID\n");
3802+ if (AST2400) {
3803+ printf (" | bit6 : 1->Enable MAC int-loop 0->Disable MAC int-loop\n");
3804+ }
3805+}
3806+
3807+//------------------------------------------------------------
3808+void PrintLoop (void) {
3809+ printf ("loop_max[dec] | 1G : 20 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX * 20);
3810+ printf (" | 100M: 2 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX * 2);
3811+ printf (" | 10M : 1 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX);
3812+}
3813+
3814+//------------------------------------------------------------
3815+void PrintTest (void) {
3816+ if ( ModeSwitch == MODE_NSCI ) {
3817+ printf ("test_mode[dec] | 0: NCSI configuration with Disable_Channel request\n");
3818+ printf ("(default:%3d) | 1: NCSI configuration without Disable_Channel request\n", DEF_TESTMODE);
3819+ }
3820+ else {
3821+ printf ("test_mode[dec] | 0: Tx/Rx frame checking\n");
3822+ printf ("(default:%3d) | 1: Tx output 0xff frame\n", DEF_TESTMODE);
3823+ printf (" | 2: Tx output 0x55 frame\n");
3824+ printf (" | 3: Tx output random frame\n");
3825+ printf (" | 4: Tx output ARP frame\n");
3826+ printf (" | 5: Tx output user defined value frame (default:0x%8x)\n", DEF_USER_DEF_PACKET_VAL);
3827+ } // End if ( ModeSwitch == MODE_NSCI )
3828+
3829+ if (AST2300) {
3830+ printf (" | 6: IO timing testing\n");
3831+ printf (" | 7: IO timing/strength testing\n");
3832+ }
3833+}
3834+
3835+//------------------------------------------------------------
3836+void PrintPHYAdr (void) {
3837+ printf ("phy_adr[dec] | 0~31: PHY Address (default:%d)\n", DEF_PHY_ADR);
3838+}
3839+
3840+//------------------------------------------------------------
3841+void PrintIOTimingBund (void) {
3842+ printf ("IO margin[dec] | 0/1/3/5 (default:%d)\n", DEF_IOTIMINGBUND);
3843+}
3844+
3845+//------------------------------------------------------------
3846+void PrintPakNUm (void) {
3847+ printf ("package_num[dec] | 1~ 8: Total Number of NCSI Package (default:%d)\n", DEF_PACKAGE2NUM);
3848+}
3849+
3850+//------------------------------------------------------------
3851+void PrintChlNUm (void) {
3852+ printf ("channel_num[dec] | 1~32: Total Number of NCSI Channel (default:%d)\n", DEF_CHANNEL2NUM);
3853+}
3854+
3855+//------------------------------------------------------------
3856+
3857+void Print_Header (BYTE option) {
3858+
3859+ FILE_VAR
3860+
3861+ GET_OBJ( option )
3862+
3863+ if (GSpeed_sel[0]) PRINT(OUT_OBJ " 1G ");
3864+ else if (GSpeed_sel[1]) PRINT(OUT_OBJ " 100M ");
3865+ else PRINT(OUT_OBJ " 10M ");
3866+
3867+ switch (TestMode) {
3868+ case 0 : PRINT(OUT_OBJ "Tx/Rx frame checking \n" ); break;
3869+ case 1 : PRINT(OUT_OBJ "Tx output 0xff frame \n" ); break;
3870+ case 2 : PRINT(OUT_OBJ "Tx output 0x55 frame \n" ); break;
3871+ case 3 : PRINT(OUT_OBJ "Tx output random frame \n" ); break;
3872+ case 4 : PRINT(OUT_OBJ "Tx output ARP frame \n" ); break;
3873+ case 5 : PRINT(OUT_OBJ "Tx output 0x%08lx frame \n", UserDVal); break;
3874+ case 6 : PRINT(OUT_OBJ "IO delay testing \n" ); break;
3875+ case 7 : PRINT(OUT_OBJ "IO delay testing(Strength) \n" ); break;
3876+ case 8 : PRINT(OUT_OBJ "Tx frame \n" ); break;
3877+ case 9 : PRINT(OUT_OBJ "Rx frame checking \n" ); break;
3878+ }
3879+}
3880+
3881+//------------------------------------------------------------
3882+void PrintIO_Header (BYTE option) {
3883+
3884+ FILE_VAR
3885+
3886+ GET_OBJ( option )
3887+
3888+ if ( IOStrength ) {
3889+ if (GSpeed_sel[0]) PRINT(OUT_OBJ "[Strength %ld][1G ]========================================\n", IOStr_i);
3890+ else if (GSpeed_sel[1]) PRINT(OUT_OBJ "[Strength %ld][100M]========================================\n", IOStr_i);
3891+ else PRINT(OUT_OBJ "[Strength %ld][10M ]========================================\n", IOStr_i);
3892+ } else {
3893+ if (GSpeed_sel[0]) PRINT(OUT_OBJ "[1G ]========================================\n");
3894+ else if (GSpeed_sel[1]) PRINT(OUT_OBJ "[100M]========================================\n");
3895+ else PRINT(OUT_OBJ "[10M ]========================================\n");
3896+ }
3897+
3898+#ifdef Enable_Old_Style
3899+ if (Enable_RMII) PRINT(OUT_OBJ "Tx:SCU48[ %2d]= ", IOdly_out_shf);
3900+ else PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]= ", IOdly_out_shf+3, IOdly_out_shf);
3901+
3902+ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
3903+ IOdly_out = valary[IOdly_j];
3904+ PRINT(OUT_OBJ "%2x", IOdly_out);
3905+ }
3906+
3907+ PRINT(OUT_OBJ "\n ");
3908+ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
3909+ if (IOdly_out_reg_idx == IOdly_j) PRINT(OUT_OBJ " |");
3910+ else PRINT(OUT_OBJ " ");
3911+ }
3912+#else
3913+ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]= ", IOdly_in_shf+3, IOdly_in_shf);
3914+
3915+ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
3916+ IOdly_in = valary[IOdly_i];
3917+ PRINT(OUT_OBJ "%2x", IOdly_in);
3918+ }
3919+
3920+ PRINT(OUT_OBJ "\n ");
3921+ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
3922+ if (IOdly_in_reg_idx == IOdly_i) PRINT(OUT_OBJ " |");
3923+ else PRINT(OUT_OBJ " ");
3924+ }
3925+#endif
3926+
3927+ PRINT(OUT_OBJ "\n");
3928+} // End void PrintIO_Header (BYTE option)
3929+
3930+//------------------------------------------------------------
3931+void PrintIO_LineS (BYTE option) {
3932+
3933+ FILE_VAR
3934+
3935+ GET_OBJ( option )
3936+
3937+
3938+#ifdef Enable_Old_Style
3939+ if (IOdly_in_reg == IOdly_in) {
3940+ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]=%01x:-", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
3941+ }
3942+ else {
3943+ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]=%01x: ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
3944+ }
3945+#else
3946+ if (Enable_RMII) {
3947+ if (IOdly_out_reg == IOdly_out) {
3948+ PRINT(OUT_OBJ "Tx:SCU48[ %2d]=%01x:-", IOdly_out_shf, IOdly_out);
3949+ }
3950+ else {
3951+ PRINT(OUT_OBJ "Tx:SCU48[ %2d]=%01x: ", IOdly_out_shf, IOdly_out);
3952+ }
3953+ } else {
3954+ if (IOdly_out_reg == IOdly_out) {
3955+ PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]=%01x:-", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
3956+ }
3957+ else {
3958+ PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]=%01x: ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
3959+ }
3960+ }
3961+#endif
3962+} // void PrintIO_LineS (BYTE option)
3963+
3964+//------------------------------------------------------------
3965+void PrintIO_Line (BYTE option) {
3966+
3967+ FILE_VAR
3968+
3969+ GET_OBJ( option )
3970+
3971+ if ( ( IOdly_in_reg == IOdly_in ) && ( IOdly_out_reg == IOdly_out ) ) {
3972+ if (dlymap[IOdly_i][IOdly_j]) PRINT(OUT_OBJ " X");
3973+ else PRINT(OUT_OBJ " O");
3974+ }
3975+ else {
3976+ if (dlymap[IOdly_i][IOdly_j]) PRINT(OUT_OBJ " x");
3977+ else PRINT(OUT_OBJ " o");
3978+ }
3979+} // End void PrintIO_Line (BYTE option)
3980+
3981+//------------------------------------------------------------
3982+void PrintIO_Line_LOG (void) {
3983+#ifndef SLT_UBOOT
3984+#ifdef Enable_Old_Style
3985+ if (Enable_RMII) fprintf(fp_log, "\nTx:SCU48[ %2d]=%2x, ", IOdly_out_shf, IOdly_out);
3986+ else fprintf(fp_log, "\nTx:SCU48[%2d:%2d]=%2x, ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
3987+
3988+ fprintf(fp_log, "Rx:SCU48[%2d:%2d]=%01x: ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
3989+
3990+ if (dlymap[IOdly_i][IOdly_j]) fprintf(fp_log, " X\n");
3991+ else fprintf(fp_log, " O\n");
3992+#else
3993+ fprintf(fp_log, "\nRx:SCU48[%2d:%2d]=%2x, ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
3994+
3995+ if (Enable_RMII) fprintf(fp_log, "Tx:SCU48[ %2d]=%01x: ", IOdly_out_shf, IOdly_out);
3996+ else fprintf(fp_log, "Tx:SCU48[%2d:%2d]=%01x: ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
3997+
3998+ if (dlymap[IOdly_i][IOdly_j]) fprintf(fp_log, " X\n");
3999+ else fprintf(fp_log, " O\n");
4000+#endif
4001+#endif
4002+}
4003+
4004+//------------------------------------------------------------
4005+// main
4006+//------------------------------------------------------------
4007+void Calculate_LOOP_CheckNum (void) {
4008+
4009+#define ONE_MBYTE 1048576
4010+
4011+ #ifdef CheckDataEveryTime
4012+ LOOP_CheckNum = 1;
4013+ #else
4014+ if (IOTiming || IOTimingBund || (GSpeed == SET_1G_100M_10MBPS)) {
4015+ LOOP_CheckNum = LOOP_MAX;
4016+ }
4017+ else {
4018+ switch ( GSpeed ) {
4019+ case SET_1GBPS : CheckBuf_MBSize = MOVE_DATA_MB_SEC ; break; // 1G
4020+ case SET_100MBPS : CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 3); break; // 100M ~ 1G / 8
4021+ case SET_10MBPS : CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 6); break; // 10M ~ 1G / 64
4022+ }
4023+ LOOP_CheckNum = ( CheckBuf_MBSize / ( ((DES_NUMBER * DMA_PakSize) / ONE_MBYTE ) + 1) );
4024+ }
4025+ #endif
4026+}
4027+
4028+//------------------------------------------------------------
4029+void TestingSetup (void) {
4030+ #ifdef DbgPrn_FuncHeader
4031+ printf ("TestingSetup\n");
4032+ Debug_delay();
4033+ #endif
4034+
4035+ #ifdef SLT_UBOOT
4036+ #else
4037+ #ifdef Rand_Sed
4038+ srand((unsigned) Rand_Sed);
4039+ #else
4040+ srand((unsigned) timestart);
4041+ #endif
4042+ #endif
4043+
4044+ //[Disable VGA]--------------------
4045+ #ifdef Disable_VGA
4046+ if ( LOOP_INFINI & ~(BurstEnable || IOTiming) ) {
4047+ VGAModeVld = 1;
4048+ outp(0x3d4, 0x17);
4049+ VGAMode = inp(0x3d5);
4050+ outp(0x3d4, 0x17);
4051+ outp(0x3d5, 0);
4052+ }
4053+ #endif
4054+
4055+ //[Setup]--------------------
4056+ setup_framesize();
4057+ setup_buf();
4058+}
4059+
4060+//------------------------------------------------------------
4061+// Return 1 ==> fail
4062+// Return 0 ==> PASS
4063+//------------------------------------------------------------
4064+char TestingLoop (ULONG loop_checknum) {
4065+ char checkprd;
4066+ char looplast;
4067+ char checken;
4068+
4069+ #ifdef SLT_UBOOT
4070+ #else
4071+ clock_t timeold;
4072+ #endif
4073+
4074+ #ifdef DbgPrn_FuncHeader
4075+ printf ("TestingLoop: %d\n", Loop);
4076+ Debug_delay();
4077+ #endif
4078+
4079+ if ( DbgPrn_DumpMACCnt )
4080+ dump_mac_ROreg();
4081+
4082+ //[Setup]--------------------
4083+ Loop = 0;
4084+ checkprd = 0;
4085+ checken = 0;
4086+ looplast = 0;
4087+
4088+ setup_des( 0 );
4089+
4090+ #ifdef SLT_UBOOT
4091+ #else
4092+ timeold = clock();
4093+ #endif
4094+
4095+ while ( (Loop < LOOP_MAX) || LOOP_INFINI ) {
4096+ looplast = !LOOP_INFINI && (Loop == LOOP_MAX - 1);
4097+
4098+ #ifdef CheckRxBuf
4099+ if (!BurstEnable) {
4100+ checkprd = ((Loop % loop_checknum) == (loop_checknum - 1));
4101+ }
4102+ checken = looplast | checkprd;
4103+ #endif
4104+
4105+ if ( DataDelay & ( Loop == 0 ) ) {
4106+ printf ("Press any key to start...\n");
4107+ GET_CAHR();
4108+ }
4109+
4110+#ifdef DbgPrn_FuncHeader
4111+ if ( DbgPrn_BufAdr ) {
4112+ printf ("for start ======> %d/%d(%d) looplast:%d checkprd:%d checken:%d\n", Loop, LOOP_MAX, LOOP_INFINI, looplast, checkprd, checken);
4113+ Debug_delay();
4114+ }
4115+#endif
4116+
4117+ //[Check DES]--------------------
4118+ if ( check_des(Loop, checken) ) {
4119+ //descriptor error
4120+ #ifdef CheckRxBuf
4121+ DES_NUMBER = CheckDesFail_DesNum + 1;
4122+ if ( checkprd ) {
4123+ check_buf(loop_checknum);
4124+ }
4125+ else {
4126+ check_buf((LOOP_MAX % loop_checknum));
4127+ }
4128+ DES_NUMBER = DES_NUMBER_Org;
4129+ #endif
4130+
4131+ if (DbgPrn_DumpMACCnt)
4132+ dump_mac_ROreg();
4133+
4134+ return(1);
4135+ }
4136+
4137+ //[Check Buf]--------------------
4138+ if ( RxDataEnable && checken ) {
4139+ #ifdef SLT_UBOOT
4140+ #else
4141+ timeused = (clock() - timeold) / (double) CLK_TCK;
4142+ #endif
4143+
4144+ if ( checkprd ) {
4145+ #ifdef SLT_DOS
4146+ #else
4147+ #ifdef SLT_UBOOT
4148+ #else
4149+ printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
4150+ fprintf(fp_log, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
4151+ #endif
4152+ #endif
4153+
4154+ #ifdef CheckRxBuf
4155+ if ( check_buf( loop_checknum ) )
4156+ return(1);
4157+ #endif
4158+ }
4159+ else {
4160+ #ifdef SLT_DOS
4161+ #else
4162+ #ifdef SLT_UBOOT
4163+ #else
4164+ printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (LOOP_MAX % loop_checknum), ((double)(LOOP_MAX % loop_checknum) * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
4165+ fprintf(fp_log, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (LOOP_MAX % loop_checknum), ((double)(LOOP_MAX % loop_checknum) * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
4166+ #endif
4167+ #endif
4168+
4169+ #ifdef CheckRxBuf
4170+ if ( check_buf( ( LOOP_MAX % loop_checknum ) ) )
4171+ return(1);
4172+ #endif
4173+ } // End if ( checkprd )
4174+
4175+ #ifdef SelectSimpleDes
4176+ #else
4177+ if ( !looplast )
4178+ setup_des_loop( Loop );
4179+ #endif
4180+
4181+ #ifdef SLT_DOS
4182+ #else
4183+ #ifdef SLT_UBOOT
4184+ #else
4185+ timeold = clock();
4186+ #endif
4187+ #endif
4188+
4189+ } // End if ( RxDataEnable && checken )
4190+
4191+ #ifdef SelectSimpleDes
4192+ if ( !looplast )
4193+ setup_des_loop( Loop );
4194+ #endif
4195+
4196+ if ( LOOP_INFINI ) {
4197+ printf("===============> Loop: %d \r", Loop);
4198+ }
4199+ else if (TestMode == 0) {
4200+ if (!(DbgPrn_BufAdr || IOTimingBund))
4201+ printf(" %d \r", Loop);
4202+// switch (Loop % 4) {
4203+// case 0x00: printf("| %d \r", Loop); break;
4204+// case 0x01: printf("/ %d \r", Loop); break;
4205+// case 0x02: printf("- %d \r", Loop); break;
4206+// default : printf("\ %d \r", Loop); break;
4207+// }
4208+ }
4209+
4210+ if ( DbgPrn_BufAdr ) {
4211+ printf ("for end ======> %d/%d(%d)\n", Loop, LOOP_MAX, LOOP_INFINI);
4212+ Debug_delay();
4213+ }
4214+
4215+ Loop++;
4216+ } // End while ((Loop < LOOP_MAX) || LOOP_INFINI)
4217+
4218+ Loop_rl[GSpeed_idx] = Loop;
4219+
4220+ return(0);
4221+} // End char TestingLoop (ULONG loop_checknum)
4222+
4223+
4224diff --git a/arch/arm/cpu/arm926ejs/aspeed/Makefile b/arch/arm/cpu/arm926ejs/aspeed/Makefile
4225new file mode 100644
4226index 0000000..378745e
4227--- /dev/null
4228+++ b/arch/arm/cpu/arm926ejs/aspeed/Makefile
4229@@ -0,0 +1,53 @@
4230+# This program is free software; you can redistribute it and/or
4231+# modify it under the terms of the GNU General Public License as
4232+# published by the Free Software Foundation; either version 2 of
4233+# the License, or (at your option) any later version.
4234+#
4235+# This program is distributed in the hope that it will be useful,
4236+# but WITHOUT ANY WARRANTY; without even the implied warranty of
4237+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4238+# GNU General Public License for more details.
4239+#
4240+# You should have received a copy of the GNU General Public License
4241+# along with this program; if not, write to the Free Software
4242+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
4243+# MA 02111-1307 USA
4244+#
4245+
4246+include $(TOPDIR)/config.mk
4247+
4248+LIB = $(obj)lib$(SOC).a
4249+
4250+COBJS = timer.o
4251+COBJS += reset.o
4252+COBJS += mactest.o
4253+COBJS += DRAM_SPI.o
4254+COBJS += IO.o
4255+COBJS += LIB.o
4256+COBJS += MAC.o
4257+COBJS += NCSI.o
4258+COBJS += PCI_SPI.o
4259+COBJS += PHY.o
4260+COBJS += SPIM.o
4261+COBJS += STDUBOOT.o
4262+COBJS += PLLTESTU.o
4263+COBJS += TRAPTEST.o
4264+COBJS += STRESS.o
4265+
4266+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
4267+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
4268+START := $(addprefix $(obj),$(START))
4269+
4270+all: $(obj).depend $(LIB)
4271+
4272+$(LIB): $(OBJS)
4273+ $(AR) $(ARFLAGS) $@ $(OBJS)
4274+
4275+#########################################################################
4276+
4277+# defines $(obj).depend target
4278+include $(SRCTREE)/rules.mk
4279+
4280+sinclude $(obj).depend
4281+
4282+#########################################################################
4283diff --git a/arch/arm/cpu/arm926ejs/aspeed/NCSI.H b/arch/arm/cpu/arm926ejs/aspeed/NCSI.H
4284new file mode 100644
4285index 0000000..a0e448b
4286--- /dev/null
4287+++ b/arch/arm/cpu/arm926ejs/aspeed/NCSI.H
4288@@ -0,0 +1,189 @@
4289+/*
4290+ * This program is distributed in the hope that it will be useful,
4291+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4292+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4293+ * GNU General Public License for more details.
4294+ *
4295+ * You should have received a copy of the GNU General Public License
4296+ * along with this program; if not, write to the Free Software
4297+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4298+ */
4299+#ifndef NCSI_H
4300+#define NCSI_H
4301+
4302+#include "TYPEDEF.H"
4303+
4304+//---------------------------------------------------------
4305+// Define
4306+//---------------------------------------------------------
4307+#define MAX_PACKAGE_NUM 8 // 1 ~ 8
4308+#define MAX_CHANNEL_NUM 4 // 1 ~ 32
4309+//#define Enable_NCSI_LOOP_INFINI //[off]
4310+
4311+//---------------------------------------------------------
4312+// Function
4313+//---------------------------------------------------------
4314+#define SENT_RETRY_COUNT 1
4315+#define NCSI_RxDESNum 50
4316+
4317+//#define NCSI_Skip_Phase1_DeSelectPackage
4318+//#define NCSI_Skip_DeSelectPackage
4319+//#define NCSI_Skip_DiSChannel
4320+//#define NCSI_EnableDelay_DeSelectPackage
4321+//#define NCSI_EnableDelay_GetLinkStatus
4322+//#define NCSI_EnableDelay_EachPackage
4323+//#define Print_Version_ID
4324+//#define Print_PackageName
4325+
4326+//---------------------------------------------------------
4327+// PCI DID/VID & Manufacturer ID
4328+//---------------------------------------------------------
4329+#define ManufacturerID_Intel 0x00000157 //343
4330+#define ManufacturerID_Broadcom 0x0000113d //4413
4331+#define ManufacturerID_Mellanox 0x000002c9 //713
4332+
4333+//PCI VID: [163c]intel
4334+//PCI VID: [8086]Intel Corporation
4335+//PCI VID: [8087]Intel
4336+//PCI VID: [14e4]Broadcom Corporation
4337+//PCI VID: [15b3]Mellanox
4338+#define PCI_DID_VID_Intel_82574L 0x10d38086 // IntelR 82574L Gigabit Ethernet Controller
4339+#define PCI_DID_VID_Intel_82575_10d6 0x10d68086 // 82566 DM-2-gigabyte
4340+#define PCI_DID_VID_Intel_82575_10a7 0x10a78086 // 82575EB Gigabit Network Connection
4341+#define PCI_DID_VID_Intel_82575_10a9 0x10a98086 // 82575EB Gigabit Network Connection
4342+#define PCI_DID_VID_Intel_82576_10c9 0x10c98086 //*82576 Gigabit ET Dual Port Server Adapter
4343+#define PCI_DID_VID_Intel_82576_10e6 0x10e68086 // 82576 Gigabit Network Connection
4344+#define PCI_DID_VID_Intel_82576_10e7 0x10e78086 // 82576 Gigabit Network Connection
4345+#define PCI_DID_VID_Intel_82576_10e8 0x10e88086 // E64750-xxx Intel Gigabit ET Quad Port Server Adapter
4346+#define PCI_DID_VID_Intel_82576_1518 0x15188086 // 82576NS SerDes Gigabit Network Connectio
4347+#define PCI_DID_VID_Intel_82576_1526 0x15268086 // Intel Gigabit ET2 Quad Port Server Adapter
4348+#define PCI_DID_VID_Intel_82576_150a 0x150a8086 // 82576NS Gigabit Ethernet Controller
4349+#define PCI_DID_VID_Intel_82576_150d 0x150d8086 // 82576 Gigabit Backplane Connection
4350+#define PCI_DID_VID_Intel_82599_10fb 0x10fb8086 // 10 Gb Ethernet controller
4351+#define PCI_DID_VID_Intel_82599_1557 0x15578086 //
4352+#define PCI_DID_VID_Intel_I350_1521 0x15218086 //
4353+#define PCI_DID_VID_Intel_I350_1523 0x15238086 //
4354+#define PCI_DID_VID_Intel_I210 0x15338086 //
4355+#define PCI_DID_VID_Intel_X540 0x15288086 //
4356+#define PCI_DID_VID_Broadcom_BCM5718 0x165614e4 //
4357+#define PCI_DID_VID_Broadcom_BCM5720 0x165f14e4 //
4358+#define PCI_DID_VID_Broadcom_BCM5725 0x164314e4 //
4359+#define PCI_DID_VID_Mellanox_ConnectX_3 0x100315b3 //*
4360+
4361+//---------------------------------------------------------
4362+// Delay (ms)
4363+//---------------------------------------------------------
4364+#define Delay_EachPackage 1000
4365+#define Delay_DeSelectPackage 50
4366+#define Delay_GetLinkStatus 50
4367+
4368+//---------------------------------------------------------
4369+// NCSI Parameter
4370+//---------------------------------------------------------
4371+//Command and Response Type
4372+#define CLEAR_INITIAL_STATE 0x00 //M
4373+#define SELECT_PACKAGE 0x01 //M
4374+#define DESELECT_PACKAGE 0x02 //M
4375+#define ENABLE_CHANNEL 0x03 //M
4376+#define DISABLE_CHANNEL 0x04 //M
4377+#define RESET_CHANNEL 0x05 //M
4378+#define ENABLE_CHANNEL_NETWORK_TX 0x06 //M
4379+#define DISABLE_CHANNEL_NETWORK_TX 0x07 //M
4380+#define AEN_ENABLE 0x08
4381+#define SET_LINK 0x09 //M
4382+#define GET_LINK_STATUS 0x0A //M
4383+#define SET_VLAN_FILTER 0x0B //M
4384+#define ENABLE_VLAN 0x0C //M
4385+#define DISABLE_VLAN 0x0D //M
4386+#define SET_MAC_ADDRESS 0x0E //M
4387+#define ENABLE_BROADCAST_FILTERING 0x10 //M
4388+#define DISABLE_BROADCAST_FILTERING 0x11 //M
4389+#define ENABLE_GLOBAL_MULTICAST_FILTERING 0x12
4390+#define DISABLE_GLOBAL_MULTICAST_FILTERING 0x13
4391+#define SET_NCSI_FLOW_CONTROL 0x14
4392+#define GET_VERSION_ID 0x15 //M
4393+#define GET_CAPABILITIES 0x16 //M
4394+#define GET_PARAMETERS 0x17 //M
4395+#define GET_CONTROLLER_PACKET_STATISTICS 0x18
4396+#define GET_NCSI_STATISTICS 0x19
4397+#define GET_NCSI_PASS_THROUGH_STATISTICS 0x1A
4398+
4399+//Standard Response Code
4400+#define COMMAND_COMPLETED 0x00
4401+#define COMMAND_FAILED 0x01
4402+#define COMMAND_UNAVAILABLE 0x02
4403+#define COMMAND_UNSUPPORTED 0x03
4404+
4405+//Standard Reason Code
4406+#define NO_ERROR 0x0000
4407+#define INTERFACE_INITIALIZATION_REQUIRED 0x0001
4408+#define PARAMETER_IS_INVALID 0x0002
4409+#define CHANNEL_NOT_READY 0x0003
4410+#define PACKAGE_NOT_READY 0x0004
4411+#define INVALID_PAYLOAD_LENGTH 0x0005
4412+#define UNKNOWN_COMMAND_TYPE 0x7FFF
4413+
4414+//SET_MAC_ADDRESS
4415+#define UNICAST ( 0x00 << 5 )
4416+#define MULTICAST ( 0x01 << 5 )
4417+#define DISABLE_MAC_ADDRESS_FILTER 0x00
4418+#define ENABLE_MAC_ADDRESS_FILTER 0x01
4419+
4420+//GET_LINK_STATUS
4421+#define LINK_DOWN 0
4422+#define LINK_UP 1
4423+
4424+#define NCSI_RxDMA_PakSize 2048
4425+#define NCSI_RxDMA_BASE (DMA_BASE+0x00100000)
4426+
4427+//---------------------------------------------------------
4428+// Variable
4429+//---------------------------------------------------------
4430+//NC-SI Command Packet
4431+typedef struct {
4432+//Ethernet Header
4433+ unsigned char DA[6]; // Destination Address
4434+ unsigned char SA[6]; // Source Address
4435+ unsigned short EtherType; // DMTF NC-SI, it should be 0x88F8
4436+//NC-SI Control Packet
4437+ unsigned char MC_ID; // Management Controller should set this field to 0x00
4438+ unsigned char Header_Revision; // For NC-SI 1.0 spec, this field has to set 0x01
4439+ unsigned char Reserved_1; // Reserved has to set to 0x00
4440+ unsigned char IID; // Instance ID
4441+ unsigned char Command;
4442+ unsigned char Channel_ID;
4443+ unsigned short Payload_Length; // Payload Length = 12 bits, 4 bits are reserved
4444+ unsigned long Reserved_2;
4445+ unsigned long Reserved_3;
4446+
4447+ unsigned short Reserved_4;
4448+ unsigned short Reserved_5;
4449+ unsigned short Response_Code;
4450+ unsigned short Reason_Code;
4451+ unsigned char Payload_Data[64];
4452+} NCSI_Command_Packet;
4453+
4454+//NC-SI Response Packet
4455+typedef struct {
4456+ unsigned char DA[6];
4457+ unsigned char SA[6];
4458+ unsigned short EtherType; //DMTF NC-SI
4459+//NC-SI Control Packet
4460+ unsigned char MC_ID; //Management Controller should set this field to 0x00
4461+ unsigned char Header_Revision; //For NC-SI 1.0 spec, this field has to set 0x01
4462+ unsigned char Reserved_1; //Reserved has to set to 0x00
4463+ unsigned char IID; //Instance ID
4464+ unsigned char Command;
4465+ unsigned char Channel_ID;
4466+ unsigned short Payload_Length; //Payload Length = 12 bits, 4 bits are reserved
4467+ unsigned short Reserved_2;
4468+ unsigned short Reserved_3;
4469+ unsigned short Reserved_4;
4470+ unsigned short Reserved_5;
4471+
4472+ unsigned short Response_Code;
4473+ unsigned short Reason_Code;
4474+ unsigned char Payload_Data[64];
4475+} NCSI_Response_Packet;
4476+
4477+#endif // NCSI_H
4478diff --git a/arch/arm/cpu/arm926ejs/aspeed/NCSI.c b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c
4479new file mode 100644
4480index 0000000..7de06c3
4481--- /dev/null
4482+++ b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c
4483@@ -0,0 +1,934 @@
4484+/*
4485+ * This program is distributed in the hope that it will be useful,
4486+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4487+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4488+ * GNU General Public License for more details.
4489+ *
4490+ * You should have received a copy of the GNU General Public License
4491+ * along with this program; if not, write to the Free Software
4492+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4493+ */
4494+#define NCSI_C
4495+static const char ThisFile[] = "NCSI.c";
4496+
4497+#include "SWFUNC.H"
4498+
4499+#ifdef SLT_UBOOT
4500+ #include <common.h>
4501+ #include <command.h>
4502+ #include <COMMINF.H>
4503+ #include <NCSI.H>
4504+ #include <IO.H>
4505+#endif
4506+#ifdef SLT_DOS
4507+ #include <stdio.h>
4508+ #include <stdlib.h>
4509+ #include <conio.h>
4510+ #include <string.h>
4511+ #include "COMMINF.H"
4512+ #include "NCSI.H"
4513+ #include "IO.H"
4514+#endif
4515+
4516+NCSI_Command_Packet NCSI_Request_SLT;
4517+NCSI_Response_Packet NCSI_Respond_SLT;
4518+int InstanceID;
4519+int NCSI_RxTimeOutScale;
4520+ULONG NCSI_RxDesBase;
4521+ULONG NCSI_TxDWBUF[512];
4522+ULONG NCSI_RxDWBUF[512];
4523+char NCSI_CommandStr[512];
4524+unsigned char *NCSI_TxByteBUF;
4525+unsigned char *NCSI_RxByteBUF;
4526+unsigned char NCSI_Payload_Data[16];
4527+unsigned long Payload_Checksum_NCSI = 0x00000000;
4528+ULONG select_flag[MAX_PACKAGE_NUM];
4529+
4530+ULONG DWSwap_SLT (ULONG in) {
4531+ return( ((in & 0xff000000) >> 24)
4532+ | ((in & 0x00ff0000) >> 8)
4533+ | ((in & 0x0000ff00) << 8)
4534+ | ((in & 0x000000ff) << 24)
4535+ );
4536+}
4537+USHORT WDSwap_SLT (USHORT in) {
4538+ return( ((in & 0xff00) >> 8)
4539+ | ((in & 0x00ff) << 8)
4540+ );
4541+}
4542+
4543+//------------------------------------------------------------
4544+int FindErr_NCSI (int value) {
4545+ NCSI_LinkFail_Val = NCSI_LinkFail_Val | value;
4546+ Err_Flag = Err_Flag | Err_NCSI_LinkFail;
4547+ if ( DbgPrn_ErrFlg )
4548+ printf ("\nErr_Flag: [%08lx] NCSI_LinkFail_Val: [%08lx]\n", Err_Flag, NCSI_LinkFail_Val);
4549+
4550+ return(1);
4551+}
4552+
4553+//------------------------------------------------------------
4554+// PHY IC(NC-SI)
4555+//------------------------------------------------------------
4556+void ncsi_respdump ( NCSI_Response_Packet *in ) {
4557+ printf ("DA : %02x %02x %02x %02x %02x %02x\n", in->DA[5], in->DA[4], in->DA[3], in->DA[2], in->DA[1], in->DA[0]);
4558+ printf ("SA : %02x %02x %02x %02x %02x %02x\n", in->SA[5], in->SA[4], in->SA[3], in->SA[2], in->SA[1], in->SA[0]);
4559+ printf ("EtherType : %04x\n", in->EtherType );//DMTF NC-SI
4560+ printf ("MC_ID : %02x\n", in->MC_ID );//Management Controller should set this field to 0x00
4561+ printf ("Header_Revision: %02x\n", in->Header_Revision );//For NC-SI 1.0 spec, this field has to set 0x01
4562+// printf ("Reserved_1 : %02x\n", in->Reserved_1 ); //Reserved has to set to 0x00
4563+ printf ("IID : %02x\n", in->IID );//Instance ID
4564+ printf ("Command : %02x\n", in->Command );
4565+ printf ("Channel_ID : %02x\n", in->Channel_ID );
4566+ printf ("Payload_Length : %04x\n", in->Payload_Length );//Payload Length = 12 bits, 4 bits are reserved
4567+// printf ("Reserved_2 : %04x\n", in->Reserved_2 );
4568+// printf ("Reserved_3 : %04x\n", in->Reserved_3 );
4569+// printf ("Reserved_4 : %04x\n", in->Reserved_4 );
4570+// printf ("Reserved_5 : %04x\n", in->Reserved_5 );
4571+ printf ("Response_Code : %04x\n", in->Response_Code );
4572+ printf ("Reason_Code : %04x\n", in->Reason_Code );
4573+ printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[ 3], in->Payload_Data[ 2], in->Payload_Data[ 1], in->Payload_Data[ 0]);
4574+// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[ 7], in->Payload_Data[ 6], in->Payload_Data[ 5], in->Payload_Data[ 4]);
4575+// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[11], in->Payload_Data[10], in->Payload_Data[ 9], in->Payload_Data[ 8]);
4576+// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[15], in->Payload_Data[14], in->Payload_Data[13], in->Payload_Data[12]);
4577+// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[19], in->Payload_Data[18], in->Payload_Data[17], in->Payload_Data[16]);
4578+// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[23], in->Payload_Data[22], in->Payload_Data[21], in->Payload_Data[20]);
4579+}
4580+
4581+//------------------------------------------------------------
4582+void NCSI_Struct_Initialize_SLT (void) {
4583+ int i;
4584+
4585+ ULONG NCSI_RxDatBase;
4586+
4587+ InstanceID = 0;
4588+ NCSI_RxTimeOutScale = 1;
4589+
4590+ for (i = 0; i < 6; i++) {
4591+ NCSI_Request_SLT.DA[i] = 0xFF;
4592+ }
4593+
4594+ for (i = 0; i < 6; i++) {
4595+// NCSI_Request.SA[i] = i<<2;
4596+ NCSI_Request_SLT.SA[i] = SA[i];
4597+ }
4598+
4599+ NCSI_Request_SLT.EtherType = WDSwap_SLT(0x88F8); // EtherType = 0x88F8 (DMTF NC-SI) page 50, table 8, NC-SI spec. version 1.0.0
4600+ NCSI_Request_SLT.MC_ID = 0;
4601+ NCSI_Request_SLT.Header_Revision = 0x01;
4602+ NCSI_Request_SLT.Reserved_1 = 0;
4603+ NCSI_Request_SLT.Reserved_2 = 0;
4604+ NCSI_Request_SLT.Reserved_3 = 0;
4605+
4606+ NCSI_TxByteBUF = (unsigned char *) &NCSI_TxDWBUF[0];
4607+ NCSI_RxByteBUF = (unsigned char *) &NCSI_RxDWBUF[0];
4608+
4609+ NCSI_RxDesBase = H_RDES_BASE;
4610+ NCSI_RxDatBase = NCSI_RxDMA_BASE;
4611+
4612+ for (i = 0; i < NCSI_RxDESNum - 1; i++) {
4613+ WriteSOC_DD( ( NCSI_RxDesBase + 0 ), 0x00000000 );
4614+ WriteSOC_DD( ( NCSI_RxDesBase + 4 ), 0x00000000 );
4615+ WriteSOC_DD( ( NCSI_RxDesBase + 8 ), 0x00000000 );
4616+ WriteSOC_DD( ( NCSI_RxDesBase + 0x0C ), (NCSI_RxDatBase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
4617+ NCSI_RxDesBase += 16;
4618+ NCSI_RxDatBase += NCSI_RxDMA_PakSize;
4619+ }
4620+ WriteSOC_DD( ( NCSI_RxDesBase + 0 ), EOR_IniVal );
4621+ WriteSOC_DD( ( NCSI_RxDesBase + 4 ), 0x00000000 );
4622+ WriteSOC_DD( ( NCSI_RxDesBase + 8 ), 0x00000000 );
4623+ WriteSOC_DD( ( NCSI_RxDesBase + 0x0C ), (NCSI_RxDatBase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
4624+
4625+ NCSI_RxDesBase = H_RDES_BASE;
4626+}
4627+
4628+//------------------------------------------------------------
4629+void Calculate_Checksum_NCSI (unsigned char *buffer_base, int Length) {
4630+ ULONG CheckSum = 0;
4631+ ULONG Data;
4632+ ULONG Data1;
4633+ int i;
4634+
4635+ // Calculate checksum is from byte 14 of ethernet Haeder and Control packet header
4636+ // Page 50, NC-SI spec. ver. 1.0.0 form DMTF
4637+ for (i = 14; i < Length; i += 2 ) {
4638+ Data = buffer_base[i];
4639+ Data1 = buffer_base[i + 1];
4640+ CheckSum += ((Data << 8) + Data1);
4641+ }
4642+ Payload_Checksum_NCSI = DWSwap_SLT(~(CheckSum) + 1); //2's complement
4643+}
4644+
4645+//------------------------------------------------------------
4646+// return 0: it is PASS
4647+// return 1: it is FAIL
4648+//------------------------------------------------------------
4649+char NCSI_Rx_SLT (unsigned char command) {
4650+
4651+#define NCSI_RX_RETRY_TIME 2
4652+ int timeout = 0;
4653+ int bytesize;
4654+ int dwsize;
4655+ int i;
4656+ int retry = 0;
4657+ char ret = 1;
4658+
4659+ ULONG NCSI_RxDatBase;
4660+ ULONG NCSI_RxDesDat;
4661+ ULONG NCSI_RxData;
4662+
4663+
4664+ do {
4665+ WriteSOC_DD( ( H_MAC_BASE + 0x1C ), 0x00000000 );//Rx Poll
4666+
4667+ do {
4668+ NCSI_RxDesDat = ReadSOC_DD(NCSI_RxDesBase);
4669+ if ( ++timeout > TIME_OUT_NCSI * NCSI_RxTimeOutScale ) {
4670+ #ifdef SLT_DOS
4671+ fprintf(fp_log, "[Cmd:%02X][NCSI-RxDesOwn] %08lX \n", command, NCSI_RxDesDat );
4672+ #endif
4673+ return( FindErr(Err_NCSI_Check_RxOwnTimeOut) );
4674+ }
4675+ } while( HWOwnRx(NCSI_RxDesDat) );
4676+
4677+ #ifdef CheckRxErr
4678+ if (NCSI_RxDesDat & 0x00040000) {
4679+ #ifdef SLT_DOS
4680+ fprintf(fp_log, "[RxDes] Error RxErr %08lx\n", NCSI_RxDesDat);
4681+ #endif
4682+ FindErr_Des(Check_Des_RxErr);
4683+ }
4684+ #endif
4685+
4686+ #ifdef CheckOddNibble
4687+ if (NCSI_RxDesDat & 0x00400000) {
4688+ #ifdef SLT_DOS
4689+ fprintf(fp_log, "[RxDes] Odd Nibble %08lx\n", NCSI_RxDesDat);
4690+ #endif
4691+ FindErr_Des(Check_Des_OddNibble);
4692+ }
4693+ #endif
4694+
4695+ #ifdef CheckCRC
4696+ if (NCSI_RxDesDat & 0x00080000) {
4697+ #ifdef SLT_DOS
4698+ fprintf(fp_log, "[RxDes] Error CRC %08lx\n", NCSI_RxDesDat);
4699+ #endif
4700+ FindErr_Des(Check_Des_CRC);
4701+ }
4702+ #endif
4703+
4704+ #ifdef CheckRxFIFOFull
4705+ if (NCSI_RxDesDat & 0x00800000) {
4706+ #ifdef SLT_DOS
4707+ fprintf(fp_log, "[RxDes] Error Rx FIFO Full %08lx\n", NCSI_RxDesDat);
4708+ #endif
4709+ FindErr_Des(Check_Des_RxFIFOFull);
4710+ }
4711+ #endif
4712+
4713+ // Get point of RX DMA buffer
4714+ NCSI_RxDatBase = ReadSOC_DD( NCSI_RxDesBase + 0x0C );
4715+ NCSI_RxData = ReadSOC_DD( NCSI_RxDatBase + 0x0C );
4716+
4717+ if ( HWEOR( NCSI_RxDesDat ) ) {
4718+ // it is last the descriptor in the receive Ring
4719+ WriteSOC_DD( NCSI_RxDesBase , EOR_IniVal );
4720+ NCSI_RxDesBase = H_RDES_BASE;
4721+ }
4722+ else {
4723+ WriteSOC_DD( NCSI_RxDesBase , 0x00000000 );
4724+ NCSI_RxDesBase += 16;
4725+ }
4726+
4727+ // Get RX valid data in offset 00h of RXDS#0
4728+ bytesize = (NCSI_RxDesDat & 0x3fff);
4729+
4730+ // Fill up to multiple of 4
4731+ if ( ( bytesize % 4 ) != 0 )
4732+ dwsize = ( bytesize >> 2 ) + 1;
4733+ else
4734+ dwsize = bytesize >> 2;
4735+
4736+ #ifdef SLT_DOS
4737+ if ( PrintNCSIEn )
4738+ fprintf(fp_log ,"[Rx] %d bytes(%xh)\n", bytesize, bytesize);
4739+ #endif
4740+
4741+ for (i = 0; i < dwsize; i++) {
4742+ NCSI_RxDWBUF[i] = ReadSOC_DD(NCSI_RxDatBase + ( i << 2 ));
4743+ if ( PrintNCSIEn ) {
4744+ if ( i == ( dwsize - 1 ) ) {
4745+ switch (bytesize % 4) {
4746+ case 0 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffffffff; break;
4747+ case 3 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffffff ; break;
4748+ case 2 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffff ; break;
4749+ case 1 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xff ; break;
4750+ }
4751+ #ifdef SLT_DOS
4752+ switch (bytesize % 4) {
4753+ case 0 : fprintf(fp_log ,"[Rx%02d]%08lx %08lx\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) ); break;
4754+ case 3 : fprintf(fp_log ,"[Rx%02d]--%06lx %06lx--\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 8 ); break;
4755+ case 2 : fprintf(fp_log ,"[Rx%02d]----%04lx %04lx----\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 16 ); break;
4756+ case 1 : fprintf(fp_log ,"[Rx%02d]------%02lx %02lx------\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 24 ); break;
4757+ default : fprintf(fp_log ,"[Rx%02d]error", i); break;
4758+ }
4759+ #endif
4760+ }
4761+ else {
4762+ #ifdef SLT_DOS
4763+ fprintf(fp_log ,"[Rx%02d]%08lx %08lx\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]));
4764+ #endif
4765+ }
4766+ }
4767+ } // End for (i = 0; i < dwsize; i++)
4768+
4769+ // EtherType field of the response packet should be 0x88F8
4770+ if ((NCSI_RxData & 0xffff) == 0xf888) {
4771+ memcpy (&NCSI_Respond_SLT, NCSI_RxByteBUF, bytesize);
4772+
4773+ #ifdef SLT_DOS
4774+ if ( PrintNCSIEn )
4775+ fprintf(fp_log ,"[Rx IID:%2d]\n", NCSI_Respond_SLT.IID);
4776+ #endif
4777+
4778+ NCSI_Respond_SLT.EtherType = WDSwap_SLT( NCSI_Respond_SLT.EtherType );
4779+ NCSI_Respond_SLT.Payload_Length = WDSwap_SLT( NCSI_Respond_SLT.Payload_Length );
4780+ NCSI_Respond_SLT.Response_Code = WDSwap_SLT( NCSI_Respond_SLT.Response_Code );
4781+ NCSI_Respond_SLT.Reason_Code = WDSwap_SLT( NCSI_Respond_SLT.Reason_Code );
4782+
4783+ ret = 0;
4784+ break;
4785+ }
4786+ else {
4787+ #ifdef SLT_DOS
4788+ if ( PrintNCSIEn )
4789+ fprintf(fp_log, "[Skip] Not NCSI Response: %08lx\n", NCSI_RxData);
4790+ #endif
4791+
4792+ retry++;
4793+ }
4794+ } while ( retry < NCSI_RX_RETRY_TIME );
4795+
4796+ return( ret );
4797+} // End char NCSI_Rx_SLT (void)
4798+
4799+//------------------------------------------------------------
4800+char NCSI_Tx (void) {
4801+ int bytesize;
4802+ int dwsize;
4803+ int i;
4804+ int timeout = 0;
4805+ ULONG NCSI_TxDesDat;
4806+
4807+ // Header of NC-SI command format is 34 bytes. page 58, NC-SI spec. ver 1.0.0 from DMTF
4808+ // The minimum size of a NC-SI package is 64 bytes.
4809+ bytesize = 34 + WDSwap_SLT(NCSI_Request_SLT.Payload_Length);
4810+ if ( bytesize < 64 ) {
4811+ memset (NCSI_TxByteBUF + bytesize, 0, 60 - bytesize);
4812+ bytesize = 64;
4813+ }
4814+
4815+ // Fill up to multiple of 4
4816+// dwsize = (bytesize + 3) >> 2;
4817+ if ( ( bytesize % 4 ) != 0 )
4818+ dwsize = ( bytesize >> 2 ) + 1;
4819+ else
4820+ dwsize = bytesize >> 2;
4821+
4822+ #ifdef SLT_DOS
4823+ if ( PrintNCSIEn )
4824+ fprintf(fp_log ,"[Tx IID:%2d] %d bytes(%xh)\n", NCSI_Request_SLT.IID, bytesize, bytesize);
4825+ #endif
4826+
4827+ // Copy data to DMA buffer
4828+ for (i = 0; i < dwsize; i++) {
4829+ WriteSOC_DD( DMA_BASE + (i << 2), NCSI_TxDWBUF[i] );
4830+ if ( PrintNCSIEn ) {
4831+ if (i == (dwsize - 1)) {
4832+ switch (bytesize % 4) {
4833+ case 0 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0xffffffff; break;
4834+ case 3 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x00ffffff; break;
4835+ case 2 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x0000ffff; break;
4836+ case 1 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x000000ff; break;
4837+ }
4838+ #ifdef SLT_DOS
4839+ switch (bytesize % 4) {
4840+ case 0 : fprintf(fp_log ,"[Tx%02d]%08x %08x\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) ); break;
4841+ case 3 : fprintf(fp_log ,"[Tx%02d]--%06x %06x--\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 8 ); break;
4842+ case 2 : fprintf(fp_log ,"[Tx%02d]----%04x %04x----\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 16 ); break;
4843+ case 1 : fprintf(fp_log ,"[Tx%02d]------%02x %02x------\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 24 ); break;
4844+ default : fprintf(fp_log ,"[Tx%02d]error", i); break;
4845+ }
4846+ #endif
4847+ }
4848+ else {
4849+ #ifdef SLT_DOS
4850+ fprintf( fp_log , "[Tx%02d]%08x %08x\n", i, NCSI_TxDWBUF[i], DWSwap_SLT(NCSI_TxDWBUF[i]) );
4851+ #endif
4852+ }
4853+ }
4854+ } // End for (i = 0; i < dwsize; i++)
4855+
4856+ // Setting one TX descriptor
4857+ WriteSOC_DD( H_TDES_BASE + 0x04, 0 );
4858+ WriteSOC_DD( H_TDES_BASE + 0x08, 0 );
4859+ WriteSOC_DD( H_TDES_BASE + 0x0C, (DMA_BASE + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
4860+ WriteSOC_DD( H_TDES_BASE , 0xf0008000 + bytesize );
4861+ // Fire
4862+ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll
4863+
4864+ do {
4865+ NCSI_TxDesDat = ReadSOC_DD(H_TDES_BASE);
4866+ if ( ++timeout > TIME_OUT_NCSI ) {
4867+ #ifdef SLT_DOS
4868+ fprintf(fp_log, "[NCSI-TxDesOwn] %08lx\n", NCSI_TxDesDat);
4869+ #endif
4870+
4871+ return(FindErr(Err_NCSI_Check_TxOwnTimeOut));
4872+ }
4873+ } while ( HWOwnTx(NCSI_TxDesDat) );
4874+
4875+ return(0);
4876+} // End char NCSI_Tx (void)
4877+
4878+//------------------------------------------------------------
4879+char NCSI_ARP (void) {
4880+ int i;
4881+ int timeout = 0;
4882+ ULONG NCSI_TxDesDat;
4883+
4884+ if ( ARPNumCnt ) {
4885+ #ifdef SLT_DOS
4886+ if ( PrintNCSIEn )
4887+ fprintf(fp_log ,"[ARP] 60 bytes x%d\n", ARPNumCnt);
4888+ #endif
4889+
4890+ for (i = 0; i < 15; i++) {
4891+ #ifdef SLT_DOS
4892+ if ( PrintNCSIEn )
4893+ fprintf(fp_log ,"[Tx%02d] %08x %08x\n", i, ARP_data[i], DWSwap_SLT(ARP_data[i]));
4894+ #endif
4895+ WriteSOC_DD( DMA_BASE + ( i << 2 ), ARP_data[i] );
4896+ }
4897+ WriteSOC_DD( H_TDES_BASE + 0x04, 0 );
4898+ WriteSOC_DD( H_TDES_BASE + 0x08, 0 );
4899+ WriteSOC_DD( H_TDES_BASE + 0x0C, (DMA_BASE + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
4900+ WriteSOC_DD( H_TDES_BASE , 0xf0008000 + 60 );
4901+
4902+ for (i = 0; i < ARPNumCnt; i++) {
4903+ WriteSOC_DD( H_TDES_BASE , 0xf0008000 + 60);
4904+
4905+ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll
4906+
4907+ timeout = 0;
4908+ do {
4909+ NCSI_TxDesDat = ReadSOC_DD(H_TDES_BASE);
4910+
4911+ if (++timeout > TIME_OUT_NCSI) {
4912+ #ifdef SLT_DOS
4913+ fprintf(fp_log, "[ARP-TxDesOwn] %08lx\n", NCSI_TxDesDat);
4914+ #endif
4915+
4916+ return(FindErr(Err_NCSI_Check_ARPOwnTimeOut));
4917+ }
4918+ } while (HWOwnTx(NCSI_TxDesDat));
4919+ }
4920+ }
4921+ return(0);
4922+} // End char NCSI_ARP (void)
4923+
4924+//------------------------------------------------------------
4925+void WrRequest (unsigned char command, unsigned char id, unsigned short length) {
4926+
4927+ NCSI_Request_SLT.IID = InstanceID;
4928+ NCSI_Request_SLT.Command = command;
4929+ NCSI_Request_SLT.Channel_ID = id;
4930+ NCSI_Request_SLT.Payload_Length = WDSwap_SLT(length);
4931+
4932+ memcpy ( NCSI_TxByteBUF , &NCSI_Request_SLT , 30 );
4933+ memcpy ((NCSI_TxByteBUF + 30 ), &NCSI_Payload_Data , length);
4934+ Calculate_Checksum_NCSI(NCSI_TxByteBUF, 30 + length);
4935+ memcpy ((NCSI_TxByteBUF + 30 + length), &Payload_Checksum_NCSI, 4 );
4936+}
4937+
4938+//------------------------------------------------------------
4939+void NCSI_PrintCommandStr (unsigned char command, unsigned iid) {
4940+ switch (command & 0x80) {
4941+ case 0x80 : sprintf(NCSI_CommandStr, "IID:%3d [%02x][Respond]", iid, command); break;
4942+ default : sprintf(NCSI_CommandStr, "IID:%3d [%02x][Request]", iid, command); break;
4943+ }
4944+ switch (command & 0x7f) {
4945+ case 0x00 : sprintf(NCSI_CommandStr, "%s[CLEAR_INITIAL_STATE ]", NCSI_CommandStr); break;
4946+ case 0x01 : sprintf(NCSI_CommandStr, "%s[SELECT_PACKAGE ]", NCSI_CommandStr); break;
4947+ case 0x02 : sprintf(NCSI_CommandStr, "%s[DESELECT_PACKAGE ]", NCSI_CommandStr); break;
4948+ case 0x03 : sprintf(NCSI_CommandStr, "%s[ENABLE_CHANNEL ]", NCSI_CommandStr); break;
4949+ case 0x04 : sprintf(NCSI_CommandStr, "%s[DISABLE_CHANNEL ]", NCSI_CommandStr); break;
4950+ case 0x05 : sprintf(NCSI_CommandStr, "%s[RESET_CHANNEL ]", NCSI_CommandStr); break;
4951+ case 0x06 : sprintf(NCSI_CommandStr, "%s[ENABLE_CHANNEL_NETWORK_TX ]", NCSI_CommandStr); break;
4952+ case 0x07 : sprintf(NCSI_CommandStr, "%s[DISABLE_CHANNEL_NETWORK_TX ]", NCSI_CommandStr); break;
4953+ case 0x08 : sprintf(NCSI_CommandStr, "%s[AEN_ENABLE ]", NCSI_CommandStr); break;
4954+ case 0x09 : sprintf(NCSI_CommandStr, "%s[SET_LINK ]", NCSI_CommandStr); break;
4955+ case 0x0A : sprintf(NCSI_CommandStr, "%s[GET_LINK_STATUS ]", NCSI_CommandStr); break;
4956+ case 0x0B : sprintf(NCSI_CommandStr, "%s[SET_VLAN_FILTER ]", NCSI_CommandStr); break;
4957+ case 0x0C : sprintf(NCSI_CommandStr, "%s[ENABLE_VLAN ]", NCSI_CommandStr); break;
4958+ case 0x0D : sprintf(NCSI_CommandStr, "%s[DISABLE_VLAN ]", NCSI_CommandStr); break;
4959+ case 0x0E : sprintf(NCSI_CommandStr, "%s[SET_MAC_ADDRESS ]", NCSI_CommandStr); break;
4960+ case 0x10 : sprintf(NCSI_CommandStr, "%s[ENABLE_BROADCAST_FILTERING ]", NCSI_CommandStr); break;
4961+ case 0x11 : sprintf(NCSI_CommandStr, "%s[DISABLE_BROADCAST_FILTERING ]", NCSI_CommandStr); break;
4962+ case 0x12 : sprintf(NCSI_CommandStr, "%s[ENABLE_GLOBAL_MULTICAST_FILTERING ]", NCSI_CommandStr); break;
4963+ case 0x13 : sprintf(NCSI_CommandStr, "%s[DISABLE_GLOBAL_MULTICAST_FILTERING ]", NCSI_CommandStr); break;
4964+ case 0x14 : sprintf(NCSI_CommandStr, "%s[SET_NCSI_FLOW_CONTROL ]", NCSI_CommandStr); break;
4965+ case 0x15 : sprintf(NCSI_CommandStr, "%s[GET_VERSION_ID ]", NCSI_CommandStr); break;
4966+ case 0x16 : sprintf(NCSI_CommandStr, "%s[GET_CAPABILITIES ]", NCSI_CommandStr); break;
4967+ case 0x17 : sprintf(NCSI_CommandStr, "%s[GET_PARAMETERS ]", NCSI_CommandStr); break;
4968+ case 0x18 : sprintf(NCSI_CommandStr, "%s[GET_CONTROLLER_PACKET_STATISTICS ]", NCSI_CommandStr); break;
4969+ case 0x19 : sprintf(NCSI_CommandStr, "%s[GET_NCSI_STATISTICS ]", NCSI_CommandStr); break;
4970+ case 0x1A : sprintf(NCSI_CommandStr, "%s[GET_NCSI_PASS_THROUGH_STATISTICS ]", NCSI_CommandStr); break;
4971+ case 0x50 : sprintf(NCSI_CommandStr, "%s[OEM_COMMAND ]", NCSI_CommandStr); break;
4972+ default : sprintf(NCSI_CommandStr, "%s Not Support Command", NCSI_CommandStr); break ;
4973+ }
4974+} // End void NCSI_PrintCommandStr (unsigned char command, unsigned iid)
4975+
4976+//------------------------------------------------------------
4977+void NCSI_PrintCommandType (unsigned char command, unsigned iid) {
4978+ NCSI_PrintCommandStr(command, iid);
4979+ printf ("%s\n", NCSI_CommandStr);
4980+}
4981+
4982+//------------------------------------------------------------
4983+void NCSI_PrintCommandType2File (unsigned char command, unsigned iid) {
4984+ NCSI_PrintCommandStr(command, iid);
4985+ #ifdef SLT_DOS
4986+ fprintf(fp_log, "%s\n", NCSI_CommandStr);
4987+ #endif
4988+}
4989+
4990+//------------------------------------------------------------
4991+char NCSI_SentWaitPacket (unsigned char command, unsigned char id, unsigned short length) {
4992+ int Retry = 0;
4993+ char ret;
4994+
4995+ do {
4996+ InstanceID++;
4997+ WrRequest(command, id, length);
4998+
4999+ ret = NCSI_Tx(); if ( ret != 0 )
5000+ {
5001+ // printf("======> NCSI_Tx return code = %X\n", ret );
5002+ return(1);
5003+ }
5004+#ifdef Print_PackageName
5005+ NCSI_PrintCommandType(command, InstanceID);
5006+#endif
5007+
5008+#ifdef NCSI_EnableDelay_EachPackage
5009+ delay(Delay_EachPackage);
5010+#endif
5011+ if ( NCSI_Rx_SLT( command ) )
5012+ return(2);
5013+
5014+ #ifdef SLT_DOS
5015+ if ( PrintNCSIEn )
5016+ fprintf(fp_log, "[Request] ETyp:%04x MC_ID:%02x HeadVer:%02x IID:%02x Comm:%02x ChlID:%02x PayLen:%04x\n", WDSwap_SLT(NCSI_Request_SLT.EtherType),
5017+ NCSI_Request_SLT.MC_ID,
5018+ NCSI_Request_SLT.Header_Revision,
5019+ NCSI_Request_SLT.IID,
5020+ NCSI_Request_SLT.Command,
5021+ NCSI_Request_SLT.Channel_ID,
5022+ WDSwap_SLT(NCSI_Request_SLT.Payload_Length) );
5023+ if ( PrintNCSIEn )
5024+ fprintf(fp_log, "[Respond] ETyp:%04x MC_ID:%02x HeadVer:%02x IID:%02x Comm:%02x ChlID:%02x PayLen:%04x ResCd:%02x ReaCd:%02x\n",
5025+ NCSI_Respond_SLT.EtherType,
5026+ NCSI_Respond_SLT.MC_ID,
5027+ NCSI_Respond_SLT.Header_Revision,
5028+ NCSI_Respond_SLT.IID,
5029+ NCSI_Respond_SLT.Command,
5030+ NCSI_Respond_SLT.Channel_ID,
5031+ NCSI_Respond_SLT.Payload_Length,
5032+ NCSI_Respond_SLT.Response_Code,
5033+ NCSI_Respond_SLT.Reason_Code);
5034+ #endif
5035+
5036+ if ( (NCSI_Respond_SLT.IID != InstanceID) ||
5037+ (NCSI_Respond_SLT.Command != (command | 0x80)) ||
5038+ (NCSI_Respond_SLT.Response_Code != COMMAND_COMPLETED) ) {
5039+ #ifdef SLT_DOS
5040+ if ( PrintNCSIEn )
5041+ fprintf(fp_log, "Retry: Command = %x, Response_Code = %x\n", NCSI_Request_SLT.Command, NCSI_Respond_SLT.Response_Code);
5042+
5043+ #endif
5044+ Retry++;
5045+ }
5046+ else {
5047+ if ( PrintNCSIEn )
5048+ NCSI_PrintCommandType2File(command, InstanceID);
5049+
5050+ return(0);
5051+ }
5052+ } while (Retry <= SENT_RETRY_COUNT);
5053+
5054+ return( 3 );
5055+} // End char NCSI_SentWaitPacket (unsigned char command, unsigned char id, unsigned short length)
5056+
5057+//------------------------------------------------------------
5058+char Clear_Initial_State_SLT (int Channel_ID) {//Command:0x00
5059+ return(NCSI_SentWaitPacket(CLEAR_INITIAL_STATE, (NCSI_Cap_SLT.Package_ID << 5) + Channel_ID, 0));//Internal Channel ID = 0
5060+}
5061+
5062+//------------------------------------------------------------
5063+char Select_Package_SLT (int Package_ID) {//Command:0x01
5064+ memset ((void *)NCSI_Payload_Data, 0, 4);
5065+ NCSI_Payload_Data[3] = 1; //Arbitration Disable
5066+
5067+ return(NCSI_SentWaitPacket(SELECT_PACKAGE, (Package_ID << 5) + 0x1F, 4));//Internal Channel ID = 0x1F, 0x1F means all channel
5068+}
5069+
5070+//------------------------------------------------------------
5071+void Select_Active_Package_SLT (void) {//Command:0x01
5072+ memset ((void *)NCSI_Payload_Data, 0, 4);
5073+ NCSI_Payload_Data[3] = 1; //Arbitration Disable
5074+
5075+ if (NCSI_SentWaitPacket(SELECT_PACKAGE, (NCSI_Cap_SLT.Package_ID << 5) + 0x1F, 4)) {//Internal Channel ID = 0x1F
5076+ FindErr_NCSI(NCSI_LinkFail_Select_Active_Package);
5077+ }
5078+}
5079+
5080+//------------------------------------------------------------
5081+void DeSelect_Package_SLT (int Package_ID) {//Command:0x02
5082+ NCSI_SentWaitPacket(DESELECT_PACKAGE, (Package_ID << 5) + 0x1F, 0);//Internal Channel ID = 0x1F, 0x1F means all channel
5083+
5084+#ifdef NCSI_EnableDelay_DeSelectPackage
5085+ delay(Delay_DeSelectPackage);
5086+#endif
5087+}
5088+
5089+//------------------------------------------------------------
5090+void Enable_Channel_SLT (void) {//Command:0x03
5091+ if ( NCSI_SentWaitPacket(ENABLE_CHANNEL, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) {
5092+ FindErr_NCSI(NCSI_LinkFail_Enable_Channel);
5093+ }
5094+}
5095+
5096+//------------------------------------------------------------
5097+void Disable_Channel_SLT (void) {//Command:0x04
5098+ memset ((void *)NCSI_Payload_Data, 0, 4);
5099+ NCSI_Payload_Data[3] = 0x1; //ALD
5100+
5101+ if (NCSI_SentWaitPacket(DISABLE_CHANNEL, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 4)) {
5102+ FindErr_NCSI(NCSI_LinkFail_Disable_Channel);
5103+ }
5104+}
5105+void Enable_Network_TX_SLT (void) {//Command:0x06
5106+ if ( NCSI_SentWaitPacket(ENABLE_CHANNEL_NETWORK_TX, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) {
5107+ FindErr_NCSI(NCSI_LinkFail_Enable_Network_TX);
5108+ }
5109+}
5110+
5111+//------------------------------------------------------------
5112+void Disable_Network_TX_SLT (void) {//Command:0x07
5113+ if ( NCSI_SentWaitPacket(DISABLE_CHANNEL_NETWORK_TX, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) {
5114+ FindErr_NCSI(NCSI_LinkFail_Disable_Network_TX);
5115+ }
5116+}
5117+
5118+//------------------------------------------------------------
5119+void Set_Link_SLT (void) {//Command:0x09
5120+ memset ((void *)NCSI_Payload_Data, 0, 8);
5121+ NCSI_Payload_Data[2] = 0x02; //full duplex
5122+// NCSI_Payload_Data[3] = 0x04; //100M, auto-disable
5123+ NCSI_Payload_Data[3] = 0x05; //100M, auto-enable
5124+
5125+ NCSI_SentWaitPacket(SET_LINK, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 8);
5126+}
5127+
5128+//------------------------------------------------------------
5129+char Get_Link_Status_SLT (void) {//Command:0x0a
5130+
5131+ if (NCSI_SentWaitPacket(GET_LINK_STATUS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0)) {
5132+ return(0);
5133+ }
5134+ else {
5135+ if (NCSI_Respond_SLT.Payload_Data[3] & 0x20) {
5136+ if (NCSI_Respond_SLT.Payload_Data[3] & 0x40) {
5137+ if (NCSI_Respond_SLT.Payload_Data[3] & 0x01)
5138+ return(1); //Link Up or Not
5139+ else
5140+ return(0);
5141+ } else
5142+ return(0); //Auto Negotiate did not finish
5143+ } else {
5144+ if (NCSI_Respond_SLT.Payload_Data[3] & 0x01)
5145+ return(1); //Link Up or Not
5146+ else
5147+ return(0);
5148+ }
5149+ }
5150+} // End char Get_Link_Status_SLT (void)
5151+
5152+//------------------------------------------------------------
5153+void Enable_Set_MAC_Address_SLT (void) {//Command:0x0e
5154+ int i;
5155+
5156+ for ( i = 0; i < 6; i++ ) {
5157+ NCSI_Payload_Data[i] = NCSI_Request_SLT.SA[i];
5158+ }
5159+ NCSI_Payload_Data[6] = 1; //MAC Address Num = 1 --> address filter 1, fixed in sample code
5160+ NCSI_Payload_Data[7] = UNICAST + 0 + ENABLE_MAC_ADDRESS_FILTER; //AT + Reserved + E
5161+
5162+ if ( NCSI_SentWaitPacket(SET_MAC_ADDRESS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 8) ) {
5163+ FindErr_NCSI(NCSI_LinkFail_Enable_Set_MAC_Address);
5164+ }
5165+}
5166+
5167+//------------------------------------------------------------
5168+void Enable_Broadcast_Filter_SLT (void) {//Command:0x10
5169+ memset ((void *)NCSI_Payload_Data, 0, 4);
5170+ NCSI_Payload_Data[3] = 0xF; //ARP, DHCP, NetBIOS
5171+
5172+ if (NCSI_SentWaitPacket(ENABLE_BROADCAST_FILTERING, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 4) ) {
5173+ FindErr_NCSI(NCSI_LinkFail_Enable_Broadcast_Filter);
5174+ }
5175+}
5176+
5177+//------------------------------------------------------------
5178+void Get_Version_ID_SLT (void) {//Command:0x15
5179+
5180+ if (NCSI_SentWaitPacket(GET_VERSION_ID, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) {
5181+ FindErr_NCSI(NCSI_LinkFail_Get_Version_ID);
5182+ }
5183+ else {
5184+#ifdef Print_Version_ID
5185+ printf ("NCSI Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 0], NCSI_Respond_SLT.Payload_Data[ 1], NCSI_Respond_SLT.Payload_Data[ 2], NCSI_Respond_SLT.Payload_Data[ 3]);
5186+ printf ("NCSI Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 4], NCSI_Respond_SLT.Payload_Data[ 5], NCSI_Respond_SLT.Payload_Data[ 6], NCSI_Respond_SLT.Payload_Data[ 7]);
5187+ printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 8], NCSI_Respond_SLT.Payload_Data[ 9], NCSI_Respond_SLT.Payload_Data[10], NCSI_Respond_SLT.Payload_Data[11]);
5188+ printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[12], NCSI_Respond_SLT.Payload_Data[13], NCSI_Respond_SLT.Payload_Data[14], NCSI_Respond_SLT.Payload_Data[15]);
5189+ printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[16], NCSI_Respond_SLT.Payload_Data[17], NCSI_Respond_SLT.Payload_Data[18], NCSI_Respond_SLT.Payload_Data[19]);
5190+ printf ("Firmware Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[20], NCSI_Respond_SLT.Payload_Data[21], NCSI_Respond_SLT.Payload_Data[22], NCSI_Respond_SLT.Payload_Data[23]);
5191+ printf ("PCI DID/VID : %02x %02x/%02x %02x\n", NCSI_Respond_SLT.Payload_Data[24], NCSI_Respond_SLT.Payload_Data[25], NCSI_Respond_SLT.Payload_Data[26], NCSI_Respond_SLT.Payload_Data[27]);
5192+ printf ("PCI SSID/SVID : %02x %02x/%02x %02x\n", NCSI_Respond_SLT.Payload_Data[28], NCSI_Respond_SLT.Payload_Data[29], NCSI_Respond_SLT.Payload_Data[30], NCSI_Respond_SLT.Payload_Data[31]);
5193+ printf ("Manufacturer ID : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[32], NCSI_Respond_SLT.Payload_Data[33], NCSI_Respond_SLT.Payload_Data[34], NCSI_Respond_SLT.Payload_Data[35]);
5194+ printf ("Checksum : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[36], NCSI_Respond_SLT.Payload_Data[37], NCSI_Respond_SLT.Payload_Data[38], NCSI_Respond_SLT.Payload_Data[39]);
5195+#endif
5196+ NCSI_Cap_SLT.PCI_DID_VID = (NCSI_Respond_SLT.Payload_Data[24]<<24)
5197+ | (NCSI_Respond_SLT.Payload_Data[25]<<16)
5198+ | (NCSI_Respond_SLT.Payload_Data[26]<< 8)
5199+ | (NCSI_Respond_SLT.Payload_Data[27] );
5200+ NCSI_Cap_SLT.ManufacturerID = (NCSI_Respond_SLT.Payload_Data[32]<<24)
5201+ | (NCSI_Respond_SLT.Payload_Data[33]<<16)
5202+ | (NCSI_Respond_SLT.Payload_Data[34]<< 8)
5203+ | (NCSI_Respond_SLT.Payload_Data[35] );
5204+ }
5205+} // End void Get_Version_ID_SLT (void)
5206+
5207+//------------------------------------------------------------
5208+void Get_Capabilities_SLT (void) {//Command:0x16
5209+
5210+ if (NCSI_SentWaitPacket(GET_CAPABILITIES, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0)) {
5211+ FindErr_NCSI(NCSI_LinkFail_Get_Capabilities);
5212+ }
5213+ else {
5214+ NCSI_Cap_SLT.Capabilities_Flags = NCSI_Respond_SLT.Payload_Data[0];
5215+ NCSI_Cap_SLT.Broadcast_Packet_Filter_Capabilities = NCSI_Respond_SLT.Payload_Data[1];
5216+ NCSI_Cap_SLT.Multicast_Packet_Filter_Capabilities = NCSI_Respond_SLT.Payload_Data[2];
5217+ NCSI_Cap_SLT.Buffering_Capabilities = NCSI_Respond_SLT.Payload_Data[3];
5218+ NCSI_Cap_SLT.AEN_Control_Support = NCSI_Respond_SLT.Payload_Data[4];
5219+ }
5220+}
5221+
5222+//------------------------------------------------------------
5223+void Get_Controller_Packet_Statistics (void) {//Command:0x18
5224+
5225+ NCSI_SentWaitPacket(GET_CONTROLLER_PACKET_STATISTICS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0);
5226+}
5227+
5228+//------------------------------------------------------------
5229+char phy_ncsi (void) {
5230+ ULONG Channel_Found = 0;
5231+ ULONG Package_Found = 0;
5232+ ULONG Re_Send;
5233+ ULONG Err_Flag_bak;
5234+ ULONG pkg_idx;
5235+ ULONG chl_idx;
5236+ ULONG Link_Status;
5237+ ULONG NCSI_LinkFail_Val_bak;
5238+
5239+ number_chl = 0;
5240+ number_pak = 0;
5241+
5242+ NCSI_LinkFail_Val = 0;
5243+ #ifdef SLT_DOS
5244+ fprintf(fp_log, "\n\n======> Start:\n" );
5245+ #endif
5246+ NCSI_Struct_Initialize_SLT();
5247+
5248+ #ifdef NCSI_Skip_Phase1_DeSelectPackage
5249+ #else
5250+
5251+ //NCSI Start
5252+ //Disable Channel then DeSelect Package
5253+ for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++) {
5254+ // Ignore error flag in the NCSI command
5255+ Err_Flag_bak = Err_Flag;
5256+ NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val;
5257+ select_flag[pkg_idx] = Select_Package_SLT (pkg_idx); // Command:0x01
5258+ Err_Flag = Err_Flag_bak;
5259+ NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak;
5260+
5261+ if ( select_flag[pkg_idx] == 0 ) {
5262+ NCSI_Cap_SLT.Package_ID = pkg_idx;
5263+
5264+ for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ ) {
5265+ NCSI_Cap_SLT.Channel_ID = chl_idx;
5266+ // Ignore error flag in the NCSI command
5267+ Err_Flag_bak = Err_Flag;
5268+ NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val;
5269+ Disable_Channel_SLT(); // Command: 0x04
5270+ Err_Flag = Err_Flag_bak;
5271+ NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak;
5272+ }
5273+ #ifdef NCSI_Skip_DeSelectPackage
5274+ #else
5275+ DeSelect_Package_SLT (pkg_idx); // Command:0x02
5276+ #endif
5277+ } // End if ( select_flag[pkg_idx] == 0 )
5278+ } // End for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++)
5279+ #endif
5280+
5281+ //Select Package
5282+ for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++) {
5283+ #ifdef NCSI_Skip_Phase1_DeSelectPackage
5284+ // Ignore error flag in the NCSI command
5285+ Err_Flag_bak = Err_Flag;
5286+ NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val;
5287+ select_flag[pkg_idx] = Select_Package_SLT (pkg_idx);//Command:0x01
5288+ Err_Flag = Err_Flag_bak;
5289+ NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak;
5290+ #endif
5291+
5292+ if (select_flag[pkg_idx] == 0) {
5293+ //NCSI_RxTimeOutScale = 1000;
5294+ NCSI_RxTimeOutScale = 10;
5295+ number_pak++;
5296+ Package_Found = 1;
5297+ NCSI_Cap_SLT.Package_ID = pkg_idx;
5298+
5299+ if ( !(IOTiming||IOTimingBund) )
5300+ printf ("====Find Package ID: %d\n", NCSI_Cap_SLT.Package_ID);
5301+ #ifdef SLT_DOS
5302+ fprintf(fp_log, "====Find Package ID: %d\n", NCSI_Cap_SLT.Package_ID);
5303+ #endif
5304+
5305+ #ifdef NCSI_Skip_Phase1_DeSelectPackage
5306+ #else
5307+ Select_Package_SLT (pkg_idx);//Command:0x01
5308+ #endif
5309+
5310+ // Scan all channel in the package
5311+ for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ ) {
5312+ // backup error flag
5313+ Err_Flag_bak = Err_Flag;
5314+ NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val;
5315+ if (Clear_Initial_State_SLT(chl_idx) == 0) { //Command:0x00
5316+ number_chl++;
5317+ Channel_Found = 1;
5318+ NCSI_Cap_SLT.Channel_ID = chl_idx;
5319+
5320+ if ( !(IOTiming || IOTimingBund) )
5321+ printf ("--------Find Channel ID: %d\n", NCSI_Cap_SLT.Channel_ID);
5322+
5323+ #ifdef SLT_DOS
5324+ fprintf(fp_log, "--------Find Channel ID: %d\n", NCSI_Cap_SLT.Channel_ID);
5325+ #endif
5326+ // Get Version and Capabilities
5327+ Get_Version_ID_SLT(); //Command:0x15
5328+ Get_Capabilities_SLT(); //Command:0x16
5329+ Select_Active_Package_SLT(); //Command:0x01
5330+ Enable_Set_MAC_Address_SLT(); //Command:0x0e
5331+ Enable_Broadcast_Filter_SLT(); //Command:0x10
5332+
5333+ // Enable TX
5334+ Enable_Network_TX_SLT(); //Command:0x06
5335+
5336+ // Enable Channel
5337+ Enable_Channel_SLT(); //Command:0x03
5338+
5339+ // Get Link Status
5340+ Re_Send = 0;
5341+ do {
5342+ #ifdef NCSI_EnableDelay_GetLinkStatus
5343+ if ( Re_Send >= 2 )
5344+ delay(Delay_GetLinkStatus);
5345+ #endif
5346+
5347+ Link_Status = Get_Link_Status_SLT();//Command:0x0a
5348+
5349+ if ( Link_Status == LINK_UP ) {
5350+ if (!(IOTiming||IOTimingBund))
5351+ printf (" This Channel is LINK_UP\n");
5352+
5353+ #ifdef SLT_DOS
5354+ fprintf(fp_log, " This Channel is LINK_UP\n");
5355+ #endif
5356+
5357+ NCSI_ARP ();
5358+
5359+ break;
5360+ }
5361+ else if ( Link_Status == LINK_DOWN ) {
5362+ if ( Re_Send >= 2 ) {
5363+ if ( !(IOTiming || IOTimingBund) )
5364+ printf (" This Channel is LINK_DOWN\n");
5365+
5366+ #ifdef SLT_DOS
5367+ fprintf(fp_log, " This Channel is LINK_DOWN\n");
5368+ #endif
5369+
5370+ break;
5371+ }
5372+ } // End if ( Link_Status == LINK_UP )
5373+ } while ( Re_Send++ <= 2 );
5374+
5375+ #ifdef NCSI_Skip_DiSChannel
5376+ #else
5377+ if ( NCSI_DiSChannel ) {
5378+ // Disable TX
5379+ Disable_Network_TX_SLT(); //Command:0x07
5380+ // Disable Channel
5381+ Disable_Channel_SLT(); //Command:0x04
5382+ }
5383+ #endif
5384+ }
5385+ else {
5386+ Err_Flag = Err_Flag_bak;
5387+ NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak;
5388+ }
5389+ } // End for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ )
5390+
5391+ #ifdef NCSI_Skip_DeSelectPackage
5392+ #else
5393+ DeSelect_Package_SLT (pkg_idx);//Command:0x02
5394+ #endif
5395+ NCSI_RxTimeOutScale = 1;
5396+ }
5397+ else {
5398+ if (!(IOTiming||IOTimingBund)) {
5399+ printf ("====Absence of Package ID: %ld\n", pkg_idx);
5400+ #ifdef SLT_DOS
5401+ fprintf(fp_log, "====Absence of Package ID: %ld\n", pkg_idx);
5402+ #endif
5403+ }
5404+ } // End if (select_flag[pkg_idx] == 0)
5405+ } // End for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++)
5406+
5407+ if ( !Package_Found ) FindErr( Err_NCSI_No_PHY );
5408+ if ( ChannelTolNum != number_chl ) FindErr( Err_NCSI_Channel_Num );
5409+ if ( PackageTolNum != number_pak ) FindErr( Err_NCSI_Package_Num );
5410+// if ( !Channel_Found) FindErr();
5411+
5412+ if ( Err_Flag )
5413+ return(1);
5414+ else
5415+ return(0);
5416+}
5417+
5418diff --git a/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c b/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c
5419new file mode 100644
5420index 0000000..77aac47
5421--- /dev/null
5422+++ b/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c
5423@@ -0,0 +1,83 @@
5424+/*
5425+ * This program is distributed in the hope that it will be useful,
5426+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5427+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5428+ * GNU General Public License for more details.
5429+ *
5430+ * You should have received a copy of the GNU General Public License
5431+ * along with this program; if not, write to the Free Software
5432+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5433+ */
5434+#define PCI_SPI_C
5435+static const char ThisFile[] = "PCI_SPI.c";
5436+
5437+#include "SWFUNC.H"
5438+
5439+#ifdef SLT_UBOOT
5440+ #include <common.h>
5441+ #include <command.h>
5442+#endif
5443+#ifdef SLT_DOS
5444+ #include <stdio.h>
5445+ #include <stdlib.h>
5446+ #include <conio.h>
5447+ #include <string.h>
5448+ #include <dos.h>
5449+#endif
5450+
5451+#include "DEF_SPI.H"
5452+#include "LIB.H"
5453+#include "TYPEDEF.H"
5454+
5455+#ifdef SPI_BUS
5456+ULONG GetPCIInfo (DEVICE_PCI_INFO *VGAPCIInfo)
5457+{
5458+ ULONG ulPCIBaseAddress, MMIOBaseAddress, LinearAddressBase, busnum, data;
5459+
5460+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, ACTIVE);
5461+ busnum = 0;
5462+ while (ulPCIBaseAddress == 0 && busnum < 256) {
5463+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, busnum);
5464+ if (ulPCIBaseAddress == 0) {
5465+ ulPCIBaseAddress = FindPCIDevice (0x1688, 0x2000, busnum);
5466+ }
5467+ if (ulPCIBaseAddress == 0) {
5468+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x1160, busnum);
5469+ }
5470+ if (ulPCIBaseAddress == 0) {
5471+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x1180, busnum);
5472+ }
5473+ busnum++;
5474+ }
5475+ printf ("ulPCIBaseAddress = %lx\n", ulPCIBaseAddress);
5476+ if (ulPCIBaseAddress != 0) {
5477+ VGAPCIInfo->ulPCIConfigurationBaseAddress = ulPCIBaseAddress;
5478+ VGAPCIInfo->usVendorID = ReadPCIReg(ulPCIBaseAddress, 0, 0xFFFF);
5479+ VGAPCIInfo->usDeviceID = ReadPCIReg(ulPCIBaseAddress, 0, 0xFFFF0000) >> 16;
5480+ LinearAddressBase = ReadPCIReg (ulPCIBaseAddress, 0x10, 0xFFFFFFF0);
5481+ VGAPCIInfo->ulPhysicalBaseAddress = MapPhysicalToLinear (LinearAddressBase, 64 * 1024 * 1024 + 0x200000);
5482+ MMIOBaseAddress = ReadPCIReg (ulPCIBaseAddress, 0x14, 0xFFFF0000);
5483+ VGAPCIInfo->ulMMIOBaseAddress = MapPhysicalToLinear (MMIOBaseAddress, 64 * 1024 * 1024);
5484+ VGAPCIInfo->usRelocateIO = ReadPCIReg (ulPCIBaseAddress, 0x18, 0x0000FF80);
5485+ OUTDWPORT(0xcf8, ulPCIBaseAddress + 0x4);
5486+ data = INDWPORT(0xcfc);
5487+ OUTDWPORT(0xcfc, data | 0x3);
5488+ return TRUE;
5489+ }
5490+ else {
5491+ return FALSE;
5492+ }
5493+} // End ULONG GetPCIInfo (DEVICE_PCI_INFO *VGAPCIInfo)
5494+
5495+BOOLEAN GetDevicePCIInfo (VIDEO_ENGINE_INFO *VideoEngineInfo)
5496+{
5497+ if (GetPCIInfo (&VideoEngineInfo->VGAPCIInfo) == TRUE) {
5498+ return TRUE;
5499+ }
5500+ else {
5501+ printf("Can not find PCI device!\n");
5502+ exit(0);
5503+ return FALSE;
5504+ }
5505+} // End
5506+#endif // End ifdef SPI_BUS
5507diff --git a/arch/arm/cpu/arm926ejs/aspeed/PHY.H b/arch/arm/cpu/arm926ejs/aspeed/PHY.H
5508new file mode 100644
5509index 0000000..81d9470
5510--- /dev/null
5511+++ b/arch/arm/cpu/arm926ejs/aspeed/PHY.H
5512@@ -0,0 +1,56 @@
5513+/*
5514+ * This program is distributed in the hope that it will be useful,
5515+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5516+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5517+ * GNU General Public License for more details.
5518+ *
5519+ * You should have received a copy of the GNU General Public License
5520+ * along with this program; if not, write to the Free Software
5521+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5522+ */
5523+#ifndef PHY_H
5524+#define PHY_H
5525+
5526+//
5527+// Define
5528+//
5529+#define Enable_SearchPHYID //[ON] (Search vlid PHY ID)
5530+#define Enable_CheckZeroPHYID //[ON] (Check PHY ID with value 0)
5531+
5532+#ifdef Enable_CheckZeroPHYID
5533+ #define PHY_IS_VALID( dat ) ( ( (dat & 0xffff) != 0xffff ) && ( ( dat & 0xffff ) != 0x0 ) )
5534+#else
5535+ #define PHY_IS_VALID( dat ) ( ( dat & 0xffff) != 0xffff )
5536+#endif
5537+
5538+// Define PHY basic register
5539+#define PHY_REG_BMCR 0x00 // Basic Mode Control Register
5540+#define PHY_REG_BMSR 0x01 // Basic Mode Status Register
5541+#define PHY_REG_ID_1 0x02
5542+#define PHY_REG_ID_2 0x03
5543+#define PHY_ANER 0x06 // Auto-negotiation Expansion Register
5544+#define PHY_GBCR 0x09 // 1000Base-T Control Register
5545+#define PHY_SR 0x11 // PHY Specific Status Register
5546+#define PHY_INER 0x12 // Interrupt Enable Register
5547+
5548+#define TIME_OUT_PHY_RW 10000
5549+#define TIME_OUT_PHY_Rst 10000
5550+
5551+#define PHYID3_Mask 0xfc00 //0xffc0
5552+
5553+/* --- Note for SettingPHY chip ---
5554+void phy_xxxx (int loop_phy) {
5555+
5556+ if ( BurstEnable ) {
5557+ // IEEE test
5558+ }
5559+ else if (loop_phy) {
5560+ // Internal loop back
5561+ }
5562+ else {
5563+ // external loop back
5564+ }
5565+}
5566+----------------------------------- */
5567+
5568+#endif // PHY_H
5569diff --git a/arch/arm/cpu/arm926ejs/aspeed/PHY.c b/arch/arm/cpu/arm926ejs/aspeed/PHY.c
5570new file mode 100644
5571index 0000000..6afed9d
5572--- /dev/null
5573+++ b/arch/arm/cpu/arm926ejs/aspeed/PHY.c
5574@@ -0,0 +1,1541 @@
5575+/*
5576+ * This program is distributed in the hope that it will be useful,
5577+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5578+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5579+ * GNU General Public License for more details.
5580+ *
5581+ * You should have received a copy of the GNU General Public License
5582+ * along with this program; if not, write to the Free Software
5583+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5584+ */
5585+#define PHY_C
5586+static const char ThisFile[] = "PHY.c";
5587+
5588+#include "SWFUNC.H"
5589+
5590+#ifdef SLT_UBOOT
5591+ #include <common.h>
5592+ #include <command.h>
5593+ #include <COMMINF.H>
5594+ #include "STDUBOOT.H"
5595+#endif
5596+#ifdef SLT_DOS
5597+ #include <stdio.h>
5598+ #include <stdlib.h>
5599+ #include <conio.h>
5600+ #include <string.h>
5601+ #include "COMMINF.H"
5602+#endif
5603+
5604+#include "PHY.H"
5605+#include "TYPEDEF.H"
5606+#include "IO.H"
5607+
5608+ULONG PHY_09h;
5609+ULONG PHY_18h;
5610+ULONG PHY_1fh;
5611+ULONG PHY_06hA[7];
5612+ULONG PHY_11h;
5613+ULONG PHY_12h;
5614+ULONG PHY_15h;
5615+ULONG PHY_06h;
5616+char PHYID[256];
5617+ULONG PHY_00h;
5618+
5619+//------------------------------------------------------------
5620+// PHY R/W basic
5621+//------------------------------------------------------------
5622+void phy_write (int adr, ULONG data) {
5623+ int timeout = 0;
5624+
5625+ if (AST2300_NewMDIO) {
5626+ WriteSOC_DD( MAC_PHYBASE + 0x60, ( data << 16 ) | MAC_PHYWr_New | (PHY_ADR<<5) | (adr & 0x1f));
5627+
5628+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYBusy_New ) {
5629+ if ( ++timeout > TIME_OUT_PHY_RW ) {
5630+ if (!BurstEnable)
5631+#ifdef SLT_DOS
5632+ fprintf(fp_log, "[PHY-Write] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
5633+#endif
5634+ FindErr( Err_PHY_TimeOut );
5635+ break;
5636+ }
5637+ }
5638+ }
5639+ else {
5640+ WriteSOC_DD( MAC_PHYBASE + 0x64, data );
5641+
5642+ WriteSOC_DD( MAC_PHYBASE + 0x60, MDC_Thres | MAC_PHYWr | (PHY_ADR<<16) | ((adr & 0x1f) << 21));
5643+
5644+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYWr ) {
5645+ if ( ++timeout > TIME_OUT_PHY_RW ) {
5646+#ifdef SLT_DOS
5647+ if (!BurstEnable)
5648+ fprintf(fp_log, "[PHY-Write] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
5649+#endif
5650+ FindErr( Err_PHY_TimeOut );
5651+ break;
5652+ }
5653+ }
5654+ } // End if (AST2300_NewMDIO)
5655+
5656+ if ( DbgPrn_PHYRW )
5657+ printf ("[Wr ]%02d: %04lx\n", adr, data);
5658+} // End void phy_write (int adr, ULONG data)
5659+
5660+//------------------------------------------------------------
5661+ULONG phy_read (int adr) {
5662+ int timeout = 0;
5663+
5664+ if ( AST2300_NewMDIO ) {
5665+ WriteSOC_DD( MAC_PHYBASE + 0x60, MAC_PHYRd_New | (PHY_ADR << 5) | ( adr & 0x1f ) );
5666+
5667+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYBusy_New ) {
5668+ if ( ++timeout > TIME_OUT_PHY_RW ) {
5669+ if ( !BurstEnable )
5670+#ifdef SLT_DOS
5671+ fprintf(fp_log, "[PHY-Read] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ));
5672+#endif
5673+ FindErr( Err_PHY_TimeOut );
5674+ break;
5675+ }
5676+ }
5677+
5678+ DELAY(Delay_PHYRd);
5679+ Dat_ULONG = ReadSOC_DD( MAC_PHYBASE + 0x64 ) & 0xffff;
5680+ }
5681+ else {
5682+ WriteSOC_DD( MAC_PHYBASE + 0x60, MDC_Thres | MAC_PHYRd | (PHY_ADR << 16) | ((adr & 0x1f) << 21) );
5683+
5684+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYRd ) {
5685+ if ( ++timeout > TIME_OUT_PHY_RW ) {
5686+#ifdef SLT_DOS
5687+ if ( !BurstEnable )
5688+ fprintf( fp_log, "[PHY-Read] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
5689+#endif
5690+ FindErr( Err_PHY_TimeOut );
5691+ break;
5692+ }
5693+ }
5694+
5695+ DELAY( Delay_PHYRd );
5696+ Dat_ULONG = ReadSOC_DD( MAC_PHYBASE + 0x64 ) >> 16;
5697+ }
5698+
5699+ if ( DbgPrn_PHYRW )
5700+ printf ("[Rd ]%02d: %04lx\n", adr, Dat_ULONG );
5701+
5702+ return( Dat_ULONG );
5703+} // End ULONG phy_read (int adr)
5704+
5705+//------------------------------------------------------------
5706+void phy_Read_Write (int adr, ULONG clr_mask, ULONG set_mask) {
5707+ if ( DbgPrn_PHYRW )
5708+ printf ("[RW ]%02d: clr:%04lx: set:%04lx\n", adr, clr_mask, set_mask);
5709+ phy_write(adr, ((phy_read(adr) & (~clr_mask)) | set_mask));
5710+}
5711+
5712+//------------------------------------------------------------
5713+void phy_out ( int adr ) {
5714+ printf ("%02d: %04lx\n", adr, phy_read(adr));
5715+}
5716+
5717+//------------------------------------------------------------
5718+//void phy_outchg ( int adr ) {
5719+// ULONG PHY_valold = 0;
5720+// ULONG PHY_val;
5721+//
5722+// while (1) {
5723+// PHY_val = phy_read(adr);
5724+// if (PHY_valold != PHY_val) {
5725+// printf ("%02d: %04lx\n", adr, PHY_val);
5726+// PHY_valold = PHY_val;
5727+// }
5728+// }
5729+//}
5730+
5731+//------------------------------------------------------------
5732+void phy_dump (char *name) {
5733+ int index;
5734+
5735+ printf ("[%s][%d]----------------\n", name, PHY_ADR);
5736+ for (index = 0; index < 32; index++) {
5737+ printf ("%02d: %04lx ", index, phy_read(index));
5738+
5739+ if ((index % 8) == 7)
5740+ printf ("\n");
5741+ }
5742+}
5743+
5744+//------------------------------------------------------------
5745+void phy_id (BYTE option) {
5746+
5747+ ULONG reg_adr;
5748+ CHAR PHY_ADR_org;
5749+ FILE_VAR
5750+
5751+ GET_OBJ( option )
5752+
5753+ PHY_ADR_org = PHY_ADR;
5754+ for (PHY_ADR = 0; PHY_ADR < 32; PHY_ADR++) {
5755+
5756+ PRINT(OUT_OBJ "[%02d] ", PHY_ADR);
5757+
5758+ for (reg_adr = 2; reg_adr <= 3; reg_adr++)
5759+ PRINT(OUT_OBJ "%ld:%04lx ", reg_adr, phy_read(reg_adr));
5760+
5761+ if ((PHY_ADR % 4) == 3)
5762+ PRINT(OUT_OBJ "\n");
5763+ }
5764+ PHY_ADR = PHY_ADR_org;
5765+}
5766+
5767+
5768+//------------------------------------------------------------
5769+void phy_delay (int dt) {
5770+ DELAY( dt );
5771+}
5772+
5773+//------------------------------------------------------------
5774+// PHY IC
5775+//------------------------------------------------------------
5776+void phy_basic_setting (int loop_phy) {
5777+ phy_Read_Write(0, 0x7140, PHY_00h); //clr set
5778+ if ( DbgPrn_PHYRW )
5779+ printf ("[Set]00: %04lx\n", phy_read( PHY_REG_BMCR ));
5780+}
5781+
5782+//------------------------------------------------------------
5783+void phy_Wait_Reset_Done (void) {
5784+ int timeout = 0;
5785+
5786+ while ( phy_read( PHY_REG_BMCR ) & 0x8000 ) {
5787+ if (DbgPrn_PHYRW)
5788+ printf ("00: %04lx\n", phy_read( PHY_REG_BMCR ));
5789+
5790+ if (++timeout > TIME_OUT_PHY_Rst) {
5791+#ifdef SLT_DOS
5792+ if (!BurstEnable) fprintf(fp_log, "[PHY-Reset] Time out: %08lx\n", ReadSOC_DD(MAC_PHYBASE+0x60));
5793+#endif
5794+ FindErr(Err_PHY_TimeOut);
5795+ break;
5796+ }
5797+ }//wait Rst Done
5798+
5799+ if (DbgPrn_PHYRW) printf ("[Clr]00: %04lx\n", phy_read( PHY_REG_BMCR ));
5800+ DELAY(Delay_PHYRst);
5801+}
5802+
5803+//------------------------------------------------------------
5804+void phy_Reset (int loop_phy) {
5805+ phy_basic_setting(loop_phy);
5806+
5807+ phy_Read_Write(0, 0x0000, 0x8000 | PHY_00h);//clr set//Rst PHY
5808+ phy_Wait_Reset_Done();
5809+
5810+ phy_basic_setting(loop_phy);
5811+ DELAY(Delay_PHYRst);
5812+}
5813+
5814+//------------------------------------------------------------
5815+void recov_phy_marvell (int loop_phy) {//88E1111
5816+ if ( BurstEnable ) {
5817+ }
5818+ else if ( loop_phy ) {
5819+ }
5820+ else {
5821+ if (GSpeed_sel[0]) {
5822+ phy_write(9, PHY_09h);
5823+
5824+ phy_Reset(loop_phy);
5825+
5826+ phy_write(29, 0x0007);
5827+ phy_Read_Write(30, 0x0008, 0x0000);//clr set
5828+ phy_write(29, 0x0010);
5829+ phy_Read_Write(30, 0x0002, 0x0000);//clr set
5830+ phy_write(29, 0x0012);
5831+ phy_Read_Write(30, 0x0001, 0x0000);//clr set
5832+
5833+ phy_write(18, PHY_12h);
5834+ }
5835+ }
5836+}
5837+
5838+//------------------------------------------------------------
5839+void phy_marvell (int loop_phy) {//88E1111
5840+ int Retry;
5841+
5842+ if ( DbgPrn_PHYName )
5843+ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
5844+
5845+ if ( BurstEnable ) {
5846+ phy_Reset(loop_phy);
5847+ }
5848+ else if ( loop_phy ) {
5849+ phy_Reset(loop_phy);
5850+ }
5851+ else {
5852+ if ( GSpeed_sel[0] ) {
5853+ PHY_09h = phy_read( PHY_GBCR );
5854+ PHY_12h = phy_read( PHY_INER );
5855+ phy_write ( 18, 0x0000 );
5856+ phy_Read_Write( 9, 0x0000, 0x1800 );//clr set
5857+ }
5858+
5859+ phy_Reset(loop_phy);
5860+
5861+ if (GSpeed_sel[0]) {
5862+ phy_write ( 29, 0x0007 );
5863+ phy_Read_Write( 30, 0x0000, 0x0008 );//clr set
5864+ phy_write ( 29, 0x0010 );
5865+ phy_Read_Write( 30, 0x0000, 0x0002 );//clr set
5866+ phy_write ( 29, 0x0012 );
5867+ phy_Read_Write( 30, 0x0000, 0x0001 );//clr set
5868+ }
5869+ }
5870+
5871+ Retry = 0;
5872+ do {
5873+ PHY_11h = phy_read( PHY_SR );
5874+ } while ( !( ( PHY_11h & 0x0400 ) | loop_phy | ( Retry++ > 20 ) ) );
5875+}
5876+
5877+//------------------------------------------------------------
5878+void recov_phy_marvell0 (int loop_phy) {//88E1310
5879+ if (BurstEnable) {
5880+ } else if (loop_phy) {
5881+ } else {
5882+ if (GSpeed_sel[0]) {
5883+ phy_write(22, 0x0006);
5884+ phy_Read_Write(16, 0x0020, 0x0000);//clr set
5885+ phy_write(22, 0x0000);
5886+ }
5887+ }
5888+}
5889+
5890+//------------------------------------------------------------
5891+void phy_marvell0 (int loop_phy) {//88E1310
5892+ int Retry;
5893+
5894+ if (DbgPrn_PHYName)
5895+ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
5896+
5897+ phy_write( 22, 0x0002 );
5898+
5899+ PHY_15h = phy_read(21);
5900+ if (PHY_15h & 0x0030) {
5901+ printf ("\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
5902+#ifdef SLT_DOS
5903+ if ( IOTiming )
5904+ fprintf (fp_io, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
5905+ if ( !BurstEnable)
5906+ fprintf (fp_log, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
5907+#endif
5908+// phy_Read_Write(21, 0x0030, 0x0000);//clr set//[5]Rx Dly, [4]Tx Dly
5909+ phy_write(21, PHY_15h & 0xffcf); // Set [5]Rx Dly, [4]Tx Dly to 0
5910+ }
5911+ phy_write(22, 0x0000);
5912+
5913+ if ( BurstEnable ) {
5914+ phy_Reset(loop_phy);
5915+ }
5916+ else if ( loop_phy ) {
5917+ phy_write( 22, 0x0002 );
5918+
5919+ if ( GSpeed_sel[0] ) {
5920+ phy_Read_Write( 21, 0x6040, 0x0040 );//clr set
5921+ }
5922+ else if ( GSpeed_sel[1] ) {
5923+ phy_Read_Write( 21, 0x6040, 0x2000 );//clr set
5924+ }
5925+ else {
5926+ phy_Read_Write( 21, 0x6040, 0x0000 );//clr set
5927+ }
5928+ phy_write( 22, 0x0000 );
5929+ phy_Reset( loop_phy );
5930+ }
5931+ else {
5932+ if ( GSpeed_sel[0] ) {
5933+ phy_write( 22, 0x0006 );
5934+ phy_Read_Write( 16, 0x0000, 0x0020 );//clr set
5935+ phy_write( 22, 0x0000 );
5936+ }
5937+
5938+ phy_Reset(loop_phy);
5939+ }
5940+
5941+ Retry = 0;
5942+ do {
5943+ PHY_11h = phy_read( PHY_SR );
5944+ } while (!((PHY_11h & 0x0400) | loop_phy | (Retry++ > 20)));
5945+}
5946+
5947+//------------------------------------------------------------
5948+void recov_phy_marvell1 (int loop_phy) {//88E6176
5949+ CHAR PHY_ADR_org;
5950+
5951+ PHY_ADR_org = PHY_ADR;
5952+ for ( PHY_ADR = 16; PHY_ADR <= 22; PHY_ADR++ ) {
5953+ if ( BurstEnable ) {
5954+ }
5955+ else {
5956+ phy_write(6, PHY_06hA[PHY_ADR-16]);//06h[5]P5 loopback, 06h[6]P6 loopback
5957+ }
5958+ }
5959+ for ( PHY_ADR = 21; PHY_ADR <= 22; PHY_ADR++ ) {
5960+ phy_write(1, 0x3); //01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
5961+ }
5962+ PHY_ADR = PHY_ADR_org;
5963+}
5964+
5965+//------------------------------------------------------------
5966+void phy_marvell1 (int loop_phy) {//88E6176
5967+// ULONG PHY_01h;
5968+ CHAR PHY_ADR_org;
5969+
5970+ if (DbgPrn_PHYName)
5971+ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
5972+
5973+ //The 88E6176 is switch with 7 Port(P0~P6) and the PHYAdr will be fixed at 0x10~0x16, and only P5/P6 can be connected to the MAC.
5974+ //Therefor, the 88E6176 only can run the internal loopback.
5975+ PHY_ADR_org = PHY_ADR;
5976+ for ( PHY_ADR = 16; PHY_ADR <= 20; PHY_ADR++ ) {
5977+ if ( BurstEnable ) {
5978+ }
5979+ else {
5980+ PHY_06hA[PHY_ADR-16] = phy_read( PHY_ANER );
5981+ phy_write(6, 0x00);//06h[5]P5 loopback, 06h[6]P6 loopback
5982+ }
5983+ }
5984+
5985+ for ( PHY_ADR = 21; PHY_ADR <= 22; PHY_ADR++ ) {
5986+// PHY_01h = phy_read( PHY_REG_BMSR );
5987+// if (GSpeed_sel[0]) phy_write(1, (PHY_01h & 0xfffc) | 0x2);//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
5988+// else if (GSpeed_sel[1]) phy_write(1, (PHY_01h & 0xfffc) | 0x1);//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
5989+// else phy_write(1, (PHY_01h & 0xfffc) );//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
5990+ if (GSpeed_sel[0]) phy_write(1, 0x2);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
5991+ else if (GSpeed_sel[1]) phy_write(1, 0x1);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
5992+ else phy_write(1, 0x0);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
5993+
5994+ if (BurstEnable) {
5995+ }
5996+ else {
5997+ PHY_06hA[PHY_ADR-16] = phy_read( PHY_ANER );
5998+ if (PHY_ADR == 21) phy_write(6, 0x20);//06h[5]P5 loopback, 06h[6]P6 loopback
5999+ else phy_write(6, 0x40);//06h[5]P5 loopback, 06h[6]P6 loopback
6000+ }
6001+ }
6002+ PHY_ADR = PHY_ADR_org;
6003+}
6004+
6005+//------------------------------------------------------------
6006+void recov_phy_marvell2 (int loop_phy) {//88E1512
6007+ if (BurstEnable) {
6008+ }
6009+ else if (loop_phy) {
6010+ }
6011+ else {
6012+ if (GSpeed_sel[0]) {
6013+ phy_write(22, 0x0006);
6014+ phy_Read_Write(18, 0x0008, 0x0000);//clr set
6015+ phy_write(22, 0x0000);
6016+ }
6017+ }
6018+}
6019+
6020+//------------------------------------------------------------
6021+void phy_marvell2 (int loop_phy) {//88E1512
6022+ int Retry = 0;
6023+ ULONG temp_reg;
6024+
6025+ if ( DbgPrn_PHYName )
6026+ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
6027+
6028+ phy_write(22, 0x0002);
6029+ PHY_15h = phy_read(21);
6030+
6031+ if ( PHY_15h & 0x0030 ) {
6032+ printf ("\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
6033+#ifdef SLT_DOS
6034+ if (IOTiming ) fprintf (fp_io, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
6035+ if (!BurstEnable) fprintf (fp_log, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
6036+#endif
6037+ // phy_Read_Write(21, 0x0030, 0x0000);//clr set//[5]Rx Dly, [4]Tx Dly
6038+// phy_write(21, PHY_15h & 0xffcf);
6039+ }
6040+ phy_write(22, 0x0000);
6041+
6042+ if ( BurstEnable ) {
6043+ phy_Reset(loop_phy);
6044+ }
6045+ else if (loop_phy) {
6046+ // Internal loopback funciton only support in copper mode
6047+ // switch page 18
6048+ phy_write(22, 0x0012);
6049+ // Change mode to Copper mode
6050+ phy_write(20, 0x8210);
6051+ // do software reset
6052+ do {
6053+ temp_reg = phy_read( 20 );
6054+ } while ( ( (temp_reg & 0x8000) == 0x8000 ) & (Retry++ < 20) );
6055+
6056+ // switch page 2
6057+ phy_write(22, 0x0002);
6058+ if (GSpeed_sel[0]) {
6059+ phy_Read_Write(21, 0x2040, 0x0040);//clr set
6060+ }
6061+ else if (GSpeed_sel[1]) {
6062+ phy_Read_Write(21, 0x2040, 0x2000);//clr set
6063+ }
6064+ else {
6065+ phy_Read_Write(21, 0x2040, 0x0000);//clr set
6066+ }
6067+ phy_write(22, 0x0000);
6068+
6069+ phy_Reset(loop_phy);
6070+ }
6071+ else {
6072+ if (GSpeed_sel[0]) {
6073+ phy_write(22, 0x0006);
6074+ phy_Read_Write(18, 0x0000, 0x0008);//clr set
6075+ phy_write(22, 0x0000);
6076+ }
6077+
6078+ phy_Reset(loop_phy);
6079+ }
6080+
6081+ Retry = 0;
6082+ do {
6083+ PHY_11h = phy_read( PHY_SR );
6084+ } while (!((PHY_11h & 0x0400) | loop_phy | (Retry++ > 20)));
6085+}
6086+
6087+//------------------------------------------------------------
6088+void phy_broadcom (int loop_phy) {//BCM5221
6089+ if (DbgPrn_PHYName)
6090+ printf ("--->(%04lx %04lx)[Broadcom] %s\n", PHY_ID2, PHY_ID3, PHYName);
6091+
6092+ phy_Reset(loop_phy);
6093+
6094+ if (IEEETesting) {
6095+ if (IOTimingBund_arg == 0) {
6096+ phy_write(25, 0x1f01);//Force MDI //Measuring from channel A
6097+ }
6098+ else {
6099+ phy_Read_Write(24, 0x0000, 0x4000);//clr set//Force Link
6100+// phy_write( 0, PHY_00h);
6101+// phy_write(30, 0x1000);
6102+ }
6103+ }
6104+}
6105+
6106+//------------------------------------------------------------
6107+void recov_phy_broadcom0 (int loop_phy) {//BCM54612
6108+
6109+ // Need to do it for AST2400
6110+ phy_write(0x1C, 0x8C00); // Disable GTXCLK Clock Delay Enable
6111+ phy_write(0x18, 0xF0E7); // Disable RGMII RXD to RXC Skew
6112+
6113+ if (BurstEnable) {
6114+ }
6115+ else if (loop_phy) {
6116+ phy_write( 0, PHY_00h);
6117+ }
6118+ else {
6119+ phy_write(0x00, PHY_00h);
6120+ phy_write(0x09, PHY_09h);
6121+ phy_write(0x18, PHY_18h);
6122+ }
6123+}
6124+
6125+//------------------------------------------------------------
6126+void phy_broadcom0 (int loop_phy) {//BCM54612
6127+ if ( DbgPrn_PHYName )
6128+ printf ("--->(%04lx %04lx)[Broadcom] %s\n", PHY_ID2, PHY_ID3, PHYName);
6129+
6130+ // Need to do it for AST2400
6131+ phy_write(0x1C, 0x8C00); // Disable GTXCLK Clock Delay Enable
6132+ phy_write(0x18, 0xF0E7); // Disable RGMII RXD to RXC Skew
6133+
6134+ // Backup org value
6135+ // read reg 18H, Page 103, BCM54612EB1KMLG_Spec.pdf
6136+ phy_write(0x18, 0x7007);
6137+ PHY_18h = phy_read(0x18);
6138+
6139+ PHY_00h = phy_read( PHY_REG_BMCR );
6140+ PHY_09h = phy_read( PHY_GBCR );
6141+
6142+ if ( BurstEnable ) {
6143+ phy_basic_setting(loop_phy);
6144+ }
6145+ else if (loop_phy) {
6146+ phy_basic_setting(loop_phy);
6147+
6148+ // Enable Internal Loopback mode
6149+ // Page 58, BCM54612EB1KMLG_Spec.pdf
6150+ phy_write(0x0, 0x5140);
6151+ DELAY(Delay_PHYRst);
6152+ /* Only 1G Test is PASS, 100M and 10M is false @20130619 */
6153+
6154+// Waiting for BCM FAE's response
6155+// if (GSpeed_sel[0]) {
6156+// // Speed 1G
6157+// // Enable Internal Loopback mode
6158+// // Page 58, BCM54612EB1KMLG_Spec.pdf
6159+// phy_write(0x0, 0x5140);
6160+// }
6161+// else if (GSpeed_sel[1]) {
6162+// // Speed 100M
6163+// // Enable Internal Loopback mode
6164+// // Page 58, BCM54612EB1KMLG_Spec.pdf
6165+// phy_write(0x0, 0x7100);
6166+// phy_write(0x1E, 0x1000);
6167+// }
6168+// else if (GSpeed_sel[2]) {
6169+// // Speed 10M
6170+// // Enable Internal Loopback mode
6171+// // Page 58, BCM54612EB1KMLG_Spec.pdf
6172+// phy_write(0x0, 0x5100);
6173+// phy_write(0x1E, 0x1000);
6174+// }
6175+//
6176+// DELAY(Delay_PHYRst);
6177+ }
6178+ else {
6179+
6180+ if (GSpeed_sel[0]) {
6181+ // Page 60, BCM54612EB1KMLG_Spec.pdf
6182+ // need to insert loopback plug
6183+ phy_write( 9, 0x1800);
6184+ phy_write( 0, 0x0140);
6185+ phy_write( 0x18, 0x8400); // Enable Transmit test mode
6186+ } else if (GSpeed_sel[1]) {
6187+ // Page 60, BCM54612EB1KMLG_Spec.pdf
6188+ // need to insert loopback plug
6189+ phy_write( 0, 0x2100);
6190+ phy_write( 0x18, 0x8400); // Enable Transmit test mode
6191+ } else {
6192+ // Page 60, BCM54612EB1KMLG_Spec.pdf
6193+ // need to insert loopback plug
6194+ phy_write( 0, 0x0100);
6195+ phy_write( 0x18, 0x8400); // Enable Transmit test mode
6196+ }
6197+ }
6198+}
6199+
6200+//------------------------------------------------------------
6201+void phy_realtek (int loop_phy) {//RTL8201N
6202+ if ( DbgPrn_PHYName )
6203+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
6204+
6205+ phy_Reset(loop_phy);
6206+}
6207+
6208+//------------------------------------------------------------
6209+//internal loop 100M: Don't support
6210+//internal loop 10M : no loopback stub
6211+void phy_realtek0 (int loop_phy) {//RTL8201E
6212+ if ( DbgPrn_PHYName )
6213+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
6214+
6215+ phy_Reset(loop_phy);
6216+
6217+// phy_Read_Write(25, 0x2800, 0x0000);//clr set
6218+// printf("Enable phy output RMII clock\n");
6219+ if (IEEETesting) {
6220+ phy_write(31, 0x0001);
6221+ if (IOTimingBund_arg == 0) {
6222+ phy_write(25, 0x1f01);//Force MDI //Measuring from channel A
6223+ }
6224+ else {
6225+ phy_write(25, 0x1f00);//Force MDIX //Measuring from channel B
6226+ }
6227+ phy_write(31, 0x0000);
6228+ }
6229+}
6230+
6231+//------------------------------------------------------------
6232+void recov_phy_realtek1 (int loop_phy) {//RTL8211D
6233+ if ( BurstEnable ) {
6234+ if ( IEEETesting ) {
6235+ if ( GSpeed_sel[0] ) {
6236+ if (IOTimingBund_arg == 0) {
6237+ //Test Mode 1
6238+ phy_write( 31, 0x0002 );
6239+ phy_write( 2, 0xc203 );
6240+ phy_write( 31, 0x0000 );
6241+ phy_write( 9, 0x0000 );
6242+ }
6243+ else {
6244+ //Test Mode 4
6245+ phy_write( 31, 0x0000 );
6246+ phy_write( 9, 0x0000 );
6247+ }
6248+
6249+ phy_write( 31, 0x0000 );
6250+ }
6251+ else if ( GSpeed_sel[1] ) {
6252+ phy_write( 23, 0x2100 );
6253+ phy_write( 16, 0x016e );
6254+ }
6255+ else {
6256+// phy_write( 31, 0x0006 );
6257+// phy_write( 0, 0x5a00 );
6258+// phy_write( 31, 0x0000 );
6259+ }
6260+ } // End if ( IEEETesting )
6261+ }
6262+ else if (loop_phy) {
6263+ if ( GSpeed_sel[0] ) {
6264+ phy_write( 31, 0x0000 ); // new in Rev. 1.6
6265+ phy_write( 0, 0x1140 ); // new in Rev. 1.6
6266+ phy_write( 20, 0x8040 ); // new in Rev. 1.6
6267+ }
6268+ }
6269+ else {
6270+ if ( GSpeed_sel[0] ) {
6271+ phy_write( 31, 0x0001 );
6272+ phy_write( 3, 0xdf41 );
6273+ phy_write( 2, 0xdf20 );
6274+ phy_write( 1, 0x0140 );
6275+ phy_write( 0, 0x00bb );
6276+ phy_write( 4, 0xb800 );
6277+ phy_write( 4, 0xb000 );
6278+
6279+ phy_write( 31, 0x0000 );
6280+// phy_write( 26, 0x0020 ); // Rev. 1.2
6281+ phy_write( 26, 0x0040 ); // new in Rev. 1.6
6282+ phy_write( 0, 0x1140 );
6283+// phy_write( 21, 0x0006 ); // Rev. 1.2
6284+ phy_write( 21, 0x1006 ); // new in Rev. 1.6
6285+ phy_write( 23, 0x2100 );
6286+// } else if ( GSpeed_sel[1] ) {//option
6287+// phy_write( 31, 0x0000 );
6288+// phy_write( 9, 0x0200 );
6289+// phy_write( 0, 0x1200 );
6290+// } else if ( GSpeed_sel[2] ) {//option
6291+// phy_write( 31, 0x0000 );
6292+// phy_write( 9, 0x0200 );
6293+// phy_write( 4, 0x05e1 );
6294+// phy_write( 0, 0x1200 );
6295+ }
6296+ } // End if ( BurstEnable )
6297+} // End void recov_phy_realtek1 (int loop_phy)
6298+
6299+//------------------------------------------------------------
6300+//internal loop 1G : no loopback stub
6301+//internal loop 100M: no loopback stub
6302+//internal loop 10M : no loopback stub
6303+void phy_realtek1 (int loop_phy) {//RTL8211D
6304+ if ( DbgPrn_PHYName )
6305+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
6306+
6307+ if ( BurstEnable ) {
6308+ if ( IEEETesting ) {
6309+ if ( GSpeed_sel[0] ) {
6310+ if (IOTimingBund_arg == 0) {
6311+ //Test Mode 1
6312+ phy_write( 31, 0x0002 );
6313+ phy_write( 2, 0xc22b );
6314+ phy_write( 31, 0x0000 );
6315+ phy_write( 9, 0x2000 );
6316+ }
6317+ else {
6318+ //Test Mode 4
6319+ phy_write( 31, 0x0000 );
6320+ phy_write( 9, 0x8000 );
6321+ }
6322+ phy_write( 31, 0x0000 );
6323+ }
6324+ else if ( GSpeed_sel[1] ) {
6325+ if ( IOTimingBund_arg == 0 ) {
6326+ //From Channel A
6327+ phy_write( 23, 0xa102 );
6328+ phy_write( 16, 0x01ae );//MDI
6329+ }
6330+ else {
6331+ //From Channel B
6332+ phy_Read_Write( 17, 0x0008, 0x0000 ); // clr set
6333+ phy_write( 23, 0xa102 ); // MDI
6334+ phy_write( 16, 0x010e );
6335+ }
6336+ } else {
6337+// if ( IOTimingBund_arg == 0 ) {//Pseudo-random pattern
6338+// phy_write( 31, 0x0006 );
6339+// phy_write( 0, 0x5a21 );
6340+// phy_write( 31, 0x0000 );
6341+// }
6342+// else if ( IOTimingBund_arg == 1 ) {//¡§FF¡¨ pattern
6343+// phy_write( 31, 0x0006 );
6344+// phy_write( 2, 0x05ee );
6345+// phy_write( 0, 0xff21 );
6346+// phy_write( 31, 0x0000 );
6347+// } else {//¡§00¡¨ pattern
6348+// phy_write( 31, 0x0006 );
6349+// phy_write( 2, 0x05ee );
6350+// phy_write( 0, 0x0021 );
6351+// phy_write( 31, 0x0000 );
6352+// }
6353+ }
6354+ }
6355+ else {
6356+ phy_Reset(loop_phy);
6357+ }
6358+ }
6359+ else if ( loop_phy ) {
6360+ phy_Reset(loop_phy);
6361+
6362+ if ( GSpeed_sel[0] ) {
6363+ phy_write(20, 0x0042);//new in Rev. 1.6
6364+ }
6365+ }
6366+ else {
6367+ if ( GSpeed_sel[0] ) {
6368+ phy_write( 31, 0x0001 );
6369+ phy_write( 3, 0xff41 );
6370+ phy_write( 2, 0xd720 );
6371+ phy_write( 1, 0x0140 );
6372+ phy_write( 0, 0x00bb );
6373+ phy_write( 4, 0xb800 );
6374+ phy_write( 4, 0xb000 );
6375+
6376+ phy_write( 31, 0x0007 );
6377+ phy_write( 30, 0x0040 );
6378+ phy_write( 24, 0x0008 );
6379+
6380+ phy_write( 31, 0x0000 );
6381+ phy_write( 9, 0x0300 );
6382+ phy_write( 26, 0x0020 );
6383+ phy_write( 0, 0x0140 );
6384+ phy_write( 23, 0xa101 );
6385+ phy_write( 21, 0x0200 );
6386+ phy_write( 23, 0xa121 );
6387+ phy_write( 23, 0xa161 );
6388+ phy_write( 0, 0x8000 );
6389+ phy_Wait_Reset_Done();
6390+ phy_delay(200); // new in Rev. 1.6
6391+// }
6392+// else if ( GSpeed_sel[1] ) {//option
6393+// phy_write( 31, 0x0000 );
6394+// phy_write( 9, 0x0000 );
6395+// phy_write( 4, 0x0061 );
6396+// phy_write( 0, 0x1200 );
6397+// phy_delay(5000);
6398+// }
6399+// else if (GSpeed_sel[2]) {//option
6400+// phy_write( 31, 0x0000 );
6401+// phy_write( 9, 0x0000 );
6402+// phy_write( 4, 0x05e1 );
6403+// phy_write( 0, 0x1200 );
6404+// phy_delay(5000);
6405+ }
6406+ else {
6407+ phy_Reset(loop_phy);
6408+ }
6409+ }
6410+} // End void phy_realtek1 (int loop_phy)
6411+
6412+//------------------------------------------------------------
6413+void recov_phy_realtek2 (int loop_phy) {//RTL8211E
6414+ if ( BurstEnable ) {
6415+ if ( IEEETesting ) {
6416+ phy_write( 31, 0x0005 );
6417+ phy_write( 5, 0x8b86 );
6418+ phy_write( 6, 0xe201 );
6419+ phy_write( 31, 0x0007 );
6420+ phy_write( 30, 0x0020 );
6421+ phy_write( 21, 0x1108 );
6422+ phy_write( 31, 0x0000 );
6423+
6424+ if ( GSpeed_sel[0] ) {
6425+ phy_write( 31, 0x0000 );
6426+ phy_write( 9, 0x0000 );
6427+ }
6428+ else if ( GSpeed_sel[1] ) {
6429+ phy_write( 31, 0x0007 );
6430+ phy_write( 30, 0x002f );
6431+ phy_write( 23, 0xd88f );
6432+ phy_write( 30, 0x002d );
6433+ phy_write( 24, 0xf050 );
6434+ phy_write( 31, 0x0000 );
6435+ phy_write( 16, 0x006e );
6436+ }
6437+ else {
6438+ }
6439+ }
6440+ else {
6441+ }
6442+ }
6443+ else if (loop_phy) {
6444+ }
6445+ else {
6446+ if (GSpeed_sel[0]) {
6447+ //Rev 1.5 //not stable
6448+// phy_write( 31, 0x0000 );
6449+// phy_write( 0, 0x8000 );
6450+// phy_Wait_Reset_Done();
6451+// phy_delay(30);
6452+// phy_write( 23, 0x2160 );
6453+// phy_write( 31, 0x0007 );
6454+// phy_write( 30, 0x0040 );
6455+// phy_write( 24, 0x0004 );
6456+// phy_write( 24, 0x1a24 );
6457+// phy_write( 25, 0xfd00 );
6458+// phy_write( 24, 0x0000 );
6459+// phy_write( 31, 0x0000 );
6460+// phy_write( 0, 0x1140 );
6461+// phy_write( 26, 0x0040 );
6462+// phy_write( 31, 0x0007 );
6463+// phy_write( 30, 0x002f );
6464+// phy_write( 23, 0xd88f );
6465+// phy_write( 30, 0x0023 );
6466+// phy_write( 22, 0x0300 );
6467+// phy_write( 31, 0x0000 );
6468+// phy_write( 21, 0x1006 );
6469+// phy_write( 23, 0x2100 );
6470+/**/
6471+ //Rev 1.6
6472+ phy_write( 31, 0x0000 );
6473+ phy_write( 0, 0x8000 );
6474+ phy_Wait_Reset_Done();
6475+ phy_delay(30);
6476+ phy_write( 31, 0x0007 );
6477+ phy_write( 30, 0x0042 );
6478+ phy_write( 21, 0x0500 );
6479+ phy_write( 31, 0x0000 );
6480+ phy_write( 0, 0x1140 );
6481+ phy_write( 26, 0x0040 );
6482+ phy_write( 31, 0x0007 );
6483+ phy_write( 30, 0x002f );
6484+ phy_write( 23, 0xd88f );
6485+ phy_write( 30, 0x0023 );
6486+ phy_write( 22, 0x0300 );
6487+ phy_write( 31, 0x0000 );
6488+ phy_write( 21, 0x1006 );
6489+ phy_write( 23, 0x2100 );
6490+/**/
6491+// } else if (GSpeed_sel[1]) {//option
6492+// phy_write( 31, 0x0000 );
6493+// phy_write( 9, 0x0200 );
6494+// phy_write( 0, 0x1200 );
6495+// } else if (GSpeed_sel[2]) {//option
6496+// phy_write( 31, 0x0000 );
6497+// phy_write( 9, 0x0200 );
6498+// phy_write( 4, 0x05e1 );
6499+// phy_write( 0, 0x1200 );
6500+ }
6501+ }
6502+} // End void recov_phy_realtek2 (int loop_phy)
6503+
6504+//------------------------------------------------------------
6505+//internal loop 1G : no loopback stub
6506+//internal loop 100M: no loopback stub
6507+//internal loop 10M : no loopback stub
6508+void phy_realtek2 (int loop_phy) {//RTL8211E
6509+
6510+ if ( DbgPrn_PHYName )
6511+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
6512+
6513+ phy_Read_Write( 0, 0x0000, 0x8000 | PHY_00h ); // clr set // Rst PHY
6514+ phy_Wait_Reset_Done();
6515+ phy_delay(30);
6516+
6517+ if ( BurstEnable ) {
6518+ if ( IEEETesting ) {
6519+ phy_write( 31, 0x0005 );
6520+ phy_write( 5, 0x8b86 );
6521+ phy_write( 6, 0xe200 );
6522+ phy_write( 31, 0x0007 );
6523+ phy_write( 30, 0x0020 );
6524+ phy_write( 21, 0x0108 );
6525+ phy_write( 31, 0x0000 );
6526+
6527+ if ( GSpeed_sel[0] ) {
6528+ phy_write( 31, 0x0000 );
6529+
6530+ if ( IOTimingBund_arg == 0 ) {
6531+ phy_write( 9, 0x2000);//Test Mode 1
6532+ }
6533+ else {
6534+ phy_write( 9, 0x8000);//Test Mode 4
6535+ }
6536+ }
6537+ else if ( GSpeed_sel[1] ) {
6538+ phy_write( 31, 0x0007 );
6539+ phy_write( 30, 0x002f );
6540+ phy_write( 23, 0xd818 );
6541+ phy_write( 30, 0x002d );
6542+ phy_write( 24, 0xf060 );
6543+ phy_write( 31, 0x0000 );
6544+
6545+ if ( IOTimingBund_arg == 0 ) {
6546+ phy_write(16, 0x00ae);//From Channel A
6547+ }
6548+ else {
6549+ phy_write(16, 0x008e);//From Channel B
6550+ }
6551+ }
6552+ else {
6553+ }
6554+ }
6555+ else {
6556+ phy_basic_setting(loop_phy);
6557+ phy_delay(30);
6558+ }
6559+ }
6560+ else if (loop_phy) {
6561+ phy_basic_setting(loop_phy);
6562+
6563+ phy_Read_Write(0, 0x0000, 0x8000 | PHY_00h);//clr set//Rst PHY
6564+ phy_Wait_Reset_Done();
6565+ phy_delay(30);
6566+
6567+ phy_basic_setting(loop_phy);
6568+ phy_delay(30);
6569+ }
6570+ else {
6571+ if ( GSpeed_sel[0] ) {
6572+ //Rev 1.5 //not stable
6573+// phy_write( 23, 0x2160 );
6574+// phy_write( 31, 0x0007 );
6575+// phy_write( 30, 0x0040 );
6576+// phy_write( 24, 0x0004 );
6577+// phy_write( 24, 0x1a24 );
6578+// phy_write( 25, 0x7d00 );
6579+// phy_write( 31, 0x0000 );
6580+// phy_write( 23, 0x2100 );
6581+// phy_write( 31, 0x0007 );
6582+// phy_write( 30, 0x0040 );
6583+// phy_write( 24, 0x0000 );
6584+// phy_write( 30, 0x0023 );
6585+// phy_write( 22, 0x0006 );
6586+// phy_write( 31, 0x0000 );
6587+// phy_write( 0, 0x0140 );
6588+// phy_write( 26, 0x0060 );
6589+// phy_write( 31, 0x0007 );
6590+// phy_write( 30, 0x002f );
6591+// phy_write( 23, 0xd820 );
6592+// phy_write( 31, 0x0000 );
6593+// phy_write( 21, 0x0206 );
6594+// phy_write( 23, 0x2120 );
6595+// phy_write( 23, 0x2160 );
6596+/**/
6597+ //Rev 1.6
6598+ phy_write( 31, 0x0007 );
6599+ phy_write( 30, 0x0042 );
6600+ phy_write( 21, 0x2500 );
6601+ phy_write( 30, 0x0023 );
6602+ phy_write( 22, 0x0006 );
6603+ phy_write( 31, 0x0000 );
6604+ phy_write( 0, 0x0140 );
6605+ phy_write( 26, 0x0060 );
6606+ phy_write( 31, 0x0007 );
6607+ phy_write( 30, 0x002f );
6608+ phy_write( 23, 0xd820 );
6609+ phy_write( 31, 0x0000 );
6610+ phy_write( 21, 0x0206 );
6611+ phy_write( 23, 0x2120 );
6612+ phy_write( 23, 0x2160 );
6613+ phy_delay(300);
6614+/**/
6615+// }
6616+// else if ( GSpeed_sel[1] ) {//option
6617+// phy_write( 31, 0x0000 );
6618+// phy_write( 9, 0x0000 );
6619+// phy_write( 4, 0x0061 );
6620+// phy_write( 0, 0x1200 );
6621+// phy_delay(5000);
6622+// }
6623+// else if ( GSpeed_sel[2] ) {//option
6624+// phy_write( 31, 0x0000 );
6625+// phy_write( 9, 0x0000 );
6626+// phy_write( 4, 0x05e1 );
6627+// phy_write( 0, 0x1200 );
6628+// phy_delay(5000);
6629+ }
6630+ else {
6631+ phy_basic_setting(loop_phy);
6632+ phy_delay(150);
6633+ }
6634+ }
6635+} // End void phy_realtek2 (int loop_phy)
6636+
6637+//------------------------------------------------------------
6638+void recov_phy_realtek3 (int loop_phy) {//RTL8211C
6639+ if ( BurstEnable ) {
6640+ if ( IEEETesting ) {
6641+ if ( GSpeed_sel[0] ) {
6642+ phy_write( 9, 0x0000 );
6643+ }
6644+ else if ( GSpeed_sel[1] ) {
6645+ phy_write( 17, PHY_11h );
6646+ phy_write( 14, 0x0000 );
6647+ phy_write( 16, 0x00a0 );
6648+ }
6649+ else {
6650+// phy_write( 31, 0x0006 );
6651+// phy_write( 0, 0x5a00 );
6652+// phy_write( 31, 0x0000 );
6653+ }
6654+ }
6655+ else {
6656+ }
6657+ }
6658+ else if (loop_phy) {
6659+ if ( GSpeed_sel[0] ) {
6660+ phy_write( 11, 0x0000 );
6661+ }
6662+ phy_write( 12, 0x1006 );
6663+ }
6664+ else {
6665+ if ( GSpeed_sel[0] ) {
6666+ phy_write( 31, 0x0001 );
6667+ phy_write( 4, 0xb000 );
6668+ phy_write( 3, 0xff41 );
6669+ phy_write( 2, 0xdf20 );
6670+ phy_write( 1, 0x0140 );
6671+ phy_write( 0, 0x00bb );
6672+ phy_write( 4, 0xb800 );
6673+ phy_write( 4, 0xb000 );
6674+
6675+ phy_write( 31, 0x0000 );
6676+ phy_write( 25, 0x8c00 );
6677+ phy_write( 26, 0x0040 );
6678+ phy_write( 0, 0x1140 );
6679+ phy_write( 14, 0x0000 );
6680+ phy_write( 12, 0x1006 );
6681+ phy_write( 23, 0x2109 );
6682+ }
6683+ }
6684+}
6685+
6686+//------------------------------------------------------------
6687+void phy_realtek3 (int loop_phy) {//RTL8211C
6688+ if ( DbgPrn_PHYName )
6689+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
6690+
6691+ if ( BurstEnable ) {
6692+ if ( IEEETesting ) {
6693+ if ( GSpeed_sel[0] ) {
6694+ if ( IOTimingBund_arg == 0 ) { //Test Mode 1
6695+ phy_write( 9, 0x2000);
6696+ }
6697+ else if (IOTimingBund_arg == 1) {//Test Mode 2
6698+ phy_write( 9, 0x4000);
6699+ }
6700+ else if (IOTimingBund_arg == 2) {//Test Mode 3
6701+ phy_write( 9, 0x6000);
6702+ }
6703+ else { //Test Mode 4
6704+ phy_write( 9, 0x8000);
6705+ }
6706+ }
6707+ else if ( GSpeed_sel[1] ) {
6708+ PHY_11h = phy_read( PHY_SR );
6709+ phy_write( 17, PHY_11h & 0xfff7 );
6710+ phy_write( 14, 0x0660 );
6711+
6712+ if ( IOTimingBund_arg == 0 ) {
6713+ phy_write( 16, 0x00a0 );//MDI //From Channel A
6714+ }
6715+ else {
6716+ phy_write( 16, 0x0080 );//MDIX //From Channel B
6717+ }
6718+ }
6719+ else {
6720+// if (IOTimingBund_arg == 0) {//Pseudo-random pattern
6721+// phy_write( 31, 0x0006 );
6722+// phy_write( 0, 0x5a21 );
6723+// phy_write( 31, 0x0000 );
6724+// }
6725+// else if (IOTimingBund_arg == 1) {//¡§FF¡¨ pattern
6726+// phy_write( 31, 0x0006 );
6727+// phy_write( 2, 0x05ee );
6728+// phy_write( 0, 0xff21 );
6729+// phy_write( 31, 0x0000 );
6730+// }
6731+// else {//¡§00¡¨ pattern
6732+// phy_write( 31, 0x0006 );
6733+// phy_write( 2, 0x05ee );
6734+// phy_write( 0, 0x0021 );
6735+// phy_write( 31, 0x0000 );
6736+// }
6737+ }
6738+ }
6739+ else {
6740+ phy_Reset(loop_phy);
6741+ }
6742+ }
6743+ else if (loop_phy) {
6744+ phy_write( 0, 0x9200);
6745+ phy_Wait_Reset_Done();
6746+ phy_delay(30);
6747+
6748+ phy_write( 17, 0x401c );
6749+ phy_write( 12, 0x0006 );
6750+
6751+ if ( GSpeed_sel[0] ) {
6752+ phy_write(11, 0x0002);
6753+ }
6754+ else {
6755+ phy_basic_setting(loop_phy);
6756+ }
6757+ }
6758+ else {
6759+ if (GSpeed_sel[0]) {
6760+ phy_write( 31, 0x0001 );
6761+ phy_write( 4, 0xb000 );
6762+ phy_write( 3, 0xff41 );
6763+ phy_write( 2, 0xd720 );
6764+ phy_write( 1, 0x0140 );
6765+ phy_write( 0, 0x00bb );
6766+ phy_write( 4, 0xb800 );
6767+ phy_write( 4, 0xb000 );
6768+
6769+ phy_write( 31, 0x0000 );
6770+ phy_write( 25, 0x8400 );
6771+ phy_write( 26, 0x0020 );
6772+ phy_write( 0, 0x0140 );
6773+ phy_write( 14, 0x0210 );
6774+ phy_write( 12, 0x0200 );
6775+ phy_write( 23, 0x2109 );
6776+ phy_write( 23, 0x2139 );
6777+ }
6778+ else {
6779+ phy_Reset(loop_phy);
6780+ }
6781+ }
6782+} // End void phy_realtek3 (int loop_phy)
6783+
6784+//------------------------------------------------------------
6785+void phy_realtek4 (int loop_phy) {//RTL8201F
6786+ if ( DbgPrn_PHYName )
6787+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
6788+
6789+ if ( BurstEnable ) {
6790+ if ( IEEETesting ) {
6791+ phy_write( 31, 0x0004 );
6792+ phy_write( 16, 0x4077 );
6793+ phy_write( 21, 0xc5a0 );
6794+ phy_write( 31, 0x0000 );
6795+
6796+ if ( GSpeed_sel[1] ) {
6797+ phy_write( 0, 0x8000 ); // Reset PHY
6798+ phy_write( 24, 0x0310 ); // Disable ALDPS
6799+
6800+ if ( IOTimingBund_arg == 0 ) {
6801+ phy_write( 28, 0x40c2 ); //Force MDI //From Channel A (RJ45 pair 1, 2)
6802+ }
6803+ else {
6804+ phy_write( 28, 0x40c0 ); //Force MDIX//From Channel B (RJ45 pair 3, 6)
6805+ }
6806+ phy_write( 0, 0x2100); //Force 100M/Full Duplex)
6807+ }
6808+ } else {
6809+ phy_Reset(loop_phy);
6810+ }
6811+ }
6812+ else {
6813+ phy_Reset(loop_phy);
6814+ }
6815+}
6816+
6817+//------------------------------------------------------------
6818+void phy_smsc (int loop_phy) {//LAN8700
6819+ if ( DbgPrn_PHYName )
6820+ printf ("--->(%04lx %04lx)[SMSC] %s\n", PHY_ID2, PHY_ID3, PHYName);
6821+
6822+ phy_Reset(loop_phy);
6823+}
6824+
6825+//------------------------------------------------------------
6826+void phy_micrel (int loop_phy) {//KSZ8041
6827+ if ( DbgPrn_PHYName )
6828+ printf ("--->(%04lx %04lx)[Micrel] %s\n", PHY_ID2, PHY_ID3, PHYName);
6829+
6830+ phy_Reset(loop_phy);
6831+
6832+// phy_write(24, 0x0600);
6833+}
6834+
6835+//------------------------------------------------------------
6836+void phy_micrel0 (int loop_phy) {//KSZ8031/KSZ8051
6837+ if ( DbgPrn_PHYName ) printf ("--->(%04lx %04lx)[Micrel] %s\n", PHY_ID2, PHY_ID3, PHYName);
6838+
6839+ //For KSZ8051RNL only
6840+ //Reg1Fh[7] = 0(default): 25MHz Mode, XI, XO(pin 9, 8) is 25MHz(crystal/oscilator).
6841+ //Reg1Fh[7] = 1 : 50MHz Mode, XI(pin 9) is 50MHz(oscilator).
6842+ PHY_1fh = phy_read(31);
6843+ if (PHY_1fh & 0x0080) sprintf(PHYName, "%s-50MHz Mode", PHYName);
6844+ else sprintf(PHYName, "%s-25MHz Mode", PHYName);
6845+
6846+ if (IEEETesting) {
6847+ phy_Read_Write( 0, 0x0000, 0x8000 | PHY_00h );//clr set//Rst PHY
6848+ phy_Wait_Reset_Done();
6849+
6850+ phy_Read_Write( 31, 0x0000, 0x2000 );//clr set//1Fh[13] = 1: Disable auto MDI/MDI-X
6851+ phy_basic_setting(loop_phy);
6852+ phy_Read_Write( 31, 0x0000, 0x0800 );//clr set//1Fh[11] = 1: Force link pass
6853+
6854+// phy_delay(2500);//2.5 sec
6855+ }
6856+ else {
6857+ phy_Reset(loop_phy);
6858+
6859+ //Reg16h[6] = 1 : RMII B-to-B override
6860+ //Reg16h[1] = 1(default): RMII override
6861+ phy_Read_Write( 22, 0x0000, 0x0042 );//clr set
6862+ }
6863+
6864+ if ( PHY_1fh & 0x0080 )
6865+ phy_Read_Write( 31, 0x0000, 0x0080 );//clr set//Reset PHY will clear Reg1Fh[7]
6866+}
6867+
6868+//------------------------------------------------------------
6869+void recov_phy_vitesse (int loop_phy) {//VSC8601
6870+ if ( BurstEnable ) {
6871+// if (IEEETesting) {
6872+// } else {
6873+// }
6874+ }
6875+ else if ( loop_phy ) {
6876+ }
6877+ else {
6878+ if ( GSpeed_sel[0] ) {
6879+ phy_write( 24, PHY_18h );
6880+ phy_write( 18, PHY_12h );
6881+ }
6882+ }
6883+}
6884+
6885+//------------------------------------------------------------
6886+void phy_vitesse (int loop_phy) {//VSC8601
6887+ if ( DbgPrn_PHYName )
6888+ printf ("--->(%04lx %04lx)[VITESSE] %s\n", PHY_ID2, PHY_ID3, PHYName);
6889+
6890+ if ( BurstEnable ) {
6891+ if ( IEEETesting ) {
6892+ phy_Reset(loop_phy);
6893+ }
6894+ else {
6895+ phy_Reset(loop_phy);
6896+ }
6897+ }
6898+ else if ( loop_phy ) {
6899+ phy_Reset(loop_phy);
6900+ }
6901+ else {
6902+ if ( GSpeed_sel[0] ) {
6903+ PHY_18h = phy_read( 24 );
6904+ PHY_12h = phy_read( PHY_INER );
6905+
6906+ phy_Reset(loop_phy);
6907+
6908+ phy_write( 24, PHY_18h | 0x0001 );
6909+ phy_write( 18, PHY_12h | 0x0020 );
6910+ }
6911+ else {
6912+ phy_Reset(loop_phy);
6913+ }
6914+ }
6915+}
6916+
6917+//------------------------------------------------------------
6918+void phy_default (int loop_phy) {
6919+ if ( DbgPrn_PHYName )
6920+ printf ("--->(%04lx %04lx)%s\n", PHY_ID2, PHY_ID3, PHYName);
6921+
6922+ phy_Reset(loop_phy);
6923+}
6924+
6925+//------------------------------------------------------------
6926+// PHY Init
6927+//------------------------------------------------------------
6928+BOOLEAN find_phyadr (void) {
6929+ ULONG PHY_val;
6930+ BOOLEAN ret = FALSE;
6931+
6932+ #ifdef DbgPrn_FuncHeader
6933+ printf ("find_phyadr\n");
6934+ Debug_delay();
6935+ #endif
6936+
6937+ do {
6938+ // Check current PHY address by user setting
6939+ PHY_val = phy_read( PHY_REG_ID_1 );
6940+ if ( PHY_IS_VALID(PHY_val) ) {
6941+ ret = TRUE;
6942+ break;
6943+ }
6944+
6945+ if ( Enable_SkipChkPHY ) {
6946+ PHY_val = phy_read( PHY_REG_BMCR );
6947+
6948+ if ((PHY_val & 0x8000) & Enable_InitPHY) {
6949+ // PHY is reseting and need to inital PHY
6950+ #ifndef Enable_SearchPHYID
6951+ break;
6952+ #endif
6953+ }
6954+ else {
6955+ ret = TRUE;
6956+ break;
6957+ }
6958+ }
6959+
6960+ #ifdef Enable_SearchPHYID
6961+ // Scan PHY address from 0 to 31
6962+ printf("Search PHY address\n");
6963+ for ( PHY_ADR = 0; PHY_ADR < 32; PHY_ADR++ ) {
6964+ PHY_val = phy_read( PHY_REG_ID_1 );
6965+ if ( PHY_IS_VALID(PHY_val) ) {
6966+ ret = TRUE;
6967+ break;
6968+ }
6969+ }
6970+ // Don't find PHY address
6971+ PHY_ADR = PHY_ADR_arg;
6972+ #endif
6973+ } while ( 0 );
6974+
6975+ if ( ret == TRUE ) {
6976+ if ( PHY_ADR_arg != PHY_ADR ) {
6977+
6978+ if ( !BurstEnable )
6979+ phy_id( FP_LOG );
6980+
6981+ phy_id( STD_OUT );
6982+ }
6983+ }
6984+ else {
6985+
6986+ if ( !BurstEnable )
6987+ phy_id( FP_LOG );
6988+
6989+ phy_id( STD_OUT );
6990+ FindErr( Err_PHY_Type );
6991+ }
6992+
6993+ return ret;
6994+} // End BOOLEAN find_phyadr (void)
6995+
6996+//------------------------------------------------------------
6997+char phy_chk (ULONG id2, ULONG id3, ULONG id3_mask) {
6998+ if ((PHY_ID2 == id2) && ((PHY_ID3 & id3_mask) == (id3 & id3_mask)))
6999+ return(1);
7000+ else
7001+ return(0);
7002+}
7003+
7004+//------------------------------------------------------------
7005+void phy_set00h (int loop_phy) {
7006+ #ifdef DbgPrn_FuncHeader
7007+ printf ("phy_set00h\n");
7008+ Debug_delay();
7009+ #endif
7010+
7011+ if (BurstEnable) {
7012+ if (IEEETesting) {
7013+ if (GSpeed_sel[0]) PHY_00h = 0x0140;
7014+ else if (GSpeed_sel[1]) PHY_00h = 0x2100;
7015+ else PHY_00h = 0x0100;
7016+ }
7017+ else {
7018+ if (GSpeed_sel[0]) PHY_00h = 0x1140;
7019+ else if (GSpeed_sel[1]) PHY_00h = 0x3100;
7020+ else PHY_00h = 0x1100;
7021+ }
7022+ }
7023+ else if (loop_phy) {
7024+ if (GSpeed_sel[0]) PHY_00h = 0x4140;
7025+ else if (GSpeed_sel[1]) PHY_00h = 0x6100;
7026+ else PHY_00h = 0x4100;
7027+ }
7028+ else {
7029+ if (GSpeed_sel[0]) PHY_00h = 0x0140;
7030+ else if (GSpeed_sel[1]) PHY_00h = 0x2100;
7031+ else PHY_00h = 0x0100;
7032+ }
7033+}
7034+
7035+//------------------------------------------------------------
7036+void phy_sel (int loop_phy) {
7037+ #ifdef DbgPrn_FuncHeader
7038+ printf ("phy_sel\n");
7039+ Debug_delay();
7040+ #endif
7041+
7042+ PHY_ID2 = phy_read( PHY_REG_ID_1 );
7043+ PHY_ID3 = phy_read( PHY_REG_ID_2 );
7044+ phy_set00h(loop_phy);
7045+
7046+ if ((PHY_ID2 == 0xffff) && (PHY_ID3 == 0xffff) && !Enable_SkipChkPHY) {
7047+ sprintf(PHYName, "--");
7048+ FindErr(Err_PHY_Type);
7049+ }
7050+#ifdef Enable_CheckZeroPHYID
7051+ else if ((PHY_ID2 == 0x0000) && (PHY_ID3 == 0x0000) && !Enable_SkipChkPHY) {
7052+ sprintf(PHYName, "--"); FindErr(Err_PHY_Type);
7053+ }
7054+#endif
7055+
7056+ if (phy_chk(0x0362, 0x5e6a, 0xfff0 )) {sprintf(PHYName, "BCM54612" ); if (Enable_InitPHY) phy_broadcom0(loop_phy);}//BCM54612 1G/100/10M RGMII
7057+ else if (phy_chk(0x0362, 0x5d10, 0xfff0 )) {sprintf(PHYName, "BCM54616S" ); if (Enable_InitPHY) phy_broadcom0(loop_phy);}//BCM54616A 1G/100/10M RGMII
7058+ else if (phy_chk(0x0040, 0x61e0, PHYID3_Mask)) {sprintf(PHYName, "BCM5221" ); if (Enable_InitPHY) phy_broadcom (loop_phy);}//BCM5221 100/10M MII, RMII
7059+ else if (phy_chk(0x0141, 0x0dd0, 0xfff0 )) {sprintf(PHYName, "88E1512" ); if (Enable_InitPHY) phy_marvell2 (loop_phy);}//88E1512 1G/100/10M RGMII
7060+ else if (phy_chk(0xff00, 0x1761, 0xffff )) {sprintf(PHYName, "88E6176(IntLoop)"); if (Enable_InitPHY) phy_marvell1 (loop_phy);}//88E6176 1G/100/10M 2 RGMII Switch
7061+ else if (phy_chk(0x0141, 0x0e90, 0xfff0 )) {sprintf(PHYName, "88E1310" ); if (Enable_InitPHY) phy_marvell0 (loop_phy);}//88E1310 1G/100/10M RGMII
7062+ else if (phy_chk(0x0141, 0x0cc0, PHYID3_Mask)) {sprintf(PHYName, "88E1111" ); if (Enable_InitPHY) phy_marvell (loop_phy);}//88E1111 1G/100/10M GMII, MII, RGMII
7063+ else if (phy_chk(0x001c, 0xc816, 0xffff )) {sprintf(PHYName, "RTL8201F" ); if (Enable_InitPHY) phy_realtek4 (loop_phy);}//RTL8201F 100/10M MII, RMII
7064+ else if (phy_chk(0x001c, 0xc815, 0xfff0 )) {sprintf(PHYName, "RTL8201E" ); if (Enable_InitPHY) phy_realtek0 (loop_phy);}//RTL8201E 100/10M MII, RMII(RTL8201E(L)-VC only)
7065+ else if (phy_chk(0x001c, 0xc912, 0xffff )) {sprintf(PHYName, "RTL8211C" ); if (Enable_InitPHY) phy_realtek3 (loop_phy);}//RTL8211C 1G/100/10M RGMII
7066+ else if (phy_chk(0x001c, 0xc914, 0xffff )) {sprintf(PHYName, "RTL8211D" ); if (Enable_InitPHY) phy_realtek1 (loop_phy);}//RTL8211D 1G/100/10M GMII(RTL8211DN/RTL8211DG only), MII(RTL8211DN/RTL8211DG only), RGMII
7067+ else if (phy_chk(0x001c, 0xc915, 0xffff )) {sprintf(PHYName, "RTL8211E" ); if (Enable_InitPHY) phy_realtek2 (loop_phy);}//RTL8211E 1G/100/10M GMII(RTL8211EG only), RGMII
7068+ else if (phy_chk(0x0000, 0x8201, PHYID3_Mask)) {sprintf(PHYName, "RTL8201N" ); if (Enable_InitPHY) phy_realtek (loop_phy);}//RTL8201N 100/10M MII, RMII
7069+ else if (phy_chk(0x0007, 0xc0c4, PHYID3_Mask)) {sprintf(PHYName, "LAN8700" ); if (Enable_InitPHY) phy_smsc (loop_phy);}//LAN8700 100/10M MII, RMII
7070+ else if (phy_chk(0x0022, 0x1555, 0xfff0 )) {sprintf(PHYName, "KSZ8031/KSZ8051" ); if (Enable_InitPHY) phy_micrel0 (loop_phy);}//KSZ8051/KSZ8031 100/10M RMII
7071+ else if (phy_chk(0x0022, 0x1560, 0xfff0 )) {sprintf(PHYName, "KSZ8081" ); if (Enable_InitPHY) phy_micrel0 (loop_phy);}//KSZ8081 100/10M RMII
7072+ else if (phy_chk(0x0022, 0x1512, 0xfff0 )) {sprintf(PHYName, "KSZ8041" ); if (Enable_InitPHY) phy_micrel (loop_phy);}//KSZ8041 100/10M RMII
7073+ else if (phy_chk(0x0007, 0x0421, 0xfff0 )) {sprintf(PHYName, "VSC8601" ); if (Enable_InitPHY) phy_vitesse (loop_phy);}//VSC8601 1G/100/10M RGMII
7074+ else {sprintf(PHYName, "default" ); if (Enable_InitPHY) phy_default (loop_phy);}//
7075+}
7076+
7077+//------------------------------------------------------------
7078+void recov_phy (int loop_phy) {
7079+ #ifdef DbgPrn_FuncHeader
7080+ printf ("recov_phy\n");
7081+ Debug_delay();
7082+ #endif
7083+
7084+ if (phy_chk(0x0362, 0x5e6a, 0xfff0 )) recov_phy_broadcom0(loop_phy);//BCM54612 1G/100/10M RGMII
7085+ else if (phy_chk(0x0362, 0x5d10, 0xfff0 )) recov_phy_broadcom0(loop_phy);//BCM54616A 1G/100/10M RGMII
7086+ else if (phy_chk(0x0141, 0x0dd0, 0xfff0 )) recov_phy_marvell2 (loop_phy);//88E1512 1G/100/10M RGMII
7087+ else if (phy_chk(0xff00, 0x1761, 0xffff )) recov_phy_marvell1 (loop_phy);//88E6176 1G/100/10M 2 RGMII Switch
7088+ else if (phy_chk(0x0141, 0x0e90, 0xfff0 )) recov_phy_marvell0 (loop_phy);//88E1310 1G/100/10M RGMII
7089+ else if (phy_chk(0x0141, 0x0cc0, PHYID3_Mask)) recov_phy_marvell (loop_phy);//88E1111 1G/100/10M GMII, MII, RGMII
7090+ else if (phy_chk(0x001c, 0xc914, 0xffff )) recov_phy_realtek1 (loop_phy);//RTL8211D 1G/100/10M GMII(RTL8211DN/RTL8211DG only), MII(RTL8211DN/RTL8211DG only), RGMII
7091+ else if (phy_chk(0x001c, 0xc915, 0xffff )) recov_phy_realtek2 (loop_phy);//RTL8211E 1G/100/10M GMII(RTL8211EG only), RGMII
7092+ else if (phy_chk(0x001c, 0xc912, 0xffff )) recov_phy_realtek3 (loop_phy);//RTL8211C 1G/100/10M RGMII
7093+ else if (phy_chk(0x0007, 0x0421, 0xfff0 )) recov_phy_vitesse (loop_phy);//VSC8601 1G/100/10M RGMII
7094+}
7095+
7096+//------------------------------------------------------------
7097+void init_phy (int loop_phy) {
7098+ #ifdef DbgPrn_FuncHeader
7099+ printf ("init_phy\n");
7100+ Debug_delay();
7101+ #endif
7102+
7103+ sprintf( PHYID, "PHY%d", SelectMAC + 1 );
7104+
7105+ if ( DbgPrn_PHYInit )
7106+ phy_dump( PHYID );
7107+
7108+ if ( find_phyadr() == TRUE )
7109+ phy_sel( loop_phy );
7110+
7111+ if ( DbgPrn_PHYInit )
7112+ phy_dump( PHYID );
7113+}
7114+
7115+
7116diff --git a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H
7117new file mode 100644
7118index 0000000..6fa96e6
7119--- /dev/null
7120+++ b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H
7121@@ -0,0 +1,50 @@
7122+/*
7123+ * This program is distributed in the hope that it will be useful,
7124+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7125+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7126+ * GNU General Public License for more details.
7127+ *
7128+ * You should have received a copy of the GNU General Public License
7129+ * along with this program; if not, write to the Free Software
7130+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7131+ */
7132+#ifndef PLLTESTU_H
7133+#define PLLTESTU_H
7134+
7135+//PLL Mode Definition
7136+#define NAND_PLLMODE 0x00
7137+#define DELAY_PLLMODE 0x04
7138+#define PCI_PLLMODE 0x08
7139+#define DPLL_PLLMODE 0x2c
7140+#define MPLL_PLLMODE 0x10
7141+#define HPLL_PLLMODE 0x14
7142+#define LPC_PLLMODE 0x18
7143+#define VIDEOA_PLLMODE 0x1c
7144+#define D2PLL_PLLMODE 0x0c
7145+#define VIDEOB_PLLMODE 0x3c
7146+
7147+#define PCI_PLLMODE_AST1160 0x10
7148+#define MPLL_PLLMODE_AST1160 0x14
7149+#define HPLL_PLLMODE_AST1160 0x14
7150+#define DPLL_PLLMODE_AST1160 0x1c
7151+
7152+#define PCI_PLLMODE_AST2300 0x2c
7153+#define MPLL_PLLMODE_AST2300 0x10
7154+#define HPLL_PLLMODE_AST2300 0x30
7155+#define DPLL_PLLMODE_AST2300 0x08
7156+#define DEL0_PLLMODE_AST2300 0x00
7157+
7158+#define ERR_FATAL 0x00000001
7159+
7160+typedef struct _VGAINFO {
7161+ USHORT usDeviceID;
7162+ UCHAR jRevision;
7163+
7164+ ULONG ulMCLK;
7165+ ULONG ulDRAMBusWidth;
7166+
7167+ ULONG ulCPUCLK;
7168+ ULONG ulAHBCLK;
7169+} _VGAInfo;
7170+
7171+#endif // End PLLTESTU_H
7172diff --git a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c
7173new file mode 100644
7174index 0000000..95958b0
7175--- /dev/null
7176+++ b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c
7177@@ -0,0 +1,411 @@
7178+/*
7179+ * This program is distributed in the hope that it will be useful,
7180+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7181+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7182+ * GNU General Public License for more details.
7183+ *
7184+ * You should have received a copy of the GNU General Public License
7185+ * along with this program; if not, write to the Free Software
7186+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7187+ */
7188+#define PLLTEST_C
7189+static const char ThisFile[] = "PLLTEST.c";
7190+
7191+#include "SWFUNC.H"
7192+
7193+#include <COMMINF.H>
7194+#include <STDUBOOT.H>
7195+#include <TYPEDEF.H>
7196+#include <IO.H>
7197+#include <PLLTESTU.H>
7198+
7199+/*
7200+ * static
7201+ */
7202+static UCHAR jVersion[] = "v.0.57.00";
7203+
7204+void print_usage( void )
7205+{
7206+ printf(" PLLTest [pll mode] [err rate]\n");
7207+ printf(" [pll mode] h-pll: ARM CPU Clock PLL\n");
7208+ printf(" m-pll: Memory Clock PLL\n");
7209+ printf(" [err rate] Error Rate: unit %\n");
7210+ printf(" default is 1%\n");
7211+}
7212+
7213+BOOL CompareToRing(_VGAInfo *VGAInfo, ULONG ulPLLMode, ULONG ulDCLK, ULONG ulErrRate)
7214+{
7215+ ULONG ulCounter, ulLowLimit, ulHighLimit;
7216+ ULONG ulData, ulValue, ulDiv;
7217+ ULONG ulSCUBase;
7218+ double del0;
7219+ ULONG uldel0;
7220+
7221+ if ((VGAInfo->usDeviceID == 0x1160) || (VGAInfo->usDeviceID == 0x1180))
7222+ ulSCUBase = 0x80fc8200;
7223+ else
7224+ ulSCUBase = 0x1e6e2000;
7225+
7226+ //Fixed AST2300 H-PLL can't Get Correct Value in VGA only mode, ycchen@081711
7227+ if ( (VGAInfo->jRevision >= 0x20) && (ulPLLMode == HPLL_PLLMODE_AST2300) )
7228+ {
7229+ WriteSOC_DD(ulSCUBase, 0x1688a8a8);
7230+ ulData = ReadSOC_DD(ulSCUBase + 0x08);
7231+ WriteSOC_DD(ulSCUBase + 0x08, ulData & 0xFFFFFF00);
7232+ }
7233+
7234+ ulCounter = (ulDCLK/1000) * 512 / 24000 - 1;
7235+ ulLowLimit = ulCounter * (100 - ulErrRate) / 100;
7236+ ulHighLimit = ulCounter * (100 + ulErrRate) / 100;
7237+
7238+ DELAY(10);
7239+ WriteSOC_DD(ulSCUBase, 0x1688a8a8);
7240+ WriteSOC_DD(ulSCUBase + 0x28, (ulHighLimit << 16) | ulLowLimit);
7241+ WriteSOC_DD(ulSCUBase + 0x10, ulPLLMode);
7242+ WriteSOC_DD(ulSCUBase + 0x10, ulPLLMode | 0x03);
7243+ DELAY(1);
7244+ do {
7245+ ulData = ReadSOC_DD(ulSCUBase + 0x10);
7246+ } while (!(ulData & 0x40));
7247+ ulValue = ReadSOC_DD(ulSCUBase + 0x14);
7248+
7249+ //Patch for AST1160/1180 DCLK calculate
7250+ if ( ((VGAInfo->usDeviceID == 0x1160) || (VGAInfo->usDeviceID == 0x1180)) && (ulPLLMode == DPLL_PLLMODE_AST1160) )
7251+ {
7252+ ulData = ReadSOC_DD(0x80fc906c);
7253+ ulDiv = ulData & 0x000c0000;
7254+ ulDiv >>= 18;
7255+ ulDiv++;
7256+ ulValue /= ulDiv;
7257+ }
7258+
7259+ if ( (VGAInfo->jRevision >= 0x20) && (ulPLLMode == DEL0_PLLMODE_AST2300) )
7260+ {
7261+ del0 = (double)(24.0 * (ulValue + 1) / 512.0);
7262+ del0 = 1000/del0/16/8;
7263+ uldel0 = (ULONG) (del0 * 1000000);
7264+ if (uldel0 < ulDCLK)
7265+ {
7266+ printf( "[PASS][DEL0] Actual DEL0:%f ns, Max. DEL0:%f ns \n", del0, (double)ulDCLK/1000000);
7267+ ulData |= 0x80;
7268+ }
7269+ else
7270+ {
7271+ printf( "[ERROR][DEL0] Actual DEL0:%f ns, Max. DEL0:%f ns \n", del0, (double)ulDCLK/1000000);
7272+ ulData == 0x00;
7273+ }
7274+ }
7275+ else
7276+ {
7277+ printf( "[INFO] PLL Predict Count = %x, Actual Count = %x \n", ulCounter, ulValue);
7278+ }
7279+
7280+ WriteSOC_DD(ulSCUBase + 0x10, 0x2C); //disable ring
7281+
7282+ if (ulData & 0x80)
7283+ return (TRUE);
7284+ else
7285+ return(FALSE);
7286+} /* CompareToRing */
7287+
7288+VOID GetDRAMInfo(_VGAInfo *VGAInfo)
7289+{
7290+ ULONG ulData, ulData2;
7291+ ULONG ulRefPLL, ulDeNumerator, ulNumerator, ulDivider, ulOD;
7292+
7293+ if (VGAInfo->jRevision >= 0x10)
7294+ {
7295+ WriteSOC_DD(0x1e6e2000, 0x1688A8A8);
7296+
7297+ //Get DRAM Bus Width
7298+ ulData = ReadSOC_DD(0x1e6e0004);
7299+ if (ulData & 0x40)
7300+ VGAInfo->ulDRAMBusWidth = 16;
7301+ else
7302+ VGAInfo->ulDRAMBusWidth = 32;
7303+
7304+ ulRefPLL = 24000;
7305+ if (VGAInfo->jRevision >= 0x30) //AST2400
7306+ {
7307+ ulData = ReadSOC_DD(0x1e6e2070);
7308+ if (ulData & 0x00800000) //D[23] = 1
7309+ ulRefPLL = 25000;
7310+ }
7311+
7312+ ulData = ReadSOC_DD(0x1e6e2020);
7313+ ulDeNumerator = ulData & 0x0F;
7314+ ulNumerator = (ulData & 0x07E0) >> 5;
7315+ ulOD = (ulData & 0x10) ? 1:2;
7316+
7317+ ulData = (ulData & 0x7000) >> 12;
7318+ switch (ulData)
7319+ {
7320+ case 0x07:
7321+ ulDivider = 16;
7322+ break;
7323+ case 0x06:
7324+ ulDivider = 8;
7325+ break;
7326+ case 0x05:
7327+ ulDivider = 4;
7328+ break;
7329+ case 0x04:
7330+ ulDivider = 2;
7331+ break;
7332+ default:
7333+ ulDivider = 0x01;
7334+ }
7335+
7336+ VGAInfo->ulMCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * ulDivider * 1000);
7337+ }
7338+} // GetDRAMInfo
7339+
7340+VOID GetCLKInfo( _VGAInfo *VGAInfo)
7341+{
7342+ ULONG ulData, ulCPUTrap, ulAHBTrap;
7343+ ULONG ulRefPLL, ulDeNumerator, ulNumerator, ulDivider, ulOD;
7344+
7345+ if (VGAInfo->jRevision >= 0x30)
7346+ {
7347+ WriteSOC_DD(0x1e6e2000, 0x1688a8a8);
7348+ ulData = ReadSOC_DD(0x1e6e2024);
7349+ if (ulData & 0x40000) //from H-PLL
7350+ {
7351+ ulRefPLL = 24000;
7352+ ulData = ReadSOC_DD(0x1e6e2070);
7353+ if (ulData & 0x00800000) //D[23] = 1
7354+ ulRefPLL = 25000;
7355+
7356+ ulData = ReadSOC_DD(0x1e6e2024);
7357+
7358+ ulDeNumerator = ulData & 0x0F;
7359+ ulNumerator = (ulData & 0x07E0) >> 5;
7360+ ulOD = (ulData & 0x10) ? 1:2;
7361+
7362+ VGAInfo->ulCPUCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * 1000);
7363+
7364+ }
7365+ else //from trapping
7366+ {
7367+ ulRefPLL = 24;
7368+ ulData = ReadSOC_DD(0x1e6e2070);
7369+ if (ulData & 0x00800000) //D[23] = 1
7370+ ulRefPLL = 25;
7371+
7372+ ulCPUTrap = ulData & 0x0300;
7373+ ulCPUTrap >>= 8;
7374+
7375+ switch (ulCPUTrap)
7376+ {
7377+ case 0x00:
7378+ VGAInfo->ulCPUCLK = ulRefPLL * 16;
7379+ break;
7380+ case 0x01:
7381+ VGAInfo->ulCPUCLK = ulRefPLL * 15;
7382+ break;
7383+ case 0x02:
7384+ VGAInfo->ulCPUCLK = ulRefPLL * 14;
7385+ break;
7386+ case 0x03:
7387+ VGAInfo->ulCPUCLK = ulRefPLL * 17;
7388+ break;
7389+ }
7390+
7391+ }
7392+
7393+ ulData = ReadSOC_DD(0x1e6e2070);
7394+ ulAHBTrap = ulData & 0x0c00;
7395+ ulAHBTrap >>= 10;
7396+ switch (ulAHBTrap)
7397+ {
7398+ case 0x00:
7399+ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK;
7400+ break;
7401+ case 0x01:
7402+ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 2;
7403+ break;
7404+ case 0x02:
7405+ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 4;
7406+ break;
7407+ case 0x03:
7408+ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 3;
7409+ break;
7410+ }
7411+
7412+ } //AST2400
7413+ else if (VGAInfo->jRevision >= 0x20)
7414+ {
7415+ WriteSOC_DD(0x1e6e2000, 0x1688a8a8);
7416+ ulData = ReadSOC_DD(0x1e6e2024);
7417+ if (ulData & 0x40000) //from H-PLL
7418+ {
7419+ ulRefPLL = 24000;
7420+
7421+ ulData = ReadSOC_DD(0x1e6e2024);
7422+
7423+ ulDeNumerator = ulData & 0x0F;
7424+ ulNumerator = (ulData & 0x07E0) >> 5;
7425+ ulOD = (ulData & 0x10) ? 1:2;
7426+
7427+ VGAInfo->ulCPUCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * 1000);
7428+
7429+ }
7430+ else //from trapping
7431+ {
7432+ ulData = ReadSOC_DD(0x1e6e2070);
7433+ ulCPUTrap = ulData & 0x0300;
7434+ ulCPUTrap >>= 8;
7435+
7436+ switch (ulCPUTrap)
7437+ {
7438+ case 0x00:
7439+ VGAInfo->ulCPUCLK = 384;
7440+ break;
7441+ case 0x01:
7442+ VGAInfo->ulCPUCLK = 360;
7443+ break;
7444+ case 0x02:
7445+ VGAInfo->ulCPUCLK = 336;
7446+ break;
7447+ case 0x03:
7448+ VGAInfo->ulCPUCLK = 408;
7449+ break;
7450+ }
7451+
7452+ }
7453+
7454+ ulData = ReadSOC_DD(0x1e6e2070);
7455+ ulAHBTrap = ulData & 0x0c00;
7456+ ulAHBTrap >>= 10;
7457+ switch (ulAHBTrap)
7458+ {
7459+ case 0x00:
7460+ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK;
7461+ break;
7462+ case 0x01:
7463+ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 2;
7464+ break;
7465+ case 0x02:
7466+ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 4;
7467+ break;
7468+ case 0x03:
7469+ VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 3;
7470+ break;
7471+ }
7472+
7473+ } //AST2300
7474+} // GetCLKInfo
7475+
7476+int pll_function(int argc, char *argv[])
7477+{
7478+ _VGAInfo *pVGAInfo;
7479+ ULONG ulErrRate = 1;
7480+ ULONG PLLMode;
7481+ ULONG RefClk;
7482+ CHAR *stop_at;
7483+ CHAR i;
7484+
7485+ printf("**************************************************** \n");
7486+ printf("*** ASPEED Graphics PLL Test %s Log *** \n", jVersion);
7487+ printf("*** for u-boot *** \n");
7488+ printf("**************************************************** \n");
7489+ printf("\n");
7490+
7491+ // Check chip type
7492+ switch ( ReadSOC_DD( 0x1e6e2000 + 0x7c ) ) {
7493+ case 0x02010303 :
7494+ case 0x02000303 :
7495+ printf("The chip is AST2400\n" );
7496+ pVGAInfo->usDeviceID = 0x2400;
7497+ pVGAInfo->jRevision = 0x30;
7498+ break;
7499+
7500+ case 0x02010103 :
7501+ case 0x02000003 :
7502+ printf("The chip is AST1400\n" );
7503+ pVGAInfo->usDeviceID = 0x1400;
7504+ pVGAInfo->jRevision = 0x30;
7505+ break;
7506+
7507+ case 0x01010303 :
7508+ case 0x01000003 :
7509+ printf("The chip is AST2300\n" );
7510+ pVGAInfo->usDeviceID = 0x2300;
7511+ pVGAInfo->jRevision = 0x20;
7512+ break;
7513+
7514+ case 0x01010203 :
7515+ printf("The chip is AST1050\n" );
7516+ pVGAInfo->usDeviceID = 0x1050;
7517+ pVGAInfo->jRevision = 0x20;
7518+ break;
7519+
7520+ default :
7521+ printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", ReadSOC_DD( 0x1e6e2000 + 0x7c ) );
7522+ return(1);
7523+ }
7524+
7525+
7526+ GetDRAMInfo( pVGAInfo );
7527+ GetCLKInfo( pVGAInfo );
7528+
7529+ if ( ( argc <= 1 ) || ( argc >= 4 ) ){
7530+ print_usage();
7531+ return (ERR_FATAL);
7532+ }
7533+ else {
7534+ for ( i = 1; i < argc; i++ ) {
7535+ switch ( i ) {
7536+ case 1:
7537+ if (!strcmp(argv[i], "m-pll"))
7538+ {
7539+ if (pVGAInfo->jRevision >= 0x20)
7540+ PLLMode = MPLL_PLLMODE_AST2300;
7541+ else
7542+ PLLMode = MPLL_PLLMODE;
7543+
7544+ RefClk = pVGAInfo->ulMCLK * 1000000;
7545+ if (pVGAInfo->jRevision >= 0x20) //dual-edge
7546+ RefClk /= 2;
7547+ }
7548+ else if (!strcmp(argv[i], "h-pll"))
7549+ {
7550+ if (pVGAInfo->jRevision >= 0x20)
7551+ PLLMode = HPLL_PLLMODE_AST2300;
7552+ else
7553+ PLLMode = HPLL_PLLMODE;
7554+
7555+ //AST2300 only has HCLK ring test mode, ycchen@040512
7556+ RefClk = pVGAInfo->ulCPUCLK * 1000000; //Other : H-PLL
7557+ if (pVGAInfo->jRevision >= 0x20) //AST2300: HCLK
7558+ RefClk = pVGAInfo->ulAHBCLK * 1000000;
7559+ }
7560+ else {
7561+ print_usage();
7562+ return (ERR_FATAL);
7563+ }
7564+ break;
7565+ case 2:
7566+ ulErrRate = (ULONG) strtoul(argv[i], &stop_at, 10);
7567+
7568+ break;
7569+ default:
7570+ break;
7571+ } // End switch()
7572+ } // End for
7573+ }
7574+
7575+ /* Compare ring */
7576+ if (CompareToRing(pVGAInfo, PLLMode, RefClk, ulErrRate ) == TRUE)
7577+ {
7578+ printf("[PASS] %s PLL Check Pass!! \n", argv[1]);
7579+ return 0;
7580+ }
7581+ else
7582+ {
7583+ printf("[ERROR] %s PLL Check Failed!! \n", argv[1]);
7584+ return (ERR_FATAL);
7585+ }
7586+}
7587+
7588+
7589diff --git a/arch/arm/cpu/arm926ejs/aspeed/SPIM.c b/arch/arm/cpu/arm926ejs/aspeed/SPIM.c
7590new file mode 100644
7591index 0000000..e1bdd07
7592--- /dev/null
7593+++ b/arch/arm/cpu/arm926ejs/aspeed/SPIM.c
7594@@ -0,0 +1,63 @@
7595+/*
7596+ * This program is distributed in the hope that it will be useful,
7597+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7598+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7599+ * GNU General Public License for more details.
7600+ *
7601+ * You should have received a copy of the GNU General Public License
7602+ * along with this program; if not, write to the Free Software
7603+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7604+ */
7605+#define SPIM_C
7606+static const char ThisFile[] = "SPIM.c";
7607+
7608+#include "SWFUNC.H"
7609+
7610+#ifdef SPI_BUS
7611+
7612+#include <stdio.h>
7613+#include <stdlib.h>
7614+#include <conio.h>
7615+#include <string.h>
7616+#include "TYPEDEF.H"
7617+#include "LIB_SPI.H"
7618+
7619+#define SPIM_CMD_WHA 0x01
7620+#define SPIM_CMD_RD 0x0B
7621+#define SPIM_CMD_DRD 0xBB
7622+#define SPIM_CMD_WR 0x02
7623+#define SPIM_CMD_DWR 0xD2
7624+#define SPIM_CMD_STA 0x05
7625+#define SPIM_CMD_ENBYTE 0x06
7626+#define SPIM_CMD_DISBYTE 0x04
7627+
7628+ULONG spim_cs;
7629+ULONG spim_base;
7630+ULONG spim_hadr;
7631+
7632+void spim_end()
7633+{
7634+ ULONG data;
7635+
7636+ data = MIndwm((ULONG)mmiobase, 0x1E620010 + (spim_cs << 2));
7637+ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (spim_cs << 2), data | 0x4);
7638+ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (spim_cs << 2), data);
7639+}
7640+
7641+//------------------------------------------------------------
7642+void spim_init(int cs)
7643+{
7644+ ULONG data;
7645+
7646+ spim_cs = cs;
7647+ MOutdwm( (ULONG)mmiobase, 0x1E620000, (0x2 << (cs << 1)) | (0x10000 << cs));
7648+ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (cs << 2), 0x00000007);
7649+ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (cs << 2), 0x00002003);
7650+ MOutdwm( (ULONG)mmiobase, 0x1E620004, 0x100 << cs);
7651+ data = MIndwm((ULONG)mmiobase, 0x1E620030 + (cs << 2));
7652+ spim_base = 0x20000000 | ((data & 0x007f0000) << 7);
7653+ MOutwm ( (ULONG)mmiobase, spim_base, SPIM_CMD_WHA);
7654+ spim_end();
7655+ spim_hadr = 0;
7656+}
7657+#endif // End SPI_BUS
7658diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H
7659new file mode 100644
7660index 0000000..7fbf590
7661--- /dev/null
7662+++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H
7663@@ -0,0 +1,18 @@
7664+/*
7665+ * This program is distributed in the hope that it will be useful,
7666+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7667+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7668+ * GNU General Public License for more details.
7669+ *
7670+ * You should have received a copy of the GNU General Public License
7671+ * along with this program; if not, write to the Free Software
7672+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7673+ */
7674+#ifndef STDUBOOT_H
7675+#define STDUBOOT_H
7676+
7677+unsigned long int strtoul(char *string, char **endPtr, int base);
7678+int atoi( char s[] );
7679+int rand(void);
7680+
7681+#endif // End STDUBOOT_H
7682diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c
7683new file mode 100644
7684index 0000000..90e2997
7685--- /dev/null
7686+++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c
7687@@ -0,0 +1,235 @@
7688+/*
7689+ * This program is distributed in the hope that it will be useful,
7690+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7691+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7692+ * GNU General Public License for more details.
7693+ *
7694+ * You should have received a copy of the GNU General Public License
7695+ * along with this program; if not, write to the Free Software
7696+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7697+ */
7698+#define STDUBOOT_C
7699+static const char ThisFile[] = "STDUBOOT.c";
7700+
7701+#include "SWFUNC.H"
7702+
7703+#ifdef SLT_UBOOT
7704+
7705+int isspace ( char c )
7706+{
7707+ if ( ( c == ' ' ) || ( c == 9 ) || ( c == 13 ) )
7708+ return 1;
7709+
7710+ return 0;
7711+}
7712+
7713+/*
7714+ * strtoul.c --
7715+ *
7716+ * Source code for the "strtoul" library procedure.
7717+ *
7718+ * Copyright 1988 Regents of the University of California
7719+ * Permission to use, copy, modify, and distribute this
7720+ * software and its documentation for any purpose and without
7721+ * fee is hereby granted, provided that the above copyright
7722+ * notice appear in all copies. The University of California
7723+ * makes no representations about the suitability of this
7724+ * software for any purpose. It is provided "as is" without
7725+ * express or implied warranty.
7726+ */
7727+
7728+//#include <ctype.h>
7729+
7730+/*
7731+ * The table below is used to convert from ASCII digits to a
7732+ * numerical equivalent. It maps from '0' through 'z' to integers
7733+ * (100 for non-digit characters).
7734+ */
7735+
7736+static char cvtIn[] = {
7737+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* '0' - '9' */
7738+ 100, 100, 100, 100, 100, 100, 100, /* punctuation */
7739+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, /* 'A' - 'Z' */
7740+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
7741+ 30, 31, 32, 33, 34, 35,
7742+ 100, 100, 100, 100, 100, 100, /* punctuation */
7743+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, /* 'a' - 'z' */
7744+ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
7745+ 30, 31, 32, 33, 34, 35};
7746+
7747+/*
7748+ *----------------------------------------------------------------------
7749+ *
7750+ * strtoul --
7751+ *
7752+ * Convert an ASCII string into an integer.
7753+ *
7754+ * Results:
7755+ * The return value is the integer equivalent of string. If endPtr
7756+ * is non-NULL, then *endPtr is filled in with the character
7757+ * after the last one that was part of the integer. If string
7758+ * doesn't contain a valid integer value, then zero is returned
7759+ * and *endPtr is set to string.
7760+ *
7761+ * Side effects:
7762+ * None.
7763+ *
7764+ *----------------------------------------------------------------------
7765+ */
7766+
7767+unsigned long int
7768+strtoul(char *string, char **endPtr, int base)
7769+ /* string; String of ASCII digits, possibly
7770+ * preceded by white space. For bases
7771+ * greater than 10, either lower- or
7772+ * upper-case digits may be used.
7773+ */
7774+ /* **endPtr; Where to store address of terminating
7775+ * character, or NULL. */
7776+ /* base; Base for conversion. Must be less
7777+ * than 37. If 0, then the base is chosen
7778+ * from the leading characters of string:
7779+ * "0x" means hex, "0" means octal, anything
7780+ * else means decimal.
7781+ */
7782+{
7783+ register char *p;
7784+ register unsigned long int result = 0;
7785+ register unsigned digit;
7786+ int anyDigits = 0;
7787+
7788+ /*
7789+ * Skip any leading blanks.
7790+ */
7791+
7792+ p = string;
7793+ while (isspace(*p)) {
7794+ p += 1;
7795+ }
7796+
7797+ /*
7798+ * If no base was provided, pick one from the leading characters
7799+ * of the string.
7800+ */
7801+
7802+ if (base == 0)
7803+ {
7804+ if (*p == '0') {
7805+ p += 1;
7806+ if (*p == 'x') {
7807+ p += 1;
7808+ base = 16;
7809+ } else {
7810+
7811+ /*
7812+ * Must set anyDigits here, otherwise "0" produces a
7813+ * "no digits" error.
7814+ */
7815+
7816+ anyDigits = 1;
7817+ base = 8;
7818+ }
7819+ }
7820+ else base = 10;
7821+ } else if (base == 16) {
7822+
7823+ /*
7824+ * Skip a leading "0x" from hex numbers.
7825+ */
7826+
7827+ if ((p[0] == '0') && (p[1] == 'x')) {
7828+ p += 2;
7829+ }
7830+ }
7831+
7832+ /*
7833+ * Sorry this code is so messy, but speed seems important. Do
7834+ * different things for base 8, 10, 16, and other.
7835+ */
7836+
7837+ if (base == 8) {
7838+ for ( ; ; p += 1) {
7839+ digit = *p - '0';
7840+ if (digit > 7) {
7841+ break;
7842+ }
7843+ result = (result << 3) + digit;
7844+ anyDigits = 1;
7845+ }
7846+ } else if (base == 10) {
7847+ for ( ; ; p += 1) {
7848+ digit = *p - '0';
7849+ if (digit > 9) {
7850+ break;
7851+ }
7852+ result = (10*result) + digit;
7853+ anyDigits = 1;
7854+ }
7855+ } else if (base == 16) {
7856+ for ( ; ; p += 1) {
7857+ digit = *p - '0';
7858+ if (digit > ('z' - '0')) {
7859+ break;
7860+ }
7861+ digit = cvtIn[digit];
7862+ if (digit > 15) {
7863+ break;
7864+ }
7865+ result = (result << 4) + digit;
7866+ anyDigits = 1;
7867+ }
7868+ } else {
7869+ for ( ; ; p += 1) {
7870+ digit = *p - '0';
7871+ if (digit > ('z' - '0')) {
7872+ break;
7873+ }
7874+ digit = cvtIn[digit];
7875+ if (digit >= base) {
7876+ break;
7877+ }
7878+ result = result*base + digit;
7879+ anyDigits = 1;
7880+ }
7881+ }
7882+
7883+ /*
7884+ * See if there were any digits at all.
7885+ */
7886+
7887+ if (!anyDigits) {
7888+ p = string;
7889+ }
7890+
7891+ if (endPtr != 0) {
7892+ *endPtr = p;
7893+ }
7894+
7895+ return result;
7896+}
7897+
7898+// -----------------------------------------------------------------------------
7899+int atoi( char s[] )
7900+{
7901+
7902+ int i;
7903+ int ans = 0;
7904+
7905+ for( i = 0; s[i] >= '0' && s[i] <= '9'; ++i )
7906+ ans = ( 10 * ans ) + ( s[i] - '0' );
7907+
7908+ return ans;
7909+}
7910+
7911+// -----------------------------------------------------------------------------
7912+/* rand:return pseudo-random integer on 0...32767 */
7913+int rand(void)
7914+{
7915+ static unsigned long int next = 1;
7916+
7917+ next = next * 1103515245 + 12345;
7918+
7919+ return (unsigned int) ( next / 65536 ) % 32768;
7920+}
7921+
7922+#endif // End SLT_UBOOT
7923diff --git a/arch/arm/cpu/arm926ejs/aspeed/STRESS.c b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c
7924new file mode 100644
7925index 0000000..dffd64f
7926--- /dev/null
7927+++ b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c
7928@@ -0,0 +1,145 @@
7929+/*
7930+ * This program is distributed in the hope that it will be useful,
7931+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7932+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7933+ * GNU General Public License for more details.
7934+ *
7935+ * You should have received a copy of the GNU General Public License
7936+ * along with this program; if not, write to the Free Software
7937+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7938+ */
7939+#define STRESS_C
7940+static const char ThisFile[] = "STRESS.c";
7941+
7942+#include "SWFUNC.H"
7943+#include <COMMINF.H>
7944+#include <IO.H>
7945+
7946+#define TIMEOUT_DRAM 5000000
7947+
7948+/* ------------------------------------------------------------------------- */
7949+int MMCTestBurst(unsigned int datagen)
7950+{
7951+ unsigned int data;
7952+ unsigned int timeout = 0;
7953+
7954+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
7955+ WriteSOC_DD( 0x1E6E0070, (0x000000C1 | (datagen << 3)) );
7956+
7957+ do {
7958+ data = ReadSOC_DD( 0x1E6E0070 ) & 0x3000;
7959+
7960+ if( data & 0x2000 )
7961+ return(0);
7962+
7963+ if( ++timeout > TIMEOUT_DRAM ) {
7964+ printf("Timeout!!\n");
7965+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
7966+
7967+ return(0);
7968+ }
7969+ } while( !data );
7970+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
7971+
7972+ return(1);
7973+}
7974+
7975+/* ------------------------------------------------------------------------- */
7976+int MMCTestSingle(unsigned int datagen)
7977+{
7978+ unsigned int data;
7979+ unsigned int timeout = 0;
7980+
7981+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
7982+ WriteSOC_DD( 0x1E6E0070, (0x00000085 | (datagen << 3)) );
7983+
7984+ do {
7985+ data = ReadSOC_DD( 0x1E6E0070 ) & 0x3000;
7986+
7987+ if( data & 0x2000 )
7988+ return(0);
7989+
7990+ if( ++timeout > TIMEOUT_DRAM ){
7991+ printf("Timeout!!\n");
7992+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
7993+
7994+ return(0);
7995+ }
7996+ } while ( !data );
7997+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
7998+
7999+ return(1);
8000+}
8001+
8002+/* ------------------------------------------------------------------------- */
8003+int MMCTest()
8004+{
8005+ unsigned int pattern;
8006+
8007+ pattern = ReadSOC_DD( 0x1E6E2078 );
8008+ printf("Pattern = %08X : ",pattern);
8009+
8010+ WriteSOC_DD(0x1E6E0074, (DRAM_MapAdr | 0x7fffff) );
8011+ WriteSOC_DD(0x1E6E007C, pattern );
8012+
8013+ if(!MMCTestBurst(0)) return(0);
8014+ if(!MMCTestBurst(1)) return(0);
8015+ if(!MMCTestBurst(2)) return(0);
8016+ if(!MMCTestBurst(3)) return(0);
8017+ if(!MMCTestBurst(4)) return(0);
8018+ if(!MMCTestBurst(5)) return(0);
8019+ if(!MMCTestBurst(6)) return(0);
8020+ if(!MMCTestBurst(7)) return(0);
8021+ if(!MMCTestSingle(0)) return(0);
8022+ if(!MMCTestSingle(1)) return(0);
8023+ if(!MMCTestSingle(2)) return(0);
8024+ if(!MMCTestSingle(3)) return(0);
8025+ if(!MMCTestSingle(4)) return(0);
8026+ if(!MMCTestSingle(5)) return(0);
8027+ if(!MMCTestSingle(6)) return(0);
8028+ if(!MMCTestSingle(7)) return(0);
8029+
8030+ return(1);
8031+}
8032+
8033+/* ------------------------------------------------------------------------- */
8034+int dram_stress_function(int argc, char *argv[])
8035+{
8036+ unsigned int Pass;
8037+ unsigned int PassCnt = 0;
8038+ unsigned int Testcounter = 0;
8039+ int ret = 1;
8040+ char *stop_at;
8041+
8042+ printf("**************************************************** \n");
8043+ printf("*** ASPEED Stress DRAM *** \n");
8044+ printf("*** 20131107 for u-boot *** \n");
8045+ printf("**************************************************** \n");
8046+ printf("\n");
8047+
8048+ if ( argc != 2 ){
8049+ ret = 0;
8050+ return ( ret );
8051+ }
8052+ else {
8053+ Testcounter = (unsigned int) strtoul(argv[1], &stop_at, 10);
8054+ }
8055+
8056+ WriteSOC_DD(0x1E6E0000, 0xFC600309);
8057+
8058+ while( ( Testcounter > PassCnt ) || ( Testcounter == 0 ) ){
8059+ if( !MMCTest() ) {
8060+ printf("FAIL...%d/%d\n", PassCnt, Testcounter);
8061+ ret = 0;
8062+
8063+ break;
8064+ }
8065+ else {
8066+ PassCnt++;
8067+ printf("Pass %d/%d\n", PassCnt, Testcounter);
8068+ }
8069+ } // End while()
8070+
8071+ return( ret );
8072+}
8073+
8074diff --git a/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H b/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H
8075new file mode 100644
8076index 0000000..0a03654
8077--- /dev/null
8078+++ b/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H
8079@@ -0,0 +1,137 @@
8080+/*
8081+ * This program is distributed in the hope that it will be useful,
8082+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
8083+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8084+ * GNU General Public License for more details.
8085+ *
8086+ * You should have received a copy of the GNU General Public License
8087+ * along with this program; if not, write to the Free Software
8088+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8089+ */
8090+#ifndef SWFUNC_H
8091+#define SWFUNC_H
8092+
8093+
8094+//---------------------------------------------------------
8095+// Program information
8096+//---------------------------------------------------------
8097+#define VER_NAME "Ver 0.34 version @2014/03/25 0932"
8098+
8099+/* == Step 1: ====== Support OS system =================== */
8100+// LinuxAP
8101+// #define Windows
8102+#define SLT_UBOOT
8103+//#define SLT_DOS
8104+
8105+/* == Step 2:======== Support interface ================== */
8106+/* Choose One */
8107+//#define SPI_BUS
8108+//#define USE_LPC
8109+//#define USE_P2A // PCI or PCIe bus to AHB bus
8110+
8111+/* == Step 3:========== Support Chip ================== */
8112+//#define AST1010_CHIP
8113+//#define AST3200_IOMAP
8114+//#define FPGA
8115+
8116+#ifdef AST1010_CHIP
8117+ #ifdef SLT_UBOOT
8118+ #define AST1010_IOMAP 1
8119+ #endif
8120+ #ifdef SLT_DOS
8121+ #define AST1010_IOMAP 2
8122+
8123+ // AST1010 only has LPC interface
8124+ #undef USE_P2A
8125+ #undef SPI_BUS
8126+ #define USE_LPC
8127+ #endif
8128+#endif
8129+
8130+/* == Step 4:========== Select PHY ================== */
8131+//#define SUPPORT_PHY_LAN9303 // Initial PHY via I2C bus
8132+#define LAN9303_I2C_BUSNUM 6 // 1-based
8133+#define LAN9303_I2C_ADR 0x14
8134+
8135+/* ====================== Program ======================== */
8136+// The "PHY_NCSI" option is only for DOS compiler
8137+#if defined (PHY_NCSI)
8138+ #ifdef SLT_UBOOT
8139+ #error Wrong setting......
8140+ #endif
8141+#endif
8142+
8143+#if defined (PHY_NCSI)
8144+ #ifdef SUPPORT_PHY_LAN9303
8145+ #error Wrong setting (Can't support LAN9303)......
8146+ #endif
8147+#endif
8148+
8149+/* ================= Check setting ===================== */
8150+#ifdef SLT_UBOOT
8151+ #ifdef SLT_DOS
8152+ #error Can NOT support two OS
8153+ #endif
8154+#endif
8155+#ifdef SLT_DOS
8156+ #ifdef SLT_UBOOT
8157+ #error Can NOT support two OS
8158+ #endif
8159+#endif
8160+
8161+#ifdef USE_P2A
8162+ #ifdef SLT_UBOOT
8163+ #error Can NOT be set PCI bus in Uboot
8164+ #endif
8165+#endif
8166+#ifdef USE_LPC
8167+ #ifdef SLT_UBOOT
8168+ #error Can NOT be set LPC bus in Uboot
8169+ #endif
8170+#endif
8171+#ifdef SPI_BUS
8172+ #ifdef SLT_UBOOT
8173+ #error Can NOT be set SPI bus in Uboot
8174+ #endif
8175+#endif
8176+
8177+/* ======================== Program flow control ======================== */
8178+#define RUN_STEP 5
8179+// 0: read_scu
8180+// 1: parameter setup
8181+// 2: init_scu1,
8182+// 3: init_scu_macrst
8183+// 4: Data Initial
8184+// 5: ALL
8185+
8186+/* ====================== Switch print debug message ====================== */
8187+#define DbgPrn_Enable_Debug_delay 0
8188+//#define DbgPrn_FuncHeader 0 //1
8189+#define DbgPrn_ErrFlg 0
8190+#define DbgPrn_BufAdr 0 //1
8191+#define DbgPrn_Bufdat 0
8192+#define DbgPrn_BufdatDetail 0
8193+#define DbgPrn_PHYRW 0
8194+#define DbgPrn_PHYInit 0
8195+#define DbgPrn_PHYName 0
8196+#define DbgPrn_DumpMACCnt 0
8197+#define DbgPrn_Info 0 //1
8198+#define DbgPrn_FRAME_LEN 0
8199+
8200+
8201+/* ============ Enable or Disable Check item of the descriptor ============ */
8202+#define CheckRxOwn
8203+#define CheckRxErr
8204+//#define CheckOddNibble
8205+#define CheckCRC
8206+#define CheckRxFIFOFull
8207+#define CheckRxLen
8208+//#define CheckDataEveryTime
8209+
8210+//#define CheckRxbufUNAVA
8211+#define CheckRPktLost
8212+//#define CheckNPTxbufUNAVA
8213+#define CheckTPktLost
8214+#define CheckRxBuf
8215+
8216+#endif // SWFUNC_H
8217diff --git a/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c
8218new file mode 100644
8219index 0000000..72936c0
8220--- /dev/null
8221+++ b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c
8222@@ -0,0 +1,151 @@
8223+/*
8224+ * This program is distributed in the hope that it will be useful,
8225+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
8226+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8227+ * GNU General Public License for more details.
8228+ *
8229+ * You should have received a copy of the GNU General Public License
8230+ * along with this program; if not, write to the Free Software
8231+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8232+ */
8233+#define PLLTEST_C
8234+static const char ThisFile[] = "PLLTEST.c";
8235+
8236+#include "SWFUNC.H"
8237+
8238+#include <COMMINF.H>
8239+#include <TYPEDEF.H>
8240+#include <IO.H>
8241+
8242+#define ASTCHIP_2400 0
8243+#define ASTCHIP_2300 1
8244+#define ASTCHIP_1400 2
8245+#define ASTCHIP_1300 3
8246+#define ASTCHIP_1050 4
8247+
8248+const UCHAR jVersion[] = "v.0.60.06";
8249+
8250+typedef struct _TRAPINFO {
8251+ USHORT CPU_clk;
8252+ UCHAR CPU_AHB_ratio;
8253+} _TrapInfo;
8254+
8255+const _TrapInfo AST_default_trap_setting[] = {
8256+ // CPU_clk, CPU_AHB_ratio
8257+ { 384, 2 }, // AST2400 or AST1250 ( ASTCHIP_2400 )
8258+ { 384, 2 }, // AST2300 ( ASTCHIP_2300 )
8259+ { 384, 0xFF }, // AST1400 ( ASTCHIP_1400 )
8260+ { 384, 0xFF }, // AST1300 ( ASTCHIP_1300 )
8261+ { 384, 2 } // AST1050 ( ASTCHIP_1050 )
8262+};
8263+
8264+int trap_function(int argc, char *argv[])
8265+{
8266+ UCHAR chiptype;
8267+ ULONG ulData, ulTemp;
8268+ UCHAR status = TRUE;
8269+ USHORT val_trap;
8270+
8271+ printf("**************************************************** \n");
8272+ printf("*** ASPEED Trap Test %s Log *** \n", jVersion);
8273+ printf("*** for u-boot *** \n");
8274+ printf("**************************************************** \n");
8275+ printf("\n");
8276+
8277+ // Check chip type
8278+ switch ( ReadSOC_DD( 0x1e6e2000 + 0x7c ) ) {
8279+ case 0x02010303 :
8280+ case 0x02000303 :
8281+ printf("The chip is AST2400 or AST1250\n" );
8282+ chiptype = ASTCHIP_2400;
8283+ break;
8284+
8285+ case 0x02010103 :
8286+ case 0x02000003 :
8287+ printf("The chip is AST1400\n" );
8288+ chiptype = ASTCHIP_1400;
8289+ break;
8290+
8291+ case 0x01010303 :
8292+ case 0x01000003 :
8293+ printf("The chip is AST2300\n" );
8294+ chiptype = ASTCHIP_2300;
8295+ break;
8296+
8297+ case 0x01010203 :
8298+ printf("The chip is AST1050\n" );
8299+ chiptype = ASTCHIP_1050;
8300+ break;
8301+
8302+ case 0x01010003 :
8303+ printf("The chip is AST1300\n" );
8304+ chiptype = ASTCHIP_1300;
8305+ break;
8306+
8307+ default :
8308+ printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", ReadSOC_DD( 0x1e6e2000 + 0x7c ) );
8309+ return(1);
8310+ }
8311+
8312+ WriteSOC_DD(0x1e6e2000, 0x1688A8A8);
8313+ ulData = ReadSOC_DD(0x1e6e2070);
8314+
8315+ // Check CPU clock
8316+ ulTemp = ulData;
8317+ ulTemp &= 0x0300;
8318+ ulTemp >>= 8;
8319+
8320+ switch (ulTemp)
8321+ {
8322+ case 0x00:
8323+ val_trap = 384;
8324+ break;
8325+ case 0x01:
8326+ val_trap = 360;
8327+ break;
8328+ case 0x02:
8329+ val_trap = 336;
8330+ break;
8331+ case 0x03:
8332+ val_trap = 408;
8333+ break;
8334+ }
8335+
8336+ if (AST_default_trap_setting[chiptype].CPU_clk != val_trap)
8337+ {
8338+ printf("[ERROR] CPU CLK: Correct is %d; Real is %d \n", AST_default_trap_setting[chiptype].CPU_clk, val_trap);
8339+ status = FALSE;
8340+ }
8341+
8342+ // Check cpu_ahb_ratio
8343+ ulTemp = ulData;
8344+ ulTemp &= 0x0c00;
8345+ ulTemp >>= 10;
8346+
8347+ switch (ulTemp)
8348+ {
8349+ case 0x00:
8350+ val_trap = 1;
8351+ break;
8352+ case 0x01:
8353+ val_trap = 2;
8354+ break;
8355+ case 0x02:
8356+ val_trap = 4;
8357+ break;
8358+ case 0x03:
8359+ val_trap = 3;
8360+ break;
8361+ }
8362+
8363+ if (AST_default_trap_setting[chiptype].CPU_AHB_ratio != val_trap)
8364+ {
8365+ printf("[ERROR] CPU:AHB: Correct is %x:1; Real is %x:1 \n", AST_default_trap_setting[chiptype].CPU_AHB_ratio, val_trap);
8366+ status = FALSE;
8367+ }
8368+
8369+ if ( status == TRUE )
8370+ printf("[PASS] hardware trap for CPU clock and CPU\\AHB ratio.\n");
8371+
8372+ return status;
8373+}
8374diff --git a/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H b/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H
8375new file mode 100644
8376index 0000000..3053ad7
8377--- /dev/null
8378+++ b/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H
8379@@ -0,0 +1,74 @@
8380+/*
8381+ * This program is distributed in the hope that it will be useful,
8382+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
8383+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8384+ * GNU General Public License for more details.
8385+ *
8386+ * You should have received a copy of the GNU General Public License
8387+ * along with this program; if not, write to the Free Software
8388+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8389+ */
8390+#ifndef TYPEDEF_H
8391+#define TYPEDEF_H
8392+
8393+#include "SWFUNC.H"
8394+
8395+//
8396+// Define
8397+//
8398+#define PCI 1
8399+#define PCIE 2
8400+#define AGP 3
8401+#define ACTIVE 4
8402+
8403+#if defined(LinuxAP)
8404+ #ifndef FLONG
8405+ #define FLONG unsigned long
8406+ #endif
8407+ #ifndef ULONG
8408+ #define ULONG unsigned long
8409+ #endif
8410+ #ifndef LONG
8411+ #define LONG long
8412+ #endif
8413+ #ifndef USHORT
8414+ #define USHORT unsigned short
8415+ #endif
8416+ #ifndef SHORT
8417+ #define SHORT short
8418+ #endif
8419+ #ifndef UCHAR
8420+ #define UCHAR unsigned char
8421+ #endif
8422+ #ifndef CHAR
8423+ #define CHAR char
8424+ #endif
8425+ #ifndef BYTE
8426+ #define BYTE unsigned char
8427+ #endif
8428+ #ifndef VOID
8429+ #define VOID void
8430+ #endif
8431+ #ifndef SCHAR
8432+ #define SCHAR signed char
8433+ #endif
8434+#else
8435+/* DOS Program */
8436+ #define VOID void
8437+ #define FLONG unsigned long
8438+ #define ULONG unsigned long
8439+ #define USHORT unsigned short
8440+ #define UCHAR unsigned char
8441+ #define LONG long
8442+ #define SHORT short
8443+ #define CHAR char
8444+ #define BYTE UCHAR
8445+ #define BOOL SHORT
8446+ #define BOOLEAN unsigned short
8447+ #define PULONG ULONG *
8448+ #define SCHAR signed char
8449+#endif
8450+ #define TRUE 1
8451+ #define FALSE 0
8452+
8453+#endif // TYPEDEF_H
8454diff --git a/arch/arm/cpu/arm926ejs/aspeed/mactest.c b/arch/arm/cpu/arm926ejs/aspeed/mactest.c
8455new file mode 100644
8456index 0000000..95bd560
8457--- /dev/null
8458+++ b/arch/arm/cpu/arm926ejs/aspeed/mactest.c
8459@@ -0,0 +1,1215 @@
8460+/*
8461+ * This program is distributed in the hope that it will be useful,
8462+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
8463+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8464+ * GNU General Public License for more details.
8465+ *
8466+ * You should have received a copy of the GNU General Public License
8467+ * along with this program; if not, write to the Free Software
8468+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8469+ */
8470+#define MACTEST_C
8471+static const char ThisFile[] = "MACTEST.c";
8472+
8473+#include "SWFUNC.H"
8474+
8475+#ifdef SLT_UBOOT
8476+ #include <common.h>
8477+ #include <command.h>
8478+ #include <post.h>
8479+ #include <malloc.h>
8480+ #include <net.h>
8481+ #include <COMMINF.H>
8482+ #include <STDUBOOT.H>
8483+ #include <IO.H>
8484+#else
8485+ #include <stdlib.h>
8486+ #include <string.h>
8487+ #include "LIB.H"
8488+ #include "COMMINF.H"
8489+ #include "IO.H"
8490+#endif
8491+
8492+const BYTE Val_Array[16] = {0,1, 2,3, 4,5, 6,7, 8,9, 10,11, 12,13, 14,15}; // AST2300-A1
8493+const BYTE Val_Array_A0[16] = {8,1, 10,3, 12,5, 14,7, 0,9, 2,11, 4,13, 6,15}; // AST2300-A0
8494+
8495+#ifdef SLT_UBOOT
8496+int main_function(int argc, char *argv[])
8497+#endif
8498+#ifdef SLT_DOS
8499+int main(int argc, char *argv[])
8500+#endif
8501+{
8502+ CHAR MAC2_Valid;
8503+ CHAR MAC_1GEn;
8504+ CHAR MAC1_RMII;
8505+ CHAR Enable_IntLoopPHY;
8506+ CHAR Disable_RecovPHY;
8507+ CHAR Force1G;
8508+ CHAR Force10M;
8509+ CHAR Force100M;
8510+ CHAR *stop_at;
8511+ ULONG IOStr_val;
8512+ ULONG IOStr_max;
8513+ ULONG IOStr_shf;
8514+ ULONG IOdly_val;
8515+ ULONG Err_Flag_allapeed;
8516+ int DES_LowNumber;
8517+ int index;
8518+ int i;
8519+ int j;
8520+ #ifdef Enable_NCSI_LOOP_INFINI
8521+ BYTE GSpeed_org[3];
8522+ #endif
8523+
8524+#ifdef SPI_BUS
8525+ VIDEO_ENGINE_INFO VideoEngineInfo;
8526+#else
8527+ // ( USE_P2A | USE_LPC )
8528+ UCHAR *ulMMIOLinearBaseAddress;
8529+#endif
8530+
8531+ #ifdef SLT_UBOOT
8532+ #else
8533+ time(&timestart);
8534+ #endif
8535+
8536+ // For DOS system
8537+ #if defined(PHY_NCSI)
8538+ // For DOS compiler OPEN WATCOM
8539+ ModeSwitch = MODE_NSCI;
8540+ #else
8541+ #ifdef SLT_DOS
8542+ ModeSwitch = MODE_DEDICATED;
8543+ #endif
8544+ #endif
8545+
8546+//------------------------------------------------------------
8547+// Argument Initial
8548+//------------------------------------------------------------
8549+ Err_Flag_allapeed = 0;
8550+ Err_Flag = 0;
8551+ Err_Flag_PrintEn = 1;
8552+ Loop_rl[0] = 0;
8553+ Loop_rl[1] = 0;
8554+ Loop_rl[2] = 0;
8555+
8556+//------------------------------------------------------------
8557+// Bus Initial
8558+//------------------------------------------------------------
8559+#if defined(LinuxAP)
8560+#else
8561+ //DOS system
8562+ #ifdef SPI_BUS
8563+ #endif
8564+ #ifdef USE_LPC
8565+
8566+ if ( findlpcport( 0x0d ) == 0) {
8567+ printf("Failed to find proper LPC port \n");
8568+
8569+ return(1);
8570+ }
8571+ open_aspeed_sio_password();
8572+ enable_aspeed_LDU( 0x0d );
8573+ #endif
8574+ #ifdef USE_P2A
8575+ // PCI bus
8576+ #ifdef DOS_PMODEW
8577+ if (CheckDOS()) return 1;
8578+ #endif
8579+
8580+ #ifdef DbgPrn_FuncHeader
8581+ printf ("Initial-MMIO\n");
8582+ Debug_delay();
8583+ #endif
8584+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, ACTIVE);
8585+ if ( ulPCIBaseAddress == 0 )
8586+ ulPCIBaseAddress = FindPCIDevice (0x1688, 0x2000, ACTIVE);
8587+ if ( ulPCIBaseAddress == 0 )
8588+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x0200, ACTIVE);
8589+ if ( ulPCIBaseAddress == 0 )
8590+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x3000, ACTIVE);
8591+ if ( ulPCIBaseAddress == 0 )
8592+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2010, ACTIVE);
8593+ if ( ulPCIBaseAddress == 0 ) {
8594+ printf ("Can't find device\n");
8595+
8596+ return(1);
8597+ }
8598+
8599+ WritePCIReg (ulPCIBaseAddress, 0x04, 0xFFFFFFFc, 0x3);
8600+ ulMMIOBaseAddress = ReadPCIReg (ulPCIBaseAddress, 0x14, 0xFFFF0000);
8601+ ulMMIOLinearBaseAddress = (UCHAR *)MapPhysicalToLinear (ulMMIOBaseAddress, 64 * 1024 * 1024);
8602+ #endif // #ifdef USE_P2A
8603+#endif // End defined(LinuxAP)
8604+
8605+#ifdef SPI_BUS
8606+ GetDevicePCIInfo (&VideoEngineInfo);
8607+ mmiobase = VideoEngineInfo.VGAPCIInfo.ulMMIOBaseAddress;
8608+ spim_init(SPI_CS);
8609+#else
8610+ // ( USE_P2A | USE_LPC )
8611+ mmiobase = ulMMIOLinearBaseAddress;
8612+#endif
8613+
8614+//------------------------------------------------------------
8615+// Check Chip Feature
8616+//------------------------------------------------------------
8617+ read_scu();
8618+
8619+ if (RUN_STEP >= 1) {
8620+ switch (SCU_7ch_old) {
8621+// case 0x02000003 : sprintf(ASTChipName, "[ ]AST3200-FPGA" ); ASTChipType = 6; AST1100 = 0; break;
8622+
8623+ case 0x03020003 : sprintf(ASTChipName, "[ ]AST1010-A2" ); ASTChipType = 5; AST1100 = 0; break;
8624+ case 0x03010003 : sprintf(ASTChipName, "[ ]AST1010-A1" ); ASTChipType = 5; AST1100 = 0; break;
8625+ case 0x03000003 : sprintf(ASTChipName, "[*]AST1010-A0" ); ASTChipType = 5; AST1100 = 0; break;
8626+
8627+ case 0x02010303 : sprintf(ASTChipName, "[*]AST2400-A1" ); ASTChipType = 4; AST1100 = 0; break;//AST2400-A1
8628+ case 0x02000303 : sprintf(ASTChipName, "[ ]AST2400-A0" ); ASTChipType = 4; AST1100 = 0; break;//AST2400-A0
8629+ case 0x02010103 : sprintf(ASTChipName, "[*]AST1400-A1" ); ASTChipType = 4; AST1100 = 0; break;//AST1400-A1
8630+ case 0x02000003 : sprintf(ASTChipName, "[ ]AST1400-A0" ); ASTChipType = 4; AST1100 = 0; break;//AST1400-A0
8631+
8632+ case 0x01010303 : sprintf(ASTChipName, "[*]AST2300-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST2300-A1
8633+ case 0x01010203 : sprintf(ASTChipName, "[*]AST1050-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST1050-A1
8634+ case 0x01010003 : sprintf(ASTChipName, "[*]AST1300-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST1300-A1
8635+ case 0x01000003 : sprintf(ASTChipName, "[ ]AST2300-A0" ); ASTChipType = 3; AST1100 = 0; break;//AST2300-A0
8636+// case 0x01860003 : sprintf(ASTChipName, "[ ]AST2300-FPGA" ); ASTChipType = 3; AST1100 = 0; break;
8637+
8638+ case 0x00000102 : sprintf(ASTChipName, "[*]AST2200-A1" ); ASTChipType = 2; AST1100 = 0; break;//AST2200-A1/A0
8639+
8640+ case 0x00000302 : sprintf(ASTChipName, "[*]AST2100-A3" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A3/A2
8641+ case 0x00000301 : sprintf(ASTChipName, "[ ]AST2100-A1" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A1
8642+ case 0x00000300 : sprintf(ASTChipName, "[ ]AST2100-A0" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A0
8643+ case 0x00000202 : sprintf(ASTChipName, "[*]AST2050/AST1100-A3, AST2150-A1"); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A3/A2 AST2150-A1/A0
8644+ case 0x00000201 : sprintf(ASTChipName, "[ ]AST2050/AST1100-A1" ); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A1
8645+ case 0x00000200 : sprintf(ASTChipName, "[ ]AST2050/AST1100-A0" ); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A0
8646+
8647+ default :
8648+ printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", SCU_7ch_old);
8649+ return(1);
8650+ } // End switch (SCU_7ch_old)
8651+
8652+ switch (ASTChipType) {
8653+ case 6 : AST2300 = 1; AST2400 = 1; AST1010 = 0; AST3200 = 1; break;
8654+ case 5 : AST2300 = 1; AST2400 = 1; AST1010 = 1; AST3200 = 0; break;
8655+ case 4 : AST2300 = 1; AST2400 = 1; AST1010 = 0; AST3200 = 0; break;
8656+ case 3 : AST2300 = 1; AST2400 = 0; AST1010 = 0; AST3200 = 0; break;
8657+ default : AST2300 = 0; AST2400 = 0; AST1010 = 0; AST3200 = 0; break;
8658+ } // End switch (ASTChipType)
8659+
8660+ if (ASTChipType == 3) {
8661+#ifdef Force_Enable_MAC34
8662+ WriteSOC_DD( SCU_BASE + 0xf0, 0xAEED0001 ); //enable mac34
8663+ Enable_MAC34 = 1;
8664+#else
8665+ if (SCU_f0h_old & 0x00000001)
8666+ Enable_MAC34 = 1;
8667+ else
8668+ Enable_MAC34 = 0;
8669+#endif
8670+ }
8671+ else {
8672+ Enable_MAC34 = 0;
8673+ } // End if (ASTChipType == 3)
8674+
8675+ Setting_scu();
8676+
8677+//------------------------------------------------------------
8678+// Argument Input
8679+//------------------------------------------------------------
8680+ // Load default value
8681+ UserDVal = DEF_USER_DEF_PACKET_VAL;
8682+ IOTimingBund_arg = DEF_IOTIMINGBUND;
8683+ PHY_ADR_arg = DEF_PHY_ADR;
8684+ TestMode = DEF_TESTMODE;
8685+ LOOP_INFINI = 0;
8686+ LOOP_MAX_arg = 0;
8687+ GCtrl = ( DEF_MAC_LOOP_BACK << 6 ) | ( DEF_SKIP_CHECK_PHY << 5 ) | ( DEF_INIT_PHY << 3 );
8688+ GSpeed = DEF_SPEED;
8689+
8690+ // Get setting information by user
8691+ GRun_Mode = (BYTE)atoi(argv[1]);
8692+
8693+ if ( ModeSwitch == MODE_NSCI ) {
8694+ ARPNumCnt = DEF_ARPNUMCNT;
8695+ ChannelTolNum = DEF_CHANNEL2NUM;
8696+ PackageTolNum = DEF_PACKAGE2NUM;
8697+ GSpeed = SET_100MBPS; // In NCSI mode, we set to 100M bps
8698+ }
8699+
8700+ // Setting user's configuration
8701+ if (argc > 1) {
8702+ if ( ModeSwitch == MODE_NSCI )
8703+ switch (argc) {
8704+ case 7: ARPNumCnt = (ULONG)atoi(argv[6]);
8705+ case 6: IOTimingBund_arg = (BYTE)atoi(argv[5]);
8706+ case 5: TestMode = (BYTE)atoi(argv[4]);
8707+ case 4: ChannelTolNum = (BYTE)atoi(argv[3]);
8708+ case 3: PackageTolNum = (BYTE)atoi(argv[2]);
8709+ default: break;
8710+ }
8711+ else
8712+ switch (argc) {
8713+ case 9: UserDVal = strtoul (argv[8], &stop_at, 16);
8714+ case 8: IOTimingBund_arg = (BYTE)atoi(argv[7]);
8715+ case 7: PHY_ADR_arg = (BYTE)atoi(argv[6]);
8716+ case 6: TestMode = (BYTE)atoi(argv[5]);
8717+ case 5: strcpy(LOOP_Str, argv[4]);
8718+ if (!strcmp(LOOP_Str, "#")) LOOP_INFINI = 1;
8719+ else LOOP_MAX_arg = (ULONG)atoi(LOOP_Str);
8720+ case 4: GCtrl = (BYTE)atoi(argv[3]);
8721+ case 3: GSpeed = (BYTE)atoi(argv[2]);
8722+ default: break;
8723+ }
8724+
8725+ IOTimingBund = IOTimingBund_arg;
8726+ PHY_ADR = PHY_ADR_arg;
8727+ }
8728+ else {
8729+ // Wrong parameter
8730+ if ( ModeSwitch == MODE_NSCI ) {
8731+ if (AST2300)
8732+ printf ("\nNCSITEST.exe run_mode <package_num> <channel_num> <test_mode> <IO margin>\n\n");
8733+ else
8734+ printf ("\nNCSITEST.exe run_mode <package_num> <channel_num> <test_mode>\n\n");
8735+ PrintMode ();
8736+ PrintPakNUm();
8737+ PrintChlNUm();
8738+ PrintTest ();
8739+ if (AST2300)
8740+ PrintIOTimingBund ();
8741+ }
8742+ else {
8743+ if (AST2300)
8744+ printf ("\nMACTEST.exe run_mode <speed> <ctrl> <loop_max> <test_mode> <phy_adr> <IO margin>\n\n");
8745+ else
8746+ printf ("\nMACTEST.exe run_mode <speed> <ctrl> <loop_max> <test_mode> <phy_adr>\n\n");
8747+ PrintMode ();
8748+ PrintSpeed ();
8749+ PrintCtrl ();
8750+ PrintLoop ();
8751+ PrintTest ();
8752+ PrintPHYAdr ();
8753+ if (AST2300)
8754+ PrintIOTimingBund ();
8755+ }
8756+ Finish_Close();
8757+
8758+ return(1);
8759+ } // End if (argc > 1)
8760+
8761+//------------------------------------------------------------
8762+// Check Argument
8763+//------------------------------------------------------------
8764+ switch ( GRun_Mode ) {
8765+ case 0: printf ("\n[MAC1]\n"); SelectMAC = 0; H_MAC_BASE = MAC_BASE1; break;
8766+ case 1: printf ("\n[MAC2]\n"); SelectMAC = 1; H_MAC_BASE = MAC_BASE2; break;
8767+ case 2: if (Enable_MAC34) {printf ("\n[MAC3]\n"); SelectMAC = 2; H_MAC_BASE = MAC_BASE3; break;}
8768+ else
8769+ goto Error_MAC_Mode;
8770+ case 3: if (Enable_MAC34) {printf ("\n[MAC4]\n"); SelectMAC = 3; H_MAC_BASE = MAC_BASE4; break;}
8771+ else
8772+ goto Error_MAC_Mode;
8773+ default:
8774+Error_MAC_Mode:
8775+ printf ("Error run_mode!!!\n");
8776+ PrintMode ();
8777+
8778+ return(1);
8779+ } // End switch ( GRun_Mode )
8780+
8781+ H_TDES_BASE = TDES_BASE1;
8782+ H_RDES_BASE = RDES_BASE1;
8783+ MAC_PHYBASE = H_MAC_BASE;
8784+
8785+ Force1G = 0;
8786+ Force10M = 0;
8787+ Force100M = 0;
8788+ GSpeed_sel[0] = 0;//1G
8789+ GSpeed_sel[1] = 0;//100M
8790+ GSpeed_sel[2] = 0;//10M
8791+
8792+ switch ( GSpeed ) {
8793+ case SET_1GBPS : Force1G = 1; GSpeed_sel[0] = 1; break;
8794+ case SET_100MBPS : Force100M = 1; GSpeed_sel[1] = 1; break;
8795+ case SET_10MBPS : Force10M = 1; GSpeed_sel[2] = 1; break;
8796+ case SET_1G_100M_10MBPS : break;
8797+ default: printf ("Error speed!!!\n");
8798+ PrintSpeed ();
8799+ return(1);
8800+ } // End switch ( GSpeed )
8801+
8802+ if ( ModeSwitch == MODE_NSCI ) {
8803+ Enable_MACLoopback = 0; // For mactest function
8804+ Enable_SkipChkPHY = 0; // For mactest function
8805+ Enable_IntLoopPHY = 0; // For mactest function
8806+ Enable_InitPHY = 0; // For mactest function
8807+ Disable_RecovPHY = 0; // For mactest function
8808+ BurstEnable = 0; // For mactest function
8809+
8810+ PrintNCSIEn = (ARPNumCnt & 0x1);
8811+ ARPNumCnt = ARPNumCnt & 0xfffffffe;
8812+
8813+ // Check parameter
8814+ if ((PackageTolNum < 1) || (PackageTolNum > 8)) {
8815+ PrintPakNUm();
8816+ return(1);
8817+ }
8818+// if ((ChannelTolNum < 0) || (ChannelTolNum > 32)) {
8819+ if (ChannelTolNum > 32) {
8820+ PrintChlNUm();
8821+ return(1);
8822+ }
8823+
8824+ switch (TestMode) {
8825+ case 0 : NCSI_DiSChannel = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break;
8826+ case 1 : NCSI_DiSChannel = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break;
8827+ case 6 : if (AST2300) {NCSI_DiSChannel = 1; IOTiming = 1; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break;}
8828+ else
8829+ goto Error_Test_Mode_NCSI;
8830+ case 7 : if (AST2300) {NCSI_DiSChannel = 1; IOTiming = 1; IOStrength = 1; TxDataEnable = 1; RxDataEnable = 1; break;}
8831+ else
8832+ goto Error_Test_Mode_NCSI;
8833+ default:
8834+ // Wrong parameter
8835+Error_Test_Mode_NCSI:
8836+ printf ("Error test_mode!!!\n");
8837+ PrintTest ();
8838+ return(1);
8839+ } // End switch (TestMode)
8840+ }
8841+ else {
8842+ if ( GCtrl & 0xffffff83 ) {
8843+ printf ("Error ctrl!!!\n");
8844+ PrintCtrl ();
8845+ return(1);
8846+ }
8847+ else {
8848+ Enable_MACLoopback = ( GCtrl >> 6 ) & 0x1; // ??
8849+ Enable_SkipChkPHY = ( GCtrl >> 5 ) & 0x1; // ??
8850+ Enable_IntLoopPHY = ( GCtrl >> 4 ) & 0x1;
8851+ Enable_InitPHY = ( GCtrl >> 3 ) & 0x1;
8852+ Disable_RecovPHY = ( GCtrl >> 2 ) & 0x1; // ??
8853+
8854+ if (!AST2400 && Enable_MACLoopback) {
8855+ printf ("Error ctrl!!!\n");
8856+ PrintCtrl ();
8857+ return(1);
8858+ }
8859+ } // End if ( GCtrl & 0xffffff83 )
8860+
8861+ if (!LOOP_MAX_arg) {
8862+ switch (GSpeed) {
8863+ case SET_1GBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 200; break; // 20140325
8864+ case SET_100MBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 20 ; break; // 20140325
8865+ case SET_10MBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 10 ; break; // 20140325
8866+ case SET_1G_100M_10MBPS: LOOP_MAX_arg = DEF_LOOP_MAX * 10 ; break; // 20140325
8867+ }
8868+ } // End if (!LOOP_MAX_arg)
8869+
8870+ LOOP_MAX = LOOP_MAX_arg * 10; // 20140325
8871+ Calculate_LOOP_CheckNum();
8872+
8873+ switch (TestMode) {
8874+ case 0 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break;
8875+ case 1 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break;
8876+ case 2 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break;
8877+ case 3 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break;
8878+ case 4 : BurstEnable = 1; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ??
8879+ case 5 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ??
8880+ case 6 : if (AST2300) {BurstEnable = 0; IEEETesting = 0; IOTiming = 1; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break;}
8881+ else
8882+ goto Error_Test_Mode;
8883+ case 7 : if (AST2300) {BurstEnable = 0; IEEETesting = 0; IOTiming = 1; IOStrength = 1; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break;}
8884+ else
8885+ goto Error_Test_Mode;
8886+ case 8 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ??
8887+ case 9 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 0; RxDataEnable = 1; DataDelay = 0; break; // ??
8888+ case 10 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 1; break; // ??
8889+ default:
8890+Error_Test_Mode:
8891+ printf ("Error test_mode!!!\n");
8892+ PrintTest ();
8893+ return(1);
8894+ } // End switch (TestMode)
8895+
8896+ if ( PHY_ADR > 31 ) {
8897+ printf ("Error phy_adr!!!\n");
8898+ PrintPHYAdr ();
8899+ return(1);
8900+ } // End if (PHY_ADR > 31)
8901+ } // End if ( ModeSwitch == MODE_NSCI )
8902+
8903+ if ( BurstEnable ) {
8904+ IOTimingBund = 0;
8905+ }
8906+ else {
8907+ if ( ~DataDelay && AST2300 ) {
8908+ if ( !( ( (7 >= IOTimingBund) && (IOTimingBund & 0x1) ) ||
8909+ ( IOTimingBund == 0 ) ) ) {
8910+ printf ("Error IO margin!!!\n");
8911+ PrintIOTimingBund ();
8912+ return(1);
8913+ }
8914+ }
8915+ else {
8916+ IOTimingBund = 0;
8917+ } // End if ( ~DataDelay && AST2300 )
8918+
8919+ // Define Output file name
8920+ if ( ModeSwitch == MODE_NSCI )
8921+ sprintf(FileNameMain, "%d", SelectMAC+1);
8922+ else {
8923+ if (Enable_IntLoopPHY)
8924+ sprintf(FileNameMain, "%dI", SelectMAC+1);
8925+ else
8926+ sprintf(FileNameMain, "%dE", SelectMAC+1);
8927+ }
8928+
8929+ #ifndef SLT_UBOOT
8930+ if ( IOTiming ) {
8931+ if ( IOStrength )
8932+ sprintf(FileName, "MIOD%sS.log", FileNameMain);
8933+ else
8934+ sprintf(FileName, "MIOD%s.log", FileNameMain);
8935+
8936+ fp_log = fopen(FileName,"w");
8937+
8938+ if ( IOStrength )
8939+ sprintf(FileName, "MIO%sS.log", FileNameMain);
8940+ else
8941+ sprintf(FileName, "MIO%s.log", FileNameMain);
8942+
8943+ fp_io = fopen(FileName,"w");
8944+ }
8945+ else {
8946+ sprintf(FileName, "MAC%s.log", FileNameMain);
8947+
8948+ fp_log = fopen(FileName,"w");
8949+ }
8950+ #endif
8951+ } // End if (BurstEnable)
8952+
8953+//------------------------------------------------------------
8954+// Check Definition
8955+//------------------------------------------------------------
8956+ for (i = 0; i < 16; i++)
8957+ valary[i] = Val_Array[i];
8958+
8959+ if ( AST3200 ) {
8960+ MAC_Mode = (SCU_70h_old >> 6) & 0x1;
8961+ MAC1_1GEn = (MAC_Mode & 0x1) ? 1 : 0;//1:RGMII, 0:RMII
8962+ MAC2_1GEn = 0;
8963+
8964+ MAC1_RMII = !MAC1_1GEn;
8965+ MAC2_RMII = 0;
8966+ MAC2_Valid = 0;
8967+ }
8968+ else if ( AST1010 ) {
8969+ MAC_Mode = 0;
8970+ MAC1_1GEn = 0;
8971+ MAC2_1GEn = 0;
8972+
8973+ MAC1_RMII = 1;
8974+ MAC2_RMII = 0;
8975+ MAC2_Valid = 0;
8976+ }
8977+ else if ( AST2300 ) {
8978+ if (SCU_7ch_old == 0x01000003) {
8979+ //AST2300-A0
8980+ for (i = 0; i < 16; i++) {
8981+ valary[i] = Val_Array_A0[i];
8982+ }
8983+ }
8984+
8985+ MAC_Mode = (SCU_70h_old >> 6) & 0x3;
8986+ MAC1_1GEn = (MAC_Mode & 0x1) ? 1 : 0;//1:RGMII, 0:RMII
8987+ MAC2_1GEn = (MAC_Mode & 0x2) ? 1 : 0;//1:RGMII, 0:RMII
8988+
8989+ MAC1_RMII = !MAC1_1GEn;
8990+ MAC2_RMII = !MAC2_1GEn;
8991+ MAC2_Valid = 1;
8992+ }
8993+ else {
8994+ MAC_Mode = (SCU_70h_old >> 6) & 0x7;
8995+ MAC1_1GEn = (MAC_Mode == 0x0) ? 1 : 0;
8996+ MAC2_1GEn = 0;
8997+
8998+ switch ( MAC_Mode ) {
8999+ case 0 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //000: Select GMII(MAC#1) only
9000+ case 1 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 1; break; //001: Select MII (MAC#1) and MII(MAC#2)
9001+ case 2 : MAC1_RMII = 1; MAC2_RMII = 0; MAC2_Valid = 1; break; //010: Select RMII(MAC#1) and MII(MAC#2)
9002+ case 3 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //011: Select MII (MAC#1) only
9003+ case 4 : MAC1_RMII = 1; MAC2_RMII = 0; MAC2_Valid = 0; break; //100: Select RMII(MAC#1) only
9004+// case 5 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //101: Reserved
9005+ case 6 : MAC1_RMII = 1; MAC2_RMII = 1; MAC2_Valid = 1; break; //110: Select RMII(MAC#1) and RMII(MAC#2)
9006+// case 7 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //111: Disable dual MAC
9007+ default: return(Finish_Check(Err_MACMode));
9008+ }
9009+ } // End if ( AST3200 )
9010+
9011+ if ( SelectMAC == 0 ) {
9012+ Enable_RMII = MAC1_RMII;
9013+ MAC_1GEn = MAC1_1GEn;
9014+
9015+ if ( Force1G & !MAC1_1GEn ) {
9016+ printf ("\nMAC1 don't support 1Gbps !!!\n");
9017+ return( Finish_Check(Err_MACMode) );
9018+ }
9019+ } else if (SelectMAC == 1) {
9020+ Enable_RMII = MAC2_RMII;
9021+ MAC_1GEn = MAC2_1GEn;
9022+
9023+ if ( Force1G & !MAC2_1GEn ) {
9024+ printf ("\nMAC2 don't support 1Gbps !!!\n");
9025+ return(Finish_Check(Err_MACMode));
9026+ }
9027+ if ( !MAC2_Valid ) {
9028+ printf ("\nMAC2 not valid !!!\n");
9029+ return(Finish_Check(Err_MACMode));
9030+ }
9031+ }
9032+ else {
9033+ Enable_RMII = 1;
9034+ MAC_1GEn = 0;
9035+
9036+ if (Force1G) {
9037+ printf ("\nMAC3/MAC4 don't support 1Gbps !!!\n");
9038+ return(Finish_Check(Err_MACMode));
9039+ }
9040+ } // End if ( SelectMAC == 0 )
9041+
9042+ if ( ModeSwitch == MODE_NSCI ) {
9043+ if (!Enable_RMII) {
9044+ printf ("\nNCSI must be RMII interface !!!\n");
9045+ return(Finish_Check(Err_MACMode));
9046+ }
9047+ }
9048+
9049+ if ( GSpeed == SET_1G_100M_10MBPS ) {
9050+ GSpeed_sel[0] = MAC_1GEn;
9051+ GSpeed_sel[1] = 1;
9052+ GSpeed_sel[2] = 1;
9053+ }
9054+
9055+ if ( AST1010 ) {
9056+ // Check bit 13:12
9057+ Dat_ULONG = SCU_08h_old & 0x00003000;
9058+ if (Dat_ULONG != 0x00000000)
9059+ return(Finish_Check(Err_MHCLK_Ratio));
9060+ }
9061+ else if ( AST2300 ) {
9062+ Dat_ULONG = (SCU_08h_old >> 16) & 0x7;
9063+ if (MAC1_1GEn | MAC2_1GEn) {
9064+ if ( (Dat_ULONG == 0) || (Dat_ULONG > 2) )
9065+ return(Finish_Check(Err_MHCLK_Ratio));
9066+ }
9067+ else {
9068+ if (Dat_ULONG != 4)
9069+ return(Finish_Check(Err_MHCLK_Ratio));
9070+ }
9071+ } // End if (AST1010)
9072+
9073+ //MAC
9074+ MAC_08h_old = ReadSOC_DD( H_MAC_BASE + 0x08 );
9075+ MAC_0ch_old = ReadSOC_DD( H_MAC_BASE + 0x0c );
9076+ MAC_40h_old = ReadSOC_DD( H_MAC_BASE + 0x40 );
9077+
9078+ if ( ((MAC_08h_old == 0x0000) && (MAC_0ch_old == 0x00000000))
9079+ || ((MAC_08h_old == 0xffff) && (MAC_0ch_old == 0xffffffff))
9080+// || (MAC_0ch_old & 0x1)
9081+// || (MAC_0ch_old & 0x2)
9082+ )
9083+ {
9084+ // Load default for MAC address
9085+ SA[0] = 0x00;
9086+ SA[1] = 0x57;
9087+ SA[2] = 0x89;
9088+ SA[3] = 0x56;
9089+ SA[4] = 0x88;
9090+ SA[5] = 0x38;
9091+ }
9092+ else {
9093+ SA[0] = (MAC_08h_old >> 8) & 0xff;
9094+ SA[1] = (MAC_08h_old ) & 0xff;
9095+ SA[2] = (MAC_0ch_old >> 24) & 0xff;
9096+ SA[3] = (MAC_0ch_old >> 16) & 0xff;
9097+ SA[4] = (MAC_0ch_old >> 8) & 0xff;
9098+ SA[5] = (MAC_0ch_old ) & 0xff;
9099+ }
9100+ // printf ("%08x %08x: %02x %02x %02x %02x %02x %02x\n", MAC_08h_old, MAC_0ch_old, SA[0], SA[1], SA[2], SA[3], SA[4], SA[5]);
9101+
9102+ if ( AST2300 ) {
9103+#ifdef Force_Enable_NewMDIO
9104+ AST2300_NewMDIO = 1;
9105+ WriteSOC_DD(H_MAC_BASE+0x40, MAC_40h_old | 0x80000000)
9106+#else
9107+ AST2300_NewMDIO = (MAC_40h_old & 0x80000000) ? 1 : 0;
9108+#endif
9109+ }
9110+ else {
9111+ AST2300_NewMDIO = 0;
9112+ } // End if (AST2300)
9113+
9114+//------------------------------------------------------------
9115+// Parameter Initial
9116+//------------------------------------------------------------
9117+ if ( AST3200 ) {
9118+ SCU_04h = 0x0c000800; //Reset Engine
9119+ }
9120+ else if (AST1010) {
9121+ SCU_04h = 0x00000010; //Reset Engine
9122+ }
9123+ else if (AST2300) {
9124+ SCU_04h = 0x0c001800; //Reset Engine
9125+ }
9126+ else {
9127+ SCU_04h = 0x00001800; //Reset Engine
9128+ } // End if ( AST3200 )
9129+
9130+ if ( ModeSwitch == MODE_NSCI )
9131+ // Set to 100Mbps and Enable RX broabcast packets and CRC_APD and Full duplex
9132+ MAC_50h = 0x000a0500;
9133+ else {
9134+ // RX_ALLADR and CRC_APD and Full duplex
9135+ MAC_50h = 0x00004500;
9136+
9137+ #ifdef Enable_Runt
9138+ MAC_50h = MAC_50h | 0x00001000;
9139+ #endif
9140+
9141+ #ifdef Enable_Jumbo
9142+ MAC_50h = MAC_50h | 0x00002000;
9143+ #endif
9144+ } // End if ( ModeSwitch == MODE_NSCI )
9145+
9146+//------------------------------------------------------------
9147+// Descriptor Number
9148+//------------------------------------------------------------
9149+ if ( ModeSwitch == MODE_DEDICATED ) {
9150+
9151+ #ifdef Enable_Jumbo
9152+ DES_LowNumber = 1;
9153+ #else
9154+ DES_LowNumber = IOTiming;
9155+ #endif
9156+ if ( Enable_SkipChkPHY && ( TestMode == 0 ) ) {
9157+ DES_NUMBER = 114;//for SMSC's LAN9303 issue
9158+ }
9159+ else {
9160+ if ( AST1010 | AST3200 ) {
9161+ DES_NUMBER = (IOTimingBund) ? 100 : 256;
9162+ }
9163+ else {
9164+ switch ( GSpeed ) {
9165+ case SET_1GBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 50 : 400; break; // 20140325
9166+ case SET_100MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 50 : 400; break; // 20140325
9167+ case SET_10MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 10 : 80; break; // 20140325
9168+ case SET_1G_100M_10MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 10 : 80; break; // 20140325
9169+ }
9170+ } // End if ( Enable_SkipChkPHY && ( TestMode == 0 ) )
9171+ }
9172+
9173+ #ifdef SelectDesNumber
9174+ DES_NUMBER = SelectDesNumber;
9175+ #endif
9176+
9177+ #ifdef USE_LPC
9178+ DES_NUMBER /= 8;
9179+ #endif
9180+
9181+ #ifdef ENABLE_ARP_2_WOL
9182+ if ( TestMode == 4 ) {
9183+ DES_NUMBER = 1;
9184+ }
9185+ #endif
9186+
9187+ DES_NUMBER_Org = DES_NUMBER;
9188+
9189+ if ( DbgPrn_Info ) {
9190+ printf ("CheckBuf_MBSize : %ld\n", CheckBuf_MBSize);
9191+ printf ("LOOP_CheckNum : %ld\n", LOOP_CheckNum);
9192+ printf ("DES_NUMBER : %ld\n", DES_NUMBER);
9193+ printf ("DMA_BufSize : %ld bytes\n", DMA_BufSize);
9194+ printf ("DMA_BufNum : %d\n", DMA_BufNum);
9195+ printf ("\n");
9196+ }
9197+// if (3 > DMA_BufNum)
9198+// return( Finish_Check(Err_DMABufNum) );
9199+
9200+ if (2 > DMA_BufNum)
9201+ return( Finish_Check(Err_DMABufNum) );
9202+ } // End if ( ModeSwitch == MODE_DEDICATED )
9203+ } // End if (RUN_STEP >= 1)
9204+
9205+//------------------------------------------------------------
9206+// SCU Initial
9207+//------------------------------------------------------------
9208+ if ( RUN_STEP >= 2 ) {
9209+ init_scu1();
9210+ }
9211+
9212+ if ( RUN_STEP >= 3 ) {
9213+ init_scu_macrst();
9214+ }
9215+
9216+//------------------------------------------------------------
9217+// Data Initial
9218+//------------------------------------------------------------
9219+ if (RUN_STEP >= 4) {
9220+ setup_arp();
9221+ if ( ModeSwitch == MODE_DEDICATED ) {
9222+
9223+ FRAME_LEN = (ULONG *)malloc(DES_NUMBER * sizeof( ULONG ));
9224+ wp_lst = (ULONG *)malloc(DES_NUMBER * sizeof( ULONG ));
9225+
9226+ if ( !FRAME_LEN )
9227+ return( Finish_Check( Err_MALLOC_FrmSize ) );
9228+
9229+ if ( !wp_lst )
9230+ return( Finish_Check( Err_MALLOC_LastWP ));
9231+
9232+ // Setup data and length
9233+ TestingSetup();
9234+ } // End if ( ModeSwitch == MODE_DEDICATED )
9235+
9236+ // Get bit (shift) of IO driving strength register
9237+ if ( IOStrength ) {
9238+ if (AST1010) {
9239+ IOStr_max = 1;//0~1
9240+ }
9241+ else if (AST2400) {
9242+ IOStr_max = 1;//0~1
9243+ switch (SelectMAC) {
9244+ case 0 : IOStr_shf = 9; break;
9245+ case 1 : IOStr_shf = 11; break;
9246+ }
9247+ }
9248+ else {
9249+ IOStr_max = 3;//0~3
9250+ switch (SelectMAC) {
9251+ case 0 : IOStr_shf = 8; break;
9252+ case 1 : IOStr_shf = 10; break;
9253+ case 2 : IOStr_shf = 12; break;
9254+ case 3 : IOStr_shf = 14; break;
9255+ }
9256+ }
9257+ }
9258+ else {
9259+ IOStr_max = 0;
9260+ IOStr_shf = 0;
9261+ } // End if (IOStrength)
9262+
9263+ // Get current clock delay value of TX(out) and RX(in) in the SCU48 register
9264+ // and setting test range
9265+ if ( Enable_RMII ) {
9266+ switch (GRun_Mode) {
9267+ case 0 : IOdly_out_shf = 24; IOdly_in_shf = 8; break;
9268+ case 1 : IOdly_out_shf = 25; IOdly_in_shf = 12; break;
9269+ case 2 : IOdly_out_shf = 26; IOdly_in_shf = 16; break;
9270+ case 3 : IOdly_out_shf = 27; IOdly_in_shf = 20; break;
9271+ }
9272+ IOdly_in_reg = (SCU_48h_old >> IOdly_in_shf ) & 0xf;
9273+ IOdly_out_reg = (SCU_48h_old >> IOdly_out_shf) & 0x1;
9274+ }
9275+ else {
9276+ switch (GRun_Mode) {
9277+ case 0 : IOdly_out_shf = 0; IOdly_in_shf = 8; break;
9278+ case 1 : IOdly_out_shf = 4; IOdly_in_shf = 12; break;
9279+ }
9280+ IOdly_in_reg = (SCU_48h_old >> IOdly_in_shf ) & 0xf;
9281+ IOdly_out_reg = (SCU_48h_old >> IOdly_out_shf) & 0xf;
9282+ } // End if ( Enable_RMII )
9283+
9284+ // Find the coordinate in X-Y axis
9285+ for ( index = 0; index <= 15; index++ )
9286+ if ( IOdly_in_reg == valary[index] ) {
9287+ IOdly_in_reg_idx = index;
9288+ break;
9289+ }
9290+ for ( index = 0; index <= 15; index++ )
9291+ if ( IOdly_out_reg == valary[index] ) {
9292+ IOdly_out_reg_idx = index;
9293+ break;
9294+ }
9295+
9296+ // Get the range for testmargin block
9297+ if ( IOTiming ) {
9298+ if ( Enable_RMII ) {
9299+ IOdly_incval = 1;
9300+ IOdly_in_str = 0;
9301+ IOdly_in_end = 15;
9302+ IOdly_out_str = 0;
9303+ IOdly_out_end = 1;
9304+ }
9305+ else {
9306+ IOdly_incval = 1;
9307+ IOdly_in_str = 0;
9308+ IOdly_in_end = 15;
9309+ IOdly_out_str = 0;
9310+ IOdly_out_end = 15;
9311+ }
9312+ }
9313+ else if ( IOTimingBund ) {
9314+ if ( Enable_RMII ) {
9315+ IOdly_incval = 1;
9316+ IOdly_in_str = IOdly_in_reg_idx - ( IOTimingBund >> 1 );
9317+ IOdly_in_end = IOdly_in_reg_idx + ( IOTimingBund >> 1 );
9318+ IOdly_out_str = IOdly_out_reg_idx;
9319+ IOdly_out_end = IOdly_out_reg_idx;
9320+ }
9321+ else {
9322+ IOdly_incval = 1;
9323+ IOdly_in_str = IOdly_in_reg_idx - ( IOTimingBund >> 1 );
9324+ IOdly_in_end = IOdly_in_reg_idx + ( IOTimingBund >> 1 );
9325+ IOdly_out_str = IOdly_out_reg_idx - ( IOTimingBund >> 1 );
9326+ IOdly_out_end = IOdly_out_reg_idx + ( IOTimingBund >> 1 );
9327+ }
9328+ if ((IOdly_in_str < 0) || (IOdly_in_end > 15))
9329+ return( Finish_Check( Err_IOMarginOUF ) );
9330+
9331+ if ((IOdly_out_str < 0) || (IOdly_out_end > 15))
9332+ return( Finish_Check( Err_IOMarginOUF ) );
9333+
9334+// if (IOdly_in_str < 0) IOdly_in_str = 0;
9335+// if (IOdly_in_end > 15) IOdly_in_end = 15;
9336+// if (IOdly_out_str < 0) IOdly_out_str = 0;
9337+// if (IOdly_out_end > 15) IOdly_out_end = 15;
9338+ }
9339+ else {
9340+ IOdly_incval = 1;
9341+ IOdly_in_str = 0;
9342+ IOdly_in_end = 0;
9343+ IOdly_out_str = 0;
9344+ IOdly_out_end = 0;
9345+ } // End if (IOTiming)
9346+ } // End if (RUN_STEP >= 4)
9347+
9348+//------------------------------------------------------------
9349+// main
9350+//------------------------------------------------------------
9351+ if (RUN_STEP >= 5) {
9352+ #ifdef DbgPrn_FuncHeader
9353+ printf ("GSpeed_sel: %d %d %d\n", GSpeed_sel[0], GSpeed_sel[1], GSpeed_sel[2]);
9354+ Debug_delay();
9355+ #endif
9356+
9357+ if ( ModeSwitch == MODE_NSCI ) {
9358+ #ifdef Enable_NCSI_LOOP_INFINI
9359+ for ( GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++ ) {
9360+ GSpeed_org[GSpeed_idx] = GSpeed_sel[GSpeed_idx];
9361+ }
9362+NCSI_LOOP_INFINI:;
9363+ for ( GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++ ) {
9364+ GSpeed_sel[GSpeed_idx] = GSpeed_org[GSpeed_idx];
9365+ }
9366+ #endif
9367+ } // End if ( ModeSwitch == MODE_NSCI )
9368+
9369+ for (GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++) {
9370+ Err_Flag_PrintEn = 1;
9371+ if ( GSpeed_sel[GSpeed_idx] ) {
9372+ // Setting the LAN speed
9373+ if ( ModeSwitch == MODE_DEDICATED ) {
9374+
9375+
9376+ // Test three speed of LAN, we will modify loop number
9377+ if (GSpeed == SET_1G_100M_10MBPS) {
9378+ if (GSpeed_sel[0]) LOOP_MAX = LOOP_MAX_arg;
9379+ else if (GSpeed_sel[1]) LOOP_MAX = LOOP_MAX_arg / 10;
9380+ else LOOP_MAX = LOOP_MAX_arg / 100;
9381+
9382+ if ( !LOOP_MAX )
9383+ LOOP_MAX = 1;
9384+
9385+ Calculate_LOOP_CheckNum();
9386+ }
9387+
9388+ // Setting speed of LAN
9389+ if (GSpeed_sel[0]) MAC_50h_Speed = 0x00000200;
9390+ else if (GSpeed_sel[1]) MAC_50h_Speed = 0x00080000;
9391+ else MAC_50h_Speed = 0x00000000;
9392+
9393+ //------------------------------------------------------------
9394+ // PHY Initial
9395+ //------------------------------------------------------------
9396+ if ( AST1100 )
9397+ init_scu2();
9398+
9399+ if ( Enable_InitPHY ) {
9400+#ifdef SUPPORT_PHY_LAN9303
9401+ LAN9303(LAN9303_I2C_BUSNUM, PHY_ADR_arg, GSpeed_idx, Enable_IntLoopPHY | (BurstEnable<<1) | IEEETesting);
9402+#else
9403+ init_phy( Enable_IntLoopPHY );
9404+#endif
9405+ DELAY( Delay_PHYRst * 10 );
9406+ } // End if (Enable_InitPHY)
9407+
9408+ if ( AST1100 )
9409+ init_scu3();
9410+
9411+ if ( Err_Flag )
9412+ return( Finish_Check( 0 ) );
9413+ } // End if ( ModeSwitch == MODE_DEDICATED )
9414+
9415+ //------------------------------------------------------------
9416+ // Start
9417+ //------------------------------------------------------------
9418+
9419+ // The loop is for different IO strength
9420+ for ( IOStr_i = 0; IOStr_i <= IOStr_max; IOStr_i++ ) {
9421+
9422+ // Print Header of report to monitor and log file
9423+ if ( IOTiming || IOTimingBund ) {
9424+ if ( IOStrength ) {
9425+ if ( AST1010 ) {
9426+ IOStr_val = (SCU_ach_old & 0xfff0ffff) | ((IOStr_i) ? 0xf0000 : 0x0);
9427+ }
9428+ else {
9429+ IOStr_val = (SCU_90h_old & 0xffff00ff) | (IOStr_i << IOStr_shf);
9430+ }
9431+ //printf("\nIOStrength_val= %08x, ", IOStr_val);
9432+ //printf("SCU90h: %08x ->", ReadSOC_DD(SCU_BASE+0x90));
9433+ WriteSOC_DD( SCU_BASE + 0x90, IOStr_val );
9434+ //printf(" %08x\n", ReadSOC_DD(SCU_BASE+0x90));
9435+
9436+ #ifndef SLT_UBOOT
9437+ if (GSpeed_sel[0]) fprintf(fp_log, "[Strength %d][1G ]========================================\n", IOStr_i);
9438+ else if (GSpeed_sel[1]) fprintf(fp_log, "[Strength %d][100M]========================================\n", IOStr_i);
9439+ else fprintf(fp_log, "[Strength %d][10M ]========================================\n", IOStr_i);
9440+ #endif
9441+ }
9442+ else {
9443+ #ifndef SLT_UBOOT
9444+ if (GSpeed_sel[0]) fprintf(fp_log, "[1G ]========================================\n");
9445+ else if (GSpeed_sel[1]) fprintf(fp_log, "[100M]========================================\n");
9446+ else fprintf(fp_log, "[10M ]========================================\n");
9447+ #endif
9448+ }
9449+
9450+ if ( IOTimingBund )
9451+ PrintIO_Header(FP_LOG);
9452+ if ( IOTiming )
9453+ PrintIO_Header(FP_IO);
9454+
9455+ PrintIO_Header(STD_OUT);
9456+
9457+ }
9458+ else {
9459+ if ( ModeSwitch == MODE_DEDICATED ) {
9460+
9461+ if (!BurstEnable)
9462+ Print_Header(FP_LOG);
9463+
9464+ Print_Header(STD_OUT);
9465+ }
9466+ } // End if (IOTiming || IOTimingBund)
9467+
9468+#ifdef Enable_Old_Style
9469+ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
9470+ IOdly_in = valary[IOdly_i];
9471+#else
9472+ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
9473+ IOdly_out = valary[IOdly_j];
9474+#endif
9475+
9476+ if (IOTiming || IOTimingBund) {
9477+#ifdef Enable_Fast_SCU
9478+ #ifdef Enable_Old_Style
9479+ WriteSOC_DD(SCU_BASE + 0x48, SCU_48h_mix | (IOdly_in << IOdly_in_shf));
9480+ #else
9481+ WriteSOC_DD(SCU_BASE + 0x48, SCU_48h_mix | (IOdly_out << IOdly_out_shf));
9482+ #endif
9483+#endif
9484+
9485+ if ( IOTimingBund )
9486+ PrintIO_LineS(FP_LOG);
9487+ if ( IOTiming )
9488+ PrintIO_LineS(FP_IO);
9489+
9490+ PrintIO_LineS(STD_OUT);
9491+ } // End if (IOTiming || IOTimingBund)
9492+
9493+ //------------------------------------------------------------
9494+ // SCU Initial
9495+ //------------------------------------------------------------
9496+#ifdef Enable_Fast_SCU
9497+ init_scu_macrst();
9498+#endif
9499+#ifdef Enable_Old_Style
9500+ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
9501+ IOdly_out = valary[IOdly_j];
9502+#else
9503+ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
9504+ IOdly_in = valary[IOdly_i];
9505+#endif
9506+ if ( IOTiming || IOTimingBund ) {
9507+ IOdly_val = (IOdly_in << IOdly_in_shf) | (IOdly_out << IOdly_out_shf);
9508+
9509+//printf("\nIOdly_val= %08x, ", IOdly_val);
9510+//printf("SCU48h: %08x ->", ReadSOC_DD( SCU_BASE + 0x48 ) );
9511+ WriteSOC_DD( SCU_BASE + 0x48, SCU_48h_mix | IOdly_val );
9512+//printf(" %08x\n", ReadSOC_DD(SCU_BASE+0x48));
9513+ } // End if (IOTiming || IOTimingBund)
9514+
9515+ //------------------------------------------------------------
9516+ // SCU Initial
9517+ //------------------------------------------------------------
9518+#ifdef Enable_Fast_SCU
9519+#else
9520+ init_scu_macrst();
9521+#endif
9522+
9523+ //------------------------------------------------------------
9524+ // MAC Initial
9525+ //------------------------------------------------------------
9526+ init_mac(H_MAC_BASE, H_TDES_BASE, H_RDES_BASE);
9527+ if ( Err_Flag )
9528+ return( Finish_Check(0) );
9529+
9530+ // Testing
9531+ if ( ModeSwitch == MODE_NSCI )
9532+ dlymap[IOdly_i][IOdly_j] = phy_ncsi();
9533+ else
9534+ dlymap[IOdly_i][IOdly_j] = TestingLoop(LOOP_CheckNum);
9535+
9536+
9537+ // Display to Log file and monitor
9538+ if ( IOTiming || IOTimingBund ) {
9539+
9540+ if ( IOTimingBund )
9541+ PrintIO_Line(FP_LOG);
9542+
9543+ if ( IOTiming )
9544+ PrintIO_Line(FP_IO);
9545+
9546+ PrintIO_Line(STD_OUT);
9547+
9548+ // Find the range of current setting
9549+ if ( ( IOdly_in_reg == IOdly_in ) && ( IOdly_out_reg == IOdly_out ) ) {
9550+ IOdly_i_min = IOdly_i - ( IOTimingBund >> 1 );
9551+ IOdly_i_max = IOdly_i + ( IOTimingBund >> 1 );
9552+
9553+ if ( Enable_RMII ) {
9554+ IOdly_j_min = IOdly_j;
9555+ IOdly_j_max = IOdly_j;
9556+ }
9557+ else {
9558+ IOdly_j_min = IOdly_j - (IOTimingBund >> 1 );
9559+ IOdly_j_max = IOdly_j + (IOTimingBund >> 1 );
9560+ }
9561+ }
9562+
9563+ PrintIO_Line_LOG();
9564+ FPri_ErrFlag(FP_LOG);
9565+
9566+// Err_Flag_allapeed = Err_Flag_allapeed | Err_Flag;
9567+ Err_Flag = 0;
9568+ }
9569+ }// End for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval)
9570+#ifndef SLT_UBOOT
9571+ if ( IOTiming || IOTimingBund ) {
9572+ if ( IOTimingBund )
9573+ fprintf(fp_log, "\n");
9574+ if (IOTiming )
9575+ fprintf(fp_io, "\n");
9576+ }
9577+#endif
9578+ printf("\n");
9579+ } // End for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval)
9580+
9581+ //------------------------------------------------------------
9582+ // End
9583+ //------------------------------------------------------------
9584+
9585+ if ( IOTiming || IOTimingBund ) {
9586+ if ( ( IOdly_i_min < 0 ) || ( IOdly_i_max > 15 ) )
9587+ FindErr(Err_IOMarginOUF);
9588+ if ( ( IOdly_j_min < 0 ) || ( IOdly_j_max > 15 ) )
9589+ FindErr(Err_IOMarginOUF);
9590+
9591+ if ( IOdly_i_min < 0 ) IOdly_i_min = 0;
9592+ if ( IOdly_i_max > 15 ) IOdly_i_max = 15;
9593+ if ( IOdly_j_min < 0 ) IOdly_j_min = 0;
9594+ if ( IOdly_j_max > 15 ) IOdly_j_max = 15;
9595+
9596+#ifdef Enable_Old_Style
9597+ for (IOdly_i = IOdly_i_min; IOdly_i <= IOdly_i_max; IOdly_i++)
9598+ for (IOdly_j = IOdly_j_min; IOdly_j <= IOdly_j_max; IOdly_j++)
9599+#else
9600+ for (IOdly_j = IOdly_j_min; IOdly_j <= IOdly_j_max; IOdly_j++)
9601+ for (IOdly_i = IOdly_i_min; IOdly_i <= IOdly_i_max; IOdly_i++)
9602+#endif
9603+ {
9604+ if ( dlymap[IOdly_i][IOdly_j] ) {
9605+#ifdef SLT_DOS
9606+ if ( IOTiming ) {
9607+#ifdef Enable_Old_Style
9608+ for (i = IOdly_i_min; i <= IOdly_i_max; i++)
9609+#else
9610+ for (j = IOdly_j_min; j <= IOdly_j_max; j++)
9611+#endif
9612+ {
9613+#ifdef Enable_Old_Style
9614+ for (j = IOdly_j_min; j <= IOdly_j_max; j++)
9615+#else
9616+ for (i = IOdly_i_min; i <= IOdly_i_max; i++)
9617+#endif
9618+ {
9619+ if (dlymap[i][j]) fprintf(fp_io, "x ");
9620+ else fprintf(fp_io, "o ");
9621+ }
9622+ fprintf(fp_io, "\n");
9623+ }
9624+ } // End if ( IOTiming )
9625+#endif // End SLT_DOS
9626+ FindErr(Err_IOMargin);
9627+ goto Find_Err_IOMargin;
9628+ } // End if ( dlymap[IOdly_i][IOdly_j] )
9629+ }
9630+ } // End if ( IOTiming || IOTimingBund )
9631+
9632+Find_Err_IOMargin:;
9633+ if ( !BurstEnable )
9634+ FPri_ErrFlag(FP_LOG);
9635+ if ( IOTiming )
9636+ FPri_ErrFlag(FP_IO);
9637+
9638+ FPri_ErrFlag(STD_OUT);
9639+
9640+ Err_Flag_allapeed = Err_Flag_allapeed | Err_Flag;
9641+ Err_Flag = 0;
9642+ } // End for (IOStr_i = 0; IOStr_i <= IOStr_max; IOStr_i++)
9643+
9644+ if ( ModeSwitch == MODE_DEDICATED ) {
9645+ if ( Enable_InitPHY & !Disable_RecovPHY )
9646+ recov_phy(Enable_IntLoopPHY);
9647+ }
9648+
9649+ GSpeed_sel[GSpeed_idx] = 0;
9650+ } // End if (GSpeed_sel[GSpeed_idx])
9651+
9652+ Err_Flag_PrintEn = 0;
9653+ } // End for (GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++)
9654+
9655+ Err_Flag = Err_Flag_allapeed;
9656+
9657+ if ( ModeSwitch == MODE_NSCI ) {
9658+ #ifdef Enable_NCSI_LOOP_INFINI
9659+ if (Err_Flag == 0) {
9660+ if (fp_log) {
9661+ fclose(fp_log);
9662+ fp_log = fopen(FileName,"w");
9663+ }
9664+ goto NCSI_LOOP_INFINI;
9665+ }
9666+ #endif
9667+ }
9668+
9669+ } // End if (RUN_STEP >= 5)
9670+
9671+ return(Finish_Check(0));
9672+
9673+}
9674+
9675diff --git a/arch/arm/cpu/arm926ejs/aspeed/reset.c b/arch/arm/cpu/arm926ejs/aspeed/reset.c
9676new file mode 100644
9677index 0000000..e0a57f9
9678--- /dev/null
9679+++ b/arch/arm/cpu/arm926ejs/aspeed/reset.c
9680@@ -0,0 +1,24 @@
9681+/*
9682+ * This program is distributed in the hope that it will be useful,
9683+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9684+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9685+ * GNU General Public License for more details.
9686+ *
9687+ * You should have received a copy of the GNU General Public License
9688+ * along with this program; if not, write to the Free Software
9689+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
9690+*/
9691+
9692+#include <common.h>
9693+#include <asm/io.h>
9694+
9695+#define AST_WDT_BASE 0x1e785000
9696+void reset_cpu(ulong addr)
9697+{
9698+ __raw_writel(0x10 , AST_WDT_BASE+0x04);
9699+ __raw_writel(0x4755, AST_WDT_BASE+0x08);
9700+ __raw_writel(0x3, AST_WDT_BASE+0x0c);
9701+
9702+ while (1)
9703+ /*nothing*/;
9704+}
9705diff --git a/arch/arm/cpu/arm926ejs/aspeed/timer.c b/arch/arm/cpu/arm926ejs/aspeed/timer.c
9706new file mode 100644
9707index 0000000..4bba5c5
9708--- /dev/null
9709+++ b/arch/arm/cpu/arm926ejs/aspeed/timer.c
9710@@ -0,0 +1,153 @@
9711+/*
9712+ * This program is free software; you can redistribute it and/or
9713+ * modify it under the terms of the GNU General Public License as
9714+ * published by the Free Software Foundation; either version 2 of
9715+ * the License, or (at your option) any later version.
9716+ *
9717+ * This program is distributed in the hope that it will be useful,
9718+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9719+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9720+ * GNU General Public License for more details.
9721+ *
9722+ * You should have received a copy of the GNU General Public License
9723+ * along with this program; if not, write to the Free Software
9724+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9725+ * MA 02111-1307 USA
9726+ */
9727+
9728+#include <common.h>
9729+#include <arm926ejs.h>
9730+
9731+#define TIMER_LOAD_VAL 0xffffffff
9732+
9733+/* macro to read the 32 bit timer */
9734+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+0))
9735+
9736+static ulong timestamp;
9737+static ulong lastdec;
9738+
9739+int timer_init (void)
9740+{
9741+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 4) = TIMER_LOAD_VAL;
9742+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x30) = 0x3; /* enable timer1 */
9743+
9744+ /* init the timestamp and lastdec value */
9745+ reset_timer_masked();
9746+
9747+ return 0;
9748+}
9749+
9750+/*
9751+ * timer without interrupts
9752+ */
9753+
9754+void reset_timer (void)
9755+{
9756+ reset_timer_masked ();
9757+}
9758+
9759+ulong get_timer (ulong base)
9760+{
9761+ return get_timer_masked () - base;
9762+}
9763+
9764+void set_timer (ulong t)
9765+{
9766+ timestamp = t;
9767+}
9768+
9769+/* delay x useconds AND perserve advance timstamp value */
9770+void udelay (unsigned long usec)
9771+{
9772+ ulong tmo, tmp;
9773+
9774+ if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
9775+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
9776+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
9777+ tmo /= 1000; /* finish normalize. */
9778+ }else{ /* else small number, don't kill it prior to HZ multiply */
9779+ tmo = usec * CONFIG_SYS_HZ;
9780+ tmo /= (1000*1000);
9781+ }
9782+
9783+ tmp = get_timer (0); /* get current timestamp */
9784+ if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
9785+ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
9786+ else
9787+ tmo += tmp; /* else, set advancing stamp wake up time */
9788+
9789+ while (get_timer_masked () < tmo)/* loop till event */
9790+ /*NOP*/;
9791+}
9792+
9793+void reset_timer_masked (void)
9794+{
9795+ /* reset time */
9796+ lastdec = READ_TIMER; /* capure current decrementer value time */
9797+ timestamp = 0; /* start "advancing" time stamp from 0 */
9798+}
9799+
9800+ulong get_timer_masked (void)
9801+{
9802+ ulong now = READ_TIMER; /* current tick value */
9803+
9804+ if (lastdec >= now) { /* normal mode (non roll) */
9805+ /* normal mode */
9806+ timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
9807+ } else { /* we have overflow of the count down timer */
9808+ /* nts = ts + ld + (TLV - now)
9809+ * ts=old stamp, ld=time that passed before passing through -1
9810+ * (TLV-now) amount of time after passing though -1
9811+ * nts = new "advancing time stamp"...it could also roll and cause problems.
9812+ */
9813+ timestamp += lastdec + TIMER_LOAD_VAL - now;
9814+ }
9815+ lastdec = now;
9816+
9817+ return timestamp;
9818+}
9819+
9820+/* waits specified delay value and resets timestamp */
9821+void udelay_masked (unsigned long usec)
9822+{
9823+ ulong tmo;
9824+ ulong endtime;
9825+ signed long diff;
9826+
9827+ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
9828+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
9829+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
9830+ tmo /= 1000; /* finish normalize. */
9831+ } else { /* else small number, don't kill it prior to HZ multiply */
9832+ tmo = usec * CONFIG_SYS_HZ;
9833+ tmo /= (1000*1000);
9834+ }
9835+
9836+ endtime = get_timer_masked () + tmo;
9837+
9838+ do {
9839+ ulong now = get_timer_masked ();
9840+ diff = endtime - now;
9841+ } while (diff >= 0);
9842+}
9843+
9844+/*
9845+ * This function is derived from PowerPC code (read timebase as long long).
9846+ * On ARM it just returns the timer value.
9847+ */
9848+unsigned long long get_ticks(void)
9849+{
9850+ return get_timer(0);
9851+}
9852+
9853+/*
9854+ * This function is derived from PowerPC code (timebase clock frequency).
9855+ * On ARM it returns the number of timer ticks per second.
9856+ */
9857+ulong get_tbclk (void)
9858+{
9859+ ulong tbclk;
9860+
9861+ tbclk = CONFIG_SYS_HZ;
9862+ return tbclk;
9863+}
9864diff --git a/arch/arm/include/asm/arch-aspeed/aspeed_i2c.h b/arch/arm/include/asm/arch-aspeed/aspeed_i2c.h
9865new file mode 100644
9866index 0000000..5419fca
9867--- /dev/null
9868+++ b/arch/arm/include/asm/arch-aspeed/aspeed_i2c.h
9869@@ -0,0 +1,69 @@
9870+/*
9871+ * This program is distributed in the hope that it will be useful,
9872+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9873+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9874+ * GNU General Public License for more details.
9875+ *
9876+ * You should have received a copy of the GNU General Public License
9877+ * along with this program; if not, write to the Free Software
9878+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
9879+ */
9880+#if defined(CONFIG_AST1300)
9881+#define SCU_BASE CONFIG_SCUREG_BASE
9882+#define I2C_BASE CONFIG_I2CREG_BASE
9883+#define I2C_CHANNEL CONFIG_I2C_CHANNEL
9884+#else
9885+#define SCU_BASE 0x1E6E2000
9886+#define I2C_BASE 0x1E78A000
9887+/* Cause U-boot i2c command limitation, it can't assign channel number. Our EEPROM is at channel 3 now*/
9888+/* AST2200's EEPROM is at channel 4 */
9889+#if defined(CONFIG_AST2200) || defined(CONFIG_AST2300) || defined(CONFIG_AST2400)
9890+#define I2C_CHANNEL 4
9891+#else
9892+#define I2C_CHANNEL 3
9893+#endif
9894+#endif
9895+
9896+/* Fix timing for EEPROM 100Khz*/
9897+#define AC_TIMING 0x77743335
9898+#define ALL_CLEAR 0xFFFFFFFF
9899+#define MASTER_ENABLE 0x01
9900+#define SLAVE_ENABLE 0x02
9901+#define LOOP_COUNT 0x100000
9902+#define SCU_RESET_CONTROL 0x04
9903+#define SCU_MULTIFUNCTION_PIN_CTL5_REG 0x90
9904+
9905+/* I2C Register */
9906+#define I2C_FUNCTION_CONTROL_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x00)
9907+#define I2C_AC_TIMING_REGISTER_1 (I2C_BASE + I2C_CHANNEL * 0x40 + 0x04)
9908+#define I2C_AC_TIMING_REGISTER_2 (I2C_BASE + I2C_CHANNEL * 0x40 + 0x08)
9909+#define I2C_INTERRUPT_CONTROL_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x0c)
9910+#define I2C_INTERRUPT_STATUS_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x10)
9911+#define I2C_COMMAND_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x14)
9912+#define I2C_DEVICE_ADDRESS_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x18)
9913+#define I2C_BUFFER_CONTROL_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x1c)
9914+#define I2C_BYTE_BUFFER_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x20)
9915+#define I2C_DMA_CONTROL_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x24)
9916+#define I2C_DMA_STATUS_REGISTER (I2C_BASE + I2C_CHANNEL * 0x40 + 0x28)
9917+
9918+/* Command Bit */
9919+#define MASTER_START_COMMAND (1 << 0)
9920+#define MASTER_TX_COMMAND (1 << 1)
9921+#define MASTER_RX_COMMAND (1 << 3)
9922+#define RX_COMMAND_LIST (1 << 4)
9923+#define MASTER_STOP_COMMAND (1 << 5)
9924+
9925+/* Interrupt Status Bit */
9926+#define TX_ACK (1 << 0)
9927+#define TX_NACK (1 << 1)
9928+#define RX_DONE (1 << 2)
9929+#define STOP_DONE (1 << 4)
9930+
9931+/* Macros to access registers */
9932+#define outb(v,p) *(volatile u8 *) (p) = v
9933+#define outw(v,p) *(volatile u16 *) (p) = v
9934+#define outl(v,p) *(volatile u32 *) (p) = v
9935+
9936+#define inb(p) *(volatile u8 *) (p)
9937+#define inw(p) *(volatile u16 *) (p)
9938+#define inl(p) *(volatile u32 *) (p)
9939diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
9940index 440b041..48fcf2b 100644
9941--- a/arch/arm/include/asm/mach-types.h
9942+++ b/arch/arm/include/asm/mach-types.h
9943@@ -175,6 +175,16 @@ extern unsigned int __machine_arch_type;
9944 #define MACH_TYPE_PALMTX 885
9945 #define MACH_TYPE_S3C2413 887
9946 #define MACH_TYPE_WG302V2 890
9947+#define MACH_TYPE_AST1100 903
9948+#define MACH_TYPE_AST2000 900
9949+#define MACH_TYPE_AST2100 902
9950+#define MACH_TYPE_AST2150 907
9951+#define MACH_TYPE_AST2200 906
9952+#define MACH_TYPE_AST2300_FPGA_1 901
9953+#define MACH_TYPE_AST2300_FPGA_2 901
9954+#define MACH_TYPE_AST2300 901
9955+#define MACH_TYPE_AST3100 901
9956+#define MACH_TYPE_ASPEED 8888
9957 #define MACH_TYPE_OMAP_2430SDP 900
9958 #define MACH_TYPE_DAVINCI_EVM 901
9959 #define MACH_TYPE_PALMZ72 904
9960@@ -840,7 +850,6 @@ extern unsigned int __machine_arch_type;
9961 #define MACH_TYPE_NV1000 3218
9962 #define MACH_TYPE_NUC950TS 3219
9963 #define MACH_TYPE_NOKIA_RM680 3220
9964-#define MACH_TYPE_AST2200 3221
9965 #define MACH_TYPE_LEAD 3222
9966 #define MACH_TYPE_UNINO1 3223
9967 #define MACH_TYPE_GREECO 3224
9968@@ -3063,6 +3072,126 @@ extern unsigned int __machine_arch_type;
9969 # define machine_is_wg302v2() (0)
9970 #endif
9971
9972+#ifdef CONFIG_MACH_AST1100
9973+# ifdef machine_arch_type
9974+# undef machine_arch_type
9975+# define machine_arch_type __machine_arch_type
9976+# else
9977+# define machine_arch_type MACH_TYPE_AST1100
9978+# endif
9979+# define machine_is_ast1100() (machine_arch_type == MACH_TYPE_AST1100)
9980+#else
9981+# define machine_is_ast1100() (0)
9982+#endif
9983+
9984+#ifdef CONFIG_MACH_AST2000
9985+# ifdef machine_arch_type
9986+# undef machine_arch_type
9987+# define machine_arch_type __machine_arch_type
9988+# else
9989+# define machine_arch_type MACH_TYPE_AST2000
9990+# endif
9991+# define machine_is_ast2000() (machine_arch_type == MACH_TYPE_AST2000)
9992+#else
9993+# define machine_is_ast2000() (0)
9994+#endif
9995+
9996+#ifdef CONFIG_MACH_AST2100
9997+# ifdef machine_arch_type
9998+# undef machine_arch_type
9999+# define machine_arch_type __machine_arch_type
10000+# else
10001+# define machine_arch_type MACH_TYPE_AST2100
10002+# endif
10003+# define machine_is_ast2100() (machine_arch_type == MACH_TYPE_AST2100)
10004+#else
10005+# define machine_is_ast2100() (0)
10006+#endif
10007+
10008+#ifdef CONFIG_MACH_AST2150
10009+# ifdef machine_arch_type
10010+# undef machine_arch_type
10011+# define machine_arch_type __machine_arch_type
10012+# else
10013+# define machine_arch_type MACH_TYPE_AST2150
10014+# endif
10015+# define machine_is_ast2150() (machine_arch_type == MACH_TYPE_AST2150)
10016+#else
10017+# define machine_is_ast2150() (0)
10018+#endif
10019+
10020+#ifdef CONFIG_MACH_AST2200
10021+# ifdef machine_arch_type
10022+# undef machine_arch_type
10023+# define machine_arch_type __machine_arch_type
10024+# else
10025+# define machine_arch_type MACH_TYPE_AST2200
10026+# endif
10027+# define machine_is_ast2200() (machine_arch_type == MACH_TYPE_AST2200)
10028+#else
10029+# define machine_is_ast2200() (0)
10030+#endif
10031+
10032+#ifdef CONFIG_MACH_AST2300_FPGA_1
10033+# ifdef machine_arch_type
10034+# undef machine_arch_type
10035+# define machine_arch_type __machine_arch_type
10036+# else
10037+# define machine_arch_type MACH_TYPE_AST2300_FPGA_1
10038+# endif
10039+# define machine_is_ast2300_fpga_1() (machine_arch_type == MACH_TYPE_AST2300_FPGA_1)
10040+#else
10041+# define machine_is_ast2300_fpga_1() (0)
10042+#endif
10043+
10044+#ifdef CONFIG_MACH_AST2300_FPGA_2
10045+# ifdef machine_arch_type
10046+# undef machine_arch_type
10047+# define machine_arch_type __machine_arch_type
10048+# else
10049+# define machine_arch_type MACH_TYPE_AST2300_FPGA_2
10050+# endif
10051+# define machine_is_ast2300_fpga_2() (machine_arch_type == MACH_TYPE_AST2300_FPGA_2)
10052+#else
10053+# define machine_is_ast2300_fpga_2() (0)
10054+#endif
10055+
10056+#ifdef CONFIG_MACH_AST3100
10057+# ifdef machine_arch_type
10058+# undef machine_arch_type
10059+# define machine_arch_type __machine_arch_type
10060+# else
10061+# define machine_arch_type MACH_TYPE_AST3100
10062+# endif
10063+# define machine_is_ast3100() (machine_arch_type == MACH_TYPE_AST3100)
10064+#else
10065+# define machine_is_ast3100() (0)
10066+#endif
10067+
10068+#ifdef CONFIG_MACH_ASPEED
10069+# ifdef machine_arch_type
10070+# undef machine_arch_type
10071+# define machine_arch_type __machine_arch_type
10072+# else
10073+# define machine_arch_type MACH_TYPE_ASPEED
10074+# endif
10075+# define machine_is_aspeed() (machine_arch_type == MACH_TYPE_ASPEED)
10076+#else
10077+# define machine_is_aspeed() (0)
10078+#endif
10079+
10080+#ifdef CONFIG_MACH_AST2300
10081+# ifdef machine_arch_type
10082+# undef machine_arch_type
10083+# define machine_arch_type __machine_arch_type
10084+# else
10085+# define machine_arch_type MACH_TYPE_AST2300
10086+# endif
10087+# define machine_is_ast2300() (machine_arch_type == MACH_TYPE_AST2300)
10088+#else
10089+# define machine_is_ast2300() (0)
10090+#endif
10091+
10092 #ifdef CONFIG_MACH_OMAP_2430SDP
10093 # ifdef machine_arch_type
10094 # undef machine_arch_type
10095@@ -11043,18 +11172,6 @@ extern unsigned int __machine_arch_type;
10096 # define machine_is_nokia_rm680() (0)
10097 #endif
10098
10099-#ifdef CONFIG_MACH_AST2200
10100-# ifdef machine_arch_type
10101-# undef machine_arch_type
10102-# define machine_arch_type __machine_arch_type
10103-# else
10104-# define machine_arch_type MACH_TYPE_AST2200
10105-# endif
10106-# define machine_is_ast2200() (machine_arch_type == MACH_TYPE_AST2200)
10107-#else
10108-# define machine_is_ast2200() (0)
10109-#endif
10110-
10111 #ifdef CONFIG_MACH_LEAD
10112 # ifdef machine_arch_type
10113 # undef machine_arch_type
10114diff --git a/board/aspeed/ast2300/Makefile b/board/aspeed/ast2300/Makefile
10115new file mode 100644
10116index 0000000..d5300e6
10117--- /dev/null
10118+++ b/board/aspeed/ast2300/Makefile
10119@@ -0,0 +1,42 @@
10120+# This program is distributed in the hope that it will be useful,
10121+# but WITHOUT ANY WARRANTY; without even the implied warranty of
10122+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10123+# GNU General Public License for more details.
10124+#
10125+# You should have received a copy of the GNU General Public License
10126+# along with this program; if not, write to the Free Software
10127+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
10128+# MA 02111-1307 USA
10129+#
10130+
10131+include $(TOPDIR)/config.mk
10132+
10133+LIB = $(obj)lib$(BOARD).a
10134+
10135+COBJS = ast2300.o flash.o flash_spi.o pci.o crc32.o slt.o regtest.o vfun.o vhace.o crt.o videotest.o mactest.o hactest.o mictest.o
10136+
10137+ifdef CONFIG_FPGA_ASPEED
10138+SOBJS := platform_fpga.o
10139+else
10140+SOBJS := platform.o
10141+endif
10142+
10143+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
10144+OBJS := $(addprefix $(obj),$(COBJS))
10145+SOBJS := $(addprefix $(obj),$(SOBJS))
10146+
10147+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
10148+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
10149+
10150+clean:
10151+ rm -f $(SOBJS) $(OBJS)
10152+
10153+distclean: clean
10154+ rm -f $(LIB) core *.bak $(obj).depend
10155+
10156+# defines $(obj).depend target
10157+include $(SRCTREE)/rules.mk
10158+
10159+sinclude .depend
10160+
10161+#########################################################################
10162diff --git a/board/aspeed/ast2300/aes.c b/board/aspeed/ast2300/aes.c
10163new file mode 100755
10164index 0000000..f30ab99
10165--- /dev/null
10166+++ b/board/aspeed/ast2300/aes.c
10167@@ -0,0 +1,573 @@
10168+/*
10169+ * AES implementation
10170+ * This program is distributed in the hope that it will be useful,
10171+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
10172+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10173+ * GNU General Public License for more details.
10174+ *
10175+ * You should have received a copy of the GNU General Public License
10176+ * along with this program; if not, write to the Free Software
10177+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10178+ */
10179+
10180+/* uncomment the following line to run the test suite */
10181+
10182+/* #define TEST */
10183+
10184+/* uncomment the following line to use pre-computed tables */
10185+/* otherwise the tables will be generated at the first run */
10186+
10187+#define FIXED_TABLES
10188+
10189+#ifndef FIXED_TABLES
10190+
10191+/* forward S-box & tables */
10192+
10193+uint32 FSb[256];
10194+uint32 FT0[256];
10195+uint32 FT1[256];
10196+uint32 FT2[256];
10197+uint32 FT3[256];
10198+
10199+/* reverse S-box & tables */
10200+
10201+uint32 RSb[256];
10202+uint32 RT0[256];
10203+uint32 RT1[256];
10204+uint32 RT2[256];
10205+uint32 RT3[256];
10206+
10207+/* round constants */
10208+
10209+uint32 RCON[10];
10210+
10211+/* tables generation flag */
10212+
10213+int do_init = 1;
10214+
10215+/* tables generation routine */
10216+
10217+#define ROTR8(x) ( ( ( x << 24 ) & 0xFFFFFFFF ) | \
10218+ ( ( x & 0xFFFFFFFF ) >> 8 ) )
10219+
10220+#define XTIME(x) ( ( x << 1 ) ^ ( ( x & 0x80 ) ? 0x1B : 0x00 ) )
10221+#define MUL(x,y) ( ( x && y ) ? pow[(log[x] + log[y]) % 255] : 0 )
10222+
10223+void aes_gen_tables( void )
10224+{
10225+ int i;
10226+ uint8 x, y;
10227+ uint8 pow[256];
10228+ uint8 log[256];
10229+
10230+ /* compute pow and log tables over GF(2^8) */
10231+
10232+ for( i = 0, x = 1; i < 256; i++, x ^= XTIME( x ) )
10233+ {
10234+ pow[i] = x;
10235+ log[x] = i;
10236+ }
10237+
10238+ /* calculate the round constants */
10239+
10240+ for( i = 0, x = 1; i < 10; i++, x = XTIME( x ) )
10241+ {
10242+ RCON[i] = (uint32) x << 24;
10243+ }
10244+
10245+ /* generate the forward and reverse S-boxes */
10246+
10247+ FSb[0x00] = 0x63;
10248+ RSb[0x63] = 0x00;
10249+
10250+ for( i = 1; i < 256; i++ )
10251+ {
10252+ x = pow[255 - log[i]];
10253+
10254+ y = x; y = ( y << 1 ) | ( y >> 7 );
10255+ x ^= y; y = ( y << 1 ) | ( y >> 7 );
10256+ x ^= y; y = ( y << 1 ) | ( y >> 7 );
10257+ x ^= y; y = ( y << 1 ) | ( y >> 7 );
10258+ x ^= y ^ 0x63;
10259+
10260+ FSb[i] = x;
10261+ RSb[x] = i;
10262+ }
10263+
10264+ /* generate the forward and reverse tables */
10265+
10266+ for( i = 0; i < 256; i++ )
10267+ {
10268+ x = (unsigned char) FSb[i]; y = XTIME( x );
10269+
10270+ FT0[i] = (uint32) ( x ^ y ) ^
10271+ ( (uint32) x << 8 ) ^
10272+ ( (uint32) x << 16 ) ^
10273+ ( (uint32) y << 24 );
10274+
10275+ FT0[i] &= 0xFFFFFFFF;
10276+
10277+ FT1[i] = ROTR8( FT0[i] );
10278+ FT2[i] = ROTR8( FT1[i] );
10279+ FT3[i] = ROTR8( FT2[i] );
10280+
10281+ y = (unsigned char) RSb[i];
10282+
10283+ RT0[i] = ( (uint32) MUL( 0x0B, y ) ) ^
10284+ ( (uint32) MUL( 0x0D, y ) << 8 ) ^
10285+ ( (uint32) MUL( 0x09, y ) << 16 ) ^
10286+ ( (uint32) MUL( 0x0E, y ) << 24 );
10287+
10288+ RT0[i] &= 0xFFFFFFFF;
10289+
10290+ RT1[i] = ROTR8( RT0[i] );
10291+ RT2[i] = ROTR8( RT1[i] );
10292+ RT3[i] = ROTR8( RT2[i] );
10293+ }
10294+}
10295+
10296+#else
10297+
10298+/* forward S-box */
10299+
10300+static const uint32 FSb[256] =
10301+{
10302+ 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5,
10303+ 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
10304+ 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
10305+ 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
10306+ 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC,
10307+ 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
10308+ 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A,
10309+ 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
10310+ 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0,
10311+ 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
10312+ 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B,
10313+ 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
10314+ 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85,
10315+ 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
10316+ 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5,
10317+ 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
10318+ 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17,
10319+ 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
10320+ 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88,
10321+ 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
10322+ 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C,
10323+ 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
10324+ 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9,
10325+ 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
10326+ 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6,
10327+ 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
10328+ 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E,
10329+ 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
10330+ 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94,
10331+ 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
10332+ 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68,
10333+ 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
10334+};
10335+
10336+/* forward tables */
10337+
10338+#define FT \
10339+\
10340+ V(C6,63,63,A5), V(F8,7C,7C,84), V(EE,77,77,99), V(F6,7B,7B,8D), \
10341+ V(FF,F2,F2,0D), V(D6,6B,6B,BD), V(DE,6F,6F,B1), V(91,C5,C5,54), \
10342+ V(60,30,30,50), V(02,01,01,03), V(CE,67,67,A9), V(56,2B,2B,7D), \
10343+ V(E7,FE,FE,19), V(B5,D7,D7,62), V(4D,AB,AB,E6), V(EC,76,76,9A), \
10344+ V(8F,CA,CA,45), V(1F,82,82,9D), V(89,C9,C9,40), V(FA,7D,7D,87), \
10345+ V(EF,FA,FA,15), V(B2,59,59,EB), V(8E,47,47,C9), V(FB,F0,F0,0B), \
10346+ V(41,AD,AD,EC), V(B3,D4,D4,67), V(5F,A2,A2,FD), V(45,AF,AF,EA), \
10347+ V(23,9C,9C,BF), V(53,A4,A4,F7), V(E4,72,72,96), V(9B,C0,C0,5B), \
10348+ V(75,B7,B7,C2), V(E1,FD,FD,1C), V(3D,93,93,AE), V(4C,26,26,6A), \
10349+ V(6C,36,36,5A), V(7E,3F,3F,41), V(F5,F7,F7,02), V(83,CC,CC,4F), \
10350+ V(68,34,34,5C), V(51,A5,A5,F4), V(D1,E5,E5,34), V(F9,F1,F1,08), \
10351+ V(E2,71,71,93), V(AB,D8,D8,73), V(62,31,31,53), V(2A,15,15,3F), \
10352+ V(08,04,04,0C), V(95,C7,C7,52), V(46,23,23,65), V(9D,C3,C3,5E), \
10353+ V(30,18,18,28), V(37,96,96,A1), V(0A,05,05,0F), V(2F,9A,9A,B5), \
10354+ V(0E,07,07,09), V(24,12,12,36), V(1B,80,80,9B), V(DF,E2,E2,3D), \
10355+ V(CD,EB,EB,26), V(4E,27,27,69), V(7F,B2,B2,CD), V(EA,75,75,9F), \
10356+ V(12,09,09,1B), V(1D,83,83,9E), V(58,2C,2C,74), V(34,1A,1A,2E), \
10357+ V(36,1B,1B,2D), V(DC,6E,6E,B2), V(B4,5A,5A,EE), V(5B,A0,A0,FB), \
10358+ V(A4,52,52,F6), V(76,3B,3B,4D), V(B7,D6,D6,61), V(7D,B3,B3,CE), \
10359+ V(52,29,29,7B), V(DD,E3,E3,3E), V(5E,2F,2F,71), V(13,84,84,97), \
10360+ V(A6,53,53,F5), V(B9,D1,D1,68), V(00,00,00,00), V(C1,ED,ED,2C), \
10361+ V(40,20,20,60), V(E3,FC,FC,1F), V(79,B1,B1,C8), V(B6,5B,5B,ED), \
10362+ V(D4,6A,6A,BE), V(8D,CB,CB,46), V(67,BE,BE,D9), V(72,39,39,4B), \
10363+ V(94,4A,4A,DE), V(98,4C,4C,D4), V(B0,58,58,E8), V(85,CF,CF,4A), \
10364+ V(BB,D0,D0,6B), V(C5,EF,EF,2A), V(4F,AA,AA,E5), V(ED,FB,FB,16), \
10365+ V(86,43,43,C5), V(9A,4D,4D,D7), V(66,33,33,55), V(11,85,85,94), \
10366+ V(8A,45,45,CF), V(E9,F9,F9,10), V(04,02,02,06), V(FE,7F,7F,81), \
10367+ V(A0,50,50,F0), V(78,3C,3C,44), V(25,9F,9F,BA), V(4B,A8,A8,E3), \
10368+ V(A2,51,51,F3), V(5D,A3,A3,FE), V(80,40,40,C0), V(05,8F,8F,8A), \
10369+ V(3F,92,92,AD), V(21,9D,9D,BC), V(70,38,38,48), V(F1,F5,F5,04), \
10370+ V(63,BC,BC,DF), V(77,B6,B6,C1), V(AF,DA,DA,75), V(42,21,21,63), \
10371+ V(20,10,10,30), V(E5,FF,FF,1A), V(FD,F3,F3,0E), V(BF,D2,D2,6D), \
10372+ V(81,CD,CD,4C), V(18,0C,0C,14), V(26,13,13,35), V(C3,EC,EC,2F), \
10373+ V(BE,5F,5F,E1), V(35,97,97,A2), V(88,44,44,CC), V(2E,17,17,39), \
10374+ V(93,C4,C4,57), V(55,A7,A7,F2), V(FC,7E,7E,82), V(7A,3D,3D,47), \
10375+ V(C8,64,64,AC), V(BA,5D,5D,E7), V(32,19,19,2B), V(E6,73,73,95), \
10376+ V(C0,60,60,A0), V(19,81,81,98), V(9E,4F,4F,D1), V(A3,DC,DC,7F), \
10377+ V(44,22,22,66), V(54,2A,2A,7E), V(3B,90,90,AB), V(0B,88,88,83), \
10378+ V(8C,46,46,CA), V(C7,EE,EE,29), V(6B,B8,B8,D3), V(28,14,14,3C), \
10379+ V(A7,DE,DE,79), V(BC,5E,5E,E2), V(16,0B,0B,1D), V(AD,DB,DB,76), \
10380+ V(DB,E0,E0,3B), V(64,32,32,56), V(74,3A,3A,4E), V(14,0A,0A,1E), \
10381+ V(92,49,49,DB), V(0C,06,06,0A), V(48,24,24,6C), V(B8,5C,5C,E4), \
10382+ V(9F,C2,C2,5D), V(BD,D3,D3,6E), V(43,AC,AC,EF), V(C4,62,62,A6), \
10383+ V(39,91,91,A8), V(31,95,95,A4), V(D3,E4,E4,37), V(F2,79,79,8B), \
10384+ V(D5,E7,E7,32), V(8B,C8,C8,43), V(6E,37,37,59), V(DA,6D,6D,B7), \
10385+ V(01,8D,8D,8C), V(B1,D5,D5,64), V(9C,4E,4E,D2), V(49,A9,A9,E0), \
10386+ V(D8,6C,6C,B4), V(AC,56,56,FA), V(F3,F4,F4,07), V(CF,EA,EA,25), \
10387+ V(CA,65,65,AF), V(F4,7A,7A,8E), V(47,AE,AE,E9), V(10,08,08,18), \
10388+ V(6F,BA,BA,D5), V(F0,78,78,88), V(4A,25,25,6F), V(5C,2E,2E,72), \
10389+ V(38,1C,1C,24), V(57,A6,A6,F1), V(73,B4,B4,C7), V(97,C6,C6,51), \
10390+ V(CB,E8,E8,23), V(A1,DD,DD,7C), V(E8,74,74,9C), V(3E,1F,1F,21), \
10391+ V(96,4B,4B,DD), V(61,BD,BD,DC), V(0D,8B,8B,86), V(0F,8A,8A,85), \
10392+ V(E0,70,70,90), V(7C,3E,3E,42), V(71,B5,B5,C4), V(CC,66,66,AA), \
10393+ V(90,48,48,D8), V(06,03,03,05), V(F7,F6,F6,01), V(1C,0E,0E,12), \
10394+ V(C2,61,61,A3), V(6A,35,35,5F), V(AE,57,57,F9), V(69,B9,B9,D0), \
10395+ V(17,86,86,91), V(99,C1,C1,58), V(3A,1D,1D,27), V(27,9E,9E,B9), \
10396+ V(D9,E1,E1,38), V(EB,F8,F8,13), V(2B,98,98,B3), V(22,11,11,33), \
10397+ V(D2,69,69,BB), V(A9,D9,D9,70), V(07,8E,8E,89), V(33,94,94,A7), \
10398+ V(2D,9B,9B,B6), V(3C,1E,1E,22), V(15,87,87,92), V(C9,E9,E9,20), \
10399+ V(87,CE,CE,49), V(AA,55,55,FF), V(50,28,28,78), V(A5,DF,DF,7A), \
10400+ V(03,8C,8C,8F), V(59,A1,A1,F8), V(09,89,89,80), V(1A,0D,0D,17), \
10401+ V(65,BF,BF,DA), V(D7,E6,E6,31), V(84,42,42,C6), V(D0,68,68,B8), \
10402+ V(82,41,41,C3), V(29,99,99,B0), V(5A,2D,2D,77), V(1E,0F,0F,11), \
10403+ V(7B,B0,B0,CB), V(A8,54,54,FC), V(6D,BB,BB,D6), V(2C,16,16,3A)
10404+
10405+#define V(a,b,c,d) 0x##a##b##c##d
10406+static const uint32 FT0[256] = { FT };
10407+#undef V
10408+
10409+#define V(a,b,c,d) 0x##d##a##b##c
10410+static const uint32 FT1[256] = { FT };
10411+#undef V
10412+
10413+#define V(a,b,c,d) 0x##c##d##a##b
10414+static const uint32 FT2[256] = { FT };
10415+#undef V
10416+
10417+#define V(a,b,c,d) 0x##b##c##d##a
10418+static const uint32 FT3[256] = { FT };
10419+#undef V
10420+
10421+#undef FT
10422+
10423+/* reverse S-box */
10424+
10425+static const uint32 RSb[256] =
10426+{
10427+ 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38,
10428+ 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB,
10429+ 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87,
10430+ 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB,
10431+ 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D,
10432+ 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E,
10433+ 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2,
10434+ 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25,
10435+ 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16,
10436+ 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92,
10437+ 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA,
10438+ 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84,
10439+ 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A,
10440+ 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06,
10441+ 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02,
10442+ 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B,
10443+ 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA,
10444+ 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73,
10445+ 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85,
10446+ 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E,
10447+ 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89,
10448+ 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B,
10449+ 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20,
10450+ 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4,
10451+ 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31,
10452+ 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F,
10453+ 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D,
10454+ 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF,
10455+ 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0,
10456+ 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61,
10457+ 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26,
10458+ 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D
10459+};
10460+
10461+/* reverse tables */
10462+
10463+#define RT \
10464+\
10465+ V(51,F4,A7,50), V(7E,41,65,53), V(1A,17,A4,C3), V(3A,27,5E,96), \
10466+ V(3B,AB,6B,CB), V(1F,9D,45,F1), V(AC,FA,58,AB), V(4B,E3,03,93), \
10467+ V(20,30,FA,55), V(AD,76,6D,F6), V(88,CC,76,91), V(F5,02,4C,25), \
10468+ V(4F,E5,D7,FC), V(C5,2A,CB,D7), V(26,35,44,80), V(B5,62,A3,8F), \
10469+ V(DE,B1,5A,49), V(25,BA,1B,67), V(45,EA,0E,98), V(5D,FE,C0,E1), \
10470+ V(C3,2F,75,02), V(81,4C,F0,12), V(8D,46,97,A3), V(6B,D3,F9,C6), \
10471+ V(03,8F,5F,E7), V(15,92,9C,95), V(BF,6D,7A,EB), V(95,52,59,DA), \
10472+ V(D4,BE,83,2D), V(58,74,21,D3), V(49,E0,69,29), V(8E,C9,C8,44), \
10473+ V(75,C2,89,6A), V(F4,8E,79,78), V(99,58,3E,6B), V(27,B9,71,DD), \
10474+ V(BE,E1,4F,B6), V(F0,88,AD,17), V(C9,20,AC,66), V(7D,CE,3A,B4), \
10475+ V(63,DF,4A,18), V(E5,1A,31,82), V(97,51,33,60), V(62,53,7F,45), \
10476+ V(B1,64,77,E0), V(BB,6B,AE,84), V(FE,81,A0,1C), V(F9,08,2B,94), \
10477+ V(70,48,68,58), V(8F,45,FD,19), V(94,DE,6C,87), V(52,7B,F8,B7), \
10478+ V(AB,73,D3,23), V(72,4B,02,E2), V(E3,1F,8F,57), V(66,55,AB,2A), \
10479+ V(B2,EB,28,07), V(2F,B5,C2,03), V(86,C5,7B,9A), V(D3,37,08,A5), \
10480+ V(30,28,87,F2), V(23,BF,A5,B2), V(02,03,6A,BA), V(ED,16,82,5C), \
10481+ V(8A,CF,1C,2B), V(A7,79,B4,92), V(F3,07,F2,F0), V(4E,69,E2,A1), \
10482+ V(65,DA,F4,CD), V(06,05,BE,D5), V(D1,34,62,1F), V(C4,A6,FE,8A), \
10483+ V(34,2E,53,9D), V(A2,F3,55,A0), V(05,8A,E1,32), V(A4,F6,EB,75), \
10484+ V(0B,83,EC,39), V(40,60,EF,AA), V(5E,71,9F,06), V(BD,6E,10,51), \
10485+ V(3E,21,8A,F9), V(96,DD,06,3D), V(DD,3E,05,AE), V(4D,E6,BD,46), \
10486+ V(91,54,8D,B5), V(71,C4,5D,05), V(04,06,D4,6F), V(60,50,15,FF), \
10487+ V(19,98,FB,24), V(D6,BD,E9,97), V(89,40,43,CC), V(67,D9,9E,77), \
10488+ V(B0,E8,42,BD), V(07,89,8B,88), V(E7,19,5B,38), V(79,C8,EE,DB), \
10489+ V(A1,7C,0A,47), V(7C,42,0F,E9), V(F8,84,1E,C9), V(00,00,00,00), \
10490+ V(09,80,86,83), V(32,2B,ED,48), V(1E,11,70,AC), V(6C,5A,72,4E), \
10491+ V(FD,0E,FF,FB), V(0F,85,38,56), V(3D,AE,D5,1E), V(36,2D,39,27), \
10492+ V(0A,0F,D9,64), V(68,5C,A6,21), V(9B,5B,54,D1), V(24,36,2E,3A), \
10493+ V(0C,0A,67,B1), V(93,57,E7,0F), V(B4,EE,96,D2), V(1B,9B,91,9E), \
10494+ V(80,C0,C5,4F), V(61,DC,20,A2), V(5A,77,4B,69), V(1C,12,1A,16), \
10495+ V(E2,93,BA,0A), V(C0,A0,2A,E5), V(3C,22,E0,43), V(12,1B,17,1D), \
10496+ V(0E,09,0D,0B), V(F2,8B,C7,AD), V(2D,B6,A8,B9), V(14,1E,A9,C8), \
10497+ V(57,F1,19,85), V(AF,75,07,4C), V(EE,99,DD,BB), V(A3,7F,60,FD), \
10498+ V(F7,01,26,9F), V(5C,72,F5,BC), V(44,66,3B,C5), V(5B,FB,7E,34), \
10499+ V(8B,43,29,76), V(CB,23,C6,DC), V(B6,ED,FC,68), V(B8,E4,F1,63), \
10500+ V(D7,31,DC,CA), V(42,63,85,10), V(13,97,22,40), V(84,C6,11,20), \
10501+ V(85,4A,24,7D), V(D2,BB,3D,F8), V(AE,F9,32,11), V(C7,29,A1,6D), \
10502+ V(1D,9E,2F,4B), V(DC,B2,30,F3), V(0D,86,52,EC), V(77,C1,E3,D0), \
10503+ V(2B,B3,16,6C), V(A9,70,B9,99), V(11,94,48,FA), V(47,E9,64,22), \
10504+ V(A8,FC,8C,C4), V(A0,F0,3F,1A), V(56,7D,2C,D8), V(22,33,90,EF), \
10505+ V(87,49,4E,C7), V(D9,38,D1,C1), V(8C,CA,A2,FE), V(98,D4,0B,36), \
10506+ V(A6,F5,81,CF), V(A5,7A,DE,28), V(DA,B7,8E,26), V(3F,AD,BF,A4), \
10507+ V(2C,3A,9D,E4), V(50,78,92,0D), V(6A,5F,CC,9B), V(54,7E,46,62), \
10508+ V(F6,8D,13,C2), V(90,D8,B8,E8), V(2E,39,F7,5E), V(82,C3,AF,F5), \
10509+ V(9F,5D,80,BE), V(69,D0,93,7C), V(6F,D5,2D,A9), V(CF,25,12,B3), \
10510+ V(C8,AC,99,3B), V(10,18,7D,A7), V(E8,9C,63,6E), V(DB,3B,BB,7B), \
10511+ V(CD,26,78,09), V(6E,59,18,F4), V(EC,9A,B7,01), V(83,4F,9A,A8), \
10512+ V(E6,95,6E,65), V(AA,FF,E6,7E), V(21,BC,CF,08), V(EF,15,E8,E6), \
10513+ V(BA,E7,9B,D9), V(4A,6F,36,CE), V(EA,9F,09,D4), V(29,B0,7C,D6), \
10514+ V(31,A4,B2,AF), V(2A,3F,23,31), V(C6,A5,94,30), V(35,A2,66,C0), \
10515+ V(74,4E,BC,37), V(FC,82,CA,A6), V(E0,90,D0,B0), V(33,A7,D8,15), \
10516+ V(F1,04,98,4A), V(41,EC,DA,F7), V(7F,CD,50,0E), V(17,91,F6,2F), \
10517+ V(76,4D,D6,8D), V(43,EF,B0,4D), V(CC,AA,4D,54), V(E4,96,04,DF), \
10518+ V(9E,D1,B5,E3), V(4C,6A,88,1B), V(C1,2C,1F,B8), V(46,65,51,7F), \
10519+ V(9D,5E,EA,04), V(01,8C,35,5D), V(FA,87,74,73), V(FB,0B,41,2E), \
10520+ V(B3,67,1D,5A), V(92,DB,D2,52), V(E9,10,56,33), V(6D,D6,47,13), \
10521+ V(9A,D7,61,8C), V(37,A1,0C,7A), V(59,F8,14,8E), V(EB,13,3C,89), \
10522+ V(CE,A9,27,EE), V(B7,61,C9,35), V(E1,1C,E5,ED), V(7A,47,B1,3C), \
10523+ V(9C,D2,DF,59), V(55,F2,73,3F), V(18,14,CE,79), V(73,C7,37,BF), \
10524+ V(53,F7,CD,EA), V(5F,FD,AA,5B), V(DF,3D,6F,14), V(78,44,DB,86), \
10525+ V(CA,AF,F3,81), V(B9,68,C4,3E), V(38,24,34,2C), V(C2,A3,40,5F), \
10526+ V(16,1D,C3,72), V(BC,E2,25,0C), V(28,3C,49,8B), V(FF,0D,95,41), \
10527+ V(39,A8,01,71), V(08,0C,B3,DE), V(D8,B4,E4,9C), V(64,56,C1,90), \
10528+ V(7B,CB,84,61), V(D5,32,B6,70), V(48,6C,5C,74), V(D0,B8,57,42)
10529+
10530+#define V(a,b,c,d) 0x##a##b##c##d
10531+static const uint32 RT0[256] = { RT };
10532+#undef V
10533+
10534+#define V(a,b,c,d) 0x##d##a##b##c
10535+static const uint32 RT1[256] = { RT };
10536+#undef V
10537+
10538+#define V(a,b,c,d) 0x##c##d##a##b
10539+static const uint32 RT2[256] = { RT };
10540+#undef V
10541+
10542+#define V(a,b,c,d) 0x##b##c##d##a
10543+static const uint32 RT3[256] = { RT };
10544+#undef V
10545+
10546+#undef RT
10547+
10548+/* round constants */
10549+
10550+static const uint32 RCON[10] =
10551+{
10552+ 0x01000000, 0x02000000, 0x04000000, 0x08000000,
10553+ 0x10000000, 0x20000000, 0x40000000, 0x80000000,
10554+ 0x1B000000, 0x36000000
10555+};
10556+
10557+int do_init = 0;
10558+
10559+void aes_gen_tables( void )
10560+{
10561+}
10562+
10563+#endif
10564+
10565+/* platform-independant 32-bit integer manipulation macros */
10566+
10567+#define GET_UINT32_aes(n,b,i) \
10568+{ \
10569+ (n) = ( (uint32) (b)[(i) ] << 24 ) \
10570+ | ( (uint32) (b)[(i) + 1] << 16 ) \
10571+ | ( (uint32) (b)[(i) + 2] << 8 ) \
10572+ | ( (uint32) (b)[(i) + 3] ); \
10573+}
10574+
10575+#define PUT_UINT32_aes(n,b,i) \
10576+{ \
10577+ (b)[(i) ] = (uint8) ( (n) >> 24 ); \
10578+ (b)[(i) + 1] = (uint8) ( (n) >> 16 ); \
10579+ (b)[(i) + 2] = (uint8) ( (n) >> 8 ); \
10580+ (b)[(i) + 3] = (uint8) ( (n) ); \
10581+}
10582+
10583+/* decryption key schedule tables */
10584+
10585+int KT_init = 1;
10586+
10587+uint32 KT0[256];
10588+uint32 KT1[256];
10589+uint32 KT2[256];
10590+uint32 KT3[256];
10591+
10592+/* AES key scheduling routine */
10593+int aes_set_key( aes_context *ctx, uint8 *key, int nbits )
10594+{
10595+ int i;
10596+ uint32 *RK, *SK;
10597+
10598+ if( do_init )
10599+ {
10600+ aes_gen_tables();
10601+
10602+ do_init = 0;
10603+ }
10604+
10605+ switch( nbits )
10606+ {
10607+ case 128: ctx->nr = 10; break;
10608+ case 192: ctx->nr = 12; break;
10609+ case 256: ctx->nr = 14; break;
10610+ default : return( 1 );
10611+ }
10612+
10613+ RK = ctx->erk;
10614+
10615+ for( i = 0; i < (nbits >> 5); i++ )
10616+ {
10617+ GET_UINT32_aes( RK[i], key, i * 4 );
10618+ }
10619+
10620+ /* setup encryption round keys */
10621+
10622+ switch( nbits )
10623+ {
10624+ case 128:
10625+
10626+ for( i = 0; i < 10; i++, RK += 4 )
10627+ {
10628+ RK[4] = RK[0] ^ RCON[i] ^
10629+ ( FSb[ (uint8) ( RK[3] >> 16 ) ] << 24 ) ^
10630+ ( FSb[ (uint8) ( RK[3] >> 8 ) ] << 16 ) ^
10631+ ( FSb[ (uint8) ( RK[3] ) ] << 8 ) ^
10632+ ( FSb[ (uint8) ( RK[3] >> 24 ) ] );
10633+
10634+ RK[5] = RK[1] ^ RK[4];
10635+ RK[6] = RK[2] ^ RK[5];
10636+ RK[7] = RK[3] ^ RK[6];
10637+ }
10638+ break;
10639+
10640+ case 192:
10641+
10642+ for( i = 0; i < 8; i++, RK += 6 )
10643+ {
10644+ RK[6] = RK[0] ^ RCON[i] ^
10645+ ( FSb[ (uint8) ( RK[5] >> 16 ) ] << 24 ) ^
10646+ ( FSb[ (uint8) ( RK[5] >> 8 ) ] << 16 ) ^
10647+ ( FSb[ (uint8) ( RK[5] ) ] << 8 ) ^
10648+ ( FSb[ (uint8) ( RK[5] >> 24 ) ] );
10649+
10650+ RK[7] = RK[1] ^ RK[6];
10651+ RK[8] = RK[2] ^ RK[7];
10652+ RK[9] = RK[3] ^ RK[8];
10653+ RK[10] = RK[4] ^ RK[9];
10654+ RK[11] = RK[5] ^ RK[10];
10655+ }
10656+ break;
10657+
10658+ case 256:
10659+
10660+ for( i = 0; i < 7; i++, RK += 8 )
10661+ {
10662+ RK[8] = RK[0] ^ RCON[i] ^
10663+ ( FSb[ (uint8) ( RK[7] >> 16 ) ] << 24 ) ^
10664+ ( FSb[ (uint8) ( RK[7] >> 8 ) ] << 16 ) ^
10665+ ( FSb[ (uint8) ( RK[7] ) ] << 8 ) ^
10666+ ( FSb[ (uint8) ( RK[7] >> 24 ) ] );
10667+
10668+ RK[9] = RK[1] ^ RK[8];
10669+ RK[10] = RK[2] ^ RK[9];
10670+ RK[11] = RK[3] ^ RK[10];
10671+
10672+ RK[12] = RK[4] ^
10673+ ( FSb[ (uint8) ( RK[11] >> 24 ) ] << 24 ) ^
10674+ ( FSb[ (uint8) ( RK[11] >> 16 ) ] << 16 ) ^
10675+ ( FSb[ (uint8) ( RK[11] >> 8 ) ] << 8 ) ^
10676+ ( FSb[ (uint8) ( RK[11] ) ] );
10677+
10678+ RK[13] = RK[5] ^ RK[12];
10679+ RK[14] = RK[6] ^ RK[13];
10680+ RK[15] = RK[7] ^ RK[14];
10681+ }
10682+ break;
10683+ }
10684+
10685+ /* setup decryption round keys */
10686+
10687+ if( KT_init )
10688+ {
10689+ for( i = 0; i < 256; i++ )
10690+ {
10691+ KT0[i] = RT0[ FSb[i] ];
10692+ KT1[i] = RT1[ FSb[i] ];
10693+ KT2[i] = RT2[ FSb[i] ];
10694+ KT3[i] = RT3[ FSb[i] ];
10695+ }
10696+
10697+ KT_init = 0;
10698+ }
10699+
10700+ SK = ctx->drk;
10701+
10702+ *SK++ = *RK++;
10703+ *SK++ = *RK++;
10704+ *SK++ = *RK++;
10705+ *SK++ = *RK++;
10706+
10707+ for( i = 1; i < ctx->nr; i++ )
10708+ {
10709+ RK -= 8;
10710+
10711+ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
10712+ KT1[ (uint8) ( *RK >> 16 ) ] ^
10713+ KT2[ (uint8) ( *RK >> 8 ) ] ^
10714+ KT3[ (uint8) ( *RK ) ]; RK++;
10715+
10716+ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
10717+ KT1[ (uint8) ( *RK >> 16 ) ] ^
10718+ KT2[ (uint8) ( *RK >> 8 ) ] ^
10719+ KT3[ (uint8) ( *RK ) ]; RK++;
10720+
10721+ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
10722+ KT1[ (uint8) ( *RK >> 16 ) ] ^
10723+ KT2[ (uint8) ( *RK >> 8 ) ] ^
10724+ KT3[ (uint8) ( *RK ) ]; RK++;
10725+
10726+ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
10727+ KT1[ (uint8) ( *RK >> 16 ) ] ^
10728+ KT2[ (uint8) ( *RK >> 8 ) ] ^
10729+ KT3[ (uint8) ( *RK ) ]; RK++;
10730+ }
10731+
10732+ RK -= 8;
10733+
10734+ *SK++ = *RK++;
10735+ *SK++ = *RK++;
10736+ *SK++ = *RK++;
10737+ *SK++ = *RK++;
10738+
10739+ return( 0 );
10740+}
10741diff --git a/board/aspeed/ast2300/ast2300.c b/board/aspeed/ast2300/ast2300.c
10742new file mode 100644
10743index 0000000..b317786
10744--- /dev/null
10745+++ b/board/aspeed/ast2300/ast2300.c
10746@@ -0,0 +1,171 @@
10747+/*
10748+ * This program is distributed in the hope that it will be useful,
10749+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
10750+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10751+ * GNU General Public License for more details.
10752+ *
10753+ * You should have received a copy of the GNU General Public License
10754+ * along with this program; if not, write to the Free Software
10755+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10756+ */
10757+
10758+#include <common.h>
10759+#include <command.h>
10760+#include <pci.h>
10761+
10762+int board_init (void)
10763+{
10764+ DECLARE_GLOBAL_DATA_PTR;
10765+ unsigned char data;
10766+ unsigned long reg;
10767+
10768+ /* AHB Controller */
10769+ *((volatile ulong*) 0x1E600000) = 0xAEED1A03; /* unlock AHB controller */
10770+ *((volatile ulong*) 0x1E60008C) |= 0x01; /* map DRAM to 0x00000000 */
10771+#ifdef CONFIG_PCI
10772+ *((volatile ulong*) 0x1E60008C) |= 0x30; /* map PCI */
10773+#endif
10774+
10775+ /* Flash Controller */
10776+#ifdef CONFIG_FLASH_AST2300
10777+ *((volatile ulong*) 0x1e620000) |= 0x800f0000; /* enable Flash Write */
10778+#else
10779+ *((volatile ulong*) 0x16000000) |= 0x00001c00; /* enable Flash Write */
10780+#endif
10781+
10782+ /* SCU */
10783+ *((volatile ulong*) 0x1e6e2000) = 0x1688A8A8; /* unlock SCU */
10784+ reg = *((volatile ulong*) 0x1e6e2008);
10785+ reg &= 0x1c0fffff;
10786+ reg |= 0x61800000; /* PCLK = HPLL/8 */
10787+#ifdef CONFIG_AST1070
10788+ reg |= 0x300000; /* LHCLK = HPLL/8 */
10789+ reg |= 0x80000; /* LPC Host Clock */
10790+#endif
10791+ *((volatile ulong*) 0x1e6e2008) = reg;
10792+ reg = *((volatile ulong*) 0x1e6e200c); /* enable 2D Clk */
10793+ *((volatile ulong*) 0x1e6e200c) &= 0xFFFFFFFD;
10794+/* enable wide screen. If your video driver does not support wide screen, don't
10795+enable this bit 0x1e6e2040 D[0]*/
10796+ reg = *((volatile ulong*) 0x1e6e2040);
10797+ *((volatile ulong*) 0x1e6e2040) |= 0x01;
10798+#ifdef CONFIG_AST1070
10799+/*set VPPL1 */
10800+
10801+ *((volatile ulong*) 0x1e6e201c) = 0x6420;
10802+
10803+// set d2-pll & enable d2-pll D[21:20], D[4]
10804+ reg = *((volatile ulong*) 0x1e6e202c);
10805+ reg &= 0xffcfffef;
10806+ reg |= 0x00200010;
10807+ *((volatile ulong*) 0x1e6e202c) = reg;
10808+
10809+// set OSCCLK = VPLL1
10810+ *((volatile ulong*) 0x1e6e2010) = 0x8;
10811+
10812+// enable OSCCLK
10813+ reg = *((volatile ulong*) 0x1e6e202c);
10814+ reg &= 0xfffffffd;
10815+ reg |= 0x00000002;
10816+ *((volatile ulong*) 0x1e6e202c) = reg;
10817+
10818+// enable AST1050's LPC master
10819+ reg = *((volatile ulong*) 0x1e7890a0);
10820+ *((volatile ulong*) 0x1e7890a0) |= 0x11;
10821+#endif
10822+ /* arch number */
10823+ gd->bd->bi_arch_number = MACH_TYPE_ASPEED;
10824+
10825+ /* adress of boot parameters */
10826+ gd->bd->bi_boot_params = 0x40000100;
10827+
10828+ return 0;
10829+}
10830+
10831+int dram_init (void)
10832+{
10833+ DECLARE_GLOBAL_DATA_PTR;
10834+
10835+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
10836+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
10837+
10838+ return 0;
10839+}
10840+
10841+/*
10842+SCU7C: Silicon Revision ID Register
10843+D[31:24]: Chip ID
10844+0: AST2050/AST2100/AST2150/AST2200/AST3000
10845+1: AST2300
10846+
10847+D[23:16] Silicon revision ID for AST2300 generation and later
10848+0: A0
10849+1: A1
10850+2: A2
10851+.
10852+.
10853+.
10854+FPGA revision starts from 0x80
10855+
10856+
10857+D[11:8] Bounding option
10858+
10859+D[7:0] Silicon revision ID for AST2050/AST2100 generation (for software compatible)
10860+0: A0
10861+1: A1
10862+2: A2
10863+3: A3
10864+.
10865+.
10866+FPGA revision starts from 0x08, 8~10 means A0, 11+ means A1, AST2300 should be assigned to 3
10867+*/
10868+int misc_init_r(void)
10869+{
10870+ unsigned int reg1, revision, chip_id;
10871+
10872+ /* Show H/W Version */
10873+ reg1 = (unsigned int) (*((ulong*) 0x1e6e207c));
10874+ chip_id = (reg1 & 0xff000000) >> 24;
10875+ revision = (reg1 & 0xff0000) >> 16;
10876+
10877+ puts ("H/W: ");
10878+ if (chip_id == 1) {
10879+ if (revision >= 0x80) {
10880+ printf("AST2300 series FPGA Rev. %02x \n", revision);
10881+ }
10882+ else {
10883+ printf("AST2300 series chip Rev. %02x \n", revision);
10884+ }
10885+ }
10886+ else if (chip_id == 0) {
10887+ printf("AST2050/AST2150 series chip\n");
10888+ }
10889+
10890+#ifdef CONFIG_AST1070
10891+ puts ("C/C: ");
10892+ revision = (unsigned int) (*((ulong*) 0x60002034));
10893+ printf("AST1070 ID [%08x] \n", revision);
10894+#endif
10895+
10896+#ifdef CONFIG_PCI
10897+ pci_init ();
10898+#endif
10899+
10900+ if (getenv ("verify") == NULL) {
10901+ setenv ("verify", "n");
10902+ }
10903+ if (getenv ("eeprom") == NULL) {
10904+ setenv ("eeprom", "y");
10905+ }
10906+}
10907+
10908+#ifdef CONFIG_PCI
10909+static struct pci_controller hose;
10910+
10911+extern void aspeed_init_pci (struct pci_controller *hose);
10912+
10913+void pci_init_board(void)
10914+{
10915+ aspeed_init_pci(&hose);
10916+}
10917+#endif
10918diff --git a/board/aspeed/ast2300/config.mk b/board/aspeed/ast2300/config.mk
10919new file mode 100755
10920index 0000000..24ca09b
10921--- /dev/null
10922+++ b/board/aspeed/ast2300/config.mk
10923@@ -0,0 +1,18 @@
10924+# This program is distributed in the hope that it will be useful,
10925+# but WITHOUT ANY WARRANTY; without even the implied warranty of
10926+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10927+# GNU General Public License for more details.
10928+#
10929+# You should have received a copy of the GNU General Public License
10930+# along with this program; if not, write to the Free Software
10931+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
10932+# MA 02111-1307 USA
10933+#
10934+
10935+# ROM version
10936+#TEXT_BASE = 0xBFC00000
10937+
10938+# RAM version
10939+TEXT_BASE = 0x40500000
10940+#TEXT_BASE = 0x00000000
10941+#TEXT_BASE = 0x00400000
10942diff --git a/board/aspeed/ast2300/crc32.c b/board/aspeed/ast2300/crc32.c
10943new file mode 100755
10944index 0000000..cc8d2ac
10945--- /dev/null
10946+++ b/board/aspeed/ast2300/crc32.c
10947@@ -0,0 +1,127 @@
10948+/*
10949+ * This program is distributed in the hope that it will be useful,
10950+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
10951+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10952+ * GNU General Public License for more details.
10953+ *
10954+ * You should have received a copy of the GNU General Public License
10955+ * along with this program; if not, write to the Free Software
10956+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10957+ */
10958+#include <common.h>
10959+#include <asm/processor.h>
10960+#include <asm/byteorder.h>
10961+#include <environment.h>
10962+
10963+#ifdef CONFIG_2SPIFLASH
10964+
10965+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
10966+
10967+/* ========================================================================
10968+ * Table of CRC-32's of all single-byte values (made by make_aspeed_crc_table)
10969+ */
10970+unsigned long aspeed_crc_table[256] = {
10971+ 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
10972+ 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
10973+ 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
10974+ 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
10975+ 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
10976+ 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
10977+ 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
10978+ 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
10979+ 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
10980+ 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
10981+ 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
10982+ 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
10983+ 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
10984+ 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
10985+ 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
10986+ 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
10987+ 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
10988+ 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
10989+ 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
10990+ 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
10991+ 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
10992+ 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
10993+ 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
10994+ 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
10995+ 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
10996+ 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
10997+ 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
10998+ 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
10999+ 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
11000+ 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
11001+ 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
11002+ 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
11003+ 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
11004+ 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
11005+ 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
11006+ 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
11007+ 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
11008+ 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
11009+ 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
11010+ 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
11011+ 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
11012+ 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
11013+ 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
11014+ 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
11015+ 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
11016+ 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
11017+ 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
11018+ 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
11019+ 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
11020+ 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
11021+ 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
11022+ 0x2d02ef8dL
11023+};
11024+
11025+/* ========================================================================= */
11026+#define ASPEED_DO1(buf) crc = aspeed_crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
11027+#define ASPEED_DO2(buf) ASPEED_DO1(buf); ASPEED_DO1(buf);
11028+#define ASPEED_DO4(buf) ASPEED_DO2(buf); ASPEED_DO2(buf);
11029+#define ASPEED_DO8(buf) ASPEED_DO4(buf); ASPEED_DO4(buf);
11030+
11031+/* ========================================================================= */
11032+unsigned long spi2_crc32(crc, buf, len)
11033+ unsigned long crc;
11034+ unsigned char *buf;
11035+ unsigned long len;
11036+{
11037+
11038+ size_t len1, len2;
11039+ char *s;
11040+
11041+ len1 = len2 = 0;
11042+ if ( (ulong)(buf) <= (flash_info[0].start[0] + flash_info[0].size) )
11043+ len1 = (flash_info[0].start[0] + flash_info[0].size) - (ulong)(buf);
11044+
11045+ len1 = (len < len1) ? len:len1;
11046+ len2 = (len < len1) ? 0: (len - len1);
11047+
11048+ crc = crc ^ 0xffffffffL;
11049+ while (len1 >= 8)
11050+ {
11051+ ASPEED_DO8(buf);
11052+ len1 -= 8;
11053+ }
11054+ if (len1) do {
11055+ ASPEED_DO1(buf);
11056+ } while (--len1);
11057+
11058+ //s = (char *) flash_info[1].start[0];
11059+ s= (char *) flash_make_addr (&flash_info[1], 0, 0);
11060+ while (len2 >= 8)
11061+ {
11062+ ASPEED_DO8(s);
11063+ len2 -= 8;
11064+ }
11065+ if (len2) do {
11066+ ASPEED_DO1(s);
11067+ } while (--len2);
11068+
11069+ return crc ^ 0xffffffffL;
11070+
11071+}
11072+
11073+#endif /* CONFIG_2SPIFLASH */
11074+
11075diff --git a/board/aspeed/ast2300/crt.c b/board/aspeed/ast2300/crt.c
11076new file mode 100755
11077index 0000000..b67f669
11078--- /dev/null
11079+++ b/board/aspeed/ast2300/crt.c
11080@@ -0,0 +1,322 @@
11081+/*
11082+ * This program is distributed in the hope that it will be useful,
11083+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11084+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11085+ * GNU General Public License for more details.
11086+ *
11087+ * You should have received a copy of the GNU General Public License
11088+ * along with this program; if not, write to the Free Software
11089+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
11090+ */
11091+#include <common.h>
11092+#include <command.h>
11093+
11094+#include "type.h"
11095+#include "vesa.h"
11096+#include "vdef.h"
11097+#include "vfun.h"
11098+#include "vreg.h"
11099+#include "crt.h"
11100+
11101+ULONG AST3000DCLKTableV [] = {
11102+ 0x00046515, /* 00: VCLK25_175 */
11103+ 0x00047255, /* 01: VCLK28_322 */
11104+ 0x0004682a, /* 02: VCLK31_5 */
11105+ 0x0004672a, /* 03: VCLK36 */
11106+ 0x00046c50, /* 04: VCLK40 */
11107+ 0x00046842, /* 05: VCLK49_5 */
11108+ 0x00006c32, /* 06: VCLK50 */
11109+ 0x00006a2f, /* 07: VCLK56_25 */
11110+ 0x00006c41, /* 08: VCLK65 */
11111+ 0x00006832, /* 09: VCLK75 */
11112+ 0x0000672e, /* 0A: VCLK78_75 */
11113+ 0x0000683f, /* 0B: VCLK94_5 */
11114+ 0x00004824, /* 0C: VCLK108 */
11115+ 0x00004723, /* 0D: VCLK119 */
11116+ 0x0000482d, /* 0E: VCLK135 */
11117+ 0x00004B37, /* 0F: VCLK146_25 */
11118+ 0x0000472e, /* 10: VCLK157_5 */
11119+ 0x00004836, /* 11: VCLK162 */
11120+
11121+};
11122+
11123+BOOL CheckDAC(int nCRTIndex)
11124+{
11125+ BYTE btValue;
11126+ BOOL bValue;
11127+
11128+ BYTE btDeviceSelect;
11129+
11130+ switch (nCRTIndex)
11131+ {
11132+ case CRT_1:
11133+ btDeviceSelect = DEVICE_ADDRESS_CH7301_CRT1;
11134+ break;
11135+ case CRT_2:
11136+ btDeviceSelect = DEVICE_ADDRESS_CH7301_CRT2;
11137+ break;
11138+ default:
11139+ printf("CRTIndex is not 1 or 2");
11140+ return FALSE;
11141+ break;
11142+ }
11143+
11144+ //Enable all DAC's and set register 21h[0] = '0'
11145+ //DVIP and DVIL disable for DAC
11146+ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_PM_REG, 0x00);
11147+
11148+ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_DC_REG);
11149+ btValue = btValue & 0xFE;
11150+ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_DC_REG, btValue);
11151+
11152+ //Set SENSE bit to 1
11153+ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG);
11154+ btValue = btValue | 0x01;
11155+ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG, btValue);
11156+
11157+ //Reset SENSE bit to 0
11158+ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG);
11159+ btValue = btValue & 0xFE;
11160+ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG, btValue);
11161+
11162+ bValue = (GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG) & CD_DACT) ? TRUE : FALSE;
11163+
11164+ return bValue;
11165+}
11166+
11167+VOID SetCH7301C(ULONG MMIOBase,
11168+ int nCRTIndex,
11169+ int inFreqRange,
11170+ int inOperating)
11171+{
11172+ BYTE btDeviceSelect;
11173+ BYTE btValue;
11174+
11175+//#ifdef EVB_CLIENT
11176+ //output RGB doesn't need to set CH7301
11177+ //if (1 == inOperating)
11178+ // return;
11179+//#endif
11180+
11181+ switch (nCRTIndex)
11182+ {
11183+ case CRT_1:
11184+ btDeviceSelect = 0xEA;
11185+
11186+ break;
11187+ case CRT_2:
11188+ btDeviceSelect = 0xEC;
11189+
11190+ break;
11191+ default:
11192+ printf("CRTIndex is not 1 or 2");
11193+ return;
11194+ break;
11195+ }
11196+
11197+ if (inFreqRange <= VCLK65)
11198+ {
11199+ printf("ch7301: low f \n");
11200+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x33, 0x08);
11201+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x34, 0x16);
11202+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x36, 0x60);
11203+ }
11204+ else
11205+ {
11206+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x33, 0x06);
11207+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x34, 0x26);
11208+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x36, 0xA0);
11209+ }
11210+
11211+ switch (inOperating)
11212+ {
11213+ case 0:
11214+ //DVI is normal function
11215+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x49, 0xC0);
11216+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1D, 0x47);
11217+ break;
11218+ case 1:
11219+ //RGB
11220+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x48, 0x18);
11221+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x49, 0x0);
11222+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x56, 0x0);
11223+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x21, 0x9);
11224+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1D, 0x48);
11225+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1C, 0x00);
11226+ break;
11227+ default:
11228+ break;
11229+ };
11230+}
11231+
11232+void SetASTModeTiming (ULONG MMIOBase, int nCRTIndex, BYTE ModeIndex, BYTE ColorDepth)
11233+{
11234+ ULONG temp, RetraceStart, RetraceEnd, DisplayOffset, TerminalCount, bpp;
11235+
11236+// Access CRT Engine
11237+ // SetPolarity
11238+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, ((vModeTable[ModeIndex].HorPolarity << HOR_SYNC_SELECT_BIT) | (vModeTable[ModeIndex].VerPolarity << VER_SYNC_SELECT_BIT)), (HOR_SYNC_SELECT_MASK|VER_SYNC_SELECT_MASK));
11239+
11240+#if CONFIG_AST3000
11241+ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0xc0);
11242+#else
11243+ //2100 is single edge
11244+ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0x80);
11245+#endif
11246+ // Horizontal Timing
11247+ temp = 0;
11248+ temp = ((vModeTable[ModeIndex].HorizontalActive - 1) << HOR_ENABLE_END_BIT) | ((vModeTable[ModeIndex].HorizontalTotal - 1) << HOR_TOTAL_BIT);
11249+ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_TOTAL_END_REG + nCRTIndex*0x60, temp);
11250+
11251+ RetraceStart = vModeTable[ModeIndex].HorizontalTotal - vModeTable[ModeIndex].HBackPorch - vModeTable[ModeIndex].HSyncTime - vModeTable[ModeIndex].HLeftBorder - 1;
11252+ RetraceEnd = (RetraceStart + vModeTable[ModeIndex].HSyncTime);
11253+ temp = 0;
11254+ temp = (RetraceEnd << HOR_RETRACE_END_BIT) | (RetraceStart << HOR_RETRACE_START_BIT);
11255+ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_RETRACE_REG + nCRTIndex*0x60, temp);
11256+
11257+ // Vertical Timing
11258+ temp = 0;
11259+ temp = ((vModeTable[ModeIndex].VerticalActive - 1) << VER_ENABLE_END_BIT) | ((vModeTable[ModeIndex].VerticalTotal - 1) << VER_TOTAL_BIT);
11260+ WriteMemoryLongClient(SCU_BASE, CRT1_VER_TOTAL_END_REG + nCRTIndex*0x60, temp);
11261+
11262+ temp = 0;
11263+ RetraceStart = vModeTable[ModeIndex].VerticalTotal - vModeTable[ModeIndex].VBackPorch - vModeTable[ModeIndex].VSyncTime - vModeTable[ModeIndex].VTopBorder - 1;
11264+ RetraceEnd = (RetraceStart + vModeTable[ModeIndex].VSyncTime);
11265+ temp = (RetraceEnd << VER_RETRACE_END_BIT) | (RetraceStart << VER_RETRACE_START_BIT);
11266+ WriteMemoryLongClient(SCU_BASE, CRT1_VER_RETRACE_REG + nCRTIndex*0x60, temp);
11267+
11268+ // Set CRT Display Offset and Terminal Count
11269+ if (ColorDepth == RGB_565) {
11270+ bpp = 16;
11271+ }
11272+ else {
11273+ bpp = 32;
11274+ }
11275+
11276+ DisplayOffset = vModeTable[ModeIndex].HorizontalActive * bpp / 8;
11277+ TerminalCount = vModeTable[ModeIndex].HorizontalActive * bpp / 64;
11278+ if (ColorDepth == YUV_444) {
11279+ TerminalCount = TerminalCount * 3 / 4;
11280+ }
11281+ if (((vModeTable[ModeIndex].HorizontalActive * bpp) % 64) != 0) {
11282+ TerminalCount++;
11283+ }
11284+
11285+ WriteMemoryLongClient(SCU_BASE, CRT1_DISPLAY_OFFSET + nCRTIndex*0x60, ((TerminalCount << TERMINAL_COUNT_BIT) | DisplayOffset));
11286+
11287+ // Set Color Format
11288+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (ColorDepth << FORMAT_SELECT_BIT), FORMAT_SELECT_MASK);
11289+
11290+ // Set Threshold
11291+ temp = 0;
11292+ temp = (CRT_HIGH_THRESHOLD_VALUE << THRES_HIGHT_BIT) | (CRT_LOW_THRESHOLD_VALUE << THRES_LOW_BIT);
11293+ WriteMemoryLongClient(SCU_BASE, CRT1_THRESHOLD_REG + nCRTIndex*0x60, temp);
11294+
11295+ WriteMemoryLongClient(SCU_BASE, CRT1_VIDEO_PLL_REG + nCRTIndex*0x60, AST3000DCLKTableV[vModeTable[ModeIndex].PixelClock]);
11296+}
11297+
11298+void SetASTCenter1024ModeTiming (ULONG MMIOBase, int nCRTIndex, BYTE ModeIndex, BYTE ColorDepth)
11299+{
11300+ ULONG temp, RetraceStart, RetraceEnd, DisplayOffset, TerminalCount, bpp;
11301+
11302+ // Access CRT Engine
11303+ // SetPolarity
11304+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (HOR_NEGATIVE << HOR_SYNC_SELECT_BIT) | (VER_NEGATIVE << VER_SYNC_SELECT_BIT), HOR_SYNC_SELECT_MASK|VER_SYNC_SELECT_MASK);
11305+
11306+ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0xC0);
11307+
11308+ // Horizontal Timing
11309+ temp = 0;
11310+ temp = ((vModeTable[ModeIndex].HorizontalActive - 1) << HOR_ENABLE_END_BIT) | ((vModeTable[10].HorizontalTotal - 1) << HOR_TOTAL_BIT);
11311+ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_TOTAL_END_REG + nCRTIndex*0x60, temp);
11312+
11313+ RetraceStart = vModeTable[10].HorizontalTotal - vModeTable[10].HBackPorch - vModeTable[10].HSyncTime - vModeTable[10].HLeftBorder - 1;
11314+ RetraceStart = RetraceStart - (vModeTable[10].HorizontalActive - vModeTable[ModeIndex].HorizontalActive) / 2 - 1;
11315+ RetraceEnd = (RetraceStart + vModeTable[10].HSyncTime);
11316+ temp = 0;
11317+ temp = (RetraceEnd << HOR_RETRACE_END_BIT) | (RetraceStart << HOR_RETRACE_START_BIT);
11318+ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_RETRACE_REG + nCRTIndex*0x60, temp);
11319+
11320+ // Vertical Timing
11321+ temp = 0;
11322+ temp = ((vModeTable[ModeIndex].VerticalActive - 1) << VER_ENABLE_END_BIT) | ((vModeTable[10].VerticalTotal - 1) << VER_TOTAL_BIT);
11323+ WriteMemoryLongClient(SCU_BASE, CRT1_VER_TOTAL_END_REG + nCRTIndex*0x60, temp);
11324+
11325+ RetraceStart = vModeTable[10].VerticalTotal - vModeTable[10].VBackPorch - vModeTable[10].VSyncTime - vModeTable[10].VTopBorder - 1;
11326+ RetraceStart = RetraceStart - (vModeTable[10].VerticalActive - vModeTable[ModeIndex].VerticalActive) / 2 - 1;
11327+ RetraceEnd = (RetraceStart + vModeTable[10].VSyncTime);
11328+ temp = (RetraceEnd << VER_RETRACE_END_BIT) | (RetraceStart << VER_RETRACE_START_BIT);
11329+ WriteMemoryLongClient(SCU_BASE, CRT1_VER_RETRACE_REG + nCRTIndex*0x60, temp);
11330+
11331+ // Set CRT Display Offset and Terminal Count
11332+ if (ColorDepth == RGB_565) {
11333+ bpp = 16;
11334+ }
11335+ else {
11336+ bpp = 32;
11337+ }
11338+ DisplayOffset = vModeTable[ModeIndex].HorizontalActive * bpp / 8;
11339+ TerminalCount = vModeTable[ModeIndex].HorizontalActive * bpp / 64;
11340+ if (ColorDepth == YUV_444) {
11341+ TerminalCount = TerminalCount * 3 / 4;
11342+ }
11343+ if (((vModeTable[ModeIndex].HorizontalActive * bpp) % 64) != 0) {
11344+ TerminalCount++;
11345+ }
11346+
11347+ WriteMemoryLongClient(SCU_BASE, CRT1_DISPLAY_OFFSET + nCRTIndex*0x60, (TerminalCount << TERMINAL_COUNT_BIT) | DisplayOffset);
11348+
11349+ // Set Color Format
11350+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (ColorDepth << FORMAT_SELECT_BIT), FORMAT_SELECT_MASK);
11351+
11352+ // Set Threshold
11353+ temp = 0;
11354+ temp = (CRT_HIGH_THRESHOLD_VALUE << THRES_HIGHT_BIT) | (CRT_LOW_THRESHOLD_VALUE << THRES_LOW_BIT);
11355+ WriteMemoryLongClient(SCU_BASE, CRT1_THRESHOLD_REG + nCRTIndex*0x60, temp);
11356+
11357+ // Set DCLK
11358+ WriteMemoryLongClient(SCU_BASE, CRT1_VIDEO_PLL_REG + nCRTIndex*0x60, AST3000DCLKTableV[vModeTable[ModeIndex].PixelClock]);
11359+
11360+}
11361+
11362+BOOL ASTSetModeV (ULONG MMIOBase, int nCRTIndex, ULONG VGABaseAddr, USHORT Horizontal, USHORT Vertical, BYTE ColorFormat, BYTE CenterMode)
11363+{
11364+ BYTE i, ModeIndex;
11365+ BOOL bDAC;
11366+ ULONG ulTemp;
11367+
11368+ // Access CRT Engine
11369+ //Enable CRT1 graph
11370+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + 0x60*nCRTIndex, GRAPH_DISPLAY_ON, GRAPH_DISPLAY_MASK);
11371+
11372+ // Set CRT Display Start Address
11373+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_DISPLAY_ADDRESS + 0x60*nCRTIndex, VGABaseAddr, DISPLAY_ADDRESS_MASK);
11374+
11375+ for (i = 0; i < Mode60HZCount; i++) {
11376+ if ((vModeTable[i].HorizontalActive == Horizontal) && (vModeTable[i].VerticalActive == Vertical)) {
11377+
11378+ ModeIndex = i;
11379+
11380+ if (CenterMode != 1) {
11381+ SetASTModeTiming(MMIOBase, nCRTIndex, i, ColorFormat);
11382+ }
11383+ else {
11384+ SetASTCenter1024ModeTiming (MMIOBase, nCRTIndex, i, ColorFormat);
11385+ }
11386+
11387+ //use internal video out sigal and don't need use 7301
11388+ /*
11389+ bDAC = CheckDAC(nCRTIndex);
11390+
11391+ SetCH7301C(0,
11392+ nCRTIndex,
11393+ vModeTable[ModeIndex].PixelClock,
11394+ bDAC); //For RGB
11395+ */
11396+ return TRUE;
11397+ }
11398+ }
11399+
11400+ return FALSE;
11401+}
11402+
11403diff --git a/board/aspeed/ast2300/crt.h b/board/aspeed/ast2300/crt.h
11404new file mode 100755
11405index 0000000..e7483be
11406--- /dev/null
11407+++ b/board/aspeed/ast2300/crt.h
11408@@ -0,0 +1,121 @@
11409+/*
11410+ * This program is distributed in the hope that it will be useful,
11411+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11412+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11413+ * GNU General Public License for more details.
11414+ *
11415+ * You should have received a copy of the GNU General Public License
11416+ * along with this program; if not, write to the Free Software
11417+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
11418+ */
11419+#ifndef _CRT_H_
11420+#define _CRT_H_
11421+
11422+#ifdef Watcom
11423+#define CRT_REMAP_OFFSET 0x10000
11424+#else
11425+#define CRT_REMAP_OFFSET 0x0
11426+#endif
11427+
11428+/********************************************************/
11429+/* CRT register */
11430+/********************************************************/
11431+#define CRT_BASE_OFFSET 0x6000+CRT_REMAP_OFFSET
11432+
11433+#define CRT1_CONTROL_REG 0x00 + CRT_BASE_OFFSET
11434+ #define GRAPH_DISPLAY_BIT 0
11435+ #define GRAPH_DISPLAY_MASK (1<<0)
11436+ #define GRAPH_DISPLAY_ON 1
11437+ #define GRAPH_DISPLAY_OFF 0
11438+ #define FORMAT_SELECT_BIT 8
11439+ #define FORMAT_SELECT_MASK (3<<8)
11440+ #define HOR_SYNC_SELECT_BIT 16
11441+ #define HOR_SYNC_SELECT_MASK (1<<16)
11442+ #define HOR_NEGATIVE 1
11443+ #define HOR_POSITIVE 0
11444+ #define VER_SYNC_SELECT_BIT 17
11445+ #define VER_SYNC_SELECT_MASK (1<<17)
11446+ #define VER_NEGATIVE 1
11447+ #define VER_POSITIVE 0
11448+
11449+#define CRT1_CONTROL2_REG 0x04 + CRT_BASE_OFFSET
11450+
11451+#define CRT1_VIDEO_PLL_REG 0x0C + CRT_BASE_OFFSET
11452+ #define POST_DIV_BIT 18
11453+ #define POST_DIV_MASK 3<<18
11454+ #define DIV_1_1 0
11455+ //#define DIV_1_2 1
11456+ #define DIV_1_2 2
11457+ #define DIV_1_4 3
11458+
11459+#define CRT1_HOR_TOTAL_END_REG 0x10 + CRT_BASE_OFFSET
11460+ #define HOR_TOTAL_BIT 0
11461+ #define HOR_ENABLE_END_BIT 16
11462+
11463+#define CRT1_HOR_RETRACE_REG 0x14 + CRT_BASE_OFFSET
11464+ #define HOR_RETRACE_START_BIT 0
11465+ #define HOR_RETRACE_END_BIT 16
11466+
11467+#define CRT1_VER_TOTAL_END_REG 0x18 + CRT_BASE_OFFSET
11468+ #define VER_TOTAL_BIT 0
11469+ #define VER_ENABLE_END_BIT 16
11470+
11471+#define CRT1_VER_RETRACE_REG 0x1C + CRT_BASE_OFFSET
11472+ #define VER_RETRACE_START_BIT 0
11473+ #define VER_RETRACE_END_BIT 16
11474+
11475+#define CRT1_DISPLAY_ADDRESS 0x20 + CRT_BASE_OFFSET
11476+ #define DISPLAY_ADDRESS_MASK 0x0FFFFFFF
11477+
11478+#define CRT1_DISPLAY_OFFSET 0x24 + CRT_BASE_OFFSET
11479+ #define DISPLAY_OFFSET_ALIGN 7 /* 8 byte alignment*/
11480+ #define TERMINAL_COUNT_BIT 16
11481+
11482+#define CRT1_THRESHOLD_REG 0x28 + CRT_BASE_OFFSET
11483+ #define THRES_LOW_BIT 0
11484+ #define THRES_HIGHT_BIT 8
11485+
11486+#define CURSOR_POSITION 0x30 + OFFSET
11487+#define CURSOR_OFFSET 0x34 + OFFSET
11488+#define CURSOR_PATTERN 0x38 + OFFSET
11489+#define OSD_HORIZONTAL 0x40 + OFFSET
11490+#define OSD_VERTICAL 0x44 + OFFSET
11491+#define OSD_PATTERN 0x48 + OFFSET
11492+#define OSD_OFFSET 0x4C + OFFSET
11493+#define OSD_THRESHOLD 0x50 + OFFSET
11494+
11495+//Ch7301c
11496+#define DEVICE_ADDRESS_CH7301_CRT1 0xEA
11497+#define DEVICE_ADDRESS_CH7301_CRT2 0xEC
11498+
11499+
11500+#define DEVICE_SELECT_CH7301 0x3
11501+
11502+/* CH7301 Register Definition */
11503+#define CH7301_CD_REG 0x20
11504+ #define CD_DACT 0x0E
11505+ #define CD_DVIT 1 << 5
11506+#define CH7301_DC_REG 0x21
11507+#define CH7301_PM_REG 0x49
11508+
11509+BOOL CheckHotPlug(int nCRTIndex);
11510+BOOL CheckDAC(int nCRTIndex);
11511+
11512+BOOL ASTSetModeV (ULONG MMIOBase,
11513+ int nCRTIndex,
11514+ ULONG VGABaseAddr,
11515+ USHORT Horizontal,
11516+ USHORT Vertical,
11517+ BYTE ColorFormat,
11518+ BYTE CenterMode);
11519+
11520+BOOL SelCRTClock(ULONG MMIOBase,
11521+ int nCRTIndex,
11522+ USHORT Horizontal,
11523+ USHORT Vertical);
11524+
11525+void DisableCRT(ULONG MMIOBase, int nCRTIndex);
11526+void ClearCRTWithBlack(ULONG ulCRTAddr, int iWidth, int iHeight);
11527+
11528+#endif /* _CRT_H_ */
11529+
11530diff --git a/board/aspeed/ast2300/flash.c b/board/aspeed/ast2300/flash.c
11531new file mode 100755
11532index 0000000..d611d0d
11533--- /dev/null
11534+++ b/board/aspeed/ast2300/flash.c
11535@@ -0,0 +1,1651 @@
11536+/*
11537+ * This program is distributed in the hope that it will be useful,
11538+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11539+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11540+ * GNU General Public License for more details.
11541+ *
11542+ * You should have received a copy of the GNU General Public License
11543+ * along with this program; if not, write to the Free Software
11544+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
11545+ * MA 02111-1307 USA
11546+ *
11547+ * History
11548+ * 01/20/2004 - combined variants of original driver.
11549+ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
11550+ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
11551+ * 01/27/2004 - Little endian support Ed Okerson
11552+ *
11553+ * Tested Architectures
11554+ * Port Width Chip Width # of banks Flash Chip Board
11555+ * 32 16 1 28F128J3 seranoa/eagle
11556+ * 64 16 1 28F128J3 seranoa/falcon
11557+ */
11558+// (Sun) This CFI driver is written for fixed-width flash chips.
11559+// It was not designed for flexible 8-bit/16-bit chips, which are the norm.
11560+// When those chips are connected to a bus in 8-bit mode, the address wires
11561+// right-shifted by 1.
11562+//FIXME: Fix the driver to auto-detect "16-bit flash wired in 8-bit mode".
11563+// Left-shift CFI offsets by 1 bit instead of doubling the #define values.
11564+
11565+/* The DEBUG define must be before common to enable debugging */
11566+// (Sun) Changed to DEBUG_FLASH because flash debug()s are too numerous.
11567+// #define DEBUG
11568+
11569+#include <common.h>
11570+#include <asm/processor.h>
11571+#include <asm/byteorder.h>
11572+#include <environment.h>
11573+#ifdef CONFIG_SYS_FLASH_CFI
11574+
11575+/*
11576+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
11577+ * The width of the port and the width of the chips are determined at initialization.
11578+ * These widths are used to calculate the address for access CFI data structures.
11579+ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
11580+ *
11581+ * References
11582+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
11583+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
11584+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
11585+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
11586+ *
11587+ * TODO
11588+ *
11589+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
11590+ * Table (ALT) to determine if protection is available
11591+ *
11592+ * Add support for other command sets Use the PRI and ALT to determine command set
11593+ * Verify erase and program timeouts.
11594+ */
11595+
11596+#ifndef CONFIG_FLASH_BANKS_LIST
11597+#define CONFIG_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
11598+#endif
11599+
11600+#define FLASH_CMD_CFI 0x98
11601+#define FLASH_CMD_READ_ID 0x90
11602+#define FLASH_CMD_RESET 0xff
11603+#define FLASH_CMD_BLOCK_ERASE 0x20
11604+#define FLASH_CMD_ERASE_CONFIRM 0xD0
11605+#define FLASH_CMD_WRITE 0x40
11606+#define FLASH_CMD_PROTECT 0x60
11607+#define FLASH_CMD_PROTECT_SET 0x01
11608+#define FLASH_CMD_PROTECT_CLEAR 0xD0
11609+#define FLASH_CMD_CLEAR_STATUS 0x50
11610+#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
11611+#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
11612+
11613+#define FLASH_STATUS_DONE 0x80
11614+#define FLASH_STATUS_ESS 0x40
11615+#define FLASH_STATUS_ECLBS 0x20
11616+#define FLASH_STATUS_PSLBS 0x10
11617+#define FLASH_STATUS_VPENS 0x08
11618+#define FLASH_STATUS_PSS 0x04
11619+#define FLASH_STATUS_DPS 0x02
11620+#define FLASH_STATUS_R 0x01
11621+#define FLASH_STATUS_PROTECT 0x01
11622+
11623+#define AMD_CMD_RESET 0xF0
11624+#define AMD_CMD_WRITE 0xA0
11625+#define AMD_CMD_ERASE_START 0x80
11626+#define AMD_CMD_ERASE_SECTOR 0x30
11627+#define AMD_CMD_UNLOCK_START 0xAA
11628+#define AMD_CMD_UNLOCK_ACK 0x55
11629+#define AMD_CMD_WRITE_TO_BUFFER 0x25
11630+#define AMD_CMD_BUFFER_TO_FLASH 0x29
11631+
11632+#define AMD_STATUS_TOGGLE 0x40
11633+#define AMD_STATUS_ERROR 0x20
11634+//FIXME: These 3 were also changed for 8-bit/16-bit flash chips.
11635+#define AMD_ADDR_ERASE_START (0xAAA/info->portwidth)
11636+#define AMD_ADDR_START (0xAAA/info->portwidth)
11637+#define AMD_ADDR_ACK (0x555/info->portwidth)
11638+
11639+//FIXME: Fix the driver to auto-detect "16-bit flash wired in 8-bit mode".
11640+// Left-shift CFI offsets by 1 bit instead of doubling the #define values.
11641+#define FLASH_OFFSET_CFI (0xAA/info->portwidth)
11642+#define FLASH_OFFSET_CFI_RESP (0x20/info->portwidth)
11643+#define FLASH_OFFSET_CFI_RESP1 (0x22/info->portwidth)
11644+#define FLASH_OFFSET_CFI_RESP2 (0x24/info->portwidth)
11645+#define FLASH_OFFSET_PRIMARY_VENDOR (0x26/info->portwidth)
11646+#define FLASH_OFFSET_WTOUT (0x3E/info->portwidth)
11647+#define FLASH_OFFSET_WBTOUT (0x40/info->portwidth)
11648+#define FLASH_OFFSET_ETOUT (0x42/info->portwidth)
11649+#define FLASH_OFFSET_CETOUT (0x44/info->portwidth)
11650+#define FLASH_OFFSET_WMAX_TOUT (0x46/info->portwidth)
11651+#define FLASH_OFFSET_WBMAX_TOUT (0x48/info->portwidth)
11652+#define FLASH_OFFSET_EMAX_TOUT (0x4A/info->portwidth)
11653+#define FLASH_OFFSET_CEMAX_TOUT (0x4C/info->portwidth)
11654+#define FLASH_OFFSET_SIZE (0x4E/info->portwidth)
11655+#define FLASH_OFFSET_INTERFACE (0x50/info->portwidth)
11656+#define FLASH_OFFSET_BUFFER_SIZE (0x54/info->portwidth)
11657+#define FLASH_OFFSET_NUM_ERASE_REGIONS (0x58/info->portwidth)
11658+#define FLASH_OFFSET_ERASE_REGIONS (0x5A/info->portwidth)
11659+#define FLASH_OFFSET_PROTECT (0x02/info->portwidth)
11660+#define FLASH_OFFSET_USER_PROTECTION (0x85/info->portwidth)
11661+#define FLASH_OFFSET_INTEL_PROTECTION (0x81/info->portwidth)
11662+
11663+#define MAX_NUM_ERASE_REGIONS 4
11664+
11665+#define FLASH_MAN_CFI 0x01000000
11666+
11667+#define CFI_CMDSET_NONE 0
11668+#define CFI_CMDSET_INTEL_EXTENDED 1
11669+#define CFI_CMDSET_AMD_STANDARD 2
11670+#define CFI_CMDSET_INTEL_STANDARD 3
11671+#define CFI_CMDSET_AMD_EXTENDED 4
11672+#define CFI_CMDSET_MITSU_STANDARD 256
11673+#define CFI_CMDSET_MITSU_EXTENDED 257
11674+#define CFI_CMDSET_SST 258
11675+
11676+
11677+#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
11678+# undef FLASH_CMD_RESET
11679+# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
11680+#endif
11681+
11682+
11683+typedef union {
11684+ unsigned char c;
11685+ unsigned short w;
11686+ unsigned long l;
11687+ unsigned long long ll;
11688+} cfiword_t;
11689+
11690+typedef union {
11691+ volatile unsigned char *cp;
11692+ volatile unsigned short *wp;
11693+ volatile unsigned long *lp;
11694+ volatile unsigned long long *llp;
11695+} cfiptr_t;
11696+
11697+/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
11698+#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
11699+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS_DETECT] = CONFIG_FLASH_BANKS_LIST;
11700+flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
11701+#else
11702+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_FLASH_BANKS_LIST;
11703+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
11704+#endif
11705+
11706+
11707+/*-----------------------------------------------------------------------
11708+ * Functions
11709+ */
11710+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
11711+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
11712+static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
11713+static void flash_write_cmd_nodbg (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
11714+static void flash_write_cmd_int (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd, int noDebug);
11715+static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
11716+static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
11717+static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
11718+static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
11719+static int flash_detect_cfi (flash_info_t * info);
11720+ulong flash_get_size (ulong base, int banknum);
11721+static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
11722+static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
11723+ ulong tout, char *prompt);
11724+static void write_buffer_abort_reset(flash_info_t * info, flash_sect_t sector);
11725+#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
11726+static flash_info_t *flash_get_info(ulong base);
11727+#endif
11728+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
11729+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
11730+static int flash_write_cfibuffer_amd (flash_info_t * info, ulong dest, uchar * cp, int len);
11731+#endif
11732+
11733+/*-----------------------------------------------------------------------
11734+ * create an address based on the offset and the port width
11735+ */
11736+inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
11737+{
11738+ return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
11739+}
11740+
11741+/*-----------------------------------------------------------------------
11742+ * Debug support
11743+ */
11744+#ifdef DEBUG_FLASH
11745+static void print_longlong (char *str, unsigned long long data)
11746+{
11747+ int i;
11748+ char *cp;
11749+
11750+ cp = (unsigned char *) &data;
11751+ for (i = 0; i < 8; i++)
11752+ sprintf (&str[i * 2], "%2.2x", *cp++);
11753+}
11754+#endif
11755+
11756+#if defined(DEBUG_FLASH)
11757+static void flash_printqry (flash_info_t * info, flash_sect_t sect)
11758+{
11759+ cfiptr_t cptr;
11760+ int x, y;
11761+
11762+ for (x = 0; x < 0x40; x += 16U / info->portwidth) {
11763+ cptr.cp =
11764+ flash_make_addr (info, sect,
11765+ x + FLASH_OFFSET_CFI_RESP);
11766+ debug ("%p : ", cptr.cp);
11767+ for (y = 0; y < 16; y++) {
11768+ debug ("%2.2x ", cptr.cp[y]);
11769+ }
11770+ debug (" ");
11771+ for (y = 0; y < 16; y++) {
11772+ if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
11773+ debug ("%c", cptr.cp[y]);
11774+ } else {
11775+ debug (".");
11776+ }
11777+ }
11778+ debug ("\n");
11779+ }
11780+}
11781+#endif
11782+
11783+/*-----------------------------------------------------------------------
11784+ * read a character at a port width address
11785+ */
11786+inline uchar flash_read_uchar (flash_info_t * info, uint offset)
11787+{
11788+ uchar *cp;
11789+
11790+ cp = flash_make_addr (info, 0, offset);
11791+#if defined(__LITTLE_ENDIAN)
11792+ return (cp[0]);
11793+#else
11794+ return (cp[info->portwidth - 1]);
11795+#endif
11796+}
11797+
11798+/*-----------------------------------------------------------------------
11799+ * read a short word by swapping for ppc format.
11800+ */
11801+#if 0
11802+static ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
11803+{
11804+ uchar *addr;
11805+ ushort retval;
11806+
11807+#ifdef DEBUG_FLASH
11808+ int x;
11809+#endif
11810+ addr = flash_make_addr (info, sect, offset);
11811+
11812+#ifdef DEBUG_FLASH
11813+ debug ("ushort addr is at %p info->portwidth = %d\n", addr,
11814+ info->portwidth);
11815+ for (x = 0; x < 2 * info->portwidth; x++) {
11816+ debug ("addr[%x] = 0x%x\n", x, addr[x]);
11817+ }
11818+#endif
11819+#if defined(__LITTLE_ENDIAN)
11820+ if (info->interface == FLASH_CFI_X8X16) {
11821+ retval = (addr[0] | (addr[2] << 8));
11822+ } else {
11823+ retval = (addr[0] | (addr[(info->portwidth)] << 8));
11824+ }
11825+#else
11826+ retval = ((addr[(2 * info->portwidth) - 1] << 8) |
11827+ addr[info->portwidth - 1]);
11828+#endif
11829+
11830+ debug ("retval = 0x%x\n", retval);
11831+ return retval;
11832+}
11833+#endif
11834+
11835+/*-----------------------------------------------------------------------
11836+ * read a long word by picking the least significant byte of each maximum
11837+ * port size word. Swap for ppc format.
11838+ */
11839+static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
11840+{
11841+ uchar *addr;
11842+ ulong retval;
11843+#ifdef DEBUG_FLASH
11844+ int x;
11845+#endif
11846+#if 0
11847+ switch (info->interface) {
11848+ case FLASH_CFI_X8:
11849+ case FLASH_CFI_X16:
11850+ break;
11851+ case FLASH_CFI_X8X16:
11852+ offset <<= 1;
11853+ }
11854+#endif
11855+ // flash_make_addr() multiplies offset by info->portwidth.
11856+ addr = flash_make_addr (info, sect, offset);
11857+
11858+#ifdef DEBUG_FLASH
11859+ debug ("long addr is at %p info->portwidth = %d\n", addr,
11860+ info->portwidth);
11861+ for (x = 0; x < 4 * info->portwidth; x++) {
11862+ debug ("addr[%x] = 0x%x\n", x, addr[x]);
11863+ }
11864+#endif
11865+#if defined(__LITTLE_ENDIAN)
11866+ if (info->interface == FLASH_CFI_X8X16) {
11867+ retval = (addr[0] | (addr[2] << 8) | (addr[4] << 16) | (addr[6] << 24));
11868+ } else {
11869+ retval = (addr[0] | (addr[(info->portwidth)] << 8) |
11870+ (addr[(2 * info->portwidth)] << 16) |
11871+ (addr[(3 * info->portwidth)] << 24));
11872+ }
11873+#else
11874+ //FIXME: This undocumented code appears to match broken bus wiring.
11875+ retval = (addr[(2 * info->portwidth) - 1] << 24) |
11876+ (addr[(info->portwidth) - 1] << 16) |
11877+ (addr[(4 * info->portwidth) - 1] << 8) |
11878+ addr[(3 * info->portwidth) - 1];
11879+#endif
11880+ return retval;
11881+}
11882+
11883+/*-----------------------------------------------------------------------
11884+ */
11885+unsigned long flash_init (void)
11886+{
11887+ unsigned long size = 0;
11888+ int i;
11889+
11890+ /* Init: no FLASHes known */
11891+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
11892+ flash_info[i].flash_id = FLASH_UNKNOWN;
11893+ size += flash_info[i].size = flash_get_size (bank_base[i], i);
11894+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
11895+#ifndef CFG_FLASH_QUIET_TEST
11896+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
11897+ i, flash_info[i].size, flash_info[i].size << 20);
11898+#endif /* CFG_FLASH_QUIET_TEST */
11899+ }
11900+ }
11901+
11902+ /* Monitor protection ON by default */
11903+#if (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
11904+ flash_protect (FLAG_PROTECT_SET,
11905+ CONFIG_MONITOR_BASE,
11906+ CONFIG_MONITOR_BASE + monitor_flash_len - 1,
11907+ flash_get_info(CONFIG_MONITOR_BASE));
11908+#endif
11909+
11910+ /* Environment protection ON by default */
11911+#ifdef CONFIG_ENV_IS_IN_FLASH
11912+ flash_protect (FLAG_PROTECT_SET,
11913+ CONFIG_ENV_ADDR,
11914+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
11915+ flash_get_info(CONFIG_ENV_ADDR));
11916+#endif
11917+
11918+ /* Redundant environment protection ON by default */
11919+#ifdef CONFIG_ENV_ADDR_REDUND
11920+ flash_protect (FLAG_PROTECT_SET,
11921+ CONFIG_ENV_ADDR_REDUND,
11922+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
11923+ flash_get_info(CONFIG_ENV_ADDR_REDUND));
11924+#endif
11925+ return (size);
11926+}
11927+
11928+/*-----------------------------------------------------------------------
11929+ */
11930+#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
11931+static flash_info_t *flash_get_info(ulong base)
11932+{
11933+ int i;
11934+ flash_info_t * info = 0;
11935+
11936+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
11937+ info = & flash_info[i];
11938+ if (info->size && info->start[0] <= base &&
11939+ base <= info->start[0] + info->size - 1)
11940+ break;
11941+ }
11942+
11943+ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
11944+}
11945+#endif
11946+
11947+/*-----------------------------------------------------------------------
11948+ */
11949+int flash_erase (flash_info_t * info, int s_first, int s_last)
11950+{
11951+ int rcode = 0;
11952+ int prot;
11953+ flash_sect_t sect;
11954+ uchar ch;
11955+ uchar *addr;
11956+
11957+ if (info->flash_id != FLASH_MAN_CFI) {
11958+ puts ("Can't erase unknown flash type - aborted\n");
11959+ return 1;
11960+ }
11961+ if ((s_first < 0) || (s_first > s_last)) {
11962+ puts ("- no sectors to erase\n");
11963+ return 1;
11964+ }
11965+
11966+ prot = 0;
11967+ for (sect = s_first; sect <= s_last; ++sect) {
11968+ if (info->protect[sect]) {
11969+ prot++;
11970+ }
11971+ }
11972+ if (prot) {
11973+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
11974+ } else {
11975+ putc ('\n');
11976+ }
11977+
11978+
11979+ for (sect = s_first; sect <= s_last; sect++) {
11980+ if (info->protect[sect] == 0) { /* not protected */
11981+ switch (info->vendor) {
11982+ case CFI_CMDSET_INTEL_STANDARD:
11983+ case CFI_CMDSET_INTEL_EXTENDED:
11984+ flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
11985+ flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
11986+ flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
11987+ break;
11988+ case CFI_CMDSET_AMD_STANDARD:
11989+ case CFI_CMDSET_AMD_EXTENDED:
11990+ flash_unlock_seq (info, sect);
11991+ flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
11992+ AMD_CMD_ERASE_START);
11993+ flash_unlock_seq (info, sect);
11994+ flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
11995+
11996+ /* toggle */
11997+ addr = flash_make_addr (info, sect, 0);
11998+ do {
11999+ ch = *(volatile uchar *)(addr);
12000+ } while ( ((ch & 0x80) == 0) || (ch != 0xFF) );
12001+ break;
12002+ default:
12003+ debug ("Unkown flash vendor %d\n",
12004+ info->vendor);
12005+ break;
12006+ }
12007+
12008+ if (flash_full_status_check
12009+ (info, sect, info->erase_blk_tout, "erase")) {
12010+ rcode = 1;
12011+ } else
12012+ putc ('.');
12013+ }
12014+ }
12015+ puts (" done\n");
12016+ return rcode;
12017+}
12018+
12019+/*-----------------------------------------------------------------------
12020+ */
12021+void flash_print_info (flash_info_t * info)
12022+{
12023+ int i;
12024+
12025+ if (info->flash_id != FLASH_MAN_CFI) {
12026+ puts ("missing or unknown FLASH type\n");
12027+ return;
12028+ }
12029+
12030+ printf ("CFI conformant FLASH (%d x %d)",
12031+ (info->portwidth << 3), (info->chipwidth << 3));
12032+ printf (" Size: %ld MB in %d Sectors\n",
12033+ info->size >> 20, info->sector_count);
12034+ printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
12035+ info->erase_blk_tout,
12036+ info->write_tout,
12037+ info->buffer_write_tout,
12038+ info->buffer_size);
12039+
12040+ puts (" Sector Start Addresses:");
12041+ for (i = 0; i < info->sector_count; ++i) {
12042+#ifdef CFG_FLASH_EMPTY_INFO
12043+ int k;
12044+ int size;
12045+ int erased;
12046+ volatile unsigned long *flash;
12047+
12048+ /*
12049+ * Check if whole sector is erased
12050+ */
12051+ if (i != (info->sector_count - 1))
12052+ size = info->start[i + 1] - info->start[i];
12053+ else
12054+ size = info->start[0] + info->size - info->start[i];
12055+ erased = 1;
12056+ flash = (volatile unsigned long *) info->start[i];
12057+ size = size >> 2; /* divide by 4 for longword access */
12058+ for (k = 0; k < size; k++) {
12059+ if (*flash++ != 0xffffffff) {
12060+ erased = 0;
12061+ break;
12062+ }
12063+ }
12064+
12065+ if ((i % 5) == 0)
12066+ printf ("\n");
12067+ /* print empty and read-only info */
12068+ printf (" %08lX%s%s",
12069+ info->start[i],
12070+ erased ? " E" : " ",
12071+ info->protect[i] ? "RO " : " ");
12072+#else /* ! CFG_FLASH_EMPTY_INFO */
12073+ if ((i % 5) == 0)
12074+ printf ("\n ");
12075+ printf (" %08lX%s",
12076+ info->start[i], info->protect[i] ? " (RO)" : " ");
12077+#endif
12078+ }
12079+ putc ('\n');
12080+ return;
12081+}
12082+
12083+/*-----------------------------------------------------------------------
12084+ * Copy memory to flash, returns:
12085+ * 0 - OK
12086+ * 1 - write timeout
12087+ * 2 - Flash not erased
12088+ */
12089+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
12090+{
12091+ ulong wp;
12092+ ulong cp;
12093+ int aln;
12094+ cfiword_t cword;
12095+ int i, rc;
12096+
12097+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
12098+ unsigned char pat[] = {'|', '-', '/', '\\'};
12099+ int patcnt = 0;
12100+ int buffered_size;
12101+#endif
12102+ /* get lower aligned address */
12103+ /* get lower aligned address */
12104+ wp = (addr & ~(info->portwidth - 1));
12105+
12106+ /* handle unaligned start */
12107+ if ((aln = addr - wp) != 0) {
12108+ cword.l = 0;
12109+ cp = wp;
12110+ for (i = 0; i < aln; ++i, ++cp)
12111+ flash_add_byte (info, &cword, (*(uchar *) cp));
12112+
12113+ for (; (i < info->portwidth) && (cnt > 0); i++) {
12114+ flash_add_byte (info, &cword, *src++);
12115+ cnt--;
12116+ cp++;
12117+ }
12118+ for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
12119+ flash_add_byte (info, &cword, (*(uchar *) cp));
12120+ if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
12121+ return rc;
12122+ wp = cp;
12123+ }
12124+
12125+ /* handle the aligned part */
12126+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
12127+ buffered_size = (info->portwidth / info->chipwidth);
12128+ buffered_size *= info->buffer_size;
12129+ while (cnt >= info->portwidth) {
12130+ /* Show processing */
12131+ if ((++patcnt % 256) == 0)
12132+ printf("%c\b", pat[(patcnt / 256) & 0x03]);
12133+
12134+ i = buffered_size > cnt ? cnt : buffered_size;
12135+ if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
12136+ return rc;
12137+ i -= i & (info->portwidth - 1);
12138+ wp += i;
12139+ src += i;
12140+ cnt -= i;
12141+ }
12142+#else
12143+ while (cnt >= info->portwidth) {
12144+ cword.l = 0;
12145+ for (i = 0; i < info->portwidth; i++) {
12146+ flash_add_byte (info, &cword, *src++);
12147+ }
12148+ if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
12149+ return rc;
12150+ wp += info->portwidth;
12151+ cnt -= info->portwidth;
12152+ }
12153+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
12154+ if (cnt == 0) {
12155+ return (0);
12156+ }
12157+
12158+ /*
12159+ * handle unaligned tail bytes
12160+ */
12161+ cword.l = 0;
12162+ for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
12163+ flash_add_byte (info, &cword, *src++);
12164+ --cnt;
12165+ }
12166+ for (; i < info->portwidth; ++i, ++cp) {
12167+ flash_add_byte (info, &cword, (*(uchar *) cp));
12168+ }
12169+
12170+ return flash_write_cfiword (info, wp, cword);
12171+}
12172+
12173+/*-----------------------------------------------------------------------
12174+ */
12175+#ifdef CFG_FLASH_PROTECTION
12176+
12177+int flash_real_protect (flash_info_t * info, long sector, int prot)
12178+{
12179+ int retcode = 0;
12180+
12181+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
12182+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
12183+ if (prot)
12184+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
12185+ else
12186+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
12187+
12188+ if ((retcode =
12189+ flash_full_status_check (info, sector, info->erase_blk_tout,
12190+ prot ? "protect" : "unprotect")) == 0) {
12191+
12192+ info->protect[sector] = prot;
12193+ /* Intel's unprotect unprotects all locking */
12194+ if (prot == 0) {
12195+ flash_sect_t i;
12196+
12197+ for (i = 0; i < info->sector_count; i++) {
12198+ if (info->protect[i])
12199+ flash_real_protect (info, i, 1);
12200+ }
12201+ }
12202+ }
12203+ return retcode;
12204+}
12205+
12206+/*-----------------------------------------------------------------------
12207+ * flash_read_user_serial - read the OneTimeProgramming cells
12208+ */
12209+void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
12210+ int len)
12211+{
12212+ uchar *src;
12213+ uchar *dst;
12214+
12215+ dst = buffer;
12216+ src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
12217+ flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
12218+ memcpy (dst, src + offset, len);
12219+ flash_write_cmd (info, 0, 0, info->cmd_reset);
12220+}
12221+
12222+/*
12223+ * flash_read_factory_serial - read the device Id from the protection area
12224+ */
12225+void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
12226+ int len)
12227+{
12228+ uchar *src;
12229+
12230+ src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
12231+ flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
12232+ memcpy (buffer, src + offset, len);
12233+ flash_write_cmd (info, 0, 0, info->cmd_reset);
12234+}
12235+
12236+#endif /* CFG_FLASH_PROTECTION */
12237+
12238+/*
12239+ * flash_is_busy - check to see if the flash is busy
12240+ * This routine checks the status of the chip and returns true if the chip is busy
12241+ */
12242+static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
12243+{
12244+ int retval;
12245+
12246+ switch (info->vendor) {
12247+ case CFI_CMDSET_INTEL_STANDARD:
12248+ case CFI_CMDSET_INTEL_EXTENDED:
12249+ retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
12250+ break;
12251+ case CFI_CMDSET_AMD_STANDARD:
12252+ case CFI_CMDSET_AMD_EXTENDED:
12253+ retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
12254+ break;
12255+ default:
12256+ retval = 0;
12257+ }
12258+#ifdef DEBUG_FLASH
12259+ if (retval)
12260+ debug ("flash_is_busy: %d\n", retval);
12261+#endif
12262+ return retval;
12263+}
12264+
12265+/*-----------------------------------------------------------------------
12266+ * wait for XSR.7 to be set. Time out with an error if it does not.
12267+ * This routine does not set the flash to read-array mode.
12268+ */
12269+static int flash_status_check (flash_info_t * info, flash_sect_t sector,
12270+ ulong tout, char *prompt)
12271+{
12272+ ulong start, now;
12273+
12274+ /* Wait for command completion */
12275+ // (Sun) Fix order of checking time so it works when the CPU is very
12276+ // slow, e.g., single-stepping or emulation.
12277+ start = get_timer (0);
12278+ while (now = get_timer(start),
12279+ flash_is_busy (info, sector))
12280+ {
12281+ if (now > info->erase_blk_tout) {
12282+ printf ("Flash %s timeout at address %lx data %lx\n",
12283+ prompt, info->start[sector],
12284+ flash_read_long (info, sector, 0));
12285+ flash_write_cmd (info, sector, 0, info->cmd_reset);
12286+ return ERR_TIMOUT;
12287+ }
12288+ }
12289+ return ERR_OK;
12290+}
12291+
12292+/*-----------------------------------------------------------------------
12293+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
12294+ * This routine sets the flash to read-array mode.
12295+ */
12296+static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
12297+ ulong tout, char *prompt)
12298+{
12299+ int retcode;
12300+
12301+ retcode = flash_status_check (info, sector, tout, prompt);
12302+ switch (info->vendor) {
12303+ case CFI_CMDSET_INTEL_EXTENDED:
12304+ case CFI_CMDSET_INTEL_STANDARD:
12305+ if ((retcode != ERR_OK)
12306+ && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
12307+ retcode = ERR_INVAL;
12308+ printf ("Flash %s error at address %lx\n", prompt,
12309+ info->start[sector]);
12310+ if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
12311+ puts ("Command Sequence Error.\n");
12312+ } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
12313+ puts ("Block Erase Error.\n");
12314+ retcode = ERR_NOT_ERASED;
12315+ } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
12316+ puts ("Locking Error\n");
12317+ }
12318+ if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
12319+ puts ("Block locked.\n");
12320+ retcode = ERR_PROTECTED;
12321+ }
12322+ if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
12323+ puts ("Vpp Low Error.\n");
12324+ }
12325+ flash_write_cmd (info, sector, 0, info->cmd_reset);
12326+ break;
12327+ default:
12328+ break;
12329+ }
12330+ return retcode;
12331+}
12332+
12333+static void write_buffer_abort_reset(flash_info_t * info, flash_sect_t sector)
12334+{
12335+ flash_write_cmd (info, sector, 0xaaa, 0xaa);
12336+ flash_write_cmd (info, sector, 0x555, 0x55);
12337+ flash_write_cmd (info, sector, 0xaaa, 0xf0);
12338+}
12339+
12340+/*-----------------------------------------------------------------------
12341+ */
12342+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
12343+{
12344+#if defined(__LITTLE_ENDIAN)
12345+ unsigned short w;
12346+ unsigned int l;
12347+ unsigned long long ll;
12348+#endif
12349+
12350+ switch (info->portwidth) {
12351+ case FLASH_CFI_8BIT:
12352+ cword->c = c;
12353+ break;
12354+ case FLASH_CFI_16BIT:
12355+#if defined(__LITTLE_ENDIAN)
12356+ w = c;
12357+ w <<= 8;
12358+ cword->w = (cword->w >> 8) | w;
12359+#else
12360+ cword->w = (cword->w << 8) | c;
12361+#endif
12362+ break;
12363+ case FLASH_CFI_32BIT:
12364+#if defined(__LITTLE_ENDIAN)
12365+ l = c;
12366+ l <<= 24;
12367+ cword->l = (cword->l >> 8) | l;
12368+#else
12369+ cword->l = (cword->l << 8) | c;
12370+#endif
12371+ break;
12372+ case FLASH_CFI_64BIT:
12373+#if defined(__LITTLE_ENDIAN)
12374+ ll = c;
12375+ ll <<= 56;
12376+ cword->ll = (cword->ll >> 8) | ll;
12377+#else
12378+ cword->ll = (cword->ll << 8) | c;
12379+#endif
12380+ break;
12381+ }
12382+}
12383+
12384+
12385+/*-----------------------------------------------------------------------
12386+ * make a proper sized command based on the port and chip widths
12387+ */
12388+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
12389+{
12390+ int i;
12391+ uchar *cp = (uchar *) cmdbuf;
12392+
12393+#if defined(__LITTLE_ENDIAN)
12394+ for (i = info->portwidth; i > 0; i--)
12395+#else
12396+ for (i = 1; i <= info->portwidth; i++)
12397+#endif
12398+ *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
12399+}
12400+
12401+/*
12402+ * Write a proper sized command to the correct address
12403+ */
12404+static void
12405+flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset,
12406+ uchar cmd)
12407+{
12408+#ifdef DEBUG_FLASH
12409+ const int noDebug = 0;
12410+#else
12411+ const int noDebug = 1;
12412+#endif
12413+ return flash_write_cmd_int(info, sect, offset, cmd, noDebug);
12414+}
12415+static void
12416+flash_write_cmd_nodbg (flash_info_t * info, flash_sect_t sect, uint offset,
12417+ uchar cmd)
12418+{
12419+ return flash_write_cmd_int(info, sect, offset, cmd, 1);
12420+}
12421+
12422+static void
12423+flash_write_cmd_int (flash_info_t * info, flash_sect_t sect, uint offset,
12424+ uchar cmd, int noDebug)
12425+{
12426+
12427+ volatile cfiptr_t addr;
12428+ cfiword_t cword;
12429+
12430+ addr.cp = flash_make_addr (info, sect, offset);
12431+ flash_make_cmd (info, cmd, &cword);
12432+ switch (info->portwidth) {
12433+ case FLASH_CFI_8BIT:
12434+ if (noDebug == 0)
12435+ debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
12436+ cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
12437+ *addr.cp = cword.c;
12438+ break;
12439+ case FLASH_CFI_16BIT:
12440+ if (noDebug == 0)
12441+ debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
12442+ cmd, cword.w,
12443+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
12444+ *addr.wp = cword.w;
12445+ break;
12446+ case FLASH_CFI_32BIT:
12447+ if (noDebug == 0)
12448+ debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
12449+ cmd, cword.l,
12450+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
12451+ *addr.lp = cword.l;
12452+ break;
12453+ case FLASH_CFI_64BIT:
12454+#ifdef DEBUG_FLASH
12455+ if (noDebug == 0)
12456+ {
12457+ char str[20];
12458+
12459+ print_longlong (str, cword.ll);
12460+
12461+ debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
12462+ addr.llp, cmd, str,
12463+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
12464+ }
12465+#endif
12466+ *addr.llp = cword.ll;
12467+ break;
12468+ }
12469+}
12470+
12471+static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
12472+{
12473+ flash_write_cmd_nodbg (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
12474+ flash_write_cmd_nodbg (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
12475+}
12476+
12477+/*-----------------------------------------------------------------------
12478+ */
12479+static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
12480+{
12481+ cfiptr_t cptr;
12482+ cfiword_t cword;
12483+ int retval;
12484+#ifdef DEBUG_FLASH
12485+ const int dbg = 1;
12486+#else
12487+ const int dbg = 0;
12488+#endif
12489+ cptr.cp = flash_make_addr (info, sect, offset);
12490+ flash_make_cmd (info, cmd, &cword);
12491+
12492+ if (dbg)
12493+ debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
12494+ switch (info->portwidth) {
12495+ case FLASH_CFI_8BIT:
12496+ if (dbg)
12497+ debug ("is= %x %x\n", cptr.cp[0], cword.c);
12498+ retval = (cptr.cp[0] == cword.c);
12499+ break;
12500+ case FLASH_CFI_16BIT:
12501+ if (dbg)
12502+ debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
12503+ retval = (cptr.wp[0] == cword.w);
12504+ break;
12505+ case FLASH_CFI_32BIT:
12506+ if (dbg)
12507+ debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
12508+ retval = (cptr.lp[0] == cword.l);
12509+ break;
12510+ case FLASH_CFI_64BIT:
12511+#ifdef DEBUG_FLASH
12512+ {
12513+ char str1[20];
12514+ char str2[20];
12515+
12516+ print_longlong (str1, cptr.llp[0]);
12517+ print_longlong (str2, cword.ll);
12518+ debug ("is= %s %s\n", str1, str2);
12519+ }
12520+#endif
12521+ retval = (cptr.llp[0] == cword.ll);
12522+ break;
12523+ default:
12524+ retval = 0;
12525+ break;
12526+ }
12527+ return retval;
12528+}
12529+
12530+/*-----------------------------------------------------------------------
12531+ */
12532+static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
12533+{
12534+ cfiptr_t cptr;
12535+ cfiword_t cword;
12536+ int retval;
12537+
12538+ cptr.cp = flash_make_addr (info, sect, offset);
12539+ flash_make_cmd (info, cmd, &cword);
12540+ switch (info->portwidth) {
12541+ case FLASH_CFI_8BIT:
12542+ retval = ((cptr.cp[0] & cword.c) == cword.c);
12543+ break;
12544+ case FLASH_CFI_16BIT:
12545+ retval = ((cptr.wp[0] & cword.w) == cword.w);
12546+ break;
12547+ case FLASH_CFI_32BIT:
12548+ retval = ((cptr.lp[0] & cword.l) == cword.l);
12549+ break;
12550+ case FLASH_CFI_64BIT:
12551+ retval = ((cptr.llp[0] & cword.ll) == cword.ll);
12552+ break;
12553+ default:
12554+ retval = 0;
12555+ break;
12556+ }
12557+ return retval;
12558+}
12559+
12560+/*-----------------------------------------------------------------------
12561+ */
12562+static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
12563+{
12564+ cfiptr_t cptr;
12565+ cfiword_t cword;
12566+ int retval;
12567+
12568+ cptr.cp = flash_make_addr (info, sect, offset);
12569+ flash_make_cmd (info, cmd, &cword);
12570+ switch (info->portwidth) {
12571+ case FLASH_CFI_8BIT:
12572+ retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
12573+ break;
12574+ case FLASH_CFI_16BIT:
12575+ retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
12576+ break;
12577+ case FLASH_CFI_32BIT:
12578+ retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
12579+ break;
12580+ case FLASH_CFI_64BIT:
12581+ retval = ((cptr.llp[0] & cword.ll) !=
12582+ (cptr.llp[0] & cword.ll));
12583+ break;
12584+ default:
12585+ retval = 0;
12586+ break;
12587+ }
12588+ return retval;
12589+}
12590+
12591+/*-----------------------------------------------------------------------
12592+ * detect if flash is compatible with the Common Flash Interface (CFI)
12593+ * http://www.jedec.org/download/search/jesd68.pdf
12594+ *
12595+*/
12596+static int flash_detect_cfi (flash_info_t * info)
12597+{
12598+ ulong data;
12599+
12600+ debug ("flash_detect_cfi()... ");
12601+
12602+#if defined(CONFIG_FLASH_AST2300)
12603+ data = *(ulong *)(0x1e6e2070); /* hardware traping */
12604+ if (data & 0x10) /* D[4]: 0/1 (8/16) */
12605+ info->portwidth = FLASH_CFI_16BIT;
12606+ else
12607+ info->portwidth = FLASH_CFI_8BIT;
12608+#else
12609+ info->portwidth = FLASH_CFI_8BIT;
12610+#endif
12611+
12612+ {
12613+ for (info->chipwidth = FLASH_CFI_BY8;
12614+ info->chipwidth <= info->portwidth;
12615+ info->chipwidth <<= 1) {
12616+ flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
12617+ flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
12618+ if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
12619+ //FIXME: Next 3 lines were changed for 8-bit/16-bit flash chips.
12620+ && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP1, 'R')
12621+ && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP2, 'Y')) {
12622+ info->interface = flash_read_uchar (info, FLASH_OFFSET_INTERFACE);
12623+ debug ("device interface is %d\n",
12624+ info->interface);
12625+ debug ("found port %d chip %d ",
12626+ info->portwidth, info->chipwidth);
12627+ debug ("port %d bits chip %d bits\n",
12628+ info->portwidth << CFI_FLASH_SHIFT_WIDTH,
12629+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
12630+ return 1;
12631+ }
12632+ }
12633+ }
12634+ debug ("not found\n");
12635+ return 0;
12636+}
12637+
12638+/*
12639+ * The following code cannot be run from FLASH!
12640+ *
12641+ */
12642+ulong flash_get_size (ulong base, int banknum)
12643+{
12644+ flash_info_t *info = &flash_info[banknum];
12645+ int i, j;
12646+ flash_sect_t sect_cnt;
12647+ unsigned long sector;
12648+ unsigned long tmp;
12649+ int size_ratio;
12650+ uchar num_erase_regions;
12651+ int erase_region_size;
12652+ int erase_region_count;
12653+
12654+ info->start[0] = base;
12655+
12656+ if (flash_detect_cfi (info)) {
12657+ info->vendor = flash_read_uchar (info, FLASH_OFFSET_PRIMARY_VENDOR);
12658+#if defined(DEBUG_FLASH)
12659+ flash_printqry (info, 0);
12660+#endif
12661+ switch (info->vendor) {
12662+ case CFI_CMDSET_INTEL_STANDARD:
12663+ case CFI_CMDSET_INTEL_EXTENDED:
12664+ default:
12665+ info->cmd_reset = FLASH_CMD_RESET;
12666+ break;
12667+ case CFI_CMDSET_AMD_STANDARD:
12668+ case CFI_CMDSET_AMD_EXTENDED:
12669+ info->cmd_reset = AMD_CMD_RESET;
12670+ break;
12671+ }
12672+
12673+ debugX(2, "manufacturer is %d\n", info->vendor);
12674+ size_ratio = info->portwidth / info->chipwidth;
12675+ /* if the chip is x8/x16 reduce the ratio by half */
12676+#if 0
12677+ if ((info->interface == FLASH_CFI_X8X16)
12678+ && (info->chipwidth == FLASH_CFI_BY8)) {
12679+ size_ratio >>= 1;
12680+ }
12681+#endif
12682+ num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
12683+ debugX(2, "size_ratio %d port %d bits chip %d bits\n",
12684+ size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
12685+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
12686+ debugX(2, "found %d erase regions\n", num_erase_regions);
12687+ sect_cnt = 0;
12688+ sector = base;
12689+ for (i = 0; i < num_erase_regions; i++) {
12690+ if (i > MAX_NUM_ERASE_REGIONS) {
12691+ printf ("%d erase regions found, only %d used\n",
12692+ num_erase_regions, MAX_NUM_ERASE_REGIONS);
12693+ break;
12694+ }
12695+ // CFI Erase Block Region Information:
12696+ // Bits[31:16] = sect_size/256, 0 means 128-byte
12697+ // Bits[15:0] = num_sectors - 1
12698+ tmp = flash_read_long(info, 0,
12699+ FLASH_OFFSET_ERASE_REGIONS + i * 4);
12700+ debug("CFI erase block region info[%d]: 0x%08x, ",
12701+ i, tmp);
12702+ erase_region_count = (tmp & 0xffff) + 1;
12703+ tmp >>= 16;
12704+ erase_region_size = (tmp ? tmp * 256 : 128);
12705+ debug ("erase_region_count=%d erase_region_size=%d\n",
12706+ erase_region_count, erase_region_size);
12707+#if 0
12708+ erase_region_size = CFG_FLASH_SECTOR_SIZE; // Commented out
12709+ erase_region_count = CFG_FLASH_SECTOR_COUNT; // Commented out
12710+#endif
12711+ if (sect_cnt + erase_region_count > CONFIG_SYS_MAX_FLASH_SECT) {
12712+ printf("Warning: Erase region %d adds too many flash sectors"
12713+ " %d+%d; reducing to fit total limit of %d\n",
12714+ i, sect_cnt, erase_region_count, CONFIG_SYS_MAX_FLASH_SECT);
12715+ erase_region_count = CONFIG_SYS_MAX_FLASH_SECT - sect_cnt;
12716+ }
12717+ for (j = 0; j < erase_region_count; j++) {
12718+ info->start[sect_cnt] = sector;
12719+ sector += (erase_region_size * size_ratio);
12720+
12721+ /*
12722+ * Only read protection status from supported devices (intel...)
12723+ */
12724+ switch (info->vendor) {
12725+ case CFI_CMDSET_INTEL_EXTENDED:
12726+ case CFI_CMDSET_INTEL_STANDARD:
12727+ info->protect[sect_cnt] =
12728+ flash_isset (info, sect_cnt,
12729+ FLASH_OFFSET_PROTECT,
12730+ FLASH_STATUS_PROTECT);
12731+ break;
12732+ default:
12733+ info->protect[sect_cnt] = 0; /* default: not protected */
12734+ }
12735+
12736+ sect_cnt++;
12737+ }
12738+ }
12739+
12740+ info->sector_count = sect_cnt;
12741+ /* multiply the size by the number of chips */
12742+ // info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
12743+ // Use only the sectors that fit within the flash_info array size.
12744+ info->size = sector - base;
12745+ printf("Flash bank %d at %08x has 0x%x bytes in %d sectors"
12746+ " (chipSize 1<<%d, size_ratio %d).\n",
12747+ banknum, base, info->size, info->sector_count,
12748+ flash_read_uchar(info, FLASH_OFFSET_SIZE), size_ratio);
12749+
12750+ info->buffer_size = (1 << flash_read_uchar (info, FLASH_OFFSET_BUFFER_SIZE));
12751+ /* Limit the buffer size to 32bytes to meet most of AMD-styles flash's minimum requirement */
12752+ if (info->buffer_size > 32)
12753+ info->buffer_size = 32;
12754+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
12755+ info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
12756+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
12757+ info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
12758+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
12759+ info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
12760+ info->flash_id = FLASH_MAN_CFI;
12761+#if 0
12762+ if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
12763+ info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
12764+ }
12765+#endif
12766+ }
12767+
12768+ flash_write_cmd (info, 0, 0, info->cmd_reset);
12769+ return (info->size);
12770+}
12771+
12772+
12773+/*-----------------------------------------------------------------------
12774+ */
12775+static int flash_write_cfiword (flash_info_t * info, ulong dest,
12776+ cfiword_t cword)
12777+{
12778+
12779+ cfiptr_t ctladdr;
12780+ cfiptr_t cptr;
12781+ int flag;
12782+
12783+ ctladdr.cp = flash_make_addr (info, 0, 0);
12784+ cptr.cp = (uchar *) dest;
12785+
12786+
12787+ /* Check if Flash is (sufficiently) erased */
12788+ switch (info->portwidth) {
12789+ case FLASH_CFI_8BIT:
12790+ flag = ((cptr.cp[0] & cword.c) == cword.c);
12791+ break;
12792+ case FLASH_CFI_16BIT:
12793+ flag = ((cptr.wp[0] & cword.w) == cword.w);
12794+ break;
12795+ case FLASH_CFI_32BIT:
12796+ flag = ((cptr.lp[0] & cword.l) == cword.l);
12797+ break;
12798+ case FLASH_CFI_64BIT:
12799+ flag = ((cptr.llp[0] & cword.ll) == cword.ll);
12800+ break;
12801+ default:
12802+ return 2;
12803+ }
12804+ if (!flag)
12805+ return 2;
12806+
12807+ /* Disable interrupts which might cause a timeout here */
12808+ flag = disable_interrupts ();
12809+
12810+ switch (info->vendor) {
12811+ case CFI_CMDSET_INTEL_EXTENDED:
12812+ case CFI_CMDSET_INTEL_STANDARD:
12813+ flash_write_cmd_nodbg (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
12814+ flash_write_cmd_nodbg (info, 0, 0, FLASH_CMD_WRITE);
12815+ break;
12816+ case CFI_CMDSET_AMD_EXTENDED:
12817+ case CFI_CMDSET_AMD_STANDARD:
12818+ flash_unlock_seq (info, 0);
12819+ flash_write_cmd_nodbg (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
12820+ break;
12821+ }
12822+
12823+ switch (info->portwidth) {
12824+ case FLASH_CFI_8BIT:
12825+ cptr.cp[0] = cword.c;
12826+ break;
12827+ case FLASH_CFI_16BIT:
12828+ cptr.wp[0] = cword.w;
12829+ break;
12830+ case FLASH_CFI_32BIT:
12831+ cptr.lp[0] = cword.l;
12832+ break;
12833+ case FLASH_CFI_64BIT:
12834+ cptr.llp[0] = cword.ll;
12835+ break;
12836+ }
12837+
12838+ /* re-enable interrupts if necessary */
12839+ if (flag)
12840+ enable_interrupts ();
12841+
12842+ return flash_full_status_check (info, 0, info->write_tout, "write");
12843+}
12844+
12845+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
12846+
12847+/* loop through the sectors from the highest address
12848+ * when the passed address is greater or equal to the sector address
12849+ * we have a match
12850+ */
12851+static flash_sect_t find_sector (flash_info_t * info, ulong addr)
12852+{
12853+ flash_sect_t sector;
12854+
12855+ for (sector = info->sector_count - 1; sector >= 0; sector--) {
12856+ if (addr >= info->start[sector])
12857+ break;
12858+ }
12859+ return sector;
12860+}
12861+
12862+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
12863+ int len)
12864+{
12865+ flash_sect_t sector;
12866+ int cnt;
12867+ int retcode;
12868+ volatile cfiptr_t src;
12869+ volatile cfiptr_t dst;
12870+
12871+/* Add AMD write buffer mode support, ycchen@102006 */
12872+#if 0
12873+ /* buffered writes in the AMD chip set is not supported yet */
12874+ if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
12875+ (info->vendor == CFI_CMDSET_AMD_EXTENDED))
12876+ return ERR_INVAL;
12877+#endif
12878+ if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
12879+ (info->vendor == CFI_CMDSET_AMD_EXTENDED))
12880+ {
12881+ retcode = flash_write_cfibuffer_amd(info, dest, cp, len);
12882+ return retcode;
12883+ }
12884+
12885+ src.cp = cp;
12886+ dst.cp = (uchar *) dest;
12887+ sector = find_sector (info, dest);
12888+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
12889+ flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
12890+ if ((retcode =
12891+ flash_status_check (info, sector, info->buffer_write_tout,
12892+ "write to buffer")) == ERR_OK) {
12893+ /* reduce the number of loops by the width of the port */
12894+ switch (info->portwidth) {
12895+ case FLASH_CFI_8BIT:
12896+ cnt = len;
12897+ break;
12898+ case FLASH_CFI_16BIT:
12899+ cnt = len >> 1;
12900+ break;
12901+ case FLASH_CFI_32BIT:
12902+ cnt = len >> 2;
12903+ break;
12904+ case FLASH_CFI_64BIT:
12905+ cnt = len >> 3;
12906+ break;
12907+ default:
12908+ return ERR_INVAL;
12909+ break;
12910+ }
12911+ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
12912+ while (cnt-- > 0) {
12913+ switch (info->portwidth) {
12914+ case FLASH_CFI_8BIT:
12915+ *dst.cp++ = *src.cp++;
12916+ break;
12917+ case FLASH_CFI_16BIT:
12918+ *dst.wp++ = *src.wp++;
12919+ break;
12920+ case FLASH_CFI_32BIT:
12921+ *dst.lp++ = *src.lp++;
12922+ break;
12923+ case FLASH_CFI_64BIT:
12924+ *dst.llp++ = *src.llp++;
12925+ break;
12926+ default:
12927+ return ERR_INVAL;
12928+ break;
12929+ }
12930+ }
12931+ flash_write_cmd (info, sector, 0,
12932+ FLASH_CMD_WRITE_BUFFER_CONFIRM);
12933+ retcode =
12934+ flash_full_status_check (info, sector,
12935+ info->buffer_write_tout,
12936+ "buffer write");
12937+ }
12938+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
12939+ return retcode;
12940+}
12941+
12942+
12943+static int flash_write_cfibuffer_amd (flash_info_t * info, ulong dest, uchar * cp,
12944+ int len)
12945+{
12946+ flash_sect_t sector;
12947+ int cnt;
12948+ int retcode;
12949+ volatile cfiptr_t src;
12950+ volatile cfiptr_t dst;
12951+ volatile cfiword_t tmpsrc, tmpdst;
12952+
12953+ src.cp = cp;
12954+ dst.cp = (uchar *) dest;
12955+ sector = find_sector (info, dest);
12956+ flash_unlock_seq (info, 0);
12957+ if ((retcode =
12958+ flash_status_check (info, sector, info->buffer_write_tout,
12959+ "write to buffer")) == ERR_OK) {
12960+ /* reduce the number of loops by the width of the port */
12961+ switch (info->portwidth) {
12962+ case FLASH_CFI_8BIT:
12963+ cnt = len;
12964+ *dst.cp = (uchar) (AMD_CMD_WRITE_TO_BUFFER);
12965+ *dst.cp = (uchar) (cnt -1);
12966+ break;
12967+ case FLASH_CFI_16BIT:
12968+ cnt = len >> 1;
12969+ *dst.wp = (unsigned short) (AMD_CMD_WRITE_TO_BUFFER);
12970+ *dst.wp = (unsigned short) (cnt -1);
12971+ break;
12972+ case FLASH_CFI_32BIT:
12973+ cnt = len >> 2;
12974+ *dst.lp = (unsigned long) (AMD_CMD_WRITE_TO_BUFFER);
12975+ *dst.lp = (unsigned long) (cnt -1);
12976+ break;
12977+ case FLASH_CFI_64BIT:
12978+ cnt = len >> 3;
12979+ *dst.llp = (unsigned long long) (AMD_CMD_WRITE_TO_BUFFER);
12980+ *dst.llp = (unsigned long long) (cnt -1);
12981+ break;
12982+ default:
12983+ return ERR_INVAL;
12984+ break;
12985+ }
12986+ while (cnt-- > 0) {
12987+ switch (info->portwidth) {
12988+ case FLASH_CFI_8BIT:
12989+ *dst.cp++ = *src.cp++;
12990+ break;
12991+ case FLASH_CFI_16BIT:
12992+ *dst.wp++ = *src.wp++;
12993+ break;
12994+ case FLASH_CFI_32BIT:
12995+ *dst.lp++ = *src.lp++;
12996+ break;
12997+ case FLASH_CFI_64BIT:
12998+ *dst.llp++ = *src.llp++;
12999+ break;
13000+ default:
13001+ return ERR_INVAL;
13002+ break;
13003+ }
13004+ }
13005+ switch (info->portwidth) {
13006+ case FLASH_CFI_8BIT:
13007+ src.cp--;
13008+ dst.cp--;
13009+ *dst.cp = (unsigned char) (AMD_CMD_BUFFER_TO_FLASH);
13010+ tmpsrc.c = *src.cp & 0x80;
13011+
13012+ do {
13013+ tmpdst.c = *(volatile uchar *)(dst.cp);
13014+
13015+ if (tmpdst.c & 0x20) { /* toggle DQ5 */
13016+ tmpdst.c = *(volatile uchar *)(dst.cp);
13017+ if ((tmpdst.c & 0x80) != tmpsrc.c)
13018+ {
13019+ printf("program error occurred\n");
13020+ flash_write_cmd (info, sector, 0, info->cmd_reset);
13021+ return ERR_PROG_ERROR;
13022+ }
13023+ }
13024+ else if (tmpdst.c & 0x02) { /* toggle DQ1 */
13025+ tmpdst.c = *(volatile uchar *)(dst.cp);
13026+ if ((tmpdst.c & 0x80) != tmpsrc.c)
13027+ {
13028+ printf("write buffer error occurred \n");
13029+ write_buffer_abort_reset(info, sector);
13030+ return ERR_PROG_ERROR;
13031+ }
13032+ }
13033+
13034+ } while ((tmpdst.c & 0x80) != tmpsrc.c);
13035+
13036+ break;
13037+ case FLASH_CFI_16BIT:
13038+ src.wp--;
13039+ dst.wp--;
13040+ *dst.wp = (unsigned short) (AMD_CMD_BUFFER_TO_FLASH);
13041+ tmpsrc.w = *src.wp & 0x80;
13042+
13043+ do {
13044+ tmpdst.w = *(volatile short *)(dst.wp);
13045+
13046+ if (tmpdst.w & 0x20) { /* toggle DQ5 */
13047+ tmpdst.w = *(volatile ushort *)(dst.wp);
13048+ if ((tmpdst.w & 0x80) != tmpsrc.w)
13049+ {
13050+ printf("program error occurred\n");
13051+ flash_write_cmd (info, sector, 0, info->cmd_reset);
13052+ return ERR_PROG_ERROR;
13053+ }
13054+ }
13055+ else if (tmpdst.w & 0x02) { /* toggle DQ1 */
13056+ tmpdst.w = *(volatile ushort *)(dst.wp);
13057+ if ((tmpdst.w & 0x80) != tmpsrc.w)
13058+ {
13059+ printf("write buffer error occurred \n");
13060+ write_buffer_abort_reset(info, sector);
13061+ return ERR_PROG_ERROR;
13062+ }
13063+ }
13064+
13065+ } while ((tmpdst.w & 0x80) != tmpsrc.w);
13066+
13067+ break;
13068+ case FLASH_CFI_32BIT:
13069+ src.lp--;
13070+ dst.lp--;
13071+ *dst.lp = (unsigned long) (AMD_CMD_BUFFER_TO_FLASH);
13072+ tmpsrc.l = *src.lp & 0x80;
13073+
13074+ do {
13075+ tmpdst.l = *(volatile ulong *)(dst.lp);
13076+
13077+ if (tmpdst.l & 0x20) { /* toggle DQ5 */
13078+ tmpdst.l = *(volatile ulong *)(dst.lp);
13079+ if ((tmpdst.l & 0x80) != tmpsrc.l)
13080+ {
13081+ printf("program error occurred\n");
13082+ flash_write_cmd (info, sector, 0, info->cmd_reset);
13083+ return ERR_PROG_ERROR;
13084+ }
13085+ }
13086+ else if (tmpdst.l & 0x02) { /* toggle DQ1 */
13087+ tmpdst.l = *(volatile ulong *)(dst.lp);
13088+ if ((tmpdst.l & 0x80) != tmpsrc.l)
13089+ {
13090+ printf("write buffer error occurred \n");
13091+ write_buffer_abort_reset(info, sector);
13092+ return ERR_PROG_ERROR;
13093+ }
13094+ }
13095+
13096+ } while ((tmpdst.l & 0x80) != tmpsrc.l);
13097+
13098+ break;
13099+ case FLASH_CFI_64BIT:
13100+ src.llp--;
13101+ dst.llp--;
13102+ *dst.llp = (unsigned long long) (AMD_CMD_BUFFER_TO_FLASH);
13103+ tmpsrc.ll = *src.llp & 0x80;
13104+
13105+ do {
13106+ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
13107+
13108+ if (tmpdst.ll & 0x20) { /* toggle DQ5 */
13109+ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
13110+ if ((tmpdst.ll & 0x80) != tmpsrc.ll)
13111+ {
13112+ printf("program error occurred\n");
13113+ flash_write_cmd (info, sector, 0, info->cmd_reset);
13114+ return ERR_PROG_ERROR;
13115+ }
13116+ }
13117+ else if (tmpdst.ll & 0x02) { /* toggle DQ1 */
13118+ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
13119+ if ((tmpdst.ll & 0x80) != tmpsrc.ll)
13120+ {
13121+ printf("write buffer error occurred \n");
13122+ write_buffer_abort_reset(info, sector);
13123+ return ERR_PROG_ERROR;
13124+ }
13125+ }
13126+
13127+ } while ((tmpdst.ll & 0x80) != tmpsrc.ll);
13128+
13129+ break;
13130+ default:
13131+ return ERR_INVAL;
13132+ break;
13133+ }
13134+
13135+ retcode =
13136+ flash_full_status_check (info, sector,
13137+ info->buffer_write_tout,
13138+ "buffer write");
13139+ }
13140+
13141+ return retcode;
13142+}
13143+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
13144+
13145+#ifdef CONFIG_FLASH_AST2300_DMA
13146+#define STCBaseAddress 0x1e620000
13147+
13148+/* for DMA */
13149+#define REG_FLASH_INTERRUPT_STATUS 0x08
13150+#define REG_FLASH_DMA_CONTROL 0x80
13151+#define REG_FLASH_DMA_FLASH_BASE 0x84
13152+#define REG_FLASH_DMA_DRAM_BASE 0x88
13153+#define REG_FLASH_DMA_LENGTH 0x8c
13154+
13155+#define FLASH_STATUS_DMA_BUSY 0x0000
13156+#define FLASH_STATUS_DMA_READY 0x0800
13157+#define FLASH_STATUS_DMA_CLEAR 0x0800
13158+
13159+#define FLASH_DMA_ENABLE 0x01
13160+
13161+void * memmove_dma(void * dest,const void *src,size_t count)
13162+{
13163+ ulong count_align, poll_time, data;
13164+
13165+ count_align = (count + 3) & 0xFFFFFFFC; /* 4-bytes align */
13166+ poll_time = 100; /* set 100 us as default */
13167+
13168+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE);
13169+
13170+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_FLASH_BASE) = (ulong *) (src);
13171+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_DRAM_BASE) = (ulong *) (dest);
13172+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_LENGTH) = (ulong) (count_align);
13173+ udelay(10);
13174+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE);
13175+
13176+ /* wait poll */
13177+ do {
13178+ udelay(poll_time);
13179+ data = *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS);
13180+ } while (!(data & FLASH_STATUS_DMA_READY));
13181+
13182+ /* clear status */
13183+ *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR;
13184+}
13185+#endif
13186+#endif /* CFG_FLASH_CFI */
13187diff --git a/board/aspeed/ast2300/flash_spi.c b/board/aspeed/ast2300/flash_spi.c
13188new file mode 100755
13189index 0000000..6660628
13190--- /dev/null
13191+++ b/board/aspeed/ast2300/flash_spi.c
13192@@ -0,0 +1,1639 @@
13193+/*
13194+ * This program is free software; you can redistribute it and/or
13195+ * modify it under the terms of the GNU General Public License as
13196+ * published by the Free Software Foundation; either version 2 of
13197+ * the License, or (at your option) any later version.
13198+ *
13199+ * This program is distributed in the hope that it will be useful,
13200+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
13201+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13202+ * GNU General Public License for more details.
13203+ *
13204+ * You should have received a copy of the GNU General Public License
13205+ * along with this program; if not, write to the Free Software
13206+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
13207+ * MA 02111-1307 USA
13208+ *
13209+ * History
13210+ * 01/20/2004 - combined variants of original driver.
13211+ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
13212+ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
13213+ * 01/27/2004 - Little endian support Ed Okerson
13214+ *
13215+ * Tested Architectures
13216+ * Port Width Chip Width # of banks Flash Chip Board
13217+ * 32 16 1 28F128J3 seranoa/eagle
13218+ * 64 16 1 28F128J3 seranoa/falcon
13219+ *
13220+ */
13221+
13222+/* The DEBUG define must be before common to enable debugging */
13223+/* #define DEBUG */
13224+
13225+#include <common.h>
13226+#include <asm/processor.h>
13227+#include <asm/byteorder.h>
13228+#include <environment.h>
13229+#ifdef CONFIG_FLASH_SPI
13230+
13231+/*
13232+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
13233+ * The width of the port and the width of the chips are determined at initialization.
13234+ * These widths are used to calculate the address for access CFI data structures.
13235+ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
13236+ *
13237+ * References
13238+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
13239+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
13240+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
13241+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
13242+ *
13243+ * TODO
13244+ *
13245+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
13246+ * Table (ALT) to determine if protection is available
13247+ *
13248+ * Add support for other command sets Use the PRI and ALT to determine command set
13249+ * Verify erase and program timeouts.
13250+ */
13251+
13252+#ifndef CONFIG_FLASH_BANKS_LIST
13253+#define CONFIG_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
13254+#endif
13255+
13256+/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
13257+#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
13258+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS_DETECT] = CONFIG_FLASH_BANKS_LIST;
13259+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
13260+#else
13261+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_FLASH_BANKS_LIST;
13262+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
13263+#endif
13264+
13265+/* Support Flash ID */
13266+#define STM25P64 0x172020
13267+#define STM25P128 0x182020
13268+#define N25Q256 0x19ba20
13269+#define N25Q512 0x20ba20
13270+#define S25FL064A 0x160201
13271+#define S25FL128P 0x182001
13272+#define S25FL256S 0x190201
13273+#define W25X16 0x1530ef
13274+#define W25X64 0x1730ef
13275+#define W25Q64BV 0x1740ef
13276+#define W25Q128BV 0x1840ef
13277+#define W25Q256FV 0x1940ef
13278+#define MX25L1605D 0x1520C2
13279+#define MX25L12805D 0x1820C2
13280+#define MX25L25635E 0x1920C2
13281+#define SST25VF016B 0x4125bf
13282+#define SST25VF064C 0x4b25bf
13283+#define AT25DF161 0x02461F
13284+#define AT25DF321 0x01471F
13285+
13286+/* SPI Define */
13287+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
13288+#if defined(CONFIG_AST1300)
13289+#define STCBaseAddress 0x00620000
13290+#else
13291+#define STCBaseAddress 0x1e620000
13292+#endif
13293+#define SCU_REVISION_REGISTER 0x1e6e207c
13294+#define SCU_CACHE_CTRL_REGISTER 0x1e6e2118
13295+
13296+#define SPICtrlRegOffset 0x10
13297+#define SPICtrlRegOffset2 0x14
13298+
13299+#define SPIMiscCtrlRegOffset 0x54
13300+
13301+/* for DMA */
13302+#define REG_FLASH_INTERRUPT_STATUS 0x08
13303+#define REG_FLASH_DMA_CONTROL 0x80
13304+#define REG_FLASH_DMA_FLASH_BASE 0x84
13305+#define REG_FLASH_DMA_DRAM_BASE 0x88
13306+#define REG_FLASH_DMA_LENGTH 0x8c
13307+
13308+#define FLASH_STATUS_DMA_BUSY 0x0000
13309+#define FLASH_STATUS_DMA_READY 0x0800
13310+#define FLASH_STATUS_DMA_CLEAR 0x0800
13311+
13312+#define FLASH_DMA_ENABLE 0x01
13313+#else
13314+#define STCBaseAddress 0x16000000
13315+
13316+#define SPICtrlRegOffset 0x04
13317+#define SPICtrlRegOffset2 0x0C
13318+#endif /* CONFIG_FLASH_AST2300 */
13319+
13320+#define CMD_MASK 0xFFFFFFF8
13321+
13322+#define NORMALREAD 0x00
13323+#define FASTREAD 0x01
13324+#define NORMALWRITE 0x02
13325+#define USERMODE 0x03
13326+
13327+#define CE_LOW 0x00
13328+#define CE_HIGH 0x04
13329+
13330+/* AST2300 only */
13331+#define IOMODEx1 0x00000000
13332+#define IOMODEx2 0x20000000
13333+#define IOMODEx2_dummy 0x30000000
13334+#define IOMODEx4 0x40000000
13335+#define IOMODEx4_dummy 0x50000000
13336+
13337+#define DUMMY_COMMAND_OUT 0x00008000
13338+/* ~AST2300 only */
13339+
13340+/* specificspi */
13341+#define SpecificSPI_N25Q512 0x00000001
13342+
13343+static ulong AST2300_SPICLK_DIV[16] = {0x0F, 0x07, 0x0E, 0x06, 0x0D, 0x05, 0x0C, 0x04, \
13344+ 0x0B, 0x03, 0x0A, 0x02, 0x09, 0x01, 0x08, 0x00 };
13345+
13346+/*-----------------------------------------------------------------------
13347+ * Functions
13348+ */
13349+static void reset_flash (flash_info_t * info);
13350+static void enable_write (flash_info_t * info);
13351+static void write_status_register (flash_info_t * info, uchar data);
13352+static void enable4b (flash_info_t * info);
13353+static void enable4b_spansion (flash_info_t * info);
13354+static void enable4b_numonyx (flash_info_t * info);
13355+static ulong flash_get_size (ulong base, int banknum);
13356+static int flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len);
13357+#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
13358+static flash_info_t *flash_get_info(ulong base);
13359+#endif
13360+
13361+
13362+/*-----------------------------------------------------------------------
13363+ * create an address based on the offset and the port width
13364+ */
13365+inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
13366+{
13367+#ifdef CONFIG_2SPIFLASH
13368+ if (info->start[0] >= PHYS_FLASH_2)
13369+ return ((uchar *) (info->start[sect] + (offset * 1) - (PHYS_FLASH_2 - PHYS_FLASH_2_BASE) ));
13370+ else
13371+ return ((uchar *) (info->start[sect] + (offset * 1)));
13372+#else
13373+ return ((uchar *) (info->start[sect] + (offset * 1)));
13374+#endif
13375+}
13376+
13377+/*-----------------------------------------------------------------------
13378+ * read a character at a port width address
13379+ */
13380+inline uchar flash_read_uchar (flash_info_t * info, uint offset)
13381+{
13382+ uchar *cp;
13383+
13384+ cp = flash_make_addr (info, 0, offset);
13385+#if defined(__LITTLE_ENDIAN)
13386+ return (cp[0]);
13387+#else
13388+ return (cp[1 - 1]);
13389+#endif
13390+}
13391+
13392+/*-----------------------------------------------------------------------
13393+ * read a short word by swapping for ppc format.
13394+ */
13395+ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
13396+{
13397+ uchar *addr;
13398+ ushort retval;
13399+
13400+#ifdef DEBUG
13401+ int x;
13402+#endif
13403+ addr = flash_make_addr (info, sect, offset);
13404+
13405+#ifdef DEBUG
13406+ debug ("ushort addr is at %p 1 = %d\n", addr,
13407+ 1);
13408+ for (x = 0; x < 2 * 1; x++) {
13409+ debug ("addr[%x] = 0x%x\n", x, addr[x]);
13410+ }
13411+#endif
13412+#if defined(__LITTLE_ENDIAN)
13413+ retval = ((addr[(1)] << 8) | addr[0]);
13414+#else
13415+ retval = ((addr[(2 * 1) - 1] << 8) |
13416+ addr[1 - 1]);
13417+#endif
13418+
13419+ debug ("retval = 0x%x\n", retval);
13420+ return retval;
13421+}
13422+
13423+/*-----------------------------------------------------------------------
13424+ * read a long word by picking the least significant byte of each maiximum
13425+ * port size word. Swap for ppc format.
13426+ */
13427+ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
13428+{
13429+ uchar *addr;
13430+ ulong retval;
13431+
13432+#ifdef DEBUG
13433+ int x;
13434+#endif
13435+ addr = flash_make_addr (info, sect, offset);
13436+
13437+#ifdef DEBUG
13438+ debug ("long addr is at %p 1 = %d\n", addr,
13439+ 1);
13440+ for (x = 0; x < 4 * 1; x++) {
13441+ debug ("addr[%x] = 0x%x\n", x, addr[x]);
13442+ }
13443+#endif
13444+#if defined(__LITTLE_ENDIAN)
13445+ retval = (addr[0] << 16) | (addr[(1)] << 24) |
13446+ (addr[(2 * 1)]) | (addr[(3 * 1)] << 8);
13447+#else
13448+ retval = (addr[(2 * 1) - 1] << 24) |
13449+ (addr[(1) - 1] << 16) |
13450+ (addr[(4 * 1) - 1] << 8) |
13451+ addr[(3 * 1) - 1];
13452+#endif
13453+ return retval;
13454+}
13455+
13456+/*-----------------------------------------------------------------------
13457+ */
13458+static void disable_cache(void)
13459+{
13460+#if defined(AST1300_CPU_CACHE_ENABLE)
13461+ ulong uldata;
13462+
13463+ uldata = *(volatile ulong *) (SCU_CACHE_CTRL_REGISTER);
13464+ uldata &= 0xfffffffd;
13465+ *(ulong *) (SCU_CACHE_CTRL_REGISTER) = uldata;
13466+#endif
13467+}
13468+
13469+static void enable_cache(void)
13470+{
13471+#if defined(AST1300_CPU_CACHE_ENABLE)
13472+ ulong uldata;
13473+
13474+ uldata = *(volatile ulong *) (SCU_CACHE_CTRL_REGISTER);
13475+ uldata |= 0x00000002;
13476+ *(ulong *) (SCU_CACHE_CTRL_REGISTER) = uldata;
13477+#endif
13478+}
13479+
13480+static void reset_flash (flash_info_t * info)
13481+{
13482+ ulong ulCtrlData, CtrlOffset, MiscCtrlOffset;
13483+
13484+ if (info->CE == 2)
13485+ {
13486+ CtrlOffset = SPICtrlRegOffset2;
13487+ }
13488+ else
13489+ {
13490+ CtrlOffset = SPICtrlRegOffset;
13491+ }
13492+
13493+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
13494+ ulCtrlData = info->iomode | (info->readcmd << 16) | (info->tCK_Read << 8) | (info->dummybyte << 6) | FASTREAD;
13495+#if 0
13496+ if (info->quadport)
13497+ {
13498+ MiscCtrlOffset = SPIMiscCtrlRegOffset;
13499+ *(ulong *) (STCBaseAddress + MiscCtrlOffset) = info->dummydata;
13500+ ulCtrlData |= DUMMY_COMMAND_OUT;
13501+ }
13502+#endif
13503+#else
13504+ ulCtrlData = (info->readcmd << 16) | (info->tCK_Read << 8) | (info->dummybyte << 6) | FASTREAD;
13505+ if (info->dualport)
13506+ ulCtrlData |= 0x08;
13507+#endif
13508+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13509+
13510+ enable_cache();
13511+}
13512+
13513+static void enable_write (flash_info_t * info)
13514+{
13515+ ulong base;
13516+ ulong ulCtrlData, CtrlOffset;
13517+ uchar jReg;
13518+
13519+ if (info->CE == 2)
13520+ {
13521+ CtrlOffset = SPICtrlRegOffset2;
13522+ }
13523+ else
13524+ {
13525+ CtrlOffset = SPICtrlRegOffset;
13526+ }
13527+
13528+ //base = info->start[0];
13529+ base = flash_make_addr (info, 0, 0);
13530+
13531+ ulCtrlData = (info->tCK_Write << 8);
13532+ ulCtrlData |= CE_LOW | USERMODE;
13533+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13534+ udelay(200);
13535+ *(uchar *) (base) = (uchar) (0x06);
13536+ udelay(10);
13537+ ulCtrlData &= CMD_MASK;
13538+ ulCtrlData |= CE_HIGH | USERMODE;
13539+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13540+ udelay(200);
13541+
13542+ ulCtrlData &= CMD_MASK;
13543+ ulCtrlData |= CE_LOW | USERMODE;
13544+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13545+ udelay(200);
13546+ *(uchar *) (base) = (uchar) (0x05);
13547+ udelay(10);
13548+ do {
13549+ jReg = *(volatile uchar *) (base);
13550+ } while (!(jReg & 0x02));
13551+ ulCtrlData &= CMD_MASK;
13552+ ulCtrlData |= CE_HIGH | USERMODE;
13553+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13554+ udelay(200);
13555+
13556+}
13557+
13558+static void write_status_register (flash_info_t * info, uchar data)
13559+{
13560+ ulong base;
13561+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
13562+ uchar jReg;
13563+
13564+ if (info->CE == 2)
13565+ {
13566+ CtrlOffset = SPICtrlRegOffset2;
13567+ }
13568+ else
13569+ {
13570+ CtrlOffset = SPICtrlRegOffset;
13571+ }
13572+
13573+ //base = info->start[0];
13574+ base = flash_make_addr (info, 0, 0);
13575+
13576+ enable_write (info);
13577+
13578+ ulCtrlData = (info->tCK_Write << 8);
13579+ ulCtrlData |= CE_LOW | USERMODE;
13580+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13581+ udelay(200);
13582+ *(uchar *) (base) = (uchar) (0x01);
13583+ udelay(10);
13584+ *(uchar *) (base) = (uchar) (data);
13585+ ulCtrlData &= CMD_MASK;
13586+ ulCtrlData |= CE_HIGH | USERMODE;
13587+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13588+ udelay(200);
13589+
13590+ ulCtrlData &= CMD_MASK;
13591+ ulCtrlData |= CE_LOW | USERMODE;
13592+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13593+ udelay(200);
13594+ *(uchar *) (base) = (uchar) (0x05);
13595+ udelay(10);
13596+ do {
13597+ jReg = *(volatile uchar *) (base);
13598+ } while (jReg & 0x01);
13599+ ulCtrlData &= CMD_MASK;
13600+ ulCtrlData |= CE_HIGH | USERMODE;
13601+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13602+ udelay(200);
13603+
13604+}
13605+
13606+static void enable4b (flash_info_t * info)
13607+{
13608+ ulong base;
13609+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
13610+ uchar jReg;
13611+
13612+ if (info->CE == 2)
13613+ {
13614+ CtrlOffset = SPICtrlRegOffset2;
13615+ }
13616+ else
13617+ {
13618+ CtrlOffset = SPICtrlRegOffset;
13619+ }
13620+
13621+ //base = info->start[0];
13622+ base = flash_make_addr (info, 0, 0);
13623+
13624+ ulCtrlData = (info->tCK_Write << 8);
13625+ ulCtrlData |= CE_LOW | USERMODE;
13626+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13627+ udelay(200);
13628+ *(uchar *) (base) = (uchar) (0xb7);
13629+ ulCtrlData &= CMD_MASK;
13630+ ulCtrlData |= CE_HIGH | USERMODE;
13631+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13632+ udelay(200);
13633+
13634+} /* enable4b */
13635+
13636+static void enable4b_spansion (flash_info_t * info)
13637+{
13638+ ulong base;
13639+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
13640+ uchar jReg;
13641+
13642+ if (info->CE == 2)
13643+ {
13644+ CtrlOffset = SPICtrlRegOffset2;
13645+ }
13646+ else
13647+ {
13648+ CtrlOffset = SPICtrlRegOffset;
13649+ }
13650+
13651+ //base = info->start[0];
13652+ base = flash_make_addr (info, 0, 0);
13653+
13654+ /* Enable 4B: BAR0 D[7] = 1 */
13655+ ulCtrlData = (info->tCK_Write << 8);
13656+ ulCtrlData |= CE_LOW | USERMODE;
13657+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13658+ udelay(200);
13659+ *(uchar *) (base) = (uchar) (0x17);
13660+ udelay(10);
13661+ *(uchar *) (base) = (uchar) (0x80);
13662+ ulCtrlData &= CMD_MASK;
13663+ ulCtrlData |= CE_HIGH | USERMODE;
13664+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13665+ udelay(200);
13666+
13667+ ulCtrlData &= CMD_MASK;
13668+ ulCtrlData |= CE_LOW | USERMODE;
13669+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13670+ udelay(200);
13671+ *(uchar *) (base) = (uchar) (0x16);
13672+ udelay(10);
13673+ do {
13674+ jReg = *(volatile uchar *) (base);
13675+ } while (!(jReg & 0x80));
13676+ ulCtrlData &= CMD_MASK;
13677+ ulCtrlData |= CE_HIGH | USERMODE;
13678+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13679+ udelay(200);
13680+
13681+} /* enable4b_spansion */
13682+
13683+static void enable4b_numonyx (flash_info_t * info)
13684+{
13685+ ulong base;
13686+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
13687+ uchar jReg;
13688+
13689+ if (info->CE == 2)
13690+ {
13691+ CtrlOffset = SPICtrlRegOffset2;
13692+ }
13693+ else
13694+ {
13695+ CtrlOffset = SPICtrlRegOffset;
13696+ }
13697+
13698+ //base = info->start[0];
13699+ base = flash_make_addr (info, 0, 0);
13700+
13701+ /* Enable Write */
13702+ enable_write (info);
13703+
13704+ /* Enable 4B: CMD:0xB7 */
13705+ ulCtrlData = (info->tCK_Write << 8);
13706+ ulCtrlData |= CE_LOW | USERMODE;
13707+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13708+ udelay(200);
13709+ *(uchar *) (base) = (uchar) (0xB7);
13710+ udelay(10);
13711+ ulCtrlData &= CMD_MASK;
13712+ ulCtrlData |= CE_HIGH | USERMODE;
13713+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13714+ udelay(200);
13715+
13716+} /* enable4b_numonyx */
13717+
13718+/*
13719+ *
13720+ */
13721+static ulong flash_get_size (ulong base, int banknum)
13722+{
13723+ flash_info_t *info = &flash_info[banknum];
13724+ int j;
13725+ unsigned long sector;
13726+ int erase_region_size;
13727+ ulong ulCtrlData, CtrlOffset;
13728+ ulong ulID;
13729+ uchar ch[3];
13730+ ulong cpuclk, div, reg;
13731+ ulong WriteClk, EraseClk, ReadClk;
13732+ ulong vbase;
13733+ ulong SCURevision;
13734+
13735+ ulong ulRefPLL;
13736+ ulong ulDeNumerator;
13737+ ulong ulNumerator;
13738+ ulong ulOD;
13739+
13740+ disable_cache();
13741+
13742+ info->start[0] = base;
13743+ vbase = flash_make_addr (info, 0, 0);
13744+
13745+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
13746+ CtrlOffset = SPICtrlRegOffset;
13747+ info->CE = 0;
13748+#else
13749+ if (vbase == PHYS_FLASH_1)
13750+ {
13751+ CtrlOffset = SPICtrlRegOffset2;
13752+ info->CE = 2;
13753+ }
13754+ else
13755+ {
13756+ CtrlOffset = SPICtrlRegOffset;
13757+ info->CE = 0;
13758+ }
13759+#endif
13760+
13761+ /* Get Flash ID */
13762+ ulCtrlData = *(ulong *) (STCBaseAddress + CtrlOffset) & CMD_MASK;
13763+ ulCtrlData |= CE_LOW | USERMODE;
13764+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13765+ udelay(200);
13766+ *(uchar *) (vbase) = (uchar) (0x9F);
13767+ udelay(10);
13768+ ch[0] = *(volatile uchar *)(vbase);
13769+ udelay(10);
13770+ ch[1] = *(volatile uchar *)(vbase);
13771+ udelay(10);
13772+ ch[2] = *(volatile uchar *)(vbase);
13773+ udelay(10);
13774+ ulCtrlData = *(ulong *) (STCBaseAddress + CtrlOffset) & CMD_MASK;
13775+ ulCtrlData |= CE_HIGH | USERMODE;
13776+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
13777+ udelay(200);
13778+ ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ;
13779+ info->flash_id = ulID;
13780+
13781+ //printf("SPI Flash ID: %x \n", ulID);
13782+
13783+ /* init default */
13784+ info->iomode = IOMODEx1;
13785+ info->address32 = 0;
13786+ info->quadport = 0;
13787+ info->specificspi = 0;
13788+
13789+ switch (info->flash_id)
13790+ {
13791+ case STM25P64:
13792+ info->sector_count = 128;
13793+ info->size = 0x800000;
13794+ erase_region_size = 0x10000;
13795+ info->readcmd = 0x0b;
13796+ info->dualport = 0;
13797+ info->dummybyte = 1;
13798+ info->buffersize = 256;
13799+ WriteClk = 40;
13800+ EraseClk = 20;
13801+ ReadClk = 40;
13802+ break;
13803+
13804+ case STM25P128:
13805+ info->sector_count = 64;
13806+ info->size = 0x1000000;
13807+ erase_region_size = 0x40000;
13808+ info->readcmd = 0x0b;
13809+ info->dualport = 0;
13810+ info->dummybyte = 1;
13811+ info->buffersize = 256;
13812+ WriteClk = 50;
13813+ EraseClk = 20;
13814+ ReadClk = 50;
13815+ break;
13816+
13817+ case N25Q256:
13818+ info->sector_count = 256;
13819+ info->size = 0x1000000;
13820+ erase_region_size = 0x10000;
13821+ info->readcmd = 0x0b;
13822+ info->dualport = 0;
13823+ info->dummybyte = 1;
13824+ info->buffersize = 256;
13825+ WriteClk = 50;
13826+ EraseClk = 20;
13827+ ReadClk = 50;
13828+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
13829+ info->sector_count = 512;
13830+ info->size = 0x2000000;
13831+ info->address32 = 1;
13832+#endif
13833+ break;
13834+
13835+ case N25Q512:
13836+ info->sector_count = 256;
13837+ info->size = 0x1000000;
13838+ erase_region_size = 0x10000;
13839+ info->readcmd = 0x0b;
13840+ info->dualport = 0;
13841+ info->dummybyte = 1;
13842+ info->buffersize = 256;
13843+ info->specificspi = SpecificSPI_N25Q512;
13844+ WriteClk = 50;
13845+ EraseClk = 20;
13846+ ReadClk = 50;
13847+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
13848+ info->sector_count = 1024;
13849+ info->size = 0x4000000;
13850+ info->address32 = 1;
13851+#endif
13852+ break;
13853+
13854+ case W25X16:
13855+ info->sector_count = 32;
13856+ info->size = 0x200000;
13857+ erase_region_size = 0x10000;
13858+ info->readcmd = 0x3b;
13859+ info->dualport = 1;
13860+ info->dummybyte = 1;
13861+ info->iomode = IOMODEx2;
13862+ info->buffersize = 256;
13863+ WriteClk = 50;
13864+ EraseClk = 25;
13865+ ReadClk = 50;
13866+ break;
13867+
13868+ case W25X64:
13869+ info->sector_count = 128;
13870+ info->size = 0x800000;
13871+ erase_region_size = 0x10000;
13872+ info->readcmd = 0x3b;
13873+ info->dualport = 1;
13874+ info->dummybyte = 1;
13875+ info->iomode = IOMODEx2;
13876+ info->buffersize = 256;
13877+ WriteClk = 50;
13878+ EraseClk = 25;
13879+ ReadClk = 50;
13880+ break;
13881+
13882+ case W25Q64BV:
13883+ info->sector_count = 128;
13884+ info->size = 0x800000;
13885+ erase_region_size = 0x10000;
13886+ info->readcmd = 0x3b;
13887+ info->dualport = 1;
13888+ info->dummybyte = 1;
13889+ info->iomode = IOMODEx2;
13890+ info->buffersize = 256;
13891+ WriteClk = 80;
13892+ EraseClk = 40;
13893+ ReadClk = 80;
13894+ break;
13895+
13896+ case W25Q128BV:
13897+ info->sector_count = 256;
13898+ info->size = 0x1000000;
13899+ erase_region_size = 0x10000;
13900+ info->readcmd = 0x3b;
13901+ info->dualport = 1;
13902+ info->dummybyte = 1;
13903+ info->iomode = IOMODEx2;
13904+ info->buffersize = 256;
13905+ WriteClk = 104;
13906+ EraseClk = 50;
13907+ ReadClk = 104;
13908+ break;
13909+
13910+ case W25Q256FV:
13911+ info->sector_count = 256;
13912+ info->size = 0x1000000;
13913+ erase_region_size = 0x10000;
13914+ info->readcmd = 0x0b;
13915+ info->dualport = 0;
13916+ info->dummybyte = 1;
13917+ info->buffersize = 256;
13918+ WriteClk = 50;
13919+ EraseClk = 20;
13920+ ReadClk = 50;
13921+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
13922+ info->sector_count = 512;
13923+ info->size = 0x2000000;
13924+ info->address32 = 1;
13925+#endif
13926+ break;
13927+
13928+ case S25FL064A:
13929+ info->sector_count = 128;
13930+ info->size = 0x800000;
13931+ erase_region_size = 0x10000;
13932+ info->readcmd = 0x0b;
13933+ info->dualport = 0;
13934+ info->dummybyte = 1;
13935+ info->buffersize = 256;
13936+ WriteClk = 50;
13937+ EraseClk = 25;
13938+ ReadClk = 50;
13939+ break;
13940+
13941+ case S25FL128P:
13942+ info->sector_count = 256;
13943+ info->size = 0x1000000;
13944+ erase_region_size = 0x10000;
13945+ info->readcmd = 0x0b;
13946+ info->dualport = 0;
13947+ info->dummybyte = 1;
13948+ info->buffersize = 256;
13949+ WriteClk = 100;
13950+ EraseClk = 40;
13951+ ReadClk = 100;
13952+ break;
13953+
13954+ case S25FL256S:
13955+ info->sector_count = 256;
13956+ info->size = 0x1000000;
13957+ erase_region_size = 0x10000;
13958+ info->readcmd = 0x0b;
13959+ info->dualport = 0;
13960+ info->dummybyte = 1;
13961+ info->buffersize = 256;
13962+ WriteClk = 50;
13963+ EraseClk = 20;
13964+ ReadClk = 50;
13965+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
13966+ info->sector_count = 512;
13967+ info->size = 0x2000000;
13968+ info->address32 = 1;
13969+#endif
13970+ break;
13971+
13972+ case MX25L25635E:
13973+ info->sector_count = 256;
13974+ info->size = 0x1000000;
13975+ erase_region_size = 0x10000;
13976+ info->readcmd = 0x0b;
13977+ info->dualport = 0;
13978+ info->dummybyte = 1;
13979+ info->buffersize = 256;
13980+ WriteClk = 50;
13981+ EraseClk = 20;
13982+ ReadClk = 50;
13983+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
13984+ info->sector_count = 512;
13985+ info->size = 0x2000000;
13986+ info->address32 = 1;
13987+#if defined(CONFIG_FLASH_SPIx2_Dummy)
13988+ info->readcmd = 0xbb;
13989+ info->dummybyte = 1;
13990+ info->dualport = 1;
13991+ info->iomode = IOMODEx2_dummy;
13992+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
13993+ info->readcmd = 0xeb;
13994+ info->dummybyte = 3;
13995+ info->dualport = 0;
13996+ info->iomode = IOMODEx4_dummy;
13997+ info->quadport = 1;
13998+ info->dummydata = 0xaa;
13999+#endif
14000+#endif
14001+ break;
14002+
14003+ case MX25L12805D:
14004+ info->sector_count = 256;
14005+ info->size = 0x1000000;
14006+ erase_region_size = 0x10000;
14007+ info->readcmd = 0x0b;
14008+ info->dualport = 0;
14009+ info->dummybyte = 1;
14010+ info->buffersize = 256;
14011+/*
14012+SCU7C: Silicon Revision ID Register
14013+D[31:24]: Chip ID
14014+0: AST2050/AST2100/AST2150/AST2200/AST3000
14015+1: AST2300
14016+
14017+D[23:16] Silicon revision ID for AST2300 generation and later
14018+0: A0
14019+1: A1
14020+2: A2
14021+.
14022+.
14023+.
14024+FPGA revision starts from 0x80
14025+
14026+AST2300 A0 SPI can't run faster than 50Mhz
14027+*/
14028+ WriteClk = 50;
14029+ EraseClk = 20;
14030+ ReadClk = 50;
14031+
14032+ SCURevision = *(ulong *) (SCU_REVISION_REGISTER);
14033+ if (((SCURevision >> 24) & 0xff) == 0x01) { //AST2300
14034+ if (((SCURevision >> 16) & 0xff) == 0x00) { //A0
14035+ WriteClk = 25;
14036+ EraseClk = 20;
14037+ ReadClk = 25;
14038+ }
14039+ }
14040+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
14041+#if defined(CONFIG_FLASH_SPIx2_Dummy)
14042+ info->readcmd = 0xbb;
14043+ info->dummybyte = 1;
14044+ info->dualport = 1;
14045+ info->iomode = IOMODEx2_dummy;
14046+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
14047+ info->readcmd = 0xeb;
14048+ info->dummybyte = 3;
14049+ info->dualport = 0;
14050+ info->iomode = IOMODEx4_dummy;
14051+ info->quadport = 1;
14052+ info->dummydata = 0xaa;
14053+#endif
14054+#endif
14055+ break;
14056+
14057+ case MX25L1605D:
14058+ info->sector_count = 32;
14059+ info->size = 0x200000;
14060+ erase_region_size = 0x10000;
14061+ info->readcmd = 0x0b;
14062+ info->dualport = 0;
14063+ info->dummybyte = 1;
14064+ info->buffersize = 256;
14065+ WriteClk = 50;
14066+ EraseClk = 20;
14067+ ReadClk = 50;
14068+ break;
14069+
14070+ case SST25VF016B:
14071+ info->sector_count = 32;
14072+ info->size = 0x200000;
14073+ erase_region_size = 0x10000;
14074+ info->readcmd = 0x0b;
14075+ info->dualport = 0;
14076+ info->dummybyte = 1;
14077+ info->buffersize = 1;
14078+ WriteClk = 50;
14079+ EraseClk = 25;
14080+ ReadClk = 50;
14081+ break;
14082+
14083+ case SST25VF064C:
14084+ info->sector_count = 128;
14085+ info->size = 0x800000;
14086+ erase_region_size = 0x10000;
14087+ info->readcmd = 0x0b;
14088+ info->dualport = 0;
14089+ info->dummybyte = 1;
14090+ info->buffersize = 1;
14091+ WriteClk = 50;
14092+ EraseClk = 25;
14093+ ReadClk = 50;
14094+ break;
14095+
14096+ case AT25DF161:
14097+ info->sector_count = 32;
14098+ info->size = 0x200000;
14099+ erase_region_size = 0x10000;
14100+ info->readcmd = 0x0b;
14101+ info->dualport = 0;
14102+ info->dummybyte = 1;
14103+ info->buffersize = 1;
14104+ WriteClk = 50;
14105+ EraseClk = 25;
14106+ ReadClk = 50;
14107+ break;
14108+
14109+ case AT25DF321:
14110+ info->sector_count = 32;
14111+ info->size = 0x400000;
14112+ erase_region_size = 0x10000;
14113+ info->readcmd = 0x0b;
14114+ info->dualport = 0;
14115+ info->dummybyte = 1;
14116+ info->buffersize = 1;
14117+ WriteClk = 50;
14118+ EraseClk = 25;
14119+ ReadClk = 50;
14120+ break;
14121+
14122+ default: /* use JEDEC ID */
14123+ erase_region_size = 0x10000;
14124+ info->readcmd = 0x0b;
14125+ info->dualport = 0;
14126+ info->dummybyte = 1;
14127+ info->buffersize = 1;
14128+ WriteClk = 50;
14129+ EraseClk = 25;
14130+ ReadClk = 50;
14131+ if ((info->flash_id & 0xFF) == 0x1F) /* Atmel */
14132+ {
14133+ switch (info->flash_id & 0x001F00)
14134+ {
14135+ case 0x000400:
14136+ info->sector_count = 8;
14137+ info->size = 0x80000;
14138+ break;
14139+ case 0x000500:
14140+ info->sector_count = 16;
14141+ info->size = 0x100000;
14142+ break;
14143+ case 0x000600:
14144+ info->sector_count = 32;
14145+ info->size = 0x200000;
14146+ break;
14147+ case 0x000700:
14148+ info->sector_count = 64;
14149+ info->size = 0x400000;
14150+ break;
14151+ case 0x000800:
14152+ info->sector_count = 128;
14153+ info->size = 0x800000;
14154+ break;
14155+ case 0x000900:
14156+ info->sector_count = 256;
14157+ info->size = 0x1000000;
14158+ break;
14159+ default:
14160+ printf("Can't support this SPI Flash!! \n");
14161+ return 0;
14162+ }
14163+ } /* Atmel JDEC */
14164+ else /* JDEC */
14165+ {
14166+ switch (info->flash_id & 0xFF0000)
14167+ {
14168+ case 0x120000:
14169+ info->sector_count = 4;
14170+ info->size = 0x40000;
14171+ break;
14172+ case 0x130000:
14173+ info->sector_count = 8;
14174+ info->size = 0x80000;
14175+ break;
14176+ case 0x140000:
14177+ info->sector_count =16;
14178+ info->size = 0x100000;
14179+ break;
14180+ case 0x150000:
14181+ info->sector_count =32;
14182+ info->size = 0x200000;
14183+ break;
14184+ case 0x160000:
14185+ info->sector_count =64;
14186+ info->size = 0x400000;
14187+ break;
14188+ case 0x170000:
14189+ info->sector_count =128;
14190+ info->size = 0x800000;
14191+ break;
14192+ case 0x180000:
14193+ info->sector_count =256;
14194+ info->size = 0x1000000;
14195+ break;
14196+ case 0x190000:
14197+ info->sector_count =256;
14198+ info->size = 0x1000000;
14199+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
14200+ info->sector_count = 512;
14201+ info->size = 0x2000000;
14202+ info->address32 = 1;
14203+#if defined(CONFIG_FLASH_SPIx2_Dummy)
14204+ info->readcmd = 0xbb;
14205+ info->dummybyte = 1;
14206+ info->dualport = 1;
14207+ info->iomode = IOMODEx2_dummy;
14208+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
14209+ info->readcmd = 0xeb;
14210+ info->dummybyte = 3;
14211+ info->dualport = 0;
14212+ info->iomode = IOMODEx4_dummy;
14213+ info->quadport = 1;
14214+ info->dummydata = 0xaa;
14215+#endif
14216+#endif
14217+ break;
14218+
14219+ case 0x200000:
14220+ info->sector_count =256;
14221+ info->size = 0x1000000;
14222+ if ((info->flash_id & 0xFF) == 0x20) /* numonyx */
14223+ info->specificspi = SpecificSPI_N25Q512;
14224+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
14225+ info->sector_count = 1024;
14226+ info->size = 0x4000000;
14227+ info->address32 = 1;
14228+#if defined(CONFIG_FLASH_SPIx2_Dummy)
14229+ info->readcmd = 0xbb;
14230+ info->dummybyte = 1;
14231+ info->dualport = 1;
14232+ info->iomode = IOMODEx2_dummy;
14233+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
14234+ info->readcmd = 0xeb;
14235+ info->dummybyte = 3;
14236+ info->dualport = 0;
14237+ info->iomode = IOMODEx4_dummy;
14238+ info->quadport = 1;
14239+ info->dummydata = 0xaa;
14240+#endif
14241+#endif
14242+ break;
14243+
14244+ default:
14245+ printf("Can't support this SPI Flash!! \n");
14246+ return 0;
14247+ }
14248+ } /* JDEC */
14249+ }
14250+
14251+ debug ("erase_region_count = %d erase_region_size = %d\n",
14252+ erase_region_count, erase_region_size);
14253+
14254+ sector = base;
14255+ for (j = 0; j < info->sector_count; j++) {
14256+
14257+ info->start[j] = sector;
14258+ sector += erase_region_size;
14259+ info->protect[j] = 0; /* default: not protected */
14260+ }
14261+
14262+ /* set SPI flash extended info */
14263+#if defined(CONFIG_AST1300)
14264+ if (info->size > 0x200000) /* limit MAX Flash to 2MB for AST1300 */
14265+ info->size = 0x200000;
14266+#endif
14267+#if defined(CONFIG_AST2400) || defined(CONFIG_AST2300) || defined(CONFIG_AST2300_FPGA_1) || defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST1300)
14268+ reg = *((volatile ulong*) 0x1e6e2024);
14269+ if (reg & 0x40000)
14270+ {
14271+ reg = *((volatile ulong*) 0x1e6e2070);
14272+
14273+ ulRefPLL = 24;
14274+ ulDeNumerator = reg & 0x0F;
14275+ ulNumerator = (reg & 0x07E0) >> 5;
14276+ ulOD = (reg & 0x10) ? 1:2;
14277+
14278+ cpuclk = ulRefPLL * ulOD * (ulNumerator + 2) / (ulDeNumerator + 1);
14279+ }
14280+ else
14281+ {
14282+ reg = *((volatile ulong*) 0x1e6e2070);
14283+#if defined(CONFIG_AST2400)
14284+ if (reg & 0x00800000) //ref. clk:25MHz
14285+ {
14286+ switch (reg & 0x300)
14287+ {
14288+ case 0x000:
14289+ cpuclk = 400;
14290+ break;
14291+ case 0x100:
14292+ cpuclk = 375;
14293+ break;
14294+ case 0x200:
14295+ cpuclk = 350;
14296+ break;
14297+ case 0x300:
14298+ cpuclk = 325;
14299+ break;
14300+ }
14301+ }
14302+ else
14303+ {
14304+ switch (reg & 0x300) //ref. clk:24MHz
14305+ {
14306+ case 0x000:
14307+ cpuclk = 384;
14308+ break;
14309+ case 0x100:
14310+ cpuclk = 360;
14311+ break;
14312+ case 0x200:
14313+ cpuclk = 336;
14314+ break;
14315+ case 0x300:
14316+ cpuclk = 312;
14317+ break;
14318+ }
14319+ }
14320+#else
14321+ switch (reg & 0x300)
14322+ {
14323+ case 0x000:
14324+ cpuclk = 384;
14325+ break;
14326+ case 0x100:
14327+ cpuclk = 360;
14328+ break;
14329+ case 0x200:
14330+ cpuclk = 336;
14331+ break;
14332+ case 0x300:
14333+ cpuclk = 408;
14334+ break;
14335+ }
14336+#endif
14337+ }
14338+
14339+ reg = *((volatile ulong*) 0x1e6e2070);
14340+ switch (reg & 0xc00)
14341+ {
14342+ case 0x000:
14343+ cpuclk /= 1;
14344+ break;
14345+ case 0x400:
14346+ cpuclk /= 2;
14347+ break;
14348+ case 0x800:
14349+ cpuclk /= 4;
14350+ break;
14351+ case 0xC00:
14352+ cpuclk /= 3;
14353+ break;
14354+ }
14355+#else /* AST2100 */
14356+ reg = *((volatile ulong*) 0x1e6e2070);
14357+ switch (reg & 0xe00)
14358+ {
14359+ case 0x000:
14360+ cpuclk = 266;
14361+ break;
14362+ case 0x200:
14363+ cpuclk = 233;
14364+ break;
14365+ case 0x400:
14366+ cpuclk = 200;
14367+ break;
14368+ case 0x600:
14369+ cpuclk = 166;
14370+ break;
14371+ case 0x800:
14372+ cpuclk = 133;
14373+ break;
14374+ case 0xA00:
14375+ cpuclk = 100;
14376+ break;
14377+ case 0xC00:
14378+ cpuclk = 300;
14379+ break;
14380+ case 0xE00:
14381+ cpuclk = 24;
14382+ break;
14383+ }
14384+ switch (reg & 0x3000)
14385+ {
14386+ case 0x1000:
14387+ cpuclk /= 2;
14388+ break;
14389+ case 0x2000:
14390+ cpuclk /= 4;
14391+ break;
14392+ case 0x3000:
14393+ cpuclk /= 3;
14394+ break;
14395+ }
14396+#endif
14397+
14398+#if defined(CONFIG_AST2400) || defined(CONFIG_AST2300) || defined(CONFIG_AST2300_FPGA_1) || defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST1300)
14399+
14400+#if defined(CONFIG_AST2300) || defined(CONFIG_AST1300)
14401+ /* limit Max SPI CLK to 50MHz (Datasheet v1.2) */
14402+ if (WriteClk > 50) WriteClk = 50;
14403+ if (EraseClk > 50) EraseClk = 50;
14404+ if (ReadClk > 50) ReadClk = 50;
14405+#endif
14406+
14407+ div = 1;
14408+ while ( ((cpuclk/div) > WriteClk) && (div < 16) )
14409+ {
14410+ div++;
14411+ }
14412+ info->tCK_Write = AST2300_SPICLK_DIV[div-1];
14413+
14414+ div = 1;
14415+ while ( ((cpuclk/div) > EraseClk) && (div < 16) )
14416+ {
14417+ div++;
14418+ }
14419+ info->tCK_Erase = AST2300_SPICLK_DIV[div-1];
14420+
14421+ div = 1;
14422+ while ( ((cpuclk/div) > ReadClk) && (div < 16) )
14423+ {
14424+ div++;
14425+ }
14426+ info->tCK_Read = AST2300_SPICLK_DIV[div-1];
14427+#else
14428+ div = 2;
14429+ info->tCK_Write = 7;
14430+ while ( (cpuclk/div) > WriteClk )
14431+ {
14432+ info->tCK_Write--;
14433+ div +=2;
14434+ }
14435+ div = 2;
14436+ info->tCK_Erase = 7;
14437+ while ( (cpuclk/div) > EraseClk )
14438+ {
14439+ info->tCK_Erase--;
14440+ div +=2;
14441+ }
14442+ div = 2;
14443+ info->tCK_Read = 7;
14444+ while ( (cpuclk/div) > ReadClk )
14445+ {
14446+ info->tCK_Read--;
14447+ div +=2;
14448+ }
14449+#endif
14450+
14451+ /* unprotect flash */
14452+ write_status_register(info, 0);
14453+
14454+ if (info->quadport)
14455+ write_status_register(info, 0x40); /* enable QE */
14456+
14457+ if (info->address32)
14458+ {
14459+ reg = *((volatile ulong*) 0x1e6e2070); /* set H/W Trappings */
14460+ reg |= 0x10;
14461+ *((volatile ulong*) 0x1e6e2070) = reg;
14462+
14463+ reg = *((volatile ulong*) 0x1e620004); /* enable 32b control bit*/
14464+ reg |= (0x01 << info->CE);
14465+ *((volatile ulong*) 0x1e620004) = reg;
14466+
14467+ /* set flash chips to 32bits addressing mode */
14468+ if ((info->flash_id & 0xFF) == 0x01) /* Spansion */
14469+ enable4b_spansion(info);
14470+ else if ((info->flash_id & 0xFF) == 0x20) /* Numonyx */
14471+ enable4b_numonyx(info);
14472+ else /* MXIC, Winbond */
14473+ enable4b(info);
14474+
14475+ }
14476+
14477+ reset_flash(info);
14478+
14479+ return (info->size);
14480+}
14481+
14482+
14483+/*-----------------------------------------------------------------------
14484+ */
14485+static int flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len)
14486+{
14487+ ulong j, base, offset;
14488+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
14489+ uchar jReg;
14490+
14491+ if (info->CE == 2)
14492+ {
14493+ CtrlOffset = SPICtrlRegOffset2;
14494+ }
14495+ else
14496+ {
14497+ CtrlOffset = SPICtrlRegOffset;
14498+ }
14499+
14500+ base = info->start[0];
14501+ offset = addr - base;
14502+ base = flash_make_addr (info, 0, 0);
14503+
14504+ enable_write (info);
14505+
14506+ ulCtrlData = (info->tCK_Write << 8);
14507+
14508+ ulCtrlData &= CMD_MASK;
14509+ ulCtrlData |= CE_LOW | USERMODE;
14510+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14511+ udelay(200);
14512+ *(uchar *) (base) = (uchar) (0x02);
14513+ udelay(10);
14514+ if (info->address32)
14515+ {
14516+ *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24);
14517+ udelay(10);
14518+ }
14519+ *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
14520+ udelay(10);
14521+ *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
14522+ udelay(10);
14523+ *(uchar *) (base) = (uchar) ((offset & 0x0000ff));
14524+ udelay(10);
14525+
14526+ for (j=0; j<len; j++)
14527+ {
14528+ *(uchar *) (base) = *(uchar *) (src++);
14529+ udelay(10);
14530+ }
14531+
14532+ ulCtrlData &= CMD_MASK;
14533+ ulCtrlData |= CE_HIGH | USERMODE;
14534+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14535+ udelay(200);
14536+
14537+ ulCtrlData &= CMD_MASK;
14538+ ulCtrlData |= CE_LOW | USERMODE;
14539+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14540+ udelay(200);
14541+ *(uchar *) (base) = (uchar) (0x05);
14542+ udelay(10);
14543+ do {
14544+ jReg = *(volatile uchar *) (base);
14545+ } while ((jReg & 0x01));
14546+ ulCtrlData &= CMD_MASK;
14547+ ulCtrlData |= CE_HIGH | USERMODE;
14548+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14549+ udelay(200);
14550+
14551+ /* RFSR */
14552+ if (info->specificspi == SpecificSPI_N25Q512)
14553+ {
14554+ ulCtrlData &= CMD_MASK;
14555+ ulCtrlData |= CE_LOW | USERMODE;
14556+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14557+ udelay(200);
14558+ *(uchar *) (base) = (uchar) (0x70);
14559+ udelay(10);
14560+ do {
14561+ jReg = *(volatile uchar *) (base);
14562+ } while (!(jReg & 0x80));
14563+ ulCtrlData &= CMD_MASK;
14564+ ulCtrlData |= CE_HIGH | USERMODE;
14565+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14566+ udelay(200);
14567+ }
14568+}
14569+
14570+/*-----------------------------------------------------------------------
14571+ *
14572+ * export functions
14573+ *
14574+ */
14575+
14576+/*-----------------------------------------------------------------------
14577+ *
14578+ */
14579+unsigned long flash_init (void)
14580+{
14581+ unsigned long size = 0;
14582+ int i;
14583+
14584+ /* Init: no FLASHes known */
14585+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
14586+ flash_info[i].flash_id = FLASH_UNKNOWN;
14587+ size += flash_info[i].size = flash_get_size (bank_base[i], i);
14588+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
14589+#ifndef CFG_FLASH_QUIET_TEST
14590+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
14591+ i, flash_info[i].size, flash_info[i].size << 20);
14592+#endif /* CFG_FLASH_QUIET_TEST */
14593+ }
14594+ }
14595+
14596+ /* Monitor protection ON by default */
14597+#if (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
14598+ flash_protect (FLAG_PROTECT_SET,
14599+ CONFIG_MONITOR_BASE,
14600+ CONFIG_MONITOR_BASE + monitor_flash_len - 1,
14601+ flash_get_info(CONFIG_MONITOR_BASE));
14602+#endif
14603+
14604+ /* Environment protection ON by default */
14605+#ifdef CONFIG_ENV_IS_IN_FLASH
14606+ flash_protect (FLAG_PROTECT_SET,
14607+ CONFIG_ENV_ADDR,
14608+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
14609+ flash_get_info(CONFIG_ENV_ADDR));
14610+#endif
14611+
14612+ /* Redundant environment protection ON by default */
14613+#ifdef CONFIG_ENV_ADDR_REDUND
14614+ flash_protect (FLAG_PROTECT_SET,
14615+ CONFIG_ENV_ADDR_REDUND,
14616+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
14617+ flash_get_info(CONFIG_ENV_ADDR_REDUND));
14618+#endif
14619+ return (size);
14620+}
14621+
14622+/*-----------------------------------------------------------------------
14623+ */
14624+#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
14625+static flash_info_t *flash_get_info(ulong base)
14626+{
14627+ int i;
14628+ flash_info_t * info = 0;
14629+
14630+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
14631+ info = & flash_info[i];
14632+ if (info->size && info->start[0] <= base &&
14633+ base <= info->start[0] + info->size - 1)
14634+ break;
14635+ }
14636+
14637+ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
14638+}
14639+#endif
14640+
14641+/*-----------------------------------------------------------------------
14642+ */
14643+int flash_erase (flash_info_t * info, int s_first, int s_last)
14644+{
14645+ int rcode = 0;
14646+ int prot;
14647+ flash_sect_t sect;
14648+
14649+ ulong base, offset;
14650+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
14651+ uchar jReg;
14652+
14653+ disable_cache();
14654+
14655+ if (info->CE == 2)
14656+ {
14657+ CtrlOffset = SPICtrlRegOffset2;
14658+ }
14659+ else
14660+ {
14661+ CtrlOffset = SPICtrlRegOffset;
14662+ }
14663+
14664+ if ((s_first < 0) || (s_first > s_last)) {
14665+ puts ("- no sectors to erase\n");
14666+ return 1;
14667+ }
14668+
14669+ prot = 0;
14670+ for (sect = s_first; sect <= s_last; ++sect) {
14671+ if (info->protect[sect]) {
14672+ prot++;
14673+ }
14674+ }
14675+ if (prot) {
14676+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
14677+ } else {
14678+ putc ('\n');
14679+ }
14680+
14681+ ulCtrlData = (info->tCK_Erase << 8);
14682+ for (sect = s_first; sect <= s_last; sect++) {
14683+ if (info->protect[sect] == 0) { /* not protected */
14684+ /* start erasing */
14685+ enable_write(info);
14686+
14687+ base = info->start[0];
14688+ offset = info->start[sect] - base;
14689+ base = flash_make_addr (info, 0, 0);
14690+
14691+ ulCtrlData &= CMD_MASK;
14692+ ulCtrlData |= CE_LOW | USERMODE;
14693+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14694+ udelay(200);
14695+ *(uchar *) (base) = (uchar) (0xd8);
14696+ udelay(10);
14697+ if (info->address32)
14698+ {
14699+ *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24);
14700+ udelay(10);
14701+ }
14702+ *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
14703+ udelay(10);
14704+ *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
14705+ udelay(10);
14706+ *(uchar *) (base) = (uchar) ((offset & 0x0000ff));
14707+ udelay(10);
14708+
14709+ ulCtrlData &= CMD_MASK;
14710+ ulCtrlData |= CE_HIGH | USERMODE;
14711+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14712+ udelay(200);
14713+
14714+ ulCtrlData &= CMD_MASK;
14715+ ulCtrlData |= CE_LOW | USERMODE;
14716+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14717+ udelay(200);
14718+ *(uchar *) (base) = (uchar) (0x05);
14719+ udelay(10);
14720+ do {
14721+ jReg = *(volatile uchar *) (base);
14722+ } while ((jReg & 0x01));
14723+ ulCtrlData &= CMD_MASK;
14724+ ulCtrlData |= CE_HIGH | USERMODE;
14725+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14726+ udelay(200);
14727+
14728+ /* RFSR */
14729+ if (info->specificspi == SpecificSPI_N25Q512)
14730+ {
14731+ ulCtrlData &= CMD_MASK;
14732+ ulCtrlData |= CE_LOW | USERMODE;
14733+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14734+ udelay(200);
14735+ *(uchar *) (base) = (uchar) (0x70);
14736+ udelay(10);
14737+ do {
14738+ jReg = *(volatile uchar *) (base);
14739+ } while (!(jReg & 0x80));
14740+ ulCtrlData &= CMD_MASK;
14741+ ulCtrlData |= CE_HIGH | USERMODE;
14742+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
14743+ udelay(200);
14744+ }
14745+
14746+ putc ('.');
14747+ }
14748+ }
14749+ puts (" done\n");
14750+
14751+ reset_flash(info);
14752+
14753+ return rcode;
14754+}
14755+
14756+/*-----------------------------------------------------------------------
14757+ */
14758+void flash_print_info (flash_info_t * info)
14759+{
14760+ putc ('\n');
14761+ return;
14762+}
14763+
14764+/*-----------------------------------------------------------------------
14765+ * Copy memory to flash, returns:
14766+ * 0 - OK
14767+ * 1 - write timeout
14768+ * 2 - Flash not erased
14769+ */
14770+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
14771+{
14772+ int count;
14773+ unsigned char pat[] = {'|', '-', '/', '\\'};
14774+ int patcnt;
14775+
14776+ disable_cache();
14777+
14778+ /* get lower aligned address */
14779+ if (addr & (info->buffersize - 1))
14780+ {
14781+ count = cnt >= info->buffersize ? (info->buffersize - (addr & 0xff)):cnt;
14782+ flash_write_buffer (info, src, addr, count);
14783+ addr+= count;
14784+ src += count;
14785+ cnt -= count;
14786+ }
14787+
14788+ /* prog */
14789+ while (cnt > 0) {
14790+ count = cnt >= info->buffersize ? info->buffersize:cnt;
14791+ flash_write_buffer (info, src, addr, count);
14792+ addr+= count;
14793+ src += count;
14794+ cnt -= count;
14795+ printf("%c\b", pat[(patcnt++) & 0x03]);
14796+ }
14797+
14798+ reset_flash(info);
14799+
14800+ return (0);
14801+}
14802+
14803+#ifdef CONFIG_FLASH_AST2300_DMA
14804+void * memmove_dma(void * dest,const void *src,size_t count)
14805+{
14806+ ulong count_align, poll_time, data;
14807+
14808+ count_align = (count + 3) & 0xFFFFFFFC; /* 4-bytes align */
14809+ poll_time = 100; /* set 100 us as default */
14810+
14811+ /* force end of burst read */
14812+ *(volatile ulong *) (STCBaseAddress + SPICtrlRegOffset) |= CE_HIGH;
14813+ *(volatile ulong *) (STCBaseAddress + SPICtrlRegOffset) &= ~CE_HIGH;
14814+
14815+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE);
14816+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_FLASH_BASE) = (ulong *) (src);
14817+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_DRAM_BASE) = (ulong *) (dest);
14818+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_LENGTH) = (ulong) (count_align);
14819+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE);
14820+
14821+ /* wait poll */
14822+ do {
14823+ udelay(poll_time);
14824+ data = *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS);
14825+ } while (!(data & FLASH_STATUS_DMA_READY));
14826+
14827+ /* clear status */
14828+ *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR;
14829+}
14830+#endif
14831+#endif /* CONFIG_FLASH_SPI */
14832diff --git a/board/aspeed/ast2300/hactest.c b/board/aspeed/ast2300/hactest.c
14833new file mode 100755
14834index 0000000..bfa87d5
14835--- /dev/null
14836+++ b/board/aspeed/ast2300/hactest.c
14837@@ -0,0 +1,762 @@
14838+/*
14839+ * This program is distributed in the hope that it will be useful,
14840+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
14841+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14842+ * GNU General Public License for more details.
14843+ *
14844+ * You should have received a copy of the GNU General Public License
14845+ * along with this program; if not, write to the Free Software
14846+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
14847+ * MA 02111-1307 USA
14848+ */
14849+
14850+/*
14851+ * Diagnostics support
14852+ */
14853+#include <common.h>
14854+#include <command.h>
14855+#include <post.h>
14856+#include "slt.h"
14857+
14858+#if ((CFG_CMD_SLT & CFG_CMD_HACTEST) && defined(CONFIG_SLT))
14859+#include "hactest.h"
14860+
14861+#include "aes.c"
14862+#include "rc4.c"
14863+
14864+static unsigned char crypto_src[CRYPTO_MAX_SRC], crypto_dst[CRYPTO_MAX_DST], crypto_context[CRYPTO_MAX_CONTEXT];
14865+static unsigned char hash_src[HASH_MAX_SRC], hash_dst[HASH_MAX_DST], hmac_key[HMAC_MAX_KEY];
14866+
14867+/*
14868+ * table
14869+ */
14870+static aes_test aestest[] = {
14871+ { CRYPTOMODE_ECB, 128,
14872+ {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c, '\0'},
14873+ {0x32, 0x43, 0xf6, 0xa8, 0x88, 0x5a, 0x30, 0x8d, 0x31, 0x31, 0x98, 0xa2, 0xe0, 0x37, 0x07, 0x34, '\0'},
14874+ {0x39, 0x25, 0x84, 0x1d, 0x02, 0xdc, 0x09, 0xfb, 0xdc, 0x11, 0x85, 0x97, 0x19, 0x6a, 0x0b, 0x32, '\0'} },
14875+ {0xFF, 0xFF, "", "", ""}, /* End Mark */
14876+};
14877+
14878+static rc4_test rc4test[] = {
14879+ {{0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, '\0'},
14880+ {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, '\0'}},
14881+ {{0xff}, {0xff}}, /* End Mark */
14882+};
14883+
14884+static hash_test hashtest[] = {
14885+ {HASHMODE_SHA1, 20,
14886+ "abc",
14887+ {0x53, 0x20, 0xb0, 0x8c, 0xa1, 0xf5, 0x74, 0x62, 0x50, 0x71, 0x89, 0x41, 0xc5, 0x0a, 0xdf, 0x4e, 0xbb, 0x55, 0x76, 0x06, '\0'}},
14888+ {0xFF, 0xFF, "", ""}, /* End Mark */
14889+};
14890+
14891+static hmac_test hmactest[] = {
14892+ {HASHMODE_SHA1, 64, 20,
14893+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16,0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, '\0' },
14894+ "Sample #1",
14895+ {0xbf, 0x39, 0xda, 0xb1, 0x7d, 0xc2, 0xe1, 0x23, 0x0d, 0x28, 0x35, 0x3b, 0x8c, 0xcb, 0x14, 0xb6, 0x22, 0x02, 0x65, 0xb3, '\0'}},
14896+ {0xFF, 0xFF, 0xFF, "", "", ""}, /* End Mark */
14897+};
14898+
14899+void EnableHMAC(void)
14900+{
14901+ unsigned long ulData;
14902+
14903+ /* init SCU */
14904+ *(unsigned long *) (0x1e6e2000) = 0x1688a8a8;
14905+
14906+ ulData = *(volatile unsigned long *) (0x1e6e200c);
14907+ ulData &= 0xfdfff;
14908+ *(unsigned long *) (0x1e6e200c) = ulData;
14909+ udelay(100);
14910+ ulData = *(volatile unsigned long *) (0x1e6e2004);
14911+ ulData &= 0xfffef;
14912+ *(unsigned long *) (0x1e6e2004) = ulData;
14913+
14914+}
14915+
14916+/* AES */
14917+void aes_enc_ast3000(aes_context *ctx, uint8 *input, uint8 *iv, uint8 *output, uint32 ulMsgLength , uint32 ulAESMode)
14918+{
14919+
14920+ unsigned long i, ulTemp, ulCommand;
14921+ unsigned char ch;
14922+ unsigned char *pjsrc, *pjdst, *pjcontext;
14923+
14924+ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
14925+ CRYPTO_AES | CRYPTO_ENCRYPTO | CRYPTO_SYNC_MODE_ASYNC;
14926+
14927+ switch (ctx->nr)
14928+ {
14929+ case 10:
14930+ ulCommand |= CRYPTO_AES128;
14931+ break;
14932+ case 12:
14933+ ulCommand |= CRYPTO_AES192;
14934+ break;
14935+ case 14:
14936+ ulCommand |= CRYPTO_AES256;
14937+ break;
14938+ }
14939+
14940+ switch (ulAESMode)
14941+ {
14942+ case CRYPTOMODE_ECB:
14943+ ulCommand |= CRYPTO_AES_ECB;
14944+ break;
14945+ case CRYPTOMODE_CBC:
14946+ ulCommand |= CRYPTO_AES_CBC;
14947+ break;
14948+ case CRYPTOMODE_CFB:
14949+ ulCommand |= CRYPTO_AES_CFB;
14950+ break;
14951+ case CRYPTOMODE_OFB:
14952+ ulCommand |= CRYPTO_AES_OFB;
14953+ break;
14954+ case CRYPTOMODE_CTR:
14955+ ulCommand |= CRYPTO_AES_CTR;
14956+ break;
14957+ }
14958+
14959+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
14960+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
14961+ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
14962+
14963+ /* Init HW */
14964+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
14965+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
14966+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
14967+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
14968+
14969+ /* Set source */
14970+ for (i=0; i< ulMsgLength; i++)
14971+ {
14972+ ch = *(uint8 *)(input + i);
14973+ *(uint8 *) (pjsrc + i) = ch;
14974+ }
14975+
14976+ /* Set Context */
14977+ /* Set IV */
14978+ for (i=0; i<16; i++)
14979+ {
14980+ ch = *(uint8 *) (iv + i);
14981+ *(uint8 *) (pjcontext + i) = ch;
14982+ }
14983+
14984+ /* Set Expansion Key */
14985+ for (i=0; i<(4*(ctx->nr+1)); i++)
14986+ {
14987+ ulTemp = ((ctx->erk[i] & 0xFF) << 24) + ((ctx->erk[i] & 0xFF00) << 8) + ((ctx->erk[i] & 0xFF0000) >> 8) + ((ctx->erk[i] & 0xFF000000) >> 24);
14988+ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
14989+ }
14990+
14991+ /* fire cmd */
14992+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
14993+ do {
14994+ ulTemp = *(volatile unsigned long *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
14995+ } while (ulTemp & CRYPTO_BUSY);
14996+
14997+ /* Output */
14998+ for (i=0; i<ulMsgLength; i++)
14999+ {
15000+ ch = *(uint8 *) (pjdst + i);
15001+ *(uint8 *) (output + i) = ch;
15002+ }
15003+
15004+} /* aes_enc_ast3000 */
15005+
15006+
15007+void aes_dec_ast3000(aes_context *ctx, uint8 *input, uint8 *iv, uint8 *output, uint32 ulMsgLength , uint32 ulAESMode)
15008+{
15009+ unsigned long i, ulTemp, ulCommand;
15010+ unsigned char ch;
15011+ unsigned char *pjsrc, *pjdst, *pjcontext;
15012+
15013+ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
15014+ CRYPTO_AES | CRYPTO_DECRYPTO | CRYPTO_SYNC_MODE_ASYNC;
15015+
15016+ switch (ctx->nr)
15017+ {
15018+ case 10:
15019+ ulCommand |= CRYPTO_AES128;
15020+ break;
15021+ case 12:
15022+ ulCommand |= CRYPTO_AES192;
15023+ break;
15024+ case 14:
15025+ ulCommand |= CRYPTO_AES256;
15026+ break;
15027+ }
15028+
15029+ switch (ulAESMode)
15030+ {
15031+ case CRYPTOMODE_ECB:
15032+ ulCommand |= CRYPTO_AES_ECB;
15033+ break;
15034+ case CRYPTOMODE_CBC:
15035+ ulCommand |= CRYPTO_AES_CBC;
15036+ break;
15037+ case CRYPTOMODE_CFB:
15038+ ulCommand |= CRYPTO_AES_CFB;
15039+ break;
15040+ case CRYPTOMODE_OFB:
15041+ ulCommand |= CRYPTO_AES_OFB;
15042+ break;
15043+ case CRYPTOMODE_CTR:
15044+ ulCommand |= CRYPTO_AES_CTR;
15045+ break;
15046+ }
15047+
15048+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
15049+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
15050+ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
15051+
15052+ /* Init HW */
15053+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
15054+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
15055+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
15056+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
15057+
15058+ /* Set source */
15059+ for (i=0; i< ulMsgLength; i++)
15060+ {
15061+ ch = *(uint8 *)(input + i);
15062+ *(uint8 *) (pjsrc + i) = ch;
15063+ }
15064+
15065+ /* Set Context */
15066+ /* Set IV */
15067+ for (i=0; i<16; i++)
15068+ {
15069+ ch = *(uint8 *) (iv + i);
15070+ *(uint8 *) (pjcontext + i) = ch;
15071+ }
15072+
15073+ /* Set Expansion Key */
15074+ for (i=0; i<(4*(ctx->nr+1)); i++)
15075+ {
15076+ ulTemp = ((ctx->erk[i] & 0xFF) << 24) + ((ctx->erk[i] & 0xFF00) << 8) + ((ctx->erk[i] & 0xFF0000) >> 8) + ((ctx->erk[i] & 0xFF000000) >> 24);
15077+ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
15078+ }
15079+
15080+ /* fire cmd */
15081+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
15082+ do {
15083+ ulTemp = *(volatile unsigned long *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
15084+ } while (ulTemp & CRYPTO_BUSY);
15085+
15086+ /* Output */
15087+ for (i=0; i<ulMsgLength; i++)
15088+ {
15089+ ch = *(uint8 *) (pjdst + i);
15090+ *(uint8 *) (output + i) = ch;
15091+ }
15092+
15093+} /* aes_dec_ast3000 */
15094+
15095+void rc4_crypt_ast3000(uint8 *data, int ulMsgLength, uint8 *rc4_key, uint32 ulKeyLength)
15096+{
15097+ struct rc4_state s;
15098+ unsigned long i, ulTemp, ulCommand;
15099+ unsigned char ch;
15100+ unsigned char *pjsrc, *pjdst, *pjcontext;
15101+
15102+ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
15103+ CRYPTO_RC4 | CRYPTO_SYNC_MODE_ASYNC;
15104+
15105+ rc4_setup( &s, rc4_key, ulKeyLength );
15106+
15107+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
15108+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
15109+ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
15110+
15111+ /* Init HW */
15112+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
15113+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
15114+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
15115+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
15116+
15117+
15118+ /* Set source */
15119+ for (i=0; i< ulMsgLength; i++)
15120+ {
15121+ ch = *(uint8 *)(data + i);
15122+ *(uint8 *) (pjsrc + i) = ch;
15123+ }
15124+
15125+ /* Set Context */
15126+ /* Set i, j */
15127+ *(uint32 *) (pjcontext + 8) = 0x0001;
15128+
15129+ /* Set Expansion Key */
15130+ for (i=0; i<(256/4); i++)
15131+ {
15132+ ulTemp = (s.m[i * 4] & 0xFF) + ((s.m[i * 4 + 1] & 0xFF) << 8) + ((s.m[i * 4 + 2] & 0xFF) << 16) + ((s.m[i * 4+ 3] & 0xFF) << 24);
15133+ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
15134+ }
15135+
15136+ /* fire cmd */
15137+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
15138+ do {
15139+ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
15140+ } while (ulTemp & CRYPTO_BUSY);
15141+
15142+ /* Output */
15143+ for (i=0; i<ulMsgLength; i++)
15144+ {
15145+ ch = *(volatile uint8 *) (pjdst + i);
15146+ *(uint8 *) (data + i) = ch;
15147+ }
15148+
15149+} /* rc4_crypt_ast3000 */
15150+
15151+/* Hash */
15152+void hash_ast3000(uint8 *msg, uint32 ulLength, unsigned char *output, uint32 ulHashMode)
15153+{
15154+ uint32 i, ulTemp, ulCommand, ulDigestLength, ulMyMsgLength;
15155+ uint8 ch;
15156+ unsigned char *pjsrc, *pjdst;
15157+
15158+ /* Get Info */
15159+ switch (ulHashMode)
15160+ {
15161+ case HASHMODE_MD5:
15162+ ulCommand = HASH_ALG_SELECT_MD5;
15163+ ulDigestLength = 16;
15164+ break;
15165+ case HASHMODE_SHA1:
15166+ ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
15167+ ulDigestLength = 20;
15168+ break;
15169+ case HASHMODE_SHA256:
15170+ ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
15171+ ulDigestLength = 32;
15172+ break;
15173+ case HASHMODE_SHA224:
15174+ ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
15175+ ulDigestLength = 28;
15176+ break;
15177+ }
15178+
15179+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
15180+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
15181+
15182+ /* 16byte alignment */
15183+ ulMyMsgLength = m16byteAlignment(ulLength);
15184+
15185+ /* Init. HW */
15186+ *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
15187+ *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
15188+ *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulMyMsgLength;
15189+
15190+ /* write src */
15191+ for (i=0; i<ulLength; i++)
15192+ {
15193+ ch = *(uint8 *)(msg+i);
15194+ *(uint8 *) (pjsrc + i) = ch;
15195+ }
15196+ for (i=ulLength; i<ulMyMsgLength; i++)
15197+ *(uint8 *) (pjsrc + i) = 0;
15198+
15199+ /* fire cmd */
15200+ *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand;
15201+
15202+ /* get digest */
15203+ do {
15204+ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);
15205+ } while (ulTemp & HASH_BUSY);
15206+
15207+ for (i=0; i<ulDigestLength; i++)
15208+ {
15209+ ch = *(volatile uint8 *) (pjdst + i);
15210+ *(uint8 *) (output + i) = ch;
15211+ }
15212+
15213+} /* hash_ast3000 */
15214+
15215+/* HMAC */
15216+void hmackey_ast3000(uint8 *key, uint32 ulKeyLength, uint32 ulHashMode)
15217+{
15218+ uint32 i, ulBlkLength, ulDigestLength, ulTemp, ulCommand;
15219+ uint8 k0[64], sum[32];
15220+ uint8 ch;
15221+ unsigned char *pjsrc, *pjdst, *pjkey;
15222+
15223+ /* Get Info */
15224+ switch (ulHashMode)
15225+ {
15226+ case HASHMODE_MD5:
15227+ ulCommand = HASH_ALG_SELECT_MD5;
15228+ ulDigestLength = 16;
15229+ break;
15230+ case HASHMODE_SHA1:
15231+ ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
15232+ ulDigestLength = 20;
15233+ break;
15234+ case HASHMODE_SHA256:
15235+ ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
15236+ ulDigestLength = 32;
15237+ break;
15238+ case HASHMODE_SHA224:
15239+ ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
15240+ ulDigestLength = 28;
15241+ break;
15242+ }
15243+ ulBlkLength = 64; /* MD5, SHA1/256/224: 64bytes */
15244+
15245+ /* Init */
15246+ memset( (void *) k0, 0, 64); /* reset to zero */
15247+ memset( (void *) sum, 0, 32); /* reset to zero */
15248+
15249+ /* Get k0 */
15250+ if (ulKeyLength <= ulBlkLength)
15251+ memcpy( (void *) k0, (void *) key, ulKeyLength );
15252+ else /* (ulKeyLength > ulBlkLength) */
15253+ {
15254+ hash_ast3000(key, ulKeyLength, sum, ulHashMode);
15255+ memcpy( (void *) k0, (void *) sum, ulDigestLength );
15256+ }
15257+
15258+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
15259+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
15260+ pjkey = (unsigned char *) m64byteAlignment((unsigned long) hmac_key);
15261+
15262+ /* Calculate digest */
15263+ *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
15264+ *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
15265+ *(uint32 *) (HAC_REG_BASE + REG_HASH_KEY_BASE_OFFSET) = (unsigned long) pjkey;
15266+ *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulBlkLength;
15267+
15268+ /* write key to src */
15269+ for (i=0; i<ulBlkLength; i++)
15270+ {
15271+ ch = *(uint8 *)(k0+i);
15272+ *(uint8 *) (pjsrc + i) = ch;
15273+ }
15274+
15275+ /* fire cmd for calculate */
15276+ *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand | HAC_DIGEST_CAL_ENABLE;
15277+ do {
15278+ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);
15279+ } while (ulTemp & HASH_BUSY);
15280+
15281+} /* hmackey_ast3000 */
15282+
15283+void hmac_ast3000(uint8 *key, uint32 ulKeyLength, uint8 *msg, uint32 ulMsgLength, uint32 ulHashMode, unsigned char *output)
15284+{
15285+ uint32 i, ulTemp, ulCommand, ulDigestLength, ulMyMsgLength;;
15286+ uint8 ch;
15287+ unsigned char *pjsrc, *pjdst, *pjkey;
15288+
15289+ /* Calculate digest */
15290+ switch (ulHashMode)
15291+ {
15292+ case HASHMODE_MD5:
15293+ ulCommand = HASH_ALG_SELECT_MD5;
15294+ ulDigestLength = 16;
15295+ break;
15296+ case HASHMODE_SHA1:
15297+ ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
15298+ ulDigestLength = 20;
15299+ break;
15300+ case HASHMODE_SHA256:
15301+ ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
15302+ ulDigestLength = 32;
15303+ break;
15304+ case HASHMODE_SHA224:
15305+ ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
15306+ ulDigestLength = 28;
15307+ break;
15308+ }
15309+
15310+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
15311+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
15312+ pjkey = (unsigned char *) m64byteAlignment((unsigned long) hmac_key);
15313+
15314+ /* 16byte alignment */
15315+ ulMyMsgLength = m16byteAlignment(ulMsgLength);
15316+
15317+ /* Init. HW */
15318+ *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
15319+ *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
15320+ *(uint32 *) (HAC_REG_BASE + REG_HASH_KEY_BASE_OFFSET) = (unsigned long) pjkey;
15321+ *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulMyMsgLength;
15322+
15323+ /* write Text to src */
15324+ for (i=0; i<ulMsgLength; i++)
15325+ {
15326+ ch = *(uint8 *)(msg+i);
15327+ *(uint8 *) (pjsrc + i) = ch;
15328+ }
15329+ for (i=ulMsgLength; i<ulMyMsgLength; i++)
15330+ *(uint8 *) (pjsrc + i) = 0;
15331+
15332+ /* fire cmd */
15333+ *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand | HAC_ENABLE;
15334+ do {
15335+ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);
15336+ } while (ulTemp & HASH_BUSY);
15337+
15338+ /* Output Digest */
15339+ for (i=0; i<ulDigestLength; i++)
15340+ {
15341+ ch = *(uint8 *) (pjdst + i);
15342+ *(uint8 *) (output + i) = ch;
15343+ }
15344+
15345+} /* hmac_ast3000 */
15346+
15347+/* main hactest procedure */
15348+int do_hactest (void)
15349+{
15350+ unsigned long i, j, Flags = 0;
15351+ aes_test *pjaes_test;
15352+ aes_context aes_ctx;
15353+ unsigned char AES_Mode[8], aes_output[64];
15354+ unsigned long ulAESMsgLength;
15355+
15356+ rc4_test *pjrc4_test;
15357+ unsigned char rc4_buf_sw[64], rc4_buf_hw[64];
15358+ unsigned long ulRC4KeyLength, ulRC4MsgLength;
15359+
15360+ hash_test *pjhash_test;
15361+ unsigned char HASH_Mode[8], hash_out[64];
15362+
15363+ hmac_test *pjhmac_test;
15364+ unsigned char HMAC_Mode[8], hmac_out[64];
15365+
15366+ EnableHMAC();
15367+
15368+ /* AES Test */
15369+ pjaes_test = aestest;
15370+ while (pjaes_test->aes_mode != 0xFF)
15371+ {
15372+
15373+ if (pjaes_test->aes_mode == CRYPTOMODE_CBC)
15374+ strcpy (AES_Mode, "CBC");
15375+ else if (pjaes_test->aes_mode == CRYPTOMODE_CFB)
15376+ strcpy (AES_Mode, "CFB");
15377+ else if (pjaes_test->aes_mode == CRYPTOMODE_OFB)
15378+ strcpy (AES_Mode, "OFB");
15379+ else if (pjaes_test->aes_mode == CRYPTOMODE_CTR)
15380+ strcpy (AES_Mode, "CTR");
15381+ else
15382+ strcpy (AES_Mode, "ECB");
15383+
15384+ /* Get Msg. Length */
15385+ ulAESMsgLength = strlen(pjaes_test->plaintext);
15386+ j = ( (ulAESMsgLength + 15) >> 4) << 4;
15387+ for (i=ulAESMsgLength; i<j; i++)
15388+ pjaes_test->plaintext[i] = 0;
15389+ ulAESMsgLength = j;
15390+
15391+ aes_set_key(&aes_ctx, pjaes_test->key, pjaes_test->key_length);
15392+
15393+ /* Encryption Test */
15394+ aes_enc_ast3000(&aes_ctx, pjaes_test->plaintext, pjaes_test->key, aes_output, ulAESMsgLength, pjaes_test->aes_mode);
15395+ if (strncmp(aes_output, pjaes_test->ciphertext, ulAESMsgLength))
15396+ {
15397+ Flags |= FLAG_AESTEST_FAIL;
15398+ printf("[INFO] AES%d %s Mode Encryption Failed \n", pjaes_test->key_length, AES_Mode);
15399+ printf("[DBG] Golden Data Dump .... \n");
15400+ for (i=0; i< ulAESMsgLength; i++)
15401+ {
15402+ printf("%02x ", pjaes_test->ciphertext[i]);
15403+ if (((i+1) % 8) == 0)
15404+ printf("\n");
15405+ }
15406+ printf("\n [DBG] Error Data Dump .... \n");
15407+ for (i=0; i< ulAESMsgLength; i++)
15408+ {
15409+ printf("%02x ", aes_output[i]);
15410+ if (((i+1) % 8) == 0)
15411+ printf("\n");
15412+ }
15413+ printf("\n");
15414+ }
15415+ else
15416+ {
15417+ /*
15418+ printf("[INFO] AES%d %s Mode Encryption Passed \n", pjaes_test->key_length, AES_Mode);
15419+ */
15420+ }
15421+
15422+ /* Decryption Test */
15423+ aes_dec_ast3000(&aes_ctx, pjaes_test->ciphertext, pjaes_test->key, aes_output, ulAESMsgLength, pjaes_test->aes_mode);
15424+ if (strncmp(aes_output, pjaes_test->plaintext, ulAESMsgLength))
15425+ {
15426+ Flags |= FLAG_AESTEST_FAIL;
15427+ printf("[INFO] AES%d %s Mode Decryption Failed \n", pjaes_test->key_length, AES_Mode);
15428+ printf("[DBG] Golden Data Dump .... \n");
15429+ for (i=0; i< ulAESMsgLength; i++)
15430+ {
15431+ printf("%02x ", pjaes_test->plaintext[i]);
15432+ if (((i+1) % 8) == 0)
15433+ printf("\n");
15434+ }
15435+ printf("\n [DBG] Error Data Dump .... \n");
15436+ for (i=0; i< ulAESMsgLength; i++)
15437+ {
15438+ printf("%02x ", aes_output[i]);
15439+ if (((i+1) % 8) == 0)
15440+ printf("\n");
15441+ }
15442+ printf("\n");
15443+ }
15444+ else
15445+ {
15446+ /*
15447+ printf("[INFO] AES%d %s Mode Decryption Passed \n", pjaes_test->key_length, AES_Mode);
15448+ */
15449+ }
15450+
15451+ pjaes_test++;
15452+ } /* AES */
15453+
15454+ /* RC4 Test */
15455+ pjrc4_test = rc4test;
15456+ while ((pjrc4_test->key[0] != 0xff) && (pjrc4_test->data[0] != 0xff))
15457+ {
15458+
15459+ /* Get Info */
15460+ ulRC4KeyLength = strlen(pjrc4_test->key);
15461+ ulRC4MsgLength = strlen(pjrc4_test->data);
15462+ memcpy( (void *) rc4_buf_sw, (void *) pjrc4_test->data, ulRC4MsgLength );
15463+ memcpy( (void *) rc4_buf_hw, (void *) pjrc4_test->data, ulRC4MsgLength );
15464+
15465+ /* Crypto */
15466+ rc4_crypt_sw(rc4_buf_sw, ulRC4MsgLength, pjrc4_test->key, ulRC4KeyLength);
15467+ rc4_crypt_ast3000(rc4_buf_hw, ulRC4MsgLength, pjrc4_test->key, ulRC4KeyLength);
15468+
15469+ if (strncmp(rc4_buf_hw, rc4_buf_sw, ulRC4MsgLength))
15470+ {
15471+ Flags |= FLAG_RC4TEST_FAIL;
15472+ printf("[INFO] RC4 Encryption Failed \n");
15473+ printf("[DBG] Golden Data Dump .... \n");
15474+ for (i=0; i< ulRC4MsgLength; i++)
15475+ {
15476+ printf("%02x ", rc4_buf_sw[i]);
15477+ if (((i+1) % 8) == 0)
15478+ printf("\n");
15479+ }
15480+ printf("\n [DBG] Error Data Dump .... \n");
15481+ for (i=0; i< ulRC4MsgLength; i++)
15482+ {
15483+ printf("%02x ", rc4_buf_hw[i]);
15484+ if (((i+1) % 8) == 0)
15485+ printf("\n");
15486+ }
15487+ printf("\n");
15488+ }
15489+ else
15490+ {
15491+ /*
15492+ printf("[INFO] RC4 Encryption Passed \n");
15493+ */
15494+ }
15495+
15496+ pjrc4_test++;
15497+
15498+ } /* RC4 */
15499+
15500+ /* Hash Test */
15501+ pjhash_test = hashtest;
15502+ while (pjhash_test->hash_mode != 0xFF)
15503+ {
15504+
15505+ if (pjhash_test->hash_mode == HASHMODE_MD5)
15506+ strcpy (HASH_Mode, "MD5");
15507+ else if (pjhash_test->hash_mode == HASHMODE_SHA1)
15508+ strcpy (HASH_Mode, "SHA1");
15509+ else if (pjhash_test->hash_mode == HASHMODE_SHA256)
15510+ strcpy (HASH_Mode, "SHA256");
15511+ else if (pjhash_test->hash_mode == HASHMODE_SHA224)
15512+ strcpy (HASH_Mode, "SHA224");
15513+
15514+ /* Hash */
15515+ hash_ast3000(pjhash_test->input, strlen(pjhash_test->input), hash_out, pjhash_test->hash_mode);
15516+ if (strncmp(hash_out, pjhash_test->digest, pjhash_test->digest_length))
15517+ {
15518+ Flags |= FLAG_HASHTEST_FAIL;
15519+ printf("[INFO] HASH %s Failed \n", HASH_Mode);
15520+ printf("[DBG] Golden Data Dump .... \n");
15521+ for (i=0; i< pjhash_test->digest_length; i++)
15522+ {
15523+ printf("%02x ",pjhash_test->digest[i]);
15524+ if (((i+1) % 8) == 0)
15525+ printf("\n");
15526+ }
15527+ printf("\n [DBG] Error Data Dump .... \n");
15528+ for (i=0; i< pjhash_test->digest_length; i++)
15529+ {
15530+ printf("%02x ",hash_out[i]);
15531+ if (((i+1) % 8) == 0)
15532+ printf("\n");
15533+ }
15534+ printf("\n");
15535+ }
15536+ else
15537+ {
15538+ /*
15539+ printf("[INFO] HASH %s Passed \n", HASH_Mode);
15540+ */
15541+ }
15542+
15543+ pjhash_test++;
15544+
15545+ } /* Hash Test */
15546+
15547+ /* HMAC Test */
15548+ pjhmac_test = hmactest;
15549+ while (pjhmac_test->hash_mode != 0xFF)
15550+ {
15551+
15552+ if (pjhmac_test->hash_mode == HASHMODE_MD5)
15553+ strcpy (HMAC_Mode, "MD5");
15554+ else if (pjhmac_test->hash_mode == HASHMODE_SHA1)
15555+ strcpy (HMAC_Mode, "SHA1");
15556+ else if (pjhmac_test->hash_mode == HASHMODE_SHA256)
15557+ strcpy (HMAC_Mode, "SHA256");
15558+ else if (pjhmac_test->hash_mode == HASHMODE_SHA224)
15559+ strcpy (HMAC_Mode, "SHA224");
15560+
15561+ /* HMAC */
15562+ hmackey_ast3000(pjhmac_test->key, pjhmac_test->key_length, pjhmac_test->hash_mode);
15563+ hmac_ast3000(pjhmac_test->key, pjhmac_test->key_length, pjhmac_test->input, strlen(pjhmac_test->input), pjhmac_test->hash_mode, hmac_out);
15564+ if (strncmp(hmac_out, pjhmac_test->digest, pjhmac_test->digest_length))
15565+ {
15566+ Flags |= FLAG_HASHTEST_FAIL;
15567+ printf("[INFO] HMAC %s Failed \n", HMAC_Mode);
15568+ printf("[DBG] Golden Data Dump .... \n");
15569+ for (i=0; i< pjhmac_test->digest_length; i++)
15570+ {
15571+ printf("%02x ",pjhmac_test->digest[i]);
15572+ if (((i+1) % 8) == 0)
15573+ printf("\n");
15574+ }
15575+ printf("\n [DBG] Error Data Dump .... \n");
15576+ for (i=0; i< pjhmac_test->digest_length; i++)
15577+ {
15578+ printf("%02x ",hmac_out[i]);
15579+ if (((i+1) % 8) == 0)
15580+ printf("\n");
15581+ }
15582+ printf("\n");
15583+ }
15584+ else
15585+ {
15586+ /*
15587+ printf("[INFO] HMAC %s Passed \n", HMAC_Mode);
15588+ */
15589+ }
15590+
15591+ pjhmac_test++;
15592+
15593+ } /* HMAC Test */
15594+
15595+ return Flags;
15596+
15597+}
15598+
15599+#endif /* CONFIG_SLT */
15600diff --git a/board/aspeed/ast2300/hactest.h b/board/aspeed/ast2300/hactest.h
15601new file mode 100755
15602index 0000000..fcf2186
15603--- /dev/null
15604+++ b/board/aspeed/ast2300/hactest.h
15605@@ -0,0 +1,194 @@
15606+/*
15607+ * This program is distributed in the hope that it will be useful,
15608+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
15609+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15610+ * GNU General Public License for more details.
15611+ *
15612+ * You should have received a copy of the GNU General Public License
15613+ * along with this program; if not, write to the Free Software
15614+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15615+ */
15616+/* Err Flags */
15617+#define FLAG_AESTEST_FAIL 0x00000001
15618+#define FLAG_RC4TEST_FAIL 0x00000002
15619+#define FLAG_HASHTEST_FAIL 0x00000004
15620+
15621+/* Specific */
15622+/*
15623+#define DRAM_BASE 0x40000000
15624+#define CRYPTO_SRC_BASE (DRAM_BASE + 0x100000)
15625+#define CRYPTO_DST_BASE (DRAM_BASE + 0x200000)
15626+#define CRYPTO_CONTEXT_BASE (DRAM_BASE + 0x300000)
15627+
15628+#define HASH_SRC_BASE (DRAM_BASE + 0x400000)
15629+#define HASH_DST_BASE (DRAM_BASE + 0x500000)
15630+#define HMAC_KEY_BASE (DRAM_BASE + 0x600000)
15631+*/
15632+#define m08byteAlignment(x) ((x + 0x00000007) & 0xFFFFFFF8)
15633+#define m16byteAlignment(x) ((x + 0x0000000F) & 0xFFFFFFF0)
15634+#define m64byteAlignment(x) ((x + 0x0000003F) & 0xFFFFFFC0)
15635+
15636+#define CRYPTO_ALIGNMENT 16
15637+#define CRYPTO_MAX_SRC (100+CRYPTO_ALIGNMENT)
15638+#define CRYPTO_MAX_DST (100+CRYPTO_ALIGNMENT)
15639+#define CRYPTO_MAX_CONTEXT (100+CRYPTO_ALIGNMENT)
15640+
15641+#define HASH_ALIGNMENT 16
15642+#define HMAC_KEY_ALIGNMENT 64
15643+#define HASH_MAX_SRC (100+HASH_ALIGNMENT)
15644+#define HASH_MAX_DST (32+HASH_ALIGNMENT)
15645+#define HMAC_MAX_KEY (64+HMAC_KEY_ALIGNMENT)
15646+
15647+/* General */
15648+#define HAC_REG_BASE 0x1e6e3000
15649+
15650+#define MAX_KEYLENGTH 100
15651+#define MAX_TEXTLENGTH 100
15652+#define MAX_AESTEXTLENGTH 256
15653+#define MAX_RC4TEXTLENGTH 256
15654+#define MAX_RC4KEYLENGTH 256
15655+
15656+#define CRYPTOMODE_ECB 0x00
15657+#define CRYPTOMODE_CBC 0x01
15658+#define CRYPTOMODE_CFB 0x02
15659+#define CRYPTOMODE_OFB 0x03
15660+#define CRYPTOMODE_CTR 0x04
15661+
15662+#define HASHMODE_MD5 0x00
15663+#define HASHMODE_SHA1 0x01
15664+#define HASHMODE_SHA256 0x02
15665+#define HASHMODE_SHA224 0x03
15666+
15667+#define MIXMODE_DISABLE 0x00
15668+#define MIXMODE_CRYPTO 0x02
15669+#define MIXMODE_HASH 0x03
15670+
15671+#define REG_CRYPTO_SRC_BASE_OFFSET 0x00
15672+#define REG_CRYPTO_DST_BASE_OFFSET 0x04
15673+#define REG_CRYPTO_CONTEXT_BASE_OFFSET 0x08
15674+#define REG_CRYPTO_LEN_OFFSET 0x0C
15675+#define REG_CRYPTO_CMD_BASE_OFFSET 0x10
15676+//#define REG_CRYPTO_ENABLE_OFFSET 0x14
15677+#define REG_CRYPTO_STATUS_OFFSET 0x1C
15678+
15679+#define REG_HASH_SRC_BASE_OFFSET 0x20
15680+#define REG_HASH_DST_BASE_OFFSET 0x24
15681+#define REG_HASH_KEY_BASE_OFFSET 0x28
15682+#define REG_HASH_LEN_OFFSET 0x2C
15683+#define REG_HASH_CMD_OFFSET 0x30
15684+//#define REG_HASH_ENABLE_OFFSET 0x14
15685+#define REG_HASH_STATUS_OFFSET 0x1C
15686+
15687+#define HASH_BUSY 0x01
15688+#define CRYPTO_BUSY 0x02
15689+
15690+//#define ENABLE_HASH 0x01
15691+//#define DISABLE_HASH 0x00
15692+//#define ENABLE_CRYPTO 0x02
15693+//#define DISABLE_CRYPTO 0x00
15694+
15695+#define CRYPTO_SYNC_MODE_MASK 0x03
15696+#define CRYPTO_SYNC_MODE_ASYNC 0x00
15697+#define CRYPTO_SYNC_MODE_PASSIVE 0x02
15698+#define CRYPTO_SYNC_MODE_ACTIVE 0x03
15699+
15700+#define CRYPTO_AES128 0x00
15701+#define CRYPTO_AES192 0x04
15702+#define CRYPTO_AES256 0x08
15703+
15704+#define CRYPTO_AES_ECB 0x00
15705+#define CRYPTO_AES_CBC 0x10
15706+#define CRYPTO_AES_CFB 0x20
15707+#define CRYPTO_AES_OFB 0x30
15708+#define CRYPTO_AES_CTR 0x40
15709+
15710+#define CRYPTO_ENCRYPTO 0x80
15711+#define CRYPTO_DECRYPTO 0x00
15712+
15713+#define CRYPTO_AES 0x000
15714+#define CRYPTO_RC4 0x100
15715+
15716+#define CRYPTO_ENABLE_RW 0x000
15717+#define CRYPTO_ENABLE_CONTEXT_LOAD 0x000
15718+#define CRYPTO_ENABLE_CONTEXT_SAVE 0x000
15719+
15720+#define HASH_SYNC_MODE_MASK 0x03
15721+#define HASH_SYNC_MODE_ASYNC 0x00
15722+#define HASH_SYNC_MODE_PASSIVE 0x02
15723+#define HASH_SYNC_MODE_ACTIVE 0x03
15724+
15725+#define HASH_READ_SWAP_ENABLE 0x04
15726+#define HMAC_SWAP_CONTROL_ENABLE 0x08
15727+
15728+#define HASH_ALG_SELECT_MASK 0x70
15729+#define HASH_ALG_SELECT_MD5 0x00
15730+#define HASH_ALG_SELECT_SHA1 0x20
15731+#define HASH_ALG_SELECT_SHA224 0x40
15732+#define HASH_ALG_SELECT_SHA256 0x50
15733+
15734+#define HAC_ENABLE 0x80
15735+#define HAC_DIGEST_CAL_ENABLE 0x180
15736+#define HASH_INT_ENABLE 0x200
15737+
15738+/* AES */
15739+#ifndef uint8
15740+#define uint8 unsigned char
15741+#endif
15742+
15743+#ifndef uint32
15744+#define uint32 unsigned long int
15745+#endif
15746+
15747+typedef struct
15748+{
15749+ uint32 erk[64]; /* encryption round keys */
15750+ uint32 drk[64]; /* decryption round keys */
15751+ int nr; /* number of rounds */
15752+}
15753+aes_context;
15754+
15755+typedef struct
15756+{
15757+ int aes_mode;
15758+ int key_length;
15759+
15760+ uint8 key[32]; /* as iv in CTR mode */
15761+ uint8 plaintext[64];
15762+ uint8 ciphertext[64];
15763+
15764+}
15765+aes_test;
15766+
15767+/* RC4 */
15768+typedef struct
15769+{
15770+ uint8 key[32];
15771+ uint8 data[64];
15772+}
15773+rc4_test;
15774+
15775+/* Hash */
15776+typedef struct
15777+{
15778+ int hash_mode;
15779+ int digest_length;
15780+
15781+ uint8 input[64];
15782+ uint8 digest[64];
15783+
15784+}
15785+hash_test;
15786+
15787+/* HMAC */
15788+typedef struct
15789+{
15790+ int hash_mode;
15791+ int key_length;
15792+ int digest_length;
15793+
15794+ uint8 key[100];
15795+ uint8 input[64];
15796+ uint8 digest[64];
15797+
15798+}
15799+hmac_test;
15800diff --git a/board/aspeed/ast2300/mactest.c b/board/aspeed/ast2300/mactest.c
15801new file mode 100755
15802index 0000000..5566b65
15803--- /dev/null
15804+++ b/board/aspeed/ast2300/mactest.c
15805@@ -0,0 +1,504 @@
15806+/*
15807+ * This program is distributed in the hope that it will be useful,
15808+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
15809+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15810+ * GNU General Public License for more details.
15811+ *
15812+ * You should have received a copy of the GNU General Public License
15813+ * along with this program; if not, write to the Free Software
15814+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15815+ */
15816+/*
15817+ * (C) Copyright 2007 ASPEED Software
15818+ * MAC Manufacture Test in ASPEED's SDK version 0.20.01
15819+ *
15820+ * Release History
15821+ * 1. First Release, river@20071130
15822+ * 2. Fix the endless loop when PHY is not ready, river@20071204
15823+ *
15824+ * Test items:
15825+ * 1. Support MARVELL PHY only in this version
15826+ * 2. MDC/MDIO
15827+ * 3. GMAC/Duplex TX/RX Full_Size, Packet_Length Test
15828+ * 4. 100M/Duplex TX/RX Full_Size, Packet_Length Test
15829+ *
15830+ *
15831+ *
15832+*/
15833+
15834+
15835+/*
15836+* Diagnostics support
15837+*/
15838+#include <common.h>
15839+#include <command.h>
15840+#include <post.h>
15841+#include <malloc.h>
15842+#include <net.h>
15843+#include "slt.h"
15844+
15845+#if ((CFG_CMD_SLT & CFG_CMD_MACTEST) && defined(CONFIG_SLT))
15846+#include "mactest.h"
15847+
15848+static int INL(u_long base, u_long addr)
15849+{
15850+ return le32_to_cpu(*(volatile u_long *)(addr + base));
15851+}
15852+
15853+static void OUTL(u_long base, int command, u_long addr)
15854+{
15855+ *(volatile u_long *)(addr + base) = cpu_to_le32(command);
15856+}
15857+
15858+
15859+static void SCU_MAC1_Enable (void)
15860+{
15861+ unsigned int SCU_Register;
15862+
15863+//MAC1 RESET/PHY_LINK in SCU
15864+ SCU_Register = INL(SCU_BASE, SCU_RESET_CONTROL_REG);
15865+ OUTL(SCU_BASE, SCU_Register & ~(0x800), SCU_RESET_CONTROL_REG);
15866+
15867+}
15868+
15869+/*------------------------------------------------------------
15870+ . Reads a register from the MII Management serial interface
15871+ .-------------------------------------------------------------*/
15872+static u16 phy_read_register (u8 PHY_Register, u8 PHY_Address)
15873+{
15874+ u32 Data, Status = 0, Loop_Count = 0, PHY_Ready = 1;
15875+ u16 Return_Data;
15876+
15877+ OUTL(MAC1_IO_BASE, (PHY_Register << 21) + (PHY_Address << 16) + MIIRD + MDC_CYCTHR, PHYCR_REG);
15878+ do {
15879+ Status = (INL (MAC1_IO_BASE, PHYCR_REG) & MIIRD);
15880+ Loop_Count++;
15881+ if (Loop_Count >= PHY_LOOP) {
15882+ PHY_Ready = 0;
15883+ break;
15884+ }
15885+ } while (Status == MIIRD);
15886+
15887+ if (PHY_Ready == 0) {
15888+ printf ("PHY NOT REDAY\n");
15889+ return 0;
15890+ }
15891+
15892+ udelay(5*1000);
15893+ Data = INL (MAC1_IO_BASE, PHYDATA_REG);
15894+ Return_Data = (Data >> 16);
15895+
15896+ return Return_Data;
15897+}
15898+
15899+static void phy_write_register (u8 PHY_Register, u8 PHY_Address, u16 PHY_Data)
15900+{
15901+ u32 Status = 0, Loop_Count = 0, PHY_Ready = 1;
15902+
15903+ OUTL(MAC1_IO_BASE, PHY_Data, PHYDATA_REG);
15904+ OUTL(MAC1_IO_BASE, (PHY_Register << 21) + (PHY_Address << 16) + MIIWR + MDC_CYCTHR, PHYCR_REG);
15905+ do {
15906+ Status = (INL (MAC1_IO_BASE, PHYCR_REG) & MIIWR);
15907+ Loop_Count++;
15908+ if (Loop_Count >= PHY_LOOP) {
15909+ PHY_Ready = 0;
15910+ break;
15911+ }
15912+ } while (Status == MIIWR);
15913+ if (PHY_Ready == 0) {
15914+ printf ("PHY NOT REDAY\n");
15915+ }
15916+}
15917+
15918+static int wait_link_resolve (void)
15919+{
15920+ int resolved_status, Loop_Count = 0, PHY_Ready = 1;
15921+
15922+ do {
15923+ resolved_status = (phy_read_register (0x11, 0) & (PHY_RESOLVED_bit | PHY_LINK_bit));
15924+ Loop_Count++;
15925+ if (Loop_Count >= PHY_LOOP) {
15926+ PHY_Ready = 0;
15927+ printf ("PHY NOT READY\n");
15928+ break;
15929+ }
15930+ } while (resolved_status != (PHY_RESOLVED_bit | PHY_LINK_bit));
15931+
15932+ return PHY_Ready;
15933+}
15934+
15935+static void set_phy_speed (int chip, int speed, int duplex)
15936+{
15937+ unsigned short data, status;
15938+
15939+
15940+ if (chip == PHYID_VENDOR_MARVELL) {
15941+ if ((speed == PHY_SPEED_1G) && (duplex == DUPLEX_FULL)) {
15942+//Manual Control
15943+ phy_write_register (18, 0, 0);
15944+ data = phy_read_register (9, 0);
15945+ phy_write_register (9, 0, data | 0x1800);
15946+//PHY Reset
15947+ phy_write_register (0, 0, 0x0140 | 0x8000);
15948+ do {
15949+ status = (phy_read_register (0, 0) & 0x8000);
15950+ } while (status != 0);
15951+
15952+//Force 1G
15953+ phy_write_register (29, 0, 0x07);
15954+ data = phy_read_register (30, 0);
15955+ phy_write_register (30, 0, data | 0x08);
15956+ phy_write_register (29, 0, 0x10);
15957+ data = phy_read_register (30, 0);
15958+ phy_write_register (30, 0, data | 0x02);
15959+ phy_write_register (29, 0, 0x12);
15960+ data = phy_read_register (30, 0);
15961+ phy_write_register (30, 0, data | 0x01);
15962+
15963+ printf ("FORCE MARVELL PHY to 1G/DUPLEX DONE\n");
15964+ }
15965+ else if ((speed == PHY_SPEED_100M) && (duplex == DUPLEX_FULL)) {
15966+//PHY Reset
15967+ phy_write_register (0, 0, 0x2100 | 0x8000);
15968+ do {
15969+ status = (phy_read_register (0, 0) & 0x8000);
15970+ } while (status != 0);
15971+
15972+//Force 100M
15973+ data = phy_read_register (0, 0);
15974+ phy_write_register (0, 0, data | 0x4000 | 0x8000);
15975+ do {
15976+ status = (phy_read_register (0, 0) & 0x8000);
15977+ } while (status != 0);
15978+ data = phy_read_register (0, 0);
15979+
15980+ printf ("FORCE MARVELL PHY to 100M/DUPLEX DONE\n");
15981+ }
15982+ }
15983+ else if ( (chip == PHYID_VENDOR_RTL8201E) || (chip == PHYID_VENDOR_BROADCOM) ){
15984+ /* basic setting */
15985+ data = phy_read_register (0, 0);
15986+ data &= 0x7140;
15987+ data |= 0x4000;
15988+ if (speed == PHY_SPEED_100M)
15989+ data |= 0x2000;
15990+ if (duplex == DUPLEX_FULL)
15991+ data |= 0x0100;
15992+ phy_write_register (0, 0, data);
15993+
15994+ /* reset */
15995+ phy_write_register (0, 0, data | 0x8000);
15996+ do {
15997+ status = (phy_read_register (0, 0) & 0x8000);
15998+ } while (status != 0);
15999+ udelay(100*1000);
16000+
16001+ /* basic setting */
16002+ phy_write_register (0, 0, data);
16003+
16004+ if (chip == PHYID_VENDOR_RTL8201E)
16005+ printf ("FORCE RTL8201E PHY to 100M/DUPLEX DONE\n");
16006+ else if (chip == PHYID_VENDOR_BROADCOM)
16007+ printf ("FORCE Broadcom PHY to 100M/DUPLEX DONE\n");
16008+
16009+ }
16010+
16011+}
16012+
16013+static void MAC1_reset (void)
16014+{
16015+ OUTL(MAC1_IO_BASE, SW_RST_bit, MACCR_REG);
16016+ for (; (INL(MAC1_IO_BASE, MACCR_REG ) & SW_RST_bit) != 0; ) {udelay(1000);}
16017+ OUTL(MAC1_IO_BASE, 0, IER_REG );
16018+}
16019+
16020+static int set_mac1_control_register (int Chip_ID)
16021+{
16022+ unsigned long MAC_CR_Register = 0;
16023+ int PHY_Ready = 1;
16024+ u16 PHY_Status, PHY_Speed, PHY_Duplex, Advertise, Link_Partner;
16025+
16026+ MAC_CR_Register = SPEED_100M_MODE_bit | RX_ALLADR_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit;
16027+
16028+ if ( (Chip_ID == PHYID_VENDOR_BROADCOM) || (Chip_ID == PHYID_VENDOR_RTL8201E)) {
16029+ Advertise = phy_read_register (0x04, 0);
16030+ Link_Partner = phy_read_register (0x05, 0);
16031+ Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK);
16032+ Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK);
16033+ if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) {
16034+ MAC_CR_Register |= SPEED_100M_MODE_bit;
16035+ MAC_CR_Register |= FULLDUP_bit;
16036+ }
16037+ else if ((Advertise & Link_Partner) & PHY_100M_HALF) {
16038+ MAC_CR_Register |= SPEED_100M_MODE_bit;
16039+ MAC_CR_Register &= ~FULLDUP_bit;
16040+ }
16041+ else if ((Advertise & Link_Partner) & PHY_10M_DUPLEX) {
16042+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
16043+ MAC_CR_Register |= FULLDUP_bit;
16044+ }
16045+ else if ((Advertise & Link_Partner) & PHY_10M_HALF) {
16046+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
16047+ MAC_CR_Register &= ~FULLDUP_bit;
16048+ }
16049+ }
16050+ else if (Chip_ID == PHYID_VENDOR_MARVELL) {
16051+
16052+ PHY_Ready = wait_link_resolve ();
16053+
16054+ if (PHY_Ready == 1) {
16055+ PHY_Status = phy_read_register (0x11, 0);
16056+ PHY_Speed = (PHY_Status & PHY_SPEED_MASK) >> 14;
16057+ PHY_Duplex = (PHY_Status & PHY_DUPLEX_MASK) >> 13;
16058+
16059+ if (PHY_Speed == SPEED_1000M) {
16060+ MAC_CR_Register |= GMAC_MODE_bit;
16061+ }
16062+ else {
16063+ MAC_CR_Register &= ~GMAC_MODE_bit;
16064+ if (PHY_Speed == SPEED_10M) {
16065+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
16066+ }
16067+ }
16068+ if (PHY_Duplex == DUPLEX_HALF) {
16069+ MAC_CR_Register &= ~FULLDUP_bit;
16070+ }
16071+ }
16072+ }
16073+ OUTL(MAC1_IO_BASE, MAC_CR_Register, MACCR_REG);
16074+
16075+ return PHY_Ready;
16076+}
16077+
16078+static void ring_buffer_alloc (void)
16079+{
16080+ unsigned int i, j;
16081+
16082+//Write data into TX buffer
16083+ for (i = 0; i < NUM_TX; i++) {
16084+ for (j = 0; j < TX_BUFF_SZ; j++) {
16085+ tx_buffer[i][j] = i * 4 + j;
16086+ }
16087+ }
16088+//Initialize RX buffer to 0
16089+ for (i = 0; i < NUM_RX; i++) {
16090+ for (j = 0; j < RX_BUFF_SZ; j++) {
16091+ rx_buffer[i][j] = 0;
16092+ }
16093+ }
16094+//Prepare descriptor
16095+ for (i = 0; i < NUM_RX; i++) {
16096+ rx_ring[i].status = cpu_to_le32(RXPKT_RDY + RX_BUFF_SZ);
16097+ rx_ring[i].buf = ((u32) &rx_buffer[i]);
16098+ rx_ring[i].reserved = 0;
16099+ }
16100+ for (i = 0; i < NUM_TX; i++) {
16101+ tx_ring[i].status = 0;
16102+ tx_ring[i].des1 = 0;
16103+ tx_ring[i].buf = ((u32) &tx_buffer[i]);
16104+ tx_ring[i].reserved = 0;
16105+ }
16106+
16107+ rx_ring[NUM_RX - 1].status |= cpu_to_le32(EDORR);
16108+ tx_ring[NUM_TX - 1].status |= cpu_to_le32(EDOTR);
16109+
16110+ OUTL(MAC1_IO_BASE, ((u32) &tx_ring), TXR_BADR_REG);
16111+ OUTL(MAC1_IO_BASE, ((u32) &rx_ring), RXR_BADR_REG);
16112+
16113+ tx_new = 0;
16114+ rx_new = 0;
16115+}
16116+
16117+static int packet_test (void)
16118+{
16119+ unsigned int rx_status, length, i, Loop_Count = 0;
16120+
16121+ tx_ring[tx_new].status |= cpu_to_le32(LTS | FTS | TX_BUFF_SZ);
16122+ tx_ring[tx_new].status |= cpu_to_le32(TXDMA_OWN);
16123+ OUTL(MAC1_IO_BASE, POLL_DEMAND, TXPD_REG);
16124+
16125+//Compare result
16126+ do {
16127+ rx_status = rx_ring[rx_new].status;
16128+ Loop_Count++;
16129+ } while (!(rx_status & RXPKT_STATUS) && (Loop_Count < PHY_LOOP));
16130+ if (rx_status & (RX_ERR | CRC_ERR | FTL | RUNT | RX_ODD_NB)) {
16131+ /* There was an error.*/
16132+ printf("RX error status = 0x%08X\n", rx_status);
16133+ return PACKET_TEST_FAIL;
16134+ } else {
16135+ length = (rx_status & BYTE_COUNT_MASK);
16136+ for (i = 0; i < RX_BUFF_SZ / 4; i++) {
16137+ if (rx_buffer[rx_new][i] != tx_buffer[tx_new][i]) {
16138+ printf ("ERROR at packet %d, address %x\n", rx_new, i);
16139+ printf ("Gold = %8x, Real = %8x\n", tx_buffer[tx_new][i], rx_buffer[rx_new][i]);
16140+ return PACKET_TEST_FAIL;
16141+ }
16142+ }
16143+ }
16144+ tx_new = (tx_new + 1) % NUM_TX;
16145+ rx_new = (rx_new + 1) % NUM_RX;
16146+
16147+ return TEST_PASS;
16148+}
16149+
16150+static int packet_length_test (int packet_length)
16151+{
16152+ unsigned int rx_status, length, i, Loop_Count = 0;
16153+
16154+ tx_ring[tx_new].status &= (~(BYTE_COUNT_MASK));
16155+ tx_ring[tx_new].status |= cpu_to_le32(LTS | FTS | packet_length);
16156+ tx_ring[tx_new].status |= cpu_to_le32(TXDMA_OWN);
16157+ OUTL(MAC1_IO_BASE, POLL_DEMAND, TXPD_REG);
16158+
16159+//Compare result
16160+ do {
16161+ rx_status = rx_ring[rx_new].status;
16162+ Loop_Count++;
16163+ } while (!(rx_status & RXPKT_STATUS) && (Loop_Count < PHY_LOOP));
16164+ if (rx_status & (RX_ERR | CRC_ERR | FTL | RUNT | RX_ODD_NB)) {
16165+ /* There was an error.*/
16166+ printf("RX error status = 0x%08X\n", rx_status);
16167+ return PACKET_LENGTH_TEST_FAIL;
16168+ } else {
16169+ length = (rx_status & BYTE_COUNT_MASK) - 4;
16170+ if (length != packet_length) {
16171+ printf ("Received Length ERROR. Gold = %d, Fail = %d\n",packet_length, length);
16172+ printf ("rx_new = %d, tx_new = %d\n", rx_new, tx_new);
16173+ return PACKET_LENGTH_TEST_FAIL;
16174+ }
16175+ for (i = 0; i < length; i++) {
16176+ if (rx_buffer[rx_new][i] != tx_buffer[tx_new][i]) {
16177+ printf ("ERROR at packet %d, address %x\n", rx_new, i);
16178+ printf ("Gold = %8x, Real = %8x\n", tx_buffer[tx_new][i], rx_buffer[rx_new][i]);
16179+ return PACKET_LENGTH_TEST_FAIL;
16180+ }
16181+ }
16182+ }
16183+ rx_ring[rx_new].status &= (~(RXPKT_STATUS));
16184+ tx_new = (tx_new + 1) % NUM_TX;
16185+ rx_new = (rx_new + 1) % NUM_RX;
16186+
16187+ return TEST_PASS;
16188+}
16189+
16190+static int MAC1_init (int id)
16191+{
16192+ int phy_status = 0;
16193+
16194+ MAC1_reset ();
16195+ phy_status = set_mac1_control_register (id);
16196+ ring_buffer_alloc ();
16197+
16198+ return phy_status;
16199+}
16200+
16201+int do_mactest (void)
16202+{
16203+ unsigned int phy_id, i;
16204+ int test_result = 0, phy_status = 0;
16205+
16206+ SCU_MAC1_Enable();
16207+ phy_id = ((phy_read_register (0x02, 0) << 16) + phy_read_register (0x03, 0)) & PHYID_VENDOR_MASK;
16208+ if (phy_id == PHYID_VENDOR_MARVELL) {
16209+ printf ("PHY DETECTED ------> MARVELL\n");
16210+
16211+ set_phy_speed (phy_id, PHY_SPEED_1G, DUPLEX_FULL);
16212+ if ((phy_status = MAC1_init (phy_id)) != 0) {
16213+ for (i = 0; i < NUM_TX; i++) {
16214+ test_result |= packet_test ();
16215+ if (test_result != 0)
16216+ break;
16217+ }
16218+ }
16219+ else if (phy_status == 0) {
16220+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
16221+ test_result = 3;
16222+ return test_result;
16223+ }
16224+ if ((phy_status = MAC1_init (phy_id)) != 0) {
16225+ for (i = 60; i < TX_BUFF_SZ; i++) {
16226+ test_result |= packet_length_test (i);
16227+ if (test_result != 0)
16228+ break;
16229+ }
16230+ }
16231+ else if (phy_status == 0) {
16232+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
16233+ test_result = 3;
16234+ return test_result;
16235+ }
16236+ set_phy_speed (phy_id, PHY_SPEED_100M, DUPLEX_FULL);
16237+ if ((phy_status = MAC1_init (phy_id)) != 0) {
16238+ for (i = 0; i < NUM_TX; i++) {
16239+ test_result |= packet_test ();
16240+ if (test_result != 0)
16241+ break;
16242+ }
16243+ }
16244+ else if (phy_status == 0) {
16245+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
16246+ test_result = 3;
16247+ return test_result;
16248+ }
16249+
16250+ if ((phy_status = MAC1_init (phy_id)) != 0) {
16251+ for (i = 60; i < TX_BUFF_SZ; i++) {
16252+ test_result |= packet_length_test (i);
16253+ if (test_result != 0)
16254+ break;
16255+ }
16256+ }
16257+ else if (phy_status == 0) {
16258+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
16259+ test_result = 3;
16260+ return test_result;
16261+ }
16262+ }
16263+ else if ( (phy_id == PHYID_VENDOR_RTL8201E) || (phy_id == PHYID_VENDOR_BROADCOM) ){
16264+
16265+ if (phy_id == PHYID_VENDOR_RTL8201E)
16266+ printf ("PHY DETECTED ------> RTL 8201E \n");
16267+ else if (phy_id == PHYID_VENDOR_BROADCOM)
16268+ printf ("PHY DETECTED ------> Broadcom \n");
16269+
16270+ set_phy_speed (phy_id, PHY_SPEED_100M, DUPLEX_FULL);
16271+ if ((phy_status = MAC1_init (phy_id)) != 0) {
16272+ for (i = 0; i < NUM_TX; i++) {
16273+ test_result |= packet_test ();
16274+ if (test_result != 0)
16275+ break;
16276+ }
16277+ }
16278+ else if (phy_status == 0) {
16279+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
16280+ test_result = 3;
16281+ return test_result;
16282+ }
16283+
16284+ if ((phy_status = MAC1_init (phy_id)) != 0) {
16285+ for (i = 60; i < TX_BUFF_SZ; i++) {
16286+ test_result |= packet_length_test (i);
16287+ if (test_result != 0)
16288+ break;
16289+ }
16290+ }
16291+ else if (phy_status == 0) {
16292+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
16293+ test_result = 3;
16294+ return test_result;
16295+ }
16296+ }
16297+
16298+ if ((phy_status == 0) && (test_result & PACKET_TEST_FAIL)) {
16299+ printf ("Packet Test FAIL !\n");
16300+ }
16301+ else if ((phy_status == 0) && (test_result & PACKET_LENGTH_TEST_FAIL)) {
16302+ printf ("Packet Length Test FAIL !\n");
16303+ }
16304+
16305+ return test_result;
16306+
16307+}
16308+
16309+#endif /* CONFIG_SLT */
16310diff --git a/board/aspeed/ast2300/mactest.h b/board/aspeed/ast2300/mactest.h
16311new file mode 100755
16312index 0000000..e75b7bb
16313--- /dev/null
16314+++ b/board/aspeed/ast2300/mactest.h
16315@@ -0,0 +1,215 @@
16316+/*
16317+ * This program is distributed in the hope that it will be useful,
16318+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
16319+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16320+ * GNU General Public License for more details.
16321+ *
16322+ * You should have received a copy of the GNU General Public License
16323+ * along with this program; if not, write to the Free Software
16324+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16325+ */
16326+/* MACTest.h */
16327+
16328+// --------------------------------------------------------------------
16329+// General Definition
16330+// --------------------------------------------------------------------
16331+#define MAC1_IO_BASE 0x1E660000
16332+#define PHY_LOOP 100000
16333+#define NUM_RX 48
16334+#define NUM_TX 48
16335+#define RX_BUFF_SZ 1514
16336+#define TX_BUFF_SZ 1514
16337+#define TOUT_LOOP 1000000
16338+#define ETH_ALEN 6
16339+#define POLL_DEMAND 1
16340+
16341+
16342+// --------------------------------------------------------------------
16343+// MAC Register Index
16344+// --------------------------------------------------------------------
16345+#define ISR_REG 0x00 // interrups status register
16346+#define IER_REG 0x04 // interrupt maks register
16347+#define MAC_MADR_REG 0x08 // MAC address (Most significant)
16348+#define MAC_LADR_REG 0x0c // MAC address (Least significant)
16349+#define MAHT0_REG 0x10 // Multicast Address Hash Table 0 register
16350+#define MAHT1_REG 0x14 // Multicast Address Hash Table 1 register
16351+#define TXPD_REG 0x18 // Transmit Poll Demand register
16352+#define RXPD_REG 0x1c // Receive Poll Demand register
16353+#define TXR_BADR_REG 0x20 // Transmit Ring Base Address register
16354+#define RXR_BADR_REG 0x24 // Receive Ring Base Address register
16355+#define HPTXPD_REG 0x28
16356+#define HPTXR_BADR_REG 0x2c
16357+#define ITC_REG 0x30 // interrupt timer control register
16358+#define APTC_REG 0x34 // Automatic Polling Timer control register
16359+#define DBLAC_REG 0x38 // DMA Burst Length and Arbitration control register
16360+#define DMAFIFOS_REG 0x3c
16361+#define FEAR_REG 0x44
16362+#define TPAFCR_REG 0x48
16363+#define RBSR_REG 0x4c
16364+#define MACCR_REG 0x50 // MAC control register
16365+#define MACSR_REG 0x54 // MAC status register
16366+#define PHYCR_REG 0x60 // PHY control register
16367+#define PHYDATA_REG 0x64 // PHY Write Data register
16368+
16369+// --------------------------------------------------------------------
16370+// PHYCR_REG
16371+// --------------------------------------------------------------------
16372+#define PHY_RE_AUTO_bit (1UL<<9)
16373+#define PHY_READ_bit (1UL<<26)
16374+#define PHY_WRITE_bit (1UL<<27)
16375+// --------------------------------------------------------------------
16376+// PHYCR_REG
16377+// --------------------------------------------------------------------
16378+#define PHY_AUTO_OK_bit (1UL<<5)
16379+// --------------------------------------------------------------------
16380+// PHY INT_STAT_REG
16381+// --------------------------------------------------------------------
16382+#define PHY_SPEED_CHG_bit (1UL<<14)
16383+#define PHY_DUPLEX_CHG_bit (1UL<<13)
16384+#define PHY_LINK_CHG_bit (1UL<<10)
16385+#define PHY_AUTO_COMP_bit (1UL<<11)
16386+// --------------------------------------------------------------------
16387+// PHY SPE_STAT_REG
16388+// --------------------------------------------------------------------
16389+#define PHY_RESOLVED_bit (1UL<<11)
16390+#define PHY_LINK_bit (1UL<<10)
16391+#define PHY_SPEED_mask 0xC000
16392+#define PHY_SPEED_10M 0x0
16393+#define PHY_SPEED_100M 0x1
16394+#define PHY_SPEED_1G 0x2
16395+#define PHY_DUPLEX_mask 0x2000
16396+#define PHY_SPEED_DUPLEX_MASK 0x01E0
16397+#define PHY_100M_DUPLEX 0x0100
16398+#define PHY_100M_HALF 0x0080
16399+#define PHY_10M_DUPLEX 0x0040
16400+#define PHY_10M_HALF 0x0020
16401+#define LINK_STATUS 0x04
16402+#define PHYID_VENDOR_MASK 0xfffffc00
16403+#define PHYID_VENDOR_MARVELL 0x01410c00
16404+#define PHYID_VENDOR_BROADCOM 0x00406000
16405+#define PHYID_VENDOR_RTL8201E 0x001cc800
16406+#define DUPLEX_FULL 0x01
16407+#define DUPLEX_HALF 0x00
16408+
16409+
16410+
16411+// --------------------------------------------------------------------
16412+// MACCR_REG
16413+// --------------------------------------------------------------------
16414+
16415+#define SW_RST_bit (1UL<<31) // software reset/
16416+#define DIRPATH_bit (1UL<<21)
16417+#define RX_IPCS_FAIL_bit (1UL<<20)
16418+#define SPEED_100M_MODE_bit (1UL<<19)
16419+#define RX_UDPCS_FAIL_bit (1UL<<18)
16420+#define RX_BROADPKT_bit (1UL<<17) // Receiving broadcast packet
16421+#define RX_MULTIPKT_bit (1UL<<16) // receiving multicast packet
16422+#define RX_HT_EN_bit (1UL<<15)
16423+#define RX_ALLADR_bit (1UL<<14) // not check incoming packet's destination address
16424+#define JUMBO_LF_bit (1UL<<13)
16425+#define RX_RUNT_bit (1UL<<12) // Store incoming packet even its length is les than 64 byte
16426+#define CRC_CHK_bit (1UL<<11)
16427+#define CRC_APD_bit (1UL<<10) // append crc to transmit packet
16428+#define GMAC_MODE_bit (1UL<<9)
16429+#define FULLDUP_bit (1UL<<8) // full duplex
16430+#define ENRX_IN_HALFTX_bit (1UL<<7)
16431+#define LOOP_EN_bit (1UL<<6) // Internal loop-back
16432+#define HPTXR_EN_bit (1UL<<5)
16433+#define REMOVE_VLAN_bit (1UL<<4)
16434+#define RXMAC_EN_bit (1UL<<3) // receiver enable
16435+#define TXMAC_EN_bit (1UL<<2) // transmitter enable
16436+#define RXDMA_EN_bit (1UL<<1) // enable DMA receiving channel
16437+#define TXDMA_EN_bit (1UL<<0) // enable DMA transmitting channel
16438+
16439+
16440+// --------------------------------------------------------------------
16441+// SCU_REG
16442+// --------------------------------------------------------------------
16443+#define SCU_BASE 0x1E6E2000
16444+#define SCU_PROTECT_KEY_REG 0x0
16445+#define SCU_PROT_KEY_MAGIC 0x1688a8a8
16446+#define SCU_RESET_CONTROL_REG 0x04
16447+#define SCU_RESET_MAC1 (1u << 11)
16448+#define SCU_RESET_MAC2 (1u << 12)
16449+#define SCU_HARDWARE_TRAPPING_REG 0x70
16450+#define SCU_HT_MAC_INTF_LSBIT 6
16451+#define SCU_HT_MAC_INTERFACE (0x7u << SCU_HT_MAC_INTF_LSBIT)
16452+#define MAC_INTF_SINGLE_PORT_MODES (1u<<0/*GMII*/ | 1u<<3/*MII_ONLY*/ | 1u<<4/*RMII_ONLY*/)
16453+#define SCU_HT_MAC_GMII 0x0u
16454+// MII and MII mode
16455+#define SCU_HT_MAC_MII_MII 0x1u
16456+#define SCU_HT_MAC_MII_ONLY 0x3u
16457+#define SCU_HT_MAC_RMII_ONLY 0x4u
16458+#define SCU_MULTIFUNCTION_PIN_REG 0x74
16459+#define SCU_MFP_MAC2_PHYLINK (1u << 26)
16460+#define SCU_MFP_MAC1_PHYLINK (1u << 25)
16461+#define SCU_MFP_MAC2_MII_INTF (1u << 21)
16462+#define SCU_MFP_MAC2_MDC_MDIO (1u << 20)
16463+#define SCU_SILICON_REVISION_REG 0x7C
16464+
16465+//---------------------------------------------------
16466+// PHY R/W Register Bit
16467+//---------------------------------------------------
16468+#define MIIWR (1UL<<27)
16469+#define MIIRD (1UL<<26)
16470+#define MDC_CYCTHR 0x34
16471+#define PHY_SPEED_MASK 0xC000
16472+#define PHY_DUPLEX_MASK 0x2000
16473+#define SPEED_1000M 0x02
16474+#define SPEED_100M 0x01
16475+#define SPEED_10M 0x00
16476+#define DUPLEX_FULL 0x01
16477+#define DUPLEX_HALF 0x00
16478+#define RESOLVED_BIT 0x800
16479+
16480+#define PHY_SPEED_DUPLEX_MASK 0x01E0
16481+#define PHY_100M_DUPLEX 0x0100
16482+#define PHY_100M_HALF 0x0080
16483+#define PHY_10M_DUPLEX 0x0040
16484+#define PHY_10M_HALF 0x0020
16485+
16486+//---------------------------------------------------
16487+// Descriptor bits.
16488+//---------------------------------------------------
16489+#define TXDMA_OWN 0x80000000 /* Own Bit */
16490+#define RXPKT_RDY 0x00000000
16491+#define RXPKT_STATUS 0x80000000
16492+#define EDORR 0x40000000 /* Receive End Of Ring */
16493+#define LRS 0x10000000 /* Last Descriptor */
16494+#define RD_ES 0x00008000 /* Error Summary */
16495+#define EDOTR 0x40000000 /* Transmit End Of Ring */
16496+#define T_OWN 0x80000000 /* Own Bit */
16497+#define LTS 0x10000000 /* Last Segment */
16498+#define FTS 0x20000000 /* First Segment */
16499+#define CRC_ERR 0x00080000
16500+#define TD_ES 0x00008000 /* Error Summary */
16501+#define TD_SET 0x08000000 /* Setup Packet */
16502+#define RX_ERR 0x00040000
16503+#define FTL 0x00100000
16504+#define RUNT 0x00200000
16505+#define RX_ODD_NB 0x00400000
16506+#define BYTE_COUNT_MASK 0x00003FFF
16507+
16508+//---------------------------------------------------
16509+// SPEED/DUPLEX Parameters
16510+//---------------------------------------------------
16511+
16512+//---------------------------------------------------
16513+// Return Status
16514+//---------------------------------------------------
16515+#define TEST_PASS 0
16516+#define PACKET_TEST_FAIL 1
16517+#define PACKET_LENGTH_TEST_FAIL 2
16518+
16519+struct mac_desc {
16520+ volatile s32 status;
16521+ u32 des1;
16522+ u32 reserved;
16523+ u32 buf;
16524+};
16525+static struct mac_desc rx_ring[NUM_RX] __attribute__ ((aligned(32))); /* RX descriptor ring */
16526+static struct mac_desc tx_ring[NUM_TX] __attribute__ ((aligned(32))); /* TX descriptor ring */
16527+static int rx_new; /* RX descriptor ring pointer */
16528+static int tx_new; /* TX descriptor ring pointer */
16529+static volatile unsigned char rx_buffer[NUM_RX][RX_BUFF_SZ] __attribute__ ((aligned(32))); /* RX buffer */
16530+static volatile unsigned char tx_buffer[NUM_TX][TX_BUFF_SZ] __attribute__ ((aligned(32))); /* TX buffer */
16531diff --git a/board/aspeed/ast2300/mictest.c b/board/aspeed/ast2300/mictest.c
16532new file mode 100755
16533index 0000000..1b2b342
16534--- /dev/null
16535+++ b/board/aspeed/ast2300/mictest.c
16536@@ -0,0 +1,146 @@
16537+/*
16538+ * This program is distributed in the hope that it will be useful,
16539+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
16540+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16541+ * GNU General Public License for more details.
16542+ *
16543+ * You should have received a copy of the GNU General Public License
16544+ * along with this program; if not, write to the Free Software
16545+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16546+ * MA 02111-1307 USA
16547+ */
16548+
16549+/*
16550+ * Diagnostics support
16551+ */
16552+#include <common.h>
16553+#include <command.h>
16554+#include <post.h>
16555+#include "slt.h"
16556+
16557+#if ((CFG_CMD_SLT & CFG_CMD_MICTEST) && defined(CONFIG_SLT))
16558+#include "mictest.h"
16559+
16560+static unsigned char ctrlbuf[MIC_MAX_CTRL];
16561+static unsigned char chksumbuf[MIC_MAX_CHKSUM];
16562+
16563+void vInitSCU(void)
16564+{
16565+ unsigned long ulData;
16566+
16567+ *(unsigned long *) (0x1e6e2000) = 0x1688A8A8;
16568+
16569+ udelay(100);
16570+
16571+ ulData = *(unsigned long *) (0x1e6e2004);
16572+ ulData &= 0xbffff;
16573+ *(unsigned long *) (0x1e6e2004) = ulData;
16574+
16575+}
16576+
16577+void vInitMIC(void)
16578+{
16579+ unsigned long i, j, ulPageNumber;
16580+ unsigned char *pjctrl, *pjsum;
16581+
16582+ ulPageNumber = DRAMSIZE >> 12;
16583+
16584+ pjctrl = (unsigned char *)(m16byteAlignment((unsigned long) ctrlbuf));
16585+ pjsum = (unsigned char *)(m16byteAlignment((unsigned long) chksumbuf));
16586+
16587+ /* init ctrl buffer (2bits for one page) */
16588+ for (i=0; i< (ulPageNumber/4); i++)
16589+ *(unsigned char *) (pjctrl + i) = DEFAULT_CTRL;
16590+
16591+ /* init chksum buf (4bytes for one page) */
16592+ for (i=0; i<ulPageNumber; i++)
16593+ *(unsigned long *) (pjsum + i*4) = DEFAULT_CHKSUM;
16594+
16595+ *(unsigned long *) (MIC_BASE + MIC_CTRLBUFF_REG) = (unsigned long) pjctrl;
16596+ *(unsigned long *) (MIC_BASE + MIC_CHKSUMBUF_REG) = (unsigned long) pjsum;
16597+ *(unsigned long *) (MIC_BASE + MIC_RATECTRL_REG) = (unsigned long) DEFAULT_RATE;
16598+ *(unsigned long *) (MIC_BASE + MIC_ENGINECTRL_REG) = MIC_ENABLE_MIC | (DRAMSIZE - 0x1000);
16599+
16600+}
16601+
16602+void vDisableMIC(void)
16603+{
16604+ *(unsigned long *) (MIC_BASE + MIC_ENGINECTRL_REG) = MIC_RESET_MIC;
16605+
16606+}
16607+
16608+int do_chksum(void)
16609+{
16610+ unsigned long i, j, k, ulPageNumber;
16611+ int Status = 0;
16612+ unsigned short tmp;
16613+ volatile unsigned long sum1, sum2;
16614+ unsigned long goldensum, chksum;
16615+ unsigned long len, tlen;
16616+ unsigned char *pjsum;
16617+
16618+ ulPageNumber = DRAMSIZE >> 12;
16619+ pjsum = (unsigned char *)(m16byteAlignment((unsigned long) chksumbuf));
16620+
16621+ /* start test */
16622+ for (i=0; i<ulPageNumber; i++)
16623+ {
16624+
16625+ sum1 = 0xffff, sum2 = 0xffff;
16626+ len = 0x0800;
16627+ j = 0;
16628+
16629+ while (len)
16630+ {
16631+ tlen = len > 360 ? 360 : len;
16632+ len -= tlen;
16633+ do {
16634+ tmp = *(unsigned short *) (DRAM_BASE + ((i << 12) + j));
16635+ sum1 += (unsigned long) tmp;
16636+ sum2 += sum1;
16637+ j+=2;
16638+ } while (--tlen);
16639+ sum1 = (sum1 & 0xffff) + (sum1 >> 16);
16640+ sum2 = (sum2 & 0xffff) + (sum2 >> 16);
16641+ }
16642+
16643+ sum1 = (sum1 & 0xffff) + (sum1 >> 16);
16644+ sum2 = (sum2 & 0xffff) + (sum2 >> 16);
16645+
16646+ goldensum = (sum2 << 16) | sum1;
16647+ k= 0;
16648+ do {
16649+ chksum = *(unsigned long *) (pjsum + i*4);
16650+ udelay(100);
16651+ k++;
16652+ } while ((chksum == 0) && (k<1000));
16653+
16654+ if (chksum != goldensum)
16655+ {
16656+ Status = 1;
16657+ printf("[FAIL] MIC Chksum Failed at Page %x \n", i);
16658+ }
16659+
16660+ } /* end of i loop */
16661+
16662+ return (Status);
16663+
16664+}
16665+
16666+int do_mictest (void)
16667+{
16668+ unsigned long Flags = 0;
16669+
16670+ vInitSCU();
16671+ vInitMIC();
16672+
16673+ if (do_chksum())
16674+ Flags = 1;
16675+
16676+ vDisableMIC();
16677+
16678+ return Flags;
16679+
16680+}
16681+
16682+#endif /* CONFIG_SLT */
16683diff --git a/board/aspeed/ast2300/mictest.h b/board/aspeed/ast2300/mictest.h
16684new file mode 100755
16685index 0000000..e14bb41
16686--- /dev/null
16687+++ b/board/aspeed/ast2300/mictest.h
16688@@ -0,0 +1,55 @@
16689+/*
16690+ * This program is distributed in the hope that it will be useful,
16691+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
16692+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16693+ * GNU General Public License for more details.
16694+ *
16695+ * You should have received a copy of the GNU General Public License
16696+ * along with this program; if not, write to the Free Software
16697+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16698+ */
16699+/* Macro */
16700+#define m08byteAlignment(x) ((x + 0x00000007) & 0xFFFFFFF8)
16701+#define m16byteAlignment(x) ((x + 0x0000000F) & 0xFFFFFFF0)
16702+#define m64byteAlignment(x) ((x + 0x0000003F) & 0xFFFFFFC0)
16703+
16704+/* Options */
16705+#define MIC_TEST_PAGE 32
16706+#define DRAMSIZE (MIC_TEST_PAGE * 0x1000)
16707+#define MIC_MAX_CTRL (MIC_TEST_PAGE / 4 + 16)
16708+#define MIC_MAX_CHKSUM (MIC_TEST_PAGE * 4 + 16)
16709+
16710+/* Default Setting */
16711+#define DEFAULT_RATE 0x00000000
16712+#define DEFAULT_CTRL 0xFF
16713+#define DEFAULT_CHKSUM 0x00000000
16714+#define DEFAULT_WRITEBACK 0x08880000
16715+
16716+/* Reg. Definition */
16717+#define DRAM_BASE 0x40000000
16718+#define MIC_BASE 0x1e640000
16719+#define MIC_CTRLBUFF_REG 0x00
16720+#define MIC_CHKSUMBUF_REG 0x04
16721+#define MIC_RATECTRL_REG 0x08
16722+#define MIC_ENGINECTRL_REG 0x0C
16723+#define MIC_STOPPAGE_REG 0x10
16724+#define MIC_STATUS_REG 0x14
16725+#define MIC_STATUS1_REG 0x18
16726+#define MIC_STATUS2_REG 0x1C
16727+
16728+#define MIC_RESET_MIC 0x00000000
16729+#define MIC_ENABLE_MIC 0x10000000
16730+#define MIC_MAXPAGE_MASK 0x0FFFF000
16731+#define MIC_WRITEBACK_MASK 0xFFFF0000
16732+#define MIC_STOPPAGE_MASK 0x0000FFFF
16733+#define MIC_PAGEERROR 0x40000000
16734+#define MIC_PAGE1ERROR 0x10000000
16735+#define MIC_PAGE2ERROR 0x20000000
16736+#define MIC_INTMASK 0x00060000
16737+#define MIC_ERRPAGENO_MASK 0x0000FFFF
16738+
16739+#define MIC_CTRL_MASK 0x03
16740+#define MIC_CTRL_SKIP 0x00
16741+#define MIC_CTRL_CHK1 0x01
16742+#define MIC_CTRL_CHK2 0x02
16743+#define MIC_CTRL_CHK3 0x03
16744diff --git a/board/aspeed/ast2300/pci.c b/board/aspeed/ast2300/pci.c
16745new file mode 100755
16746index 0000000..5b17466
16747--- /dev/null
16748+++ b/board/aspeed/ast2300/pci.c
16749@@ -0,0 +1,243 @@
16750+/*
16751+ * This program is free software; you can redistribute it and/or
16752+ * modify it under the terms of the GNU General Public License as
16753+ * published by the Free Software Foundation; either version 2, or (at
16754+ * your option) any later version.
16755+ */
16756+
16757+#include <common.h>
16758+#include <pci.h>
16759+
16760+#ifdef CONFIG_PCI
16761+
16762+#define PCI_CSR_BASE 0x60000000
16763+#define ASPEED_PCI_IO_BASE 0x00000000
16764+#define ASPEED_PCI_IO_SIZE 0x00010000
16765+#define ASPEED_PCI_MEM_BASE 0x68000000
16766+#define ASPEED_PCI_MEM_SIZE 0x18000000
16767+
16768+#define CSR_CRP_CMD_OFFSET 0x00
16769+#define CSR_CRP_WRITE_OFFSET 0x04
16770+#define CSR_CRP_READ_OFFSET 0x08
16771+#define CSR_PCI_ADDR_OFFSET 0x0C
16772+#define CSR_PCI_CMD_OFFSET 0x10
16773+#define CSR_PCI_WRITE_OFFSET 0x14
16774+#define CSR_PCI_READ_OFFSET 0x18
16775+#define CSR_PCI_STATUS_OFFSET 0x1C
16776+
16777+#define CRP_ADDR_REG (volatile ulong*) (PCI_CSR_BASE + CSR_CRP_CMD_OFFSET)
16778+#define CRP_WRITE_REG (volatile ulong*) (PCI_CSR_BASE + CSR_CRP_WRITE_OFFSET)
16779+#define CRP_READ_REG (volatile ulong*) (PCI_CSR_BASE + CSR_CRP_READ_OFFSET)
16780+#define PCI_ADDR_REG (volatile ulong*) (PCI_CSR_BASE + CSR_PCI_ADDR_OFFSET)
16781+#define PCI_CMD_REG (volatile ulong*) (PCI_CSR_BASE + CSR_PCI_CMD_OFFSET)
16782+#define PCI_WRITE_REG (volatile ulong*) (PCI_CSR_BASE + CSR_PCI_WRITE_OFFSET)
16783+#define PCI_READ_REG (volatile ulong*) (PCI_CSR_BASE + CSR_PCI_READ_OFFSET)
16784+
16785+#define PCI_CMD_READ 0x0A
16786+#define PCI_CMD_WRITE 0x0B
16787+
16788+#define RESET_PCI_STATUS *(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_STATUS_OFFSET) = 0x01
16789+#define CHK_PCI_STATUS (*(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_STATUS_OFFSET) & 0x03)
16790+
16791+static int pci_config_access (u8 access_type, u32 dev, u32 reg, u32 * data)
16792+{
16793+ u32 bus;
16794+ u32 device;
16795+ u32 function;
16796+
16797+ bus = ((dev & 0xff0000) >> 16);
16798+ device = ((dev & 0xf800) >> 11);
16799+ function = (dev & 0x0700);
16800+
16801+ if (bus == 0) {
16802+ // Type 0 Configuration
16803+ *PCI_ADDR_REG = (u32) (1UL << device | function | (reg & 0xfc));
16804+ } else {
16805+ // Type 1 Configuration
16806+ *PCI_ADDR_REG = (u32) (dev | ((reg / 4) << 2) | 1);
16807+ }
16808+
16809+ RESET_PCI_STATUS;
16810+
16811+ if (access_type == PCI_CMD_WRITE) {
16812+ *PCI_CMD_REG = (ulong) PCI_CMD_WRITE;
16813+ *PCI_WRITE_REG = *data;
16814+ } else {
16815+ *PCI_CMD_REG = (ulong) PCI_CMD_READ;
16816+ *data = *PCI_READ_REG;
16817+ }
16818+
16819+ return (CHK_PCI_STATUS);
16820+}
16821+
16822+static int aspeed_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
16823+{
16824+ u32 data;
16825+
16826+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data)) {
16827+ *val = 0;
16828+ return -1;
16829+ }
16830+
16831+ *val = (data >> ((reg & 3) << 3)) & 0xff;
16832+
16833+ return 0;
16834+}
16835+
16836+
16837+static int aspeed_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
16838+{
16839+ u32 data;
16840+
16841+ if (reg & 1)
16842+ return -1;
16843+
16844+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data)) {
16845+ *val = 0;
16846+ return -1;
16847+ }
16848+
16849+ *val = (data >> ((reg & 3) << 3)) & 0xffff;
16850+
16851+ return 0;
16852+}
16853+
16854+
16855+static int aspeed_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
16856+ u32 * val)
16857+{
16858+ u32 data = 0;
16859+
16860+ if (reg & 3)
16861+ return -1;
16862+
16863+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data)) {
16864+ *val = 0;
16865+ return -1;
16866+ }
16867+
16868+ *val = data;
16869+
16870+ return (0);
16871+}
16872+
16873+static int aspeed_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
16874+{
16875+ u32 data = 0;
16876+
16877+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data))
16878+ return -1;
16879+
16880+ data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
16881+ ((reg & 3) << 3));
16882+
16883+ if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
16884+ return -1;
16885+
16886+ return 0;
16887+}
16888+
16889+
16890+static int aspeed_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
16891+{
16892+ u32 data = 0;
16893+
16894+ if (reg & 1)
16895+ return -1;
16896+
16897+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data))
16898+ return -1;
16899+
16900+ data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
16901+ ((reg & 3) << 3));
16902+
16903+ if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
16904+ return -1;
16905+
16906+ return 0;
16907+}
16908+
16909+static int aspeed_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
16910+{
16911+ u32 data;
16912+
16913+ if (reg & 3) {
16914+ return -1;
16915+ }
16916+
16917+ data = val;
16918+
16919+ if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
16920+ return -1;
16921+
16922+ return (0);
16923+}
16924+
16925+/*
16926+ * Initialize PCIU
16927+ */
16928+aspeed_pciu_init ()
16929+{
16930+
16931+ unsigned long reg;
16932+
16933+ /* Reset PCI Host */
16934+ reg = *((volatile ulong*) 0x1e6e2004);
16935+ *((volatile ulong*) 0x1e6e2004) = reg | 0x00280000;
16936+
16937+ reg = *((volatile ulong*) 0x1e6e2074); /* REQ2 */
16938+ *((volatile ulong*) 0x1e6e2074) = reg | 0x00000010;
16939+
16940+ *((volatile ulong*) 0x1e6e2008) |= 0x00080000;
16941+ reg = *((volatile ulong*) 0x1e6e200c);
16942+ *((volatile ulong*) 0x1e6e200c) = reg & 0xfff7ffff;
16943+ udelay(1);
16944+ *((volatile ulong*) 0x1e6e2004) &= 0xfff7ffff;
16945+
16946+ /* Initial PCI Host */
16947+ RESET_PCI_STATUS;
16948+
16949+ *CRP_ADDR_REG = ((ulong)(PCI_CMD_READ) << 16) | 0x04;
16950+ reg = *CRP_READ_REG;
16951+
16952+ *CRP_ADDR_REG = ((ulong)(PCI_CMD_WRITE) << 16) | 0x04;
16953+ *CRP_WRITE_REG = reg | 0x07;
16954+
16955+}
16956+
16957+/*
16958+ * Initialize Module
16959+ */
16960+
16961+void aspeed_init_pci (struct pci_controller *hose)
16962+{
16963+ hose->first_busno = 0;
16964+ hose->last_busno = 0xff;
16965+
16966+ aspeed_pciu_init (); /* Initialize PCIU */
16967+
16968+ /* PCI memory space #1 */
16969+ pci_set_region (hose->regions + 0,
16970+ ASPEED_PCI_MEM_BASE, ASPEED_PCI_MEM_BASE, ASPEED_PCI_MEM_SIZE, PCI_REGION_MEM);
16971+
16972+ /* PCI I/O space */
16973+ pci_set_region (hose->regions + 1,
16974+ ASPEED_PCI_IO_BASE, ASPEED_PCI_IO_BASE, ASPEED_PCI_IO_SIZE, PCI_REGION_IO);
16975+
16976+ hose->region_count = 2;
16977+
16978+ hose->read_byte = aspeed_pci_read_config_byte;
16979+ hose->read_word = aspeed_pci_read_config_word;
16980+ hose->read_dword = aspeed_pci_read_config_dword;
16981+ hose->write_byte = aspeed_pci_write_config_byte;
16982+ hose->write_word = aspeed_pci_write_config_word;
16983+ hose->write_dword = aspeed_pci_write_config_dword;
16984+
16985+ pci_register_hose (hose);
16986+
16987+ hose->last_busno = pci_hose_scan (hose);
16988+
16989+ return;
16990+}
16991+#endif /* CONFIG_PCI */
16992+
16993diff --git a/board/aspeed/ast2300/platform.S b/board/aspeed/ast2300/platform.S
16994new file mode 100644
16995index 0000000..27e8f26
16996--- /dev/null
16997+++ b/board/aspeed/ast2300/platform.S
16998@@ -0,0 +1,3089 @@
16999+/*
17000+ * This program is distributed in the hope that it will be useful,
17001+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
17002+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17003+ * GNU General Public License for more details.
17004+ *
17005+ * You should have received a copy of the GNU General Public License
17006+ * along with this program; if not, write to the Free Software
17007+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17008+ */
17009+/*
17010+ * Board specific setup info
17011+ *
17012+ ******************************************************************************
17013+ * ASPEED Technology Inc.
17014+ * AST2300/AST2400 DDR2/DDR3 SDRAM controller initialization and calibration sequence
17015+ *
17016+ * Gary Hsu, <gary_hsu@aspeedtech.com>
17017+ *
17018+ * Release date: 2014.12.29 formal release for SDK0.60
17019+ *
17020+ * Modified list from v0.23
17021+ * EC1. Modify DQIDLY and DQSI-MCLK2X calibration algorithm
17022+ * EC2. Remove pass 2 DQIDLY finetune process
17023+ * EC3. Modify ECC code
17024+ * EC4. Add AST2400 supporting
17025+ * EC5. Add SPI timing calibration for AST2400
17026+ * EC6. Remove AST2300-A0 PCI-e workaround
17027+ * EC7. Add CK duty calibration for AST2400
17028+ * EC8. Remove #define CONFIG_DRAM_UART_OUT, default has message output to UART5
17029+ * EC9. Add DRAM size auto-detection
17030+ * EC10. Add GPIO register clear when watchdog reboot (only for AST2400)
17031+ * EC11. Move the "Solve ASPM" code position of AST2300 to avoid watchdog reset
17032+ *
17033+ * Modified list from v0.53
17034+ * EC1. Add solution of LPC lock issue due to watchdog reset. (AP note A2300-11)
17035+ *
17036+ * Modified list from v0.56
17037+ * EC1. Fix read DQS input mask window too late issue if DRAM's t_DQSCK is earlier too much
17038+ * (ex. Nanya NT5CB64M16FP)
17039+ * 1. Change init value of MCR18[4] from '1' to '0'
17040+ * 2. Add CBR4 code to finetune MCR18[4]
17041+ *
17042+ * Modified list from v0.59
17043+ * EC1. Add DQS input gating window delay tuning (1/2 T) when CBR retry
17044+ * EC2. Modify DLL1 MAdj = 0x4C
17045+ *
17046+ * Optional define variable
17047+ * 1. DRAM Speed //
17048+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
17049+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
17050+ * 2. ECC Function enable
17051+ * CONFIG_DRAM_ECC // define to enable ECC function
17052+ * // when enabled, must define the ECC protected memory size at 0x1e6e0054
17053+ * 3. UART5 message output //
17054+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
17055+ ******************************************************************************
17056+ */
17057+
17058+#include <config.h>
17059+#include <version.h>
17060+/******************************************************************************
17061+ Calibration Macro Start
17062+ Usable registers:
17063+ r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11
17064+ ******************************************************************************/
17065+/* PATTERN_TABLE,
17066+ init_delay_timer,
17067+ check_delay_timer,
17068+ clear_delay_timer,
17069+ record_dll2_pass_range,
17070+ record_dll2_pass_range_h,
17071+ are for DRAM calibration */
17072+
17073+PATTERN_TABLE:
17074+ .word 0xff00ff00
17075+ .word 0xcc33cc33
17076+ .word 0xaa55aa55
17077+ .word 0x88778877
17078+ .word 0x92cc4d6e @ 5
17079+ .word 0x543d3cde
17080+ .word 0xf1e843c7
17081+ .word 0x7c61d253
17082+ .word 0x00000000 @ 8
17083+
17084+ .macro init_delay_timer
17085+ ldr r0, =0x1e782024 @ Set Timer3 Reload
17086+ str r2, [r0]
17087+
17088+ ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
17089+ ldr r1, =0x00040000
17090+ str r1, [r0]
17091+
17092+ ldr r0, =0x1e782030 @ Enable Timer3
17093+ ldr r1, [r0]
17094+ mov r2, #7
17095+ orr r1, r1, r2, lsl #8
17096+ str r1, [r0]
17097+
17098+ ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout
17099+ .endm
17100+
17101+ .macro check_delay_timer
17102+ ldr r1, [r0]
17103+ bic r1, r1, #0xFFFBFFFF
17104+ mov r2, r1, lsr #18
17105+ cmp r2, #0x01
17106+ .endm
17107+
17108+ .macro clear_delay_timer
17109+ ldr r0, =0x1e782030 @ Disable Timer3
17110+ ldr r1, [r0]
17111+ bic r1, r1, #0x00000F00
17112+ str r1, [r0]
17113+
17114+ ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
17115+ ldr r1, =0x00040000
17116+ str r1, [r0]
17117+ .endm
17118+
17119+ .macro record_dll2_pass_range
17120+ ldr r1, [r0]
17121+ bic r2, r1, #0xFFFFFF00
17122+ cmp r2, r3 @ record min
17123+ bicgt r1, r1, #0x000000FF
17124+ orrgt r1, r1, r3
17125+ bic r2, r1, #0xFFFF00FF
17126+ cmp r3, r2, lsr #8 @ record max
17127+ bicgt r1, r1, #0x0000FF00
17128+ orrgt r1, r1, r3, lsl #8
17129+ str r1, [r0]
17130+ .endm
17131+
17132+ .macro record_dll2_pass_range_h
17133+ ldr r1, [r0]
17134+ bic r2, r1, #0xFF00FFFF
17135+ mov r2, r2, lsr #16
17136+ cmp r2, r3 @ record min
17137+ bicgt r1, r1, #0x00FF0000
17138+ orrgt r1, r1, r3, lsl #16
17139+ bic r2, r1, #0x00FFFFFF
17140+ cmp r3, r2, lsr #24 @ record max
17141+ bicgt r1, r1, #0xFF000000
17142+ orrgt r1, r1, r3, lsl #24
17143+ str r1, [r0]
17144+ .endm
17145+
17146+ .macro init_spi_checksum
17147+ ldr r0, =0x1e620084
17148+ ldr r1, =0x20010000
17149+ str r1, [r0]
17150+ ldr r0, =0x1e62008C
17151+ ldr r1, =0x20000200
17152+ str r1, [r0]
17153+ ldr r0, =0x1e620080
17154+ ldr r1, =0x0000000D
17155+ orr r2, r2, r7
17156+ orr r1, r1, r2, lsl #8
17157+ and r2, r6, #0xF
17158+ orr r1, r1, r2, lsl #4
17159+ str r1, [r0]
17160+ ldr r0, =0x1e620008
17161+ ldr r2, =0x00000800
17162+ .endm
17163+
17164+/******************************************************************************
17165+ Calibration Macro End
17166+ ******************************************************************************/
17167+LPC_Patch: @ load to SRAM base 0x1e720400
17168+ str r1, [r0]
17169+ str r3, [r2]
17170+ bic r1, r1, #0xFF
17171+LPC_Patch_S1:
17172+ subs r5, r5, #0x01
17173+ moveq pc, r8
17174+ ldr r3, [r2]
17175+ tst r3, #0x01
17176+ movne pc, r8
17177+ mov pc, r7
17178+LPC_Patch_S2: @ load to SRAM base 0x1e720480
17179+ str r1, [r0]
17180+ mov pc, r9
17181+LPC_Patch_E:
17182+
17183+.globl lowlevel_init
17184+lowlevel_init:
17185+
17186+init_dram:
17187+ /* save lr */
17188+ mov r4, lr
17189+/* Test - DRAM initial time */
17190+ ldr r0, =0x1e782044
17191+ ldr r1, =0xFFFFFFFF
17192+ str r1, [r0]
17193+
17194+ ldr r0, =0x1e782030
17195+ ldr r1, [r0]
17196+ bic r1, r1, #0x0000F000
17197+ str r1, [r0]
17198+ mov r2, #3
17199+ orr r1, r1, r2, lsl #12
17200+ str r1, [r0]
17201+/* Test - DRAM initial time */
17202+
17203+ /*Set Scratch register Bit 7 before initialize*/
17204+ ldr r0, =0x1e6e2000
17205+ ldr r1, =0x1688a8a8
17206+ str r1, [r0]
17207+
17208+ ldr r0, =0x1e6e2040
17209+ ldr r1, [r0]
17210+ orr r1, r1, #0x80
17211+ str r1, [r0]
17212+
17213+ /* Fix LPC lock issue for AST2300 */
17214+ ldr r0, =0x1e6e207c @ Check AST2300
17215+ ldr r1, [r0]
17216+ mov r1, r1, lsr #24
17217+ cmp r1, #0x01
17218+ bne lpc_recover_end @ not match AST2300
17219+
17220+ mov r3, #0x0
17221+lpc_recover_check:
17222+ ldr r0, =0x1e78900c @ check HICR3[4]=0x1
17223+ ldr r1, [r0]
17224+ tst r1, #0x10
17225+ beq lpc_recover_end
17226+ ldr r0, =0x1e789004 @ check HICR1[7]=0x1
17227+ ldr r1, [r0]
17228+ tst r1, #0x80
17229+ beq lpc_recover_end
17230+ ldr r0, =0x1e7890a0 @ check LHCR0[27:24]=0x6
17231+ ldr r1, [r0]
17232+ mov r1, r1, lsr #24
17233+ and r1, r1, #0xF
17234+ cmp r1, #0x06
17235+ bne lpc_recover_end
17236+ add r3, r3, #0x01
17237+ cmp r3, #0x5 @ repeat 5 times
17238+ ble lpc_recover_check
17239+
17240+ mov r3, #0x0
17241+lpc_recover_init:
17242+ ldr r0, =0x1e7890a4 @ set LHCR1[1:0]=0x0
17243+ ldr r1, =0x00000000
17244+ str r1, [r0]
17245+ add r3, r3, #0x01
17246+ cmp r3, #0x20
17247+ bge lpc_recover_end
17248+ ldr r1, [r0]
17249+ tst r1, #0x01
17250+ bne lpc_recover_init
17251+
17252+ ldr r0, =0x1e7890b0 @ set LHCR4[7:0]=0xFF
17253+ ldr r1, =0x000000FF
17254+ str r1, [r0]
17255+ ldr r0, =0x1e7890b4 @ set LHCR5[31:0]=0xFFFFFFFF
17256+ ldr r1, =0xFFFFFFFF
17257+ str r1, [r0]
17258+ ldr r0, =0x1e7890b8 @ set LHCR6[31:0]=0xFFFFFFFF
17259+ str r1, [r0]
17260+
17261+ adr r6, LPC_Patch
17262+ adr r7, LPC_Patch_S2
17263+ ldr r0, =0x1e720400
17264+copy_lpc_patch_1:
17265+ ldr r1, [r6]
17266+ str r1, [r0]
17267+ add r6, r6, #0x4
17268+ add r0, r0, #0x4
17269+ cmp r6, r7
17270+ bne copy_lpc_patch_1
17271+
17272+ adr r6, LPC_Patch_S2
17273+ adr r7, LPC_Patch_E
17274+ ldr r0, =0x1e720480
17275+copy_lpc_patch_2:
17276+ ldr r1, [r6]
17277+ str r1, [r0]
17278+ add r6, r6, #0x4
17279+ add r0, r0, #0x4
17280+ cmp r6, r7
17281+ bne copy_lpc_patch_2
17282+
17283+ ldr r0, =0x1e7890a0 @ set LHCR0[31:0]=0xFFFFFF01
17284+ ldr r1, =0xFFFFFF01
17285+ add r2, r0, #0x4
17286+ mov r3, #0x01
17287+ mov r5, #0x10
17288+ adr r9, lpc_recover_end
17289+ adr r6, LPC_Patch
17290+ adr r7, LPC_Patch_S1
17291+ sub r6, r7, r6
17292+ ldr r7, =0x1e720400
17293+ add r7, r7, r6
17294+ ldr r8, =0x1e720480
17295+ ldr pc, =0x1e720400
17296+
17297+lpc_recover_end:
17298+ ldr r0, =0x1e7890a0 @ set LHCR0[31:0]=0xFFFFFF00
17299+ ldr r1, =0xFFFFFF00
17300+ str r1, [r0]
17301+ /* <END> Fix LPC lock issue for AST2300 */
17302+
17303+ /* Check Scratch Register Bit 6 */
17304+ ldr r0, =0x1e6e2040
17305+ ldr r1, [r0]
17306+ bic r1, r1, #0xFFFFFFBF
17307+ mov r2, r1, lsr #6
17308+ cmp r2, #0x01
17309+ beq platform_exit
17310+
17311+ ldr r2, =0x033103F1 @ load PLL parameter for 24Mhz CLKIN (396:324)
17312+/* ldr r2, =0x019001F0 @ load PLL parameter for 24Mhz CLKIN (408:336) */
17313+ ldr r0, =0x1e6e207c @ Check Revision ID
17314+ ldr r1, [r0]
17315+ mov r1, r1, lsr #24
17316+ cmp r1, #0x02
17317+ bne set_MPLL @ not match AST2400
17318+
17319+ ldr r0, =0x1e6e2070 @ Check CLKIN freq
17320+ ldr r1, [r0]
17321+ mov r1, r1, lsr #23
17322+ tst r1, #0x01
17323+ ldrne r2, =0x017001D0 @ load PLL parameter for 25Mhz CLKIN (400:325)
17324+
17325+set_MPLL:
17326+ ldr r0, =0x1e6e2020 @ M-PLL (DDR SDRAM) Frequency
17327+ ldr r1, =0xFFFF
17328+#if defined(CONFIG_DRAM_336)
17329+ mov r2, r2, lsr #16
17330+#endif
17331+ and r1, r2, r1
17332+ str r1, [r0]
17333+
17334+/* Debug - UART console message */
17335+ ldr r0, =0x1e78400c
17336+ mov r1, #0x83
17337+ str r1, [r0]
17338+
17339+ ldr r0, =0x1e6e202c
17340+ ldr r2, [r0]
17341+ mov r2, r2, lsr #12
17342+ tst r2, #0x01
17343+ ldr r0, =0x1e784000
17344+ moveq r1, #0x0D @ Baudrate 115200
17345+ movne r1, #0x01 @ Baudrate 115200, div13
17346+#if defined(CONFIG_DRAM_UART_38400)
17347+ moveq r1, #0x27 @ Baudrate 38400
17348+ movne r1, #0x03 @ Baudrate 38400 , div13
17349+#endif
17350+ str r1, [r0]
17351+
17352+ ldr r0, =0x1e784004
17353+ mov r1, #0x00
17354+ str r1, [r0]
17355+
17356+ ldr r0, =0x1e78400c
17357+ mov r1, #0x03
17358+ str r1, [r0]
17359+
17360+ ldr r0, =0x1e784008
17361+ mov r1, #0x07
17362+ str r1, [r0]
17363+
17364+ ldr r0, =0x1e784000
17365+ mov r1, #0x0D @ '\r'
17366+ str r1, [r0]
17367+ mov r1, #0x0A @ '\n'
17368+ str r1, [r0]
17369+ mov r1, #0x44 @ 'D'
17370+ str r1, [r0]
17371+ mov r1, #0x52 @ 'R'
17372+ str r1, [r0]
17373+ mov r1, #0x41 @ 'A'
17374+ str r1, [r0]
17375+ mov r1, #0x4D @ 'M'
17376+ str r1, [r0]
17377+ mov r1, #0x20 @ ' '
17378+ str r1, [r0]
17379+ mov r1, #0x49 @ 'I'
17380+ str r1, [r0]
17381+ mov r1, #0x6E @ 'n'
17382+ str r1, [r0]
17383+ mov r1, #0x69 @ 'i'
17384+ str r1, [r0]
17385+ mov r1, #0x74 @ 't'
17386+ str r1, [r0]
17387+ mov r1, #0x2D @ '-'
17388+ str r1, [r0]
17389+ mov r1, #0x44 @ 'D'
17390+ str r1, [r0]
17391+ mov r1, #0x44 @ 'D'
17392+ str r1, [r0]
17393+ mov r1, #0x52 @ 'R'
17394+ str r1, [r0]
17395+/* Debug - UART console message */
17396+
17397+ /* Delay about 100us */
17398+ ldr r0, =0x1e782030 @ Init Timer3 Control
17399+ ldr r1, [r0]
17400+ bic r1, r1, #0x00000F00
17401+ str r1, [r0]
17402+
17403+ ldr r2, =0x00000064 @ Set Timer3 Reload = 100 us
17404+ init_delay_timer
17405+delay_0:
17406+ check_delay_timer
17407+ bne delay_0
17408+ clear_delay_timer
17409+ /* end delay 100us */
17410+
17411+/******************************************************************************
17412+ Init DRAM common registers
17413+ ******************************************************************************/
17414+ ldr r0, =0x1e6e0000
17415+ ldr r1, =0xfc600309
17416+ str r1, [r0]
17417+
17418+ /* Reset MMC */
17419+ ldr r1, =0x00000000
17420+ ldr r0, =0x1e6e0034
17421+ str r1, [r0]
17422+ ldr r0, =0x1e6e0018
17423+ str r1, [r0]
17424+ ldr r0, =0x1e6e0024
17425+ str r1, [r0]
17426+ ldr r0, =0x1e6e0064 @ REG_MADJ, power down DLL
17427+ str r1, [r0]
17428+
17429+ ldr r1, =0x00034C4C @ REG_MADJ, reset DLL
17430+ str r1, [r0]
17431+
17432+ ldr r0, =0x1e6e0068 @ REG_SADJ
17433+ ldr r1, =0x00001800
17434+ str r1, [r0]
17435+
17436+ /* Delay about 10us */
17437+ ldr r2, =0x0000000B @ Set Timer3 Reload = 10 us
17438+ init_delay_timer
17439+delay_1:
17440+ check_delay_timer
17441+ bne delay_1
17442+ clear_delay_timer
17443+ /* end delay 10us */
17444+
17445+ ldr r0, =0x1e6e0064 @ REG_MADJ | 0xC0000, enable DLL
17446+ ldr r1, [r0]
17447+ ldr r2, =0xC0000
17448+ orr r1, r1, r2
17449+ str r1, [r0]
17450+
17451+ ldr r0, =0x1e6e0008
17452+ ldr r1, =0x0090040f /* VGA */
17453+ str r1, [r0]
17454+
17455+ ldr r0, =0x1e6e0018
17456+ ldr r1, =0x4000A120
17457+ str r1, [r0]
17458+
17459+ ldr r0, =0x1e6e0018
17460+ ldr r1, =0x00000120
17461+ str r1, [r0]
17462+
17463+ ldr r0, =0x1e6e0038
17464+ ldr r1, =0x00000000
17465+ str r1, [r0]
17466+
17467+ ldr r0, =0x1e6e0040
17468+ ldr r1, =0xFF444444
17469+ str r1, [r0]
17470+
17471+ ldr r0, =0x1e6e0044
17472+ ldr r1, =0x22222222
17473+ str r1, [r0]
17474+
17475+ ldr r0, =0x1e6e0048
17476+ ldr r1, =0x22222222
17477+ str r1, [r0]
17478+
17479+ ldr r0, =0x1e6e004c
17480+ ldr r1, =0x22222222
17481+ str r1, [r0]
17482+
17483+ ldr r0, =0x1e6e0050
17484+ ldr r1, =0x80000000
17485+ str r1, [r0]
17486+
17487+ ldr r0, =0x1e6e0050
17488+ ldr r1, =0x00000000
17489+ str r1, [r0]
17490+
17491+ ldr r0, =0x1e6e0054
17492+ ldr r1, =0x00000000
17493+ str r1, [r0]
17494+
17495+ ldr r0, =0x1e6e0060 @ REG_DRV
17496+ ldr r1, =0x000000FA @ 408 MHz
17497+#if defined(CONFIG_DRAM_336)
17498+ ldr r1, =0x000000FA
17499+#endif
17500+ str r1, [r0]
17501+
17502+ ldr r0, =0x1e6e0070
17503+ ldr r1, =0x00000000
17504+ str r1, [r0]
17505+
17506+ ldr r0, =0x1e6e0074
17507+ ldr r1, =0x00000000
17508+ str r1, [r0]
17509+
17510+ ldr r0, =0x1e6e0078
17511+ ldr r1, =0x00000000
17512+ str r1, [r0]
17513+
17514+ ldr r0, =0x1e6e007c
17515+ ldr r1, =0x00000000
17516+ str r1, [r0]
17517+
17518+ ldr r0, =0x1e6e0080
17519+ ldr r1, =0x00000000
17520+ str r1, [r0]
17521+
17522+ ldr r0, =0x1e6e0084
17523+ ldr r1, =0x00FFFFFF
17524+ str r1, [r0]
17525+
17526+ ldr r0, =0x1e6e0088 @ REG_DQIDLY
17527+ ldr r1, =0x00000089 @ 408 MHz
17528+#if defined(CONFIG_DRAM_336)
17529+ ldr r1, =0x00000074
17530+#endif
17531+ str r1, [r0]
17532+
17533+ ldr r0, =0x1e6e0020 @ REG_DQSIC
17534+ ldr r1, =0x000000E2 @ 408 MHz
17535+#if defined(CONFIG_DRAM_336)
17536+ ldr r1, =0x000000BA
17537+#endif
17538+ str r1, [r0]
17539+
17540+ /* Delay about 10us */
17541+ ldr r2, =0x0000000B @ Set Timer3 Reload = 10 us
17542+ init_delay_timer
17543+delay_2:
17544+ check_delay_timer
17545+ bne delay_2
17546+ clear_delay_timer
17547+ /* end delay 10us */
17548+
17549+ /* Check DRAM Type by H/W Trapping */
17550+ ldr r0, =0x1e6e2070
17551+ ldr r1, [r0]
17552+ bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2
17553+ mov r2, r1, lsr #24
17554+ cmp r2, #0x01
17555+ beq ddr2_init
17556+ b ddr3_init
17557+.LTORG
17558+
17559+/******************************************************************************
17560+ DDR3 Init
17561+
17562+ tRCD = 15 ns
17563+ tRAS = 37.5 ns
17564+ tRRD = max(4 CK,10 ns)
17565+ tRP = 15 ns
17566+ tRFC = 110ns/1Gbit, 160ns/2Gbit, 300ns/4Gbit
17567+ tRTP = max(4 CK,7.5 ns)
17568+ tWR = 15 ns
17569+ tXSNR = max(10 CK,200 ns)
17570+ tWTR = max(4 CK,7.5 ns)
17571+ tFAW = 50 ns
17572+ tMRD = max(15 CK,20 ns)
17573+ ******************************************************************************/
17574+ddr3_init:
17575+/* Debug - UART console message */
17576+ ldr r0, =0x1e784000
17577+ mov r1, #0x33 @ '3'
17578+ str r1, [r0]
17579+ mov r1, #0x0D @ '\r'
17580+ str r1, [r0]
17581+ mov r1, #0x0A @ '\n'
17582+ str r1, [r0]
17583+/* Debug - UART console message */
17584+
17585+ ldr r0, =0x1e6e0004
17586+ ldr r1, =0x00000531 @ Default set to 1Gbit
17587+ str r1, [r0]
17588+
17589+ ldr r0, =0x1e6e0010 @ REG_AC1
17590+ ldr r1, =0x33302825 @ 408 MHz
17591+#if defined(CONFIG_DRAM_336)
17592+ ldr r1, =0x22202725
17593+#endif
17594+ str r1, [r0]
17595+
17596+ /* Check DRAM CL Timing by H/W Trapping */
17597+ ldr r0, =0x1e6e2070
17598+ ldr r1, [r0]
17599+ bic r1, r1, #0xF9FFFFFF
17600+ mov r2, r1, lsr #9 @ Set CL
17601+ ldr r1, =0x00020000
17602+ add r2, r2, r1
17603+ ldr r1, [r0]
17604+ bic r1, r1, #0xFBFFFFFF
17605+ mov r1, r1, lsr #6 @ Set CWL
17606+ orr r2, r2, r1
17607+ ldr r1, =0x00300000
17608+ add r2, r2, r1
17609+
17610+ ldr r0, =0x1e6e0014 @ REG_AC2
17611+ ldr r1, =0xCC00963F @ 408 MHz
17612+#if defined(CONFIG_DRAM_336)
17613+ ldr r1, =0xAA007636
17614+#endif
17615+ orr r1, r1, r2
17616+ str r1, [r0]
17617+
17618+ ldr r0, =0x1e6e0004 @ check 2400 mode
17619+ ldr r2, [r0]
17620+ mov r2, r2, lsr #10
17621+
17622+ ldr r0, =0x1e6e006c @ REG_IOZ
17623+ ldr r1, =0x00002312 @ 408 MHz
17624+#if defined(CONFIG_DRAM_336)
17625+ ldr r1, =0x00002312
17626+#endif
17627+ tst r2, #0x01
17628+ moveq r1, r1, lsr #8
17629+ str r1, [r0]
17630+
17631+ ldr r0, =0x1e6e0120
17632+ mov r1, #0
17633+ str r1, [r0]
17634+ tst r2, #0x01 @ check AST2300
17635+ beq CBRDLL1_2300_Start
17636+ ldr r0, =0x1e6e207c @ check AST2400 revision A0
17637+ ldr r1, [r0]
17638+ mov r1, r1, lsr #16
17639+ and r1, r1, #0xFF
17640+ cmp r1, #0x0
17641+ beq CBRDLL1_2300_Start
17642+ b CBRDLL1_2400_Start
17643+MCLK2X_Phase_CBR_Done_DDR3:
17644+ ldr r0, =0x1e6e0018
17645+ ldr r1, [r0]
17646+ orr r1, r1, #0x40
17647+ str r1, [r0]
17648+
17649+ ldr r0, =0x1e6e0034
17650+ ldr r1, =0x00000001
17651+ str r1, [r0]
17652+
17653+ ldr r0, =0x1e6e000c
17654+ ldr r1, =0x00000040
17655+ str r1, [r0]
17656+
17657+ /* Delay about 400us */
17658+ ldr r2, =0x00000190 @ Set Timer3 Reload = 400 us
17659+ init_delay_timer
17660+delay3_4:
17661+ check_delay_timer
17662+ bne delay3_4
17663+ clear_delay_timer
17664+ /* end delay 400us */
17665+
17666+ /* Check DRAM CL Timing by H/W Trapping */
17667+ ldr r0, =0x1e6e2070
17668+ ldr r1, [r0]
17669+ bic r1, r1, #0xF9FFFFFF
17670+ mov r2, r1, lsr #21 @ Set CL
17671+ ldr r1, =0x00000010
17672+ add r2, r2, r1
17673+ ldr r1, [r0]
17674+ bic r1, r1, #0xFBFFFFFF
17675+ mov r1, r1, lsr #7 @ Set CWL
17676+ orr r2, r2, r1
17677+
17678+ ldr r0, =0x1e6e002c @ REG_MRS
17679+ ldr r1, =0x04001700 @ 408 MHz
17680+#if defined(CONFIG_DRAM_336)
17681+ ldr r1, =0x04001500
17682+#endif
17683+ orr r1, r1, r2
17684+ str r1, [r0]
17685+
17686+ ldr r0, =0x1e6e0030 @ REG_EMRS
17687+ ldr r1, =0x00000000 @ 408 MHz
17688+#if defined(CONFIG_DRAM_336)
17689+ ldr r1, =0x00000000
17690+#endif
17691+ str r1, [r0]
17692+
17693+ ldr r0, =0x1e6e0028 @ Set EMRS2
17694+ ldr r1, =0x00000005
17695+ str r1, [r0]
17696+
17697+ ldr r0, =0x1e6e0028 @ Set EMRS3
17698+ ldr r1, =0x00000007
17699+ str r1, [r0]
17700+
17701+ ldr r0, =0x1e6e0028 @ Set EMRS
17702+ ldr r1, =0x00000003
17703+ str r1, [r0]
17704+
17705+ ldr r0, =0x1e6e0028 @ Set MRS
17706+ ldr r1, =0x00000001
17707+ str r1, [r0]
17708+
17709+ ldr r0, =0x1e6e002c @ REG_MRS
17710+ ldr r1, =0x04001600 @ 408 MHz
17711+#if defined(CONFIG_DRAM_336)
17712+ ldr r1, =0x04001400
17713+#endif
17714+ orr r1, r1, r2
17715+ str r1, [r0]
17716+
17717+ ldr r0, =0x1e6e000c @ Refresh 8 times
17718+ ldr r1, =0x00005C48
17719+ str r1, [r0]
17720+
17721+ ldr r0, =0x1e6e0028 @ Set MRS
17722+ ldr r1, =0x00000001
17723+ str r1, [r0]
17724+
17725+ ldr r0, =0x1e6e000c @ Set refresh cycle
17726+ ldr r1, =0x00002001
17727+ str r1, [r0]
17728+
17729+ ldr r0, =0x1e6e0014
17730+ ldr r1, [r0]
17731+ bic r1, r1, #0xFFF9FFFF
17732+ mov r2, r1, lsr #3 @ get CL
17733+
17734+ ldr r0, =0x1e6e0034 @ REG_PWC
17735+ ldr r1, =0x00000303 @ 408 MHz
17736+#if defined(CONFIG_DRAM_336)
17737+ ldr r1, =0x00000303
17738+#endif
17739+ orr r1, r1, r2
17740+ str r1, [r0]
17741+
17742+ b Calibration_Start
17743+.LTORG
17744+/******************************************************************************
17745+ End DDR3 Init
17746+ ******************************************************************************/
17747+
17748+/******************************************************************************
17749+ DDR2 Init
17750+
17751+ tRCD = 15 ns
17752+ tRAS = 45 ns
17753+ tRRD = 10 ns
17754+ tRP = 15 ns
17755+ tRFC = 105ns/512Mbit, 127.5ns/1Gbit, 197.5ns/2Gbit, 327.5ns/4Gbit
17756+ tRTP = 7.5 ns
17757+ tWR = 15 ns
17758+ tXSNR = 200 ns
17759+ tWTR = 7.5 ns
17760+ tFAW = 50 ns
17761+ tMRD = 4 CK
17762+ ******************************************************************************/
17763+ddr2_init:
17764+/* Debug - UART console message */
17765+ ldr r0, =0x1e784000
17766+ mov r1, #0x32 @ '2'
17767+ str r1, [r0]
17768+ mov r1, #0x0D @ '\r'
17769+ str r1, [r0]
17770+ mov r1, #0x0A @ '\n'
17771+ str r1, [r0]
17772+/* Debug - UART console message */
17773+
17774+ ldr r0, =0x1e6e0004
17775+ ldr r1, =0x00000510 @ Default set to 512Mbit
17776+ str r1, [r0]
17777+
17778+ ldr r0, =0x1e6e0010 @ REG_AC1
17779+ ldr r1, =0x33302714 @ 408 MHz
17780+#if defined(CONFIG_DRAM_336)
17781+ ldr r1, =0x22201613
17782+#endif
17783+ str r1, [r0]
17784+
17785+ /* Check DRAM CL Timing by H/W Trapping */
17786+ ldr r0, =0x1e6e2070
17787+ ldr r1, [r0]
17788+ bic r1, r1, #0xF9FFFFFF
17789+ mov r2, r1, lsr #5 @ Set CL
17790+ mov r1, r2, lsr #4 @ Set CWL
17791+ orr r2, r2, r1
17792+ ldr r1, =0x00110000
17793+ add r2, r2, r1
17794+
17795+ ldr r0, =0x1e6e0014 @ REG_AC2
17796+ ldr r1, =0xCC00B03F @ 408 MHz
17797+#if defined(CONFIG_DRAM_336)
17798+ ldr r1, =0xAA00903B
17799+#endif
17800+ orr r1, r1, r2
17801+ str r1, [r0]
17802+
17803+ ldr r0, =0x1e6e0004 @ check 2400 mode
17804+ ldr r2, [r0]
17805+ mov r2, r2, lsr #10
17806+
17807+ ldr r0, =0x1e6e006c @ REG_IOZ
17808+ ldr r1, =0x00002312 @ 408 MHz
17809+#if defined(CONFIG_DRAM_336)
17810+ ldr r1, =0x00002312
17811+#endif
17812+ tst r2, #0x01
17813+ moveq r1, r1, lsr #8
17814+ str r1, [r0]
17815+
17816+ ldr r0, =0x1e6e0120
17817+ mov r1, #1
17818+ str r1, [r0]
17819+ tst r2, #0x01 @ check AST2300
17820+ beq CBRDLL1_2300_Start
17821+ ldr r0, =0x1e6e207c @ check AST2400 revision A0
17822+ ldr r1, [r0]
17823+ mov r1, r1, lsr #16
17824+ and r1, r1, #0xFF
17825+ cmp r1, #0x0
17826+ beq CBRDLL1_2300_Start
17827+ b CBRDLL1_2400_Start
17828+MCLK2X_Phase_CBR_Done_DDR2:
17829+
17830+ ldr r0, =0x1e6e0034
17831+ ldr r1, =0x00000001
17832+ str r1, [r0]
17833+
17834+ ldr r0, =0x1e6e000c
17835+ ldr r1, =0x00000000
17836+ str r1, [r0]
17837+
17838+ /* Delay about 400us */
17839+ ldr r2, =0x00000190 @ Set Timer3 Reload = 400 us
17840+ init_delay_timer
17841+delay2_4:
17842+ check_delay_timer
17843+ bne delay2_4
17844+ clear_delay_timer
17845+ /* end delay 400us */
17846+
17847+ /* Check DRAM CL Timing by H/W Trapping */
17848+ ldr r0, =0x1e6e2070
17849+ ldr r1, [r0]
17850+ bic r1, r1, #0xF9FFFFFF
17851+ mov r2, r1, lsr #21 @ Set CL
17852+ ldr r1, =0x00000040
17853+ orr r2, r2, r1
17854+
17855+ ldr r0, =0x1e6e002c @ REG_MRS
17856+ ldr r1, =0x00000D03 @ 408 MHz
17857+#if defined(CONFIG_DRAM_336)
17858+ ldr r1, =0x00000B03
17859+#endif
17860+ orr r1, r1, r2
17861+ str r1, [r0]
17862+
17863+ ldr r0, =0x1e6e0030 @ REG_EMRS
17864+ ldr r1, =0x00000040 @ 408 MHz
17865+#if defined(CONFIG_DRAM_336)
17866+ ldr r1, =0x00000040
17867+#endif
17868+ str r1, [r0]
17869+
17870+ ldr r0, =0x1e6e0028 @ Set EMRS2
17871+ ldr r1, =0x00000005
17872+ str r1, [r0]
17873+
17874+ ldr r0, =0x1e6e0028 @ Set EMRS3
17875+ ldr r1, =0x00000007
17876+ str r1, [r0]
17877+
17878+ ldr r0, =0x1e6e0028 @ Set EMRS
17879+ ldr r1, =0x00000003
17880+ str r1, [r0]
17881+
17882+ ldr r0, =0x1e6e0028 @ Set MRS
17883+ ldr r1, =0x00000001
17884+ str r1, [r0]
17885+
17886+ ldr r0, =0x1e6e000c @ Refresh 8 times
17887+ ldr r1, =0x00005C08
17888+ str r1, [r0]
17889+
17890+ ldr r0, =0x1e6e002c @ REG_MRS
17891+ ldr r1, =0x00000C03 @ 408 MHz
17892+#if defined(CONFIG_DRAM_336)
17893+ ldr r1, =0x00000A03
17894+#endif
17895+ orr r1, r1, r2
17896+ str r1, [r0]
17897+
17898+ ldr r0, =0x1e6e0028 @ Set MRS
17899+ ldr r1, =0x00000001
17900+ str r1, [r0]
17901+
17902+ ldr r0, =0x1e6e0030 @ REG_EMRS
17903+ ldr r1, =0x000003C0 @ 408 MHz
17904+#if defined(CONFIG_DRAM_336)
17905+ ldr r1, =0x000003C0
17906+#endif
17907+ str r1, [r0]
17908+
17909+ ldr r0, =0x1e6e0028 @ Set EMRS
17910+ ldr r1, =0x00000003
17911+ str r1, [r0]
17912+
17913+ ldr r0, =0x1e6e0030 @ REG_EMRS
17914+ ldr r1, =0x00000040 @ 408 MHz
17915+#if defined(CONFIG_DRAM_336)
17916+ ldr r1, =0x00000040
17917+#endif
17918+ str r1, [r0]
17919+
17920+ ldr r0, =0x1e6e0028 @ Set EMRS
17921+ ldr r1, =0x00000003
17922+ str r1, [r0]
17923+
17924+ ldr r0, =0x1e6e000c @ Set refresh cycle
17925+ ldr r1, =0x00002001
17926+ str r1, [r0]
17927+
17928+ ldr r0, =0x1e6e0014
17929+ ldr r1, [r0]
17930+ bic r1, r1, #0xFFF9FFFF
17931+ mov r2, r1, lsr #3 @ get CL
17932+
17933+ ldr r0, =0x1e6e0034 @ REG_PWC
17934+ ldr r1, =0x00000503 @ 408 MHz
17935+#if defined(CONFIG_DRAM_336)
17936+ ldr r1, =0x00000503
17937+#endif
17938+ orr r1, r1, r2
17939+ str r1, [r0]
17940+
17941+ b Calibration_Start
17942+.LTORG
17943+/******************************************************************************
17944+ End DDR2 Init
17945+ ******************************************************************************/
17946+/******************************************************************************
17947+ DDR CK duty finetune program
17948+ SRAM buffer definition
17949+ 0x1E720204 : gdll golden DLL1 record
17950+ 0x1E720208 : gduty golden duty setting record
17951+ 0x1E72020C : gdutysum golden duty data record
17952+ 0x1E720210 : duty record of delay 0 invert
17953+ 0x1E720214 : duty record of delay 1 invert
17954+ ....
17955+ 0x1E72024C : duty record of delay 15 invert
17956+ 0x1E720250 : duty record of delay 0
17957+ 0x1E720254 : duty record of delay 1
17958+ ....
17959+ 0x1E72028C : duty record of delay 15
17960+
17961+ Register usage
17962+ r0 - r3 = free
17963+ r4 = record the return pc value, do not use
17964+ r5 = free
17965+ r6 = free
17966+ r7 = duty count
17967+ r8 = gdll
17968+ r9 = gduty
17969+ r10 = gdutysum
17970+ ******************************************************************************/
17971+CBRDLL1_2400_Start:
17972+ ldr r0, =0x1e6e0120
17973+ ldr r1, [r0]
17974+ orr r1, r1, #0x02
17975+ str r1, [r0]
17976+
17977+ ldr r1, =0x00000000
17978+ ldr r0, =0x1e720204
17979+ ldr r2, =0x1e7202a0
17980+init_sram_start0:
17981+ str r1, [r0]
17982+ add r0, r0, #4
17983+ cmp r0, r2
17984+ blt init_sram_start0
17985+
17986+ ldr r0, =0x1e6e0034
17987+ mov r1, #0x20
17988+ str r1, [r0]
17989+
17990+ ldr r0, =0x1e6e0060
17991+ ldr r1, [r0]
17992+ mov r2, #0x01
17993+ orr r1, r1, r2, lsl #13
17994+ str r1, [r0]
17995+
17996+ mov r7, #0x0 @ init duty count
17997+ mov r8, #0x0 @ init gdll
17998+ mov r9, #0x0 @ init gduty
17999+ mov r10, #0x0 @ init gdutysum
18000+cbrdll1_duty_start:
18001+ cmp r7, #32
18002+ bge cbrdll1_duty_end
18003+
18004+ ldr r0, =0x1e6e0018
18005+ ldr r1, =0x00008120
18006+ str r1, [r0]
18007+
18008+ ldr r0, =0x1e6e0060
18009+ ldr r1, [r0]
18010+ bic r1, r1, #0x00001F00
18011+ orr r1, r1, r7, lsl #8
18012+ mov r2, #0x10
18013+ eor r1, r1, r2, lsl #8
18014+ str r1, [r0]
18015+
18016+ ldr r0, =0x1e6e0000 @ dummy read
18017+ ldr r1, [r0]
18018+
18019+ b CBRDLL1_2300_Start
18020+CBRDLL1_2400_Call:
18021+
18022+ mov r5, #0x01 @ init dqidly count
18023+ mov r6, #0x00 @ init duty sum
18024+cbrdll1_duty_cal_start:
18025+ cmp r5, #0x05
18026+ bge cbrdll1_duty_cal_end
18027+
18028+ ldr r0, =0x1e6e0018
18029+ ldr r1, =0x00200120
18030+ orr r1, r1, r5, lsl #16
18031+ str r1, [r0]
18032+
18033+ ldr r0, =0x1e6e0000
18034+ ldr r1, [r0]
18035+
18036+ ldr r0, =0x1e6e0018
18037+ ldr r1, [r0]
18038+ mov r2, #0x10
18039+ orr r1, r1, r2, lsl #24
18040+ str r1, [r0]
18041+
18042+ ldr r0, =0x1e6e0080
18043+ ldr r1, =0x80000000 @ init duty cal waiting
18044+cbrdll1_duty_cal_wait:
18045+ ldr r2, [r0]
18046+ tst r2, r1
18047+ beq cbrdll1_duty_cal_wait
18048+
18049+ ldr r0, =0x1e6e008c
18050+ ldr r2, [r0]
18051+
18052+ ldr r0, =0x1e720210
18053+ add r0, r0, r7, lsl #2
18054+ str r2, [r0]
18055+
18056+ ldr r1, =0xFFFF
18057+ and r3, r1, r2
18058+ cmp r3, r1
18059+ moveq r2, r2, lsr #16
18060+ and r3, r1, r2
18061+ add r6, r6, r3
18062+ ldr r1, =0xF000
18063+ cmp r3, r1
18064+ blt cbrdll1_duty_cal_end
18065+ add r5, r5, #0x01
18066+ b cbrdll1_duty_cal_start
18067+
18068+cbrdll1_duty_cal_end:
18069+ mov r6, r6, lsr #2 @ get dutysum
18070+ cmp r6, r10 @ check dutysum > gdutysum
18071+ ble cbrdll1_duty_next
18072+ ldr r0, =0x1e6e0068
18073+ ldr r8, [r0]
18074+ eor r9, r7, #0x10
18075+ mov r10, r6
18076+
18077+cbrdll1_duty_next:
18078+ add r7, r7, #0x01
18079+ cmp r7, #16 @ check duty >= 15
18080+ blt cbrdll1_duty_start
18081+ ldr r0, =0xFA00 @ check gdutysum > 0xFA00
18082+ cmp r10, r0
18083+ blt cbrdll1_duty_start
18084+
18085+cbrdll1_duty_end:
18086+ ldr r0, =0x1e6e0060
18087+ ldr r1, [r0]
18088+ bic r1, r1, #0x00001F00
18089+ orr r1, r1, r9, lsl #8
18090+ str r1, [r0]
18091+
18092+ ldr r0, =0x1e6e0068
18093+ bic r8, r8, #0xFF000000
18094+ bic r8, r8, #0x00FF0000
18095+ str r8, [r0]
18096+
18097+ ldr r0, =0x1e720204 @ record result
18098+ str r8, [r0]
18099+ add r0, r0, #0x04
18100+ str r9, [r0]
18101+ add r0, r0, #0x04
18102+ str r10, [r0]
18103+
18104+ ldr r0, =0x1e6e0018
18105+ ldr r1, =0x00008120
18106+ str r1, [r0]
18107+ ldr r0, =0x1e6e0000 @ dummy read
18108+ ldr r1, [r0]
18109+ ldr r0, =0x1e6e0018
18110+ ldr r1, =0x00000120
18111+ str r1, [r0]
18112+
18113+ ldr r0, =0x1e6e0120
18114+ ldr r1, [r0]
18115+ cmp r1, #0x3
18116+ beq MCLK2X_Phase_CBR_Done_DDR2
18117+ b MCLK2X_Phase_CBR_Done_DDR3
18118+
18119+/******************************************************************************
18120+ MCLK2X lock to MCLK program
18121+ r0 - r3 = free
18122+ r5 = madjmax
18123+ r6 = dllend
18124+ 0x1E720200 = 0x96cnt:failcnt:dllmax:dllmin
18125+ ******************************************************************************/
18126+CBRDLL1_2300_Start:
18127+ ldr r0, =0x1e6e0064
18128+ ldr r5, [r0]
18129+ and r5, r5, #0xFF @ init madjmax
18130+ mov r6, r5 @ init dllend
18131+
18132+ ldr r1, =0x000000ff
18133+ ldr r0, =0x1e720200
18134+ str r1, [r0] @ init dllcnt2:dllmax:dllmin
18135+
18136+ mov r3, #0x0 @ init loop count
18137+cbrdll1_scan_start:
18138+ cmp r3, r6
18139+ bge cbrdll1_scan_end
18140+
18141+ ldr r0, =0x1e6e0018
18142+ ldr r1, =0x00008120
18143+ str r1, [r0]
18144+
18145+ ldr r0, =0x1e6e0068
18146+ mov r1, r3
18147+ cmp r1, r5
18148+ subge r1, r1, r5
18149+ str r1, [r0]
18150+
18151+ ldr r0, =0x1e6e0000 @ dummy read
18152+ ldr r1, [r0]
18153+
18154+ ldr r0, =0x1e6e0018
18155+ ldr r1, =0x00000120
18156+ str r1, [r0]
18157+
18158+ ldr r0, =0x1e6e0000 @ dummy read
18159+ ldr r1, [r0]
18160+ ldr r0, =0x1e6e0000 @ dummy read
18161+ ldr r1, [r0]
18162+
18163+ ldr r0, =0x1e6e001c
18164+ ldr r1, [r0]
18165+ mov r1, r1, lsr #16
18166+ and r1, r1, #0xFF
18167+
18168+ and r2, r1, #0x96
18169+ cmp r2, #0x96
18170+ beq cbrdll1_scan_pass @ if (mclk2x_phase & 0x96) == 0x96
18171+ ldr r0, =0x1e720200
18172+ ldr r1, [r0]
18173+ mov r2, r1, lsr #8
18174+ ands r2, r2, #0xFF @ get dllmax
18175+ beq cbrdll1_scan_next @ if dllmax == 0
18176+ mov r2, r1, lsr #16
18177+ and r2, r2, #0xFF
18178+ add r2, r2, #0x01
18179+ cmp r2, #0x02
18180+ movge r6, r3
18181+ bic r1, r1, #0x00FF0000
18182+ orr r1, r1, r2, lsl #16
18183+ str r1, [r0]
18184+ b cbrdll1_scan_next
18185+
18186+cbrdll1_scan_pass:
18187+ cmp r3, #0x0 @ if dll = 0
18188+ moveq r3, #0x0F
18189+ addeq r6, r6, #0x10
18190+ beq cbrdll1_scan_next
18191+ ldr r0, =0x1e720200
18192+ ldr r2, [r0]
18193+ cmp r1, #0x96
18194+ bne cbrdll1_scan_pass2
18195+ mov r1, r2, lsr #24
18196+ add r1, r1, #0x01
18197+ bic r2, r2, #0xFF000000
18198+ orr r2, r2, r1, lsl #24
18199+ cmp r1, #0x03 @ check (phase == 0x96) count == 3
18200+ bicge r2, r2, #0x0000FF00
18201+ bicge r2, r2, #0x000000FF
18202+ orrge r2, r2, r3, lsl #8
18203+ orrge r2, r2, r3
18204+ str r2, [r0]
18205+ bge cbrdll1_scan_end
18206+
18207+cbrdll1_scan_pass2:
18208+ and r1, r2, #0xFF @ if(dllmin > dll)
18209+ cmp r1, r3
18210+ bicgt r2, r2, #0x000000FF
18211+ orrgt r2, r2, r3
18212+
18213+ mov r1, r2, lsr #8 @ if(dllmax < dll)
18214+ and r1, r1, #0xFF
18215+ cmp r1, r3
18216+ biclt r2, r2, #0x0000FF00
18217+ orrlt r2, r2, r3, lsl #8
18218+
18219+ bic r2, r2, #0x00FF0000
18220+ str r2, [r0]
18221+
18222+cbrdll1_scan_next:
18223+ add r3, r3, #0x01
18224+ b cbrdll1_scan_start
18225+
18226+cbrdll1_scan_end:
18227+ ldr r0, =0x1e720200
18228+ ldr r1, [r0]
18229+ mov r2, r1, lsr #8 @ get dllmax
18230+ ands r2, r2, #0xFF
18231+ bne cbrdll1_scan_done @ if(dllmax != 0)
18232+ ldr r0, =0x1e6e0064
18233+ ldr r3, [r0]
18234+ bic r1, r3, #0x000C0000
18235+ str r1, [r0]
18236+ add r0, r0, #0x04
18237+ mov r1, #0x0
18238+ str r1, [r0]
18239+
18240+ /* Delay about 10us */
18241+ ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us
18242+ init_delay_timer
18243+delay0_1:
18244+ check_delay_timer
18245+ bne delay0_1
18246+ clear_delay_timer
18247+ /* end delay 10us */
18248+
18249+ ldr r0, =0x1e6e0064
18250+ str r3, [r0]
18251+
18252+ /* Delay about 10us */
18253+ ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us
18254+ init_delay_timer
18255+delay0_2:
18256+ check_delay_timer
18257+ bne delay0_2
18258+ clear_delay_timer
18259+ /* end delay 10us */
18260+
18261+ b CBRDLL1_2300_Start
18262+
18263+cbrdll1_scan_done:
18264+ and r1, r1, #0xFF
18265+ add r1, r1, r2
18266+ mov r6, r1, lsr #1 @ dll1.0 = (dllmin + dllmax) >> 1
18267+ cmp r6, r5
18268+ subge r6, r6, r5
18269+ add r3, r6, r5, lsr #2 @ dll1.1 = dll1.0 + (MADJ >> 2)
18270+
18271+ ldr r0, =0x1e6e0004
18272+ ldr r1, [r0]
18273+ mov r1, r1, lsr #10
18274+ tst r1, #0x1
18275+ bne cbrdll1_scan_set_2400
18276+ cmp r3, r5
18277+ subge r3, r3, r5
18278+ mov r2, #0x0
18279+ tst r3, #0x08
18280+ beq cbrdll1_scan_set_2300_2 @ if !(dll & 8)
18281+cbrdll1_scan_set_2300_1: @ if (dll & 8)
18282+ mov r1, #0x0
18283+ tst r3, #0x08
18284+ addeq r1, r1, #0x01
18285+ cmp r2, #0x05
18286+ addge r1, r1, #0x01
18287+ cmp r1, #0x02
18288+ beq cbrdll1_scan_set
18289+ add r2, r2, #0x01
18290+ add r3, r3, #0x01
18291+ cmp r3, r5
18292+ subge r3, r3, r5
18293+ b cbrdll1_scan_set_2300_1
18294+
18295+cbrdll1_scan_set_2300_2:
18296+ and r1, r3, #0x07
18297+ cmp r1, #0x07
18298+ beq cbrdll1_scan_set
18299+ cmp r2, #0x05
18300+ bge cbrdll1_scan_set
18301+ add r2, r2, #0x01
18302+ add r3, r3, #0x01
18303+ cmp r3, r5
18304+ subge r3, r3, r5
18305+ b cbrdll1_scan_set_2300_2
18306+
18307+cbrdll1_scan_set_2400:
18308+ add r3, r3, #0x05 @ dll1.1 = dll1.0 + (MADJ >> 2) + 5
18309+ cmp r3, r5
18310+ subge r3, r3, r5
18311+
18312+cbrdll1_scan_set:
18313+ orr r1, r6, r3, lsl #8
18314+ ldr r0, =0x1e6e0068
18315+ str r1, [r0]
18316+
18317+ ldr r0, =0x1e6e0120
18318+ ldr r1, [r0]
18319+ cmp r1, #0x0
18320+ beq MCLK2X_Phase_CBR_Done_DDR3
18321+ cmp r1, #0x1
18322+ beq MCLK2X_Phase_CBR_Done_DDR2
18323+ b CBRDLL1_2400_Call
18324+
18325+.LTORG
18326+
18327+/******************************************************************************
18328+ Calibration Code Start
18329+ SRAM buffer definition
18330+ 0x1E720000 : Pass 1, DLLI MIN value range
18331+ 0x1E720008 : DQS0 DLL valid range, 2nd time CBR
18332+ 0x1E72000C : DQS1 DLL valid range, 2nd time CBR
18333+ 0x1E720010 : DQ0 DLL valid range, Pass 1
18334+ 0x1E720014 : DQ1 DLL valid range, Pass 1
18335+ ....
18336+ 0x1E720048 : DQ14 DLL valid range, Pass 1
18337+ 0x1E72004C : DQ15 DLL valid range, Pass 1
18338+ 0x1E720090 : DLL1 SAdj record
18339+ 0x1E720094 : DQL Pass1 finetune result
18340+ 0x1E720098 : DQH Pass1 finetune result
18341+ 0x1E72009C : DRAM initial time, (us)
18342+ 0x1E7200A0 : CBR3 retry counter
18343+ 0x1E7200A4 : DRAM initial time, (us)
18344+ 0x1E7200A8 : Released date
18345+ 0x1E7200AC : Released SDK version
18346+ 0x1E7200B0 : DQS input mask window for MCR18[4] = 0
18347+ 0x1E7200B4 : DQS input mask window for MCR18[4] = 1
18348+ 0x1E720100 : DQIDLY=00, DLL valid range
18349+ 0x1E720104 : DQIDLY=01, DLL valid range
18350+ ....
18351+ 0x1E720178 : DQIDLY=30, DLL valid range
18352+ 0x1E72017C : DQIDLY=31, DLL valid range
18353+ 0x1E720180 : DQSI-MCLK2X P-phase pass record DLL2= 0-31
18354+ 0x1E720184 : DQSI-MCLK2X P-phase pass record DLL2=32-63
18355+ 0x1E720188 : DQSI-MCLK2X N-phase pass record DLL2= 0-31
18356+ 0x1E72018C : DQSI-MCLK2X N-phase pass record DLL2=32-63
18357+ ******************************************************************************/
18358+Calibration_Start_pre: @ Toggle DQSI mask delay
18359+ ldr r0, =0x1e6e0018
18360+ ldr r1, [r0]
18361+ eor r1, r1, #0x10
18362+ str r1, [r0]
18363+
18364+Calibration_Start:
18365+/* Init SRAM buffer */
18366+ ldr r1, =0x000000ff
18367+ ldr r0, =0x1e720000
18368+ ldr r2, =0x1e720100
18369+init_sram_start:
18370+ str r1, [r0]
18371+ add r0, r0, #4
18372+ cmp r0, r2
18373+ blt init_sram_start
18374+
18375+ ldr r1, =0x00ff00ff
18376+ ldr r0, =0x1e720100
18377+ ldr r2, =0x1e720180
18378+init_sram_start2:
18379+ str r1, [r0]
18380+ add r0, r0, #4
18381+ cmp r0, r2
18382+ blt init_sram_start2
18383+
18384+ ldr r1, =0x00000000
18385+ ldr r0, =0x1e720180
18386+ ldr r2, =0x1e720200
18387+init_sram_start3:
18388+ str r1, [r0]
18389+ add r0, r0, #4
18390+ cmp r0, r2
18391+ blt init_sram_start3
18392+
18393+ ldr r0, =0x1e6e0068 @ save the DLL1 SAdj initial value
18394+ ldr r1, [r0]
18395+ ldr r0, =0x1e720090
18396+ str r1, [r0]
18397+
18398+/* Start
18399+ r0 = free
18400+ r1 = free
18401+ r2 = free
18402+ r3 = free
18403+ r4 = record the return pc value, do not use
18404+ r5 = pattern table index
18405+ r6 = pass count
18406+ r7 = dram DLL2 parameter index (0x1e6e0068), max is 0x4C
18407+*/
18408+/******************************************************************************
18409+ Fine DQI delay and DQSI-MCLK phase
18410+ r8 = DQIDLY count
18411+ r9 = DQSI-MCLK2X phase count
18412+ r10 = pattern fail retry counter, initialize to 2 (fail 2 times)
18413+ r11 = passcnt accumulator for each DQIDLY
18414+ *****************************************************************************/
18415+CBR0_START:
18416+/* Debug - UART console message */
18417+ ldr r0, =0x1e784000
18418+ mov r1, #0x43 @ 'C'
18419+ str r1, [r0]
18420+ mov r1, #0x42 @ 'B'
18421+ str r1, [r0]
18422+ mov r1, #0x52 @ 'R'
18423+ str r1, [r0]
18424+ mov r1, #0x30 @ '0'
18425+ str r1, [r0]
18426+ mov r1, #0x2D @ '-'
18427+ str r1, [r0]
18428+/* Debug - UART console message */
18429+
18430+ ldr r0, =0x1e6e0018
18431+ ldr r1, [r0]
18432+ bic r1, r1, #0xFF000000
18433+ bic r1, r1, #0x00FF0000
18434+ str r1, [r0]
18435+
18436+ ldr r0, =0x1e6e0074 @ set the testing DRAM size = 1KB
18437+ ldr r1, =0x000003FF
18438+ str r1, [r0]
18439+
18440+ mov r8, #0x00 @ init DQIDLY
18441+ mov r9, #0x00 @ init DQSI-MCLK2X phase
18442+ mov r11, #0x01 @ init passcnt accumulator
18443+
18444+cbr0_next_dqidly:
18445+ cmp r9, #0x00
18446+ bne cbr0_next_dqsiphase
18447+ cmp r11, #0x00
18448+ addeq r8, r8, #0x01 @ jump 1 stage if no pass at previous stage
18449+ mov r11, #0x00
18450+ add r8, r8, #0x01
18451+ cmp r8, #0x1F @ max DQIDLY = 31
18452+ bgt CBR0_END
18453+
18454+/* Debug - UART console message */
18455+ ldr r0, =0x1e784000
18456+ and r1, r8, #0x07
18457+ add r1, r1, #0x30 @ '0-7'
18458+ str r1, [r0]
18459+/* Debug - UART console message */
18460+
18461+ ldr r0, =0x1e6e0018
18462+ ldr r1, [r0]
18463+ bic r1, r1, #0x00FF0000
18464+ orr r1, r1, r8, lsl #16
18465+ str r1, [r0]
18466+ mov r9, #0x01 @ '1':p_phase, '0':n_phase
18467+
18468+ /* Delay about 3us */ @ wait DQIDLY load
18469+ ldr r2, =0x00000003 @ Set Timer4 Reload = 3 us
18470+ init_delay_timer
18471+delay_4:
18472+ check_delay_timer
18473+ bne delay_4
18474+ clear_delay_timer
18475+ /* end delay 3us */
18476+
18477+ b cbr0_dll2_scan_start
18478+
18479+cbr0_next_dqsiphase:
18480+ ldr r0, =0x1e6e0018
18481+ ldr r1, [r0]
18482+ orr r1, r1, r9, lsl #23 @ set DQSI-MCLK2X phase
18483+ str r1, [r0]
18484+ mov r9, #0x00
18485+
18486+cbr0_dll2_scan_start:
18487+ mov r6, #0x00 @ init pass count
18488+ mov r7, #0x00 @ init DLL2 parameter index
18489+
18490+/****************************
18491+ DLL2 delay margin test loop
18492+ ***************************/
18493+cbr0_next_dll2_parameter:
18494+ ldr r0, =0x1e6e0068 @ load DLL2 parameter
18495+ ldr r1, [r0]
18496+ bic r1, r1, #0x00FF0000
18497+ bic r1, r1, #0xFF000000
18498+ orr r1, r1, r7, lsl #16
18499+ str r1, [r0]
18500+ ldr r2, =0x40404040 @ DLL2 max is 0x40404040
18501+ cmp r7, r2
18502+ bge cbr0_next_dqidly
18503+ ldr r2, =0x01010101
18504+ add r7, r7, r2
18505+
18506+/* CBRScan3() start */
18507+ adrl r5, PATTERN_TABLE @ init pattern table index
18508+/****************************
18509+ Test pattern iteration loop
18510+ ***************************/
18511+cbr0_next_test_pattern:
18512+ mov r10, #2 @ set the retry loop = 2 of each pattern
18513+ ldr r1, [r5] @ load test pattern
18514+ ldr r0, =0x1e6e007c
18515+ str r1, [r0]
18516+ cmp r1, #0x00 @ the last data in pattern is 0x00
18517+ bne cbr0_test_burst
18518+
18519+ and r3, r7, #0xFF
18520+ sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1
18521+ cmp r3, #0x00
18522+ beq cbr0_next_dqidly @ pass at dlli = 0, invalid
18523+ add r6, r6, #0x01 @ increment pass count
18524+ add r11, r11, #0x01 @ increment pass count
18525+
18526+ ldr r0, =0x1e720180 @ record DLL2 pass window
18527+ cmp r9, #0x00 @ DQSI-MCLK2X phase check
18528+ addeq r0, r0, #0x08
18529+ cmp r3, #32
18530+ addge r0, r0, #0x4
18531+ and r1, r3, #0x1F
18532+ mov r2, #0x1
18533+ mov r2, r2, lsl r1
18534+ ldr r1, [r0]
18535+ orr r1, r1, r2
18536+ str r1, [r0]
18537+
18538+ ldr r0, =0x1e720100 @ record DLL2 min:max value for each DQIDLY
18539+ add r0, r0, r8, lsl #2
18540+ cmp r9, #0x00 @ DQSI-MCLK2X phase check
18541+ beq cbr0_test_pass_dqsin
18542+ record_dll2_pass_range
18543+ b cbr0_next_dll2_parameter
18544+
18545+cbr0_test_pass_dqsin:
18546+ record_dll2_pass_range_h
18547+ b cbr0_next_dll2_parameter
18548+
18549+cbr0_test_pattern_fail:
18550+ cmp r6, #5 @ passcnt >= 5
18551+ bge cbr0_next_dqidly
18552+ ldr r0, =0x1e720100 @ reset DLL2 min:max value
18553+ add r0, r0, r8, lsl #2
18554+ ldr r1, [r0]
18555+ ldr r2, =0xFFFF0000
18556+ ldr r3, =0x000000FF
18557+ cmp r9, #0x00
18558+ moveq r2, r2, lsr #16
18559+ moveq r3, r3, lsl #16
18560+ and r1, r1, r2
18561+ orr r1, r1, r3
18562+ str r1, [r0]
18563+ b cbr0_next_dll2_parameter @ CBRScan3() end and test result fail, go to next step
18564+
18565+/****************************
18566+ Test fail retry loop
18567+ ***************************/
18568+cbr0_pattern_fail_retry:
18569+
18570+/* CBRTest3() start */
18571+cbr0_test_burst:
18572+ ldr r0, =0x1e6e0070
18573+ ldr r1, =0x00000000
18574+ str r1, [r0]
18575+ ldr r1, =0x000000C1
18576+ str r1, [r0]
18577+ ldr r3, =0x3000
18578+cbr0_wait_engine_idle_0:
18579+ ldr r2, [r0]
18580+ tst r2, r3 @ D[12] = idle bit
18581+ beq cbr0_wait_engine_idle_0
18582+
18583+ ldr r2, [r0] @ read fail bit status
18584+ mov r1, #0x0
18585+ str r1, [r0]
18586+ mov r2, r2, lsr #13 @ D[13] = fail bit
18587+ cmp r2, #0x00
18588+ bne cbr0_test_fail
18589+
18590+cbr0_test_single:
18591+ ldr r0, =0x1e6e0070
18592+ ldr r1, =0x00000000
18593+ str r1, [r0]
18594+ ldr r1, =0x00000085
18595+ str r1, [r0]
18596+ ldr r3, =0x3000
18597+cbr0_wait_engine_idle_1:
18598+ ldr r2, [r0]
18599+ tst r2, r3 @ D[12] = idle bit
18600+ beq cbr0_wait_engine_idle_1
18601+
18602+ ldr r2, [r0] @ read fail bit status
18603+ mov r1, #0x0
18604+ str r1, [r0]
18605+ mov r2, r2, lsr #13 @ D[13] = fail bit
18606+ cmp r2, #0x00
18607+ beq cbr0_test_pass
18608+
18609+/* CBRTest3() end */
18610+
18611+cbr0_test_fail:
18612+ subs r10, r10, #1
18613+ bne cbr0_pattern_fail_retry
18614+ b cbr0_test_pattern_fail @ CBRScan3() return(0)
18615+
18616+cbr0_test_pass:
18617+ add r5, r5, #0x04 @ increase the test pattern index
18618+ b cbr0_next_test_pattern
18619+
18620+CBR0_END:
18621+ mov r5, #0x0 @ init DQIDLY search count
18622+ mov r6, #0x0 @ init max_margin:g_margin
18623+ mov r8, #0x0 @ init g_side
18624+ mov r7, #0x0 @ init maximum margin DQIDLY,DQSI-MCLK2X phase
18625+cbr0_search_dll_margin_s:
18626+ ldr r0, =0x1e720100
18627+ add r0, r0, r5, lsl #2
18628+ ldr r1, [r0]
18629+ and r2, r1, #0xFF @ get dllmin_p
18630+ mov r1, r1, lsr #8
18631+ and r3, r1, #0xFF @ get dllmax_p
18632+ subs r2, r3, r2 @ get margin-P
18633+ movmi r2, #0x0
18634+ mov r1, r1, lsr #8
18635+ and r3, r1, #0xFF @ get dllmin_n
18636+ mov r1, r1, lsr #8
18637+ and r1, r1, #0xFF @ get dllmax_n
18638+ subs r3, r1, r3 @ get margin-N
18639+ movmi r3, #0x0
18640+ add r1, r2, r3
18641+ cmp r1, #0x0
18642+ beq cbr0_search_dll_margin_e @ if margin-P = 0 && margin-N = 0
18643+
18644+ ldr r9, [r0]
18645+ ldr r0, =0x1e720180
18646+ cmp r2, r3
18647+ orrlt r5, r5, #0x80 @ margin-N > margin-P
18648+ addlt r0, r0, #0x08
18649+ movlt r9, r9, lsr #16
18650+ movge r3, r2 @ max(margin-P/N)
18651+ add r2, r3, #0x2 @ define +/- 2 steps of variation
18652+ mov r1, r6, lsr #16
18653+ cmp r2, r1
18654+ blt cbr0_search_dll_margin_e @ if max(margin-P/N) + 2 < max_margin
18655+
18656+ and r1, r9, #0xFF @ r1 = dlli counter
18657+ cmp r1, #32
18658+ ldrge r2, [r0, #0x4] @ load pass window
18659+ ldrlt r2, [r0]
18660+ and r1, r1, #0x1F
18661+ mov r10, #0x1 @ init test bit mask
18662+ mov r10, r10, lsl r1
18663+ and r1, r9, #0xFF
18664+cbr0_search_dllmin_margin_s:
18665+ tst r2, r10
18666+ beq cbr0_search_dllmin_margin_e
18667+ mov r10, r10, lsr #1
18668+ cmp r1, #32
18669+ ldreq r2, [r0]
18670+ ldreq r10, =0x80000000
18671+ subs r1, r1, #0x1
18672+ bne cbr0_search_dllmin_margin_s
18673+
18674+cbr0_search_dllmin_margin_e:
18675+ and r2, r9, #0xFF
18676+ sub r11, r2, r1 @ get dllmin side margin
18677+
18678+ mov r9, r9, lsr #8
18679+ and r1, r9, #0xFF @ r1 = dlli counter
18680+ cmp r1, #32
18681+ ldrge r2, [r0, #0x4] @ load pass window
18682+ ldrlt r2, [r0]
18683+ and r1, r1, #0x1F
18684+ mov r10, #0x1 @ init test bit mask
18685+ mov r10, r10, lsl r1
18686+ and r1, r9, #0xFF
18687+cbr0_search_dllmax_margin_s:
18688+ tst r2, r10
18689+ beq cbr0_search_dllmax_margin_e
18690+ mov r10, r10, lsl #1
18691+ cmp r1, #31
18692+ ldreq r2, [r0, #0x4]
18693+ ldreq r10, =0x00000001
18694+ add r1, r1, #0x1
18695+ cmp r1, #64
18696+ bne cbr0_search_dllmax_margin_s
18697+
18698+cbr0_search_dllmax_margin_e:
18699+ and r2, r9, #0xFF
18700+ sub r1, r1, r2 @ get dllmax side margin
18701+ cmp r1, r11
18702+ movlt r11, r1 @ get side_margin
18703+
18704+cbr0_check_dll_margin: @ if max(margin-P/N) > g_margin && side_margin >= g_side && dqidly <= 20
18705+ cmp r5, #20
18706+ bgt cbr0_check_dll_margin2
18707+ and r1, r6, #0xFF
18708+ cmp r3, r1
18709+ ble cbr0_check_dll_margin3
18710+ cmp r11, r8
18711+ bge cbr0_set_dll_margin
18712+
18713+cbr0_check_dll_margin2: @ if max(margin-P/N) > g_margin+1 && side_margin >= g_side)
18714+ and r1, r6, #0xFF
18715+ add r2, r1, #0x1
18716+ cmp r3, r2
18717+ ble cbr0_check_dll_margin3
18718+ cmp r11, r8
18719+ bge cbr0_set_dll_margin
18720+
18721+cbr0_check_dll_margin3: @ if side_margin > g_side && g_side < 8
18722+ cmp r8, #8
18723+ bge cbr0_search_dll_margin_e
18724+ cmp r11, r8
18725+ ble cbr0_search_dll_margin_e
18726+
18727+cbr0_set_dll_margin:
18728+ mov r1, r6, lsr #16
18729+ cmp r3, r1
18730+ bicgt r6, r6, #0x00FF0000
18731+ orrgt r6, r6, r3, lsl #16
18732+ bic r6, r6, #0x000000FF
18733+ orr r6, r6, r3
18734+ mov r7, r5
18735+ mov r8, r11
18736+
18737+cbr0_search_dll_margin_e:
18738+ and r5, r5, #0x7F
18739+ add r5, r5, #0x01
18740+ cmp r5, #0x20 @ last DQIDLY
18741+ blt cbr0_search_dll_margin_s
18742+
18743+ ldr r0, =0x1e6e0018
18744+ ldr r1, [r0]
18745+ bic r1, r1, #0x00FF0000
18746+ orr r1, r1, r7, lsl #16
18747+ str r1, [r0]
18748+
18749+ ldr r0, =0x1e6e0068
18750+ ldr r1, [r0]
18751+ bic r1, r1, #0x00FF0000
18752+ bic r1, r1, #0xFF000000
18753+ str r1, [r0]
18754+
18755+ /* Delay about 5us */
18756+ ldr r2, =0x00000005 @ Set Timer5 Reload = 5 us
18757+ init_delay_timer
18758+delay_5:
18759+ check_delay_timer
18760+ bne delay_5
18761+ clear_delay_timer
18762+ /* end delay 5us */
18763+
18764+ ldr r0, =0x1e6e000c @ Set refresh cycle
18765+ ldr r1, =0x00005C01
18766+ str r1, [r0]
18767+
18768+/******************************************************************************
18769+ Fine tune per bit DQ input delay -- Pass 1, left edge align
18770+ r8 = free
18771+ r9 = DQ fail bit accumulator
18772+ r10 = pattern fail counter, initialize to 5 (fail 5 times)
18773+ r11 = free
18774+ *****************************************************************************/
18775+CBR1_START:
18776+/* Debug - UART console message */
18777+ ldr r0, =0x1e784000
18778+ mov r1, #0x0D @ '\r'
18779+ str r1, [r0]
18780+ mov r1, #0x0A @ '\n'
18781+ str r1, [r0]
18782+ mov r1, #0x43 @ 'C'
18783+ str r1, [r0]
18784+ mov r1, #0x42 @ 'B'
18785+ str r1, [r0]
18786+ mov r1, #0x52 @ 'R'
18787+ str r1, [r0]
18788+ mov r1, #0x31 @ '1'
18789+ str r1, [r0]
18790+/* Debug - UART console message */
18791+
18792+ mov r6, #0x00 @ init pass count
18793+ mov r7, #0x00 @ init DLL2 parameter index
18794+
18795+/****************************
18796+ DLL2 delay margin test loop
18797+ ***************************/
18798+cbr1_next_dll2_parameter:
18799+ ldr r0, =0x1e6e0068 @ load DLL2 parameter
18800+ ldr r1, [r0]
18801+ bic r1, r1, #0x00FF0000
18802+ bic r1, r1, #0xFF000000
18803+ orr r1, r1, r7, lsl #16
18804+ str r1, [r0]
18805+ ldr r2, =0x40404040 @ parameter's max is to 0x40404040
18806+ cmp r7, r2
18807+ bge CBR1_END
18808+ ldr r2, =0x01010101
18809+ add r7, r7, r2
18810+
18811+ ldr r0, =0x1e6e0074 @ set the testing DRAM size = 4KB
18812+ ldr r1, =0x00000FFF
18813+ str r1, [r0]
18814+
18815+/* CBRScan2() start */
18816+ ldr r9, =0xFFFF @ init test status
18817+ adrl r5, PATTERN_TABLE @ init pattern table index
18818+/****************************
18819+ Test pattern iteration loop
18820+ ***************************/
18821+cbr1_next_test_pattern:
18822+ mov r10, #5 @ set the retry loop of each pattern
18823+ ldr r1, [r5] @ load test pattern
18824+ ldr r0, =0x1e6e007c
18825+ str r1, [r0]
18826+ cmp r1, #0x00 @ the last data in pattern is 0x00
18827+ bne cbr1_test_single
18828+
18829+cbr1_test_pattern_end:
18830+ cmp r9, #0x00
18831+ bne cbr1_test_pass_dqi
18832+ cmp r6, #10
18833+ bge CBR1_END
18834+ b cbr1_next_dll2_parameter @ CBRScan2() end and test result fail, go to next step
18835+
18836+cbr1_test_pass_dqi:
18837+ and r3, r7, #0xFF
18838+ sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1
18839+ add r6, r6, #0x01 @ increment pass count
18840+ ldr r0, =0x1e720010
18841+ mov r8, #0x01
18842+cbr1_test_pass_dqi_loop_s:
18843+ tst r9, r8
18844+ beq cbr1_test_pass_dqi_loop_e
18845+ record_dll2_pass_range
18846+
18847+cbr1_test_pass_dqi_loop_e:
18848+ add r0, r0, #0x04
18849+ mov r8, r8, lsl #1
18850+ ldr r1, =0xFFFF
18851+ tst r8, r1
18852+ bne cbr1_test_pass_dqi_loop_s
18853+ b cbr1_next_dll2_parameter
18854+
18855+/****************************
18856+ Test fail retry loop
18857+ ***************************/
18858+cbr1_pattern_fail_retry:
18859+
18860+/* CBRTest2() start */
18861+cbr1_test_single:
18862+ ldr r0, =0x1e6e0070
18863+ ldr r1, =0x00000000
18864+ str r1, [r0]
18865+ ldr r1, =0x00000005
18866+ str r1, [r0]
18867+ ldr r3, =0x1000
18868+ ldr r1, =0x1000
18869+cbr1_wait_engine_idle_0:
18870+ subs r1, r1, #1
18871+ beq cbr1_test_single_end
18872+ ldr r2, [r0]
18873+ tst r2, r3 @ D[12] = idle bit
18874+ beq cbr1_wait_engine_idle_0
18875+
18876+cbr1_test_single_end:
18877+ ldr r0, =0x1e6e0078 @ read fail bit status
18878+ ldr r11, [r0]
18879+ orr r11, r11, r11, lsr #16
18880+ bic r11, r11, #0xFF000000
18881+ bic r11, r11, #0x00FF0000
18882+
18883+ ldr r1, =0xFFFF
18884+ cmp r11, r1
18885+ beq cbr1_test_fail
18886+
18887+cbr1_test_burst:
18888+ ldr r0, =0x1e6e0070
18889+ ldr r2, =0x00000000
18890+ str r2, [r0]
18891+ ldr r2, =0x00000041
18892+ str r2, [r0]
18893+ ldr r3, =0x1000
18894+ ldr r1, =0x1000
18895+cbr1_wait_engine_idle_1:
18896+ subs r1, r1, #1
18897+ beq cbr1_test_burst_end
18898+ ldr r2, [r0]
18899+ tst r2, r3 @ D[12] = idle bit
18900+ beq cbr1_wait_engine_idle_1
18901+
18902+cbr1_test_burst_end:
18903+ ldr r0, =0x1e6e0078 @ read fail bit status
18904+ ldr r2, [r0]
18905+ orr r2, r2, r2, lsr #16
18906+ bic r2, r2, #0xFF000000
18907+ bic r2, r2, #0x00FF0000
18908+ orr r11, r11, r2
18909+
18910+ ldr r2, =0xFFFF
18911+ cmp r11, r2
18912+ bne cbr1_test_pass
18913+/* CBRTest2() end */
18914+
18915+cbr1_test_fail:
18916+ subs r10, r10, #1
18917+ bne cbr1_pattern_fail_retry
18918+ mov r9, #0x00
18919+ b cbr1_test_pattern_end @ CBRScan2() return(0)
18920+
18921+cbr1_test_pass:
18922+ ldr r1, =0xFFFF @ record the pass bit
18923+ eor r11, r11, r1
18924+ and r9, r9, r11 @ DQ pass bit
18925+ cmp r9, #0x00
18926+ beq cbr1_test_pattern_end @ CBRScan2() return(0)
18927+
18928+ add r5, r5, #0x04 @ increase the test pattern index
18929+ b cbr1_next_test_pattern
18930+
18931+CBR1_END:
18932+ mov r5, #0x0 @ init DQ DLL_min sum
18933+ mov r6, #0x0 @ init DQ DLL_min valid count
18934+ ldr r0, =0x1e72000c
18935+ ldr r3, =0x1e720050
18936+cbr1_search_dllmin_s:
18937+ add r0, r0, #0x04
18938+ cmp r0, r3
18939+ beq cbr1_search_dllmin_e
18940+ ldr r1, [r0]
18941+ mov r2, r1, lsr #8
18942+ and r2, r2, #0xFF @ get dllmax
18943+ and r1, r1, #0xFF @ get dllmin
18944+ subs r2, r2, r1 @ dllmax - dllmin
18945+ bmi cbr1_search_dllmin_s @ no valid margin found, bypass fine tune
18946+ cmp r2, #10 @ (dllmax - dllmin) < 10
18947+ blt cbr1_search_dllmin_s @ no enough margin found, bypass fine tune
18948+ add r5, r5, r1
18949+ add r6, r6, #1
18950+ b cbr1_search_dllmin_s
18951+
18952+cbr1_search_dllmin_e:
18953+ cmp r6, #16
18954+ bne Calibration_Start_pre @ not all bits valid, retry again
18955+
18956+ mov r5, r5, lsr #4
18957+ ldr r0, =0x1e720000
18958+ str r5, [r0]
18959+
18960+ mov r6, #0x00 @ init DQL CBR value
18961+ ldr r0, =0x1e720030
18962+ ldr r7, =0x1e72000c
18963+cbr1_set_result_dql:
18964+ sub r0, r0, #4
18965+ cmp r0, r7
18966+ beq cbr1_set_result_next
18967+ mov r6, r6, lsl #3
18968+ ldr r1, [r0]
18969+ mov r2, r1, lsr #8
18970+ and r2, r2, #0xFF @ get dllmax
18971+ and r1, r1, #0xFF @ get dllmin
18972+ mov r3, r1 @ dll = dllmin
18973+ cmp r5, r3
18974+ blt cbr1_set_result_dql_neg
18975+ sub r1, r5, r3
18976+ mov r2, #19
18977+ mul r1, r2, r1
18978+ mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5
18979+ cmp r1, #2 @ dqi_tune max = 2
18980+ movgt r1, #2
18981+ orr r6, r6, r1
18982+ b cbr1_set_result_dql
18983+
18984+cbr1_set_result_dql_neg:
18985+ sub r1, r3, r5
18986+ mov r2, #19
18987+ mul r1, r2, r1
18988+ mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5
18989+ cmp r1, #2 @ dqi_tune max = -2
18990+ movgt r1, #2
18991+ mov r2, #8
18992+ sub r1, r2, r1
18993+ and r1, r1, #7
18994+ orr r6, r6, r1
18995+ b cbr1_set_result_dql
18996+
18997+cbr1_set_result_next:
18998+ ldr r0, =0x1e6e0080 @ save DQL fine tune result
18999+ str r6, [r0]
19000+ ldr r0, =0x1e720094
19001+ str r6, [r0]
19002+
19003+ mov r6, #0x00 @ init DQH CBR value
19004+ ldr r0, =0x1e720050
19005+ ldr r7, =0x1e72002c
19006+cbr1_set_result_dqh:
19007+ sub r0, r0, #4
19008+ cmp r0, r7
19009+ beq cbr1_set_result_end
19010+ mov r6, r6, lsl #3
19011+ ldr r1, [r0]
19012+ mov r2, r1, lsr #8
19013+ and r2, r2, #0xFF @ get dllmax
19014+ and r1, r1, #0xFF @ get dllmin
19015+ mov r3, r1 @ dll = dllmin
19016+ cmp r5, r3
19017+ blt cbr1_set_result_dqh_neg
19018+ sub r1, r5, r3
19019+ mov r2, #19
19020+ mul r1, r2, r1
19021+ mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5
19022+ cmp r1, #3 @ dqi_tune max = 2
19023+ movgt r1, #3
19024+ subs r1, r1, #1
19025+ movmi r1, #7
19026+ orr r6, r6, r1
19027+ b cbr1_set_result_dqh
19028+
19029+cbr1_set_result_dqh_neg:
19030+ sub r1, r3, r5
19031+ mov r2, #19
19032+ mul r1, r2, r1
19033+ mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5
19034+ add r1, r1, #1
19035+ cmp r1, #2 @ dqi_tune max = -2
19036+ movgt r1, #2
19037+ mov r2, #8
19038+ sub r1, r2, r1
19039+ and r1, r1, #7
19040+ orr r6, r6, r1
19041+ b cbr1_set_result_dqh
19042+
19043+cbr1_set_result_end:
19044+ ldr r0, =0x1e6e0084 @ save DQH fine tune result
19045+ str r6, [r0]
19046+ ldr r0, =0x1e720098
19047+ str r6, [r0]
19048+
19049+/******************************************************************************
19050+ Search the DLL2 detail margin
19051+ *****************************************************************************/
19052+ ldr r0, =0x1e7200a0
19053+ mov r1, #0
19054+ str r1, [r0]
19055+
19056+CBR3_START:
19057+/* Debug - UART console message */
19058+ ldr r0, =0x1e784000
19059+ mov r1, #0x33 @ '3'
19060+ str r1, [r0]
19061+/* Debug - UART console message */
19062+
19063+ mov r6, #0x00 @ init pass count
19064+ mov r7, #0x00 @ init DLL2 parameter index
19065+ ldr r1, =0x000000ff
19066+ ldr r0, =0x1e720008 @ init DQL dllmax,dllmin
19067+ str r1, [r0]
19068+ ldr r0, =0x1e72000c @ init DQH dllmax,dllmin
19069+ str r1, [r0]
19070+
19071+ ldr r0, =0x1e7200a0 @ CBR3 iteration counter
19072+ ldr r1, [r0]
19073+ add r1, r1, #1
19074+ str r1, [r0]
19075+
19076+/****************************
19077+ DLL2 delay margin test loop
19078+ ***************************/
19079+cbr3_next_dll2_parameter:
19080+ ldr r0, =0x1e6e0068 @ load DLL2 parameter
19081+ ldr r1, [r0]
19082+ bic r1, r1, #0x00FF0000
19083+ bic r1, r1, #0xFF000000
19084+ orr r1, r1, r7, lsl #16
19085+ str r1, [r0]
19086+ ldr r2, =0x40404040 @ parameter's max is to 0x40404040
19087+ cmp r7, r2
19088+ bge CBR3_END
19089+ ldr r2, =0x01010101
19090+ add r7, r7, r2
19091+
19092+ ldr r0, =0x1e6e0074 @ set the testing DRAM size = 64KB
19093+ ldr r1, =0x0000FFFF
19094+ str r1, [r0]
19095+
19096+/* CBRScan() start */
19097+ mov r9, #0x03 @ init test status
19098+ adrl r5, PATTERN_TABLE @ init pattern table index
19099+/****************************
19100+ Test pattern iteration loop
19101+ ***************************/
19102+cbr3_next_test_pattern:
19103+ mov r10, #5 @ set the retry loop of each pattern
19104+ ldr r1, [r5] @ load test pattern
19105+ ldr r0, =0x1e6e007c
19106+ str r1, [r0]
19107+ cmp r1, #0x00 @ the last data in pattern is 0x00
19108+ bne cbr3_test_single
19109+
19110+cbr3_test_pattern_end:
19111+ cmp r9, #0x00
19112+ bne cbr3_test_pass_dql
19113+ cmp r6, #10
19114+ bge CBR3_END
19115+ b cbr3_next_dll2_parameter @ CBRScan() end and test result fail, go to next step
19116+
19117+cbr3_test_pass_dql:
19118+ and r3, r7, #0xFF
19119+ sub r3, r3, #0x01 @ we add one after loop check so we need to decrease 1
19120+ add r6, r6, #0x01 @ increment pass count
19121+ tst r9, #0x01
19122+ beq cbr3_test_pass_dqh
19123+
19124+ ldr r0, =0x1E720008
19125+ record_dll2_pass_range
19126+
19127+cbr3_test_pass_dqh:
19128+ tst r9, #0x02
19129+ beq cbr3_next_dll2_parameter
19130+ ldr r0, =0x1E72000c
19131+ record_dll2_pass_range
19132+ b cbr3_next_dll2_parameter
19133+
19134+/****************************
19135+ Test fail retry loop
19136+ ***************************/
19137+cbr3_pattern_fail_retry:
19138+
19139+/* CBRTest() start */
19140+cbr3_test_single:
19141+ ldr r0, =0x1e6e0070
19142+ ldr r1, =0x00000000
19143+ str r1, [r0]
19144+ ldr r1, =0x00000005
19145+ str r1, [r0]
19146+ ldr r3, =0x1000
19147+ ldr r8, =0x10000
19148+cbr3_wait_engine_idle_0:
19149+ subs r8, r8, #1
19150+ beq cbr3_test_single_end
19151+ ldr r2, [r0]
19152+ tst r2, r3 @ D[12] = idle bit
19153+ beq cbr3_wait_engine_idle_0
19154+
19155+cbr3_test_single_end:
19156+ ldr r0, =0x1e6e0078 @ read fail bit status
19157+ ldr r11, [r0]
19158+ orr r11, r11, r11, lsr #16
19159+ bic r11, r11, #0xFF000000
19160+ bic r11, r11, #0x00FF0000
19161+
19162+ ldr r1, =0xFF
19163+ tst r11, r1
19164+ beq cbr3_test_burst
19165+ tst r11, r1, lsl #8
19166+ bne cbr3_test_fail
19167+
19168+cbr3_test_burst:
19169+ mov r1, #0x00 @ initialize loop index, r1 is loop's index
19170+cbr3_test_burst_loop:
19171+ ldr r0, =0x1e6e0070
19172+ ldr r2, =0x00000000
19173+ str r2, [r0]
19174+ mov r2, r1, lsl #3
19175+ orr r2, r2, #0x41 @ test command = 0x41 | (datagen << 3)
19176+ str r2, [r0]
19177+ ldr r3, =0x1000
19178+ ldr r8, =0x10000
19179+cbr3_wait_engine_idle_1:
19180+ subs r8, r8, #1
19181+ beq cbr3_test_burst_end
19182+ ldr r2, [r0]
19183+ tst r2, r3 @ D[12] = idle bit
19184+ beq cbr3_wait_engine_idle_1
19185+
19186+cbr3_test_burst_end:
19187+ ldr r0, =0x1e6e0078 @ read fail bit status
19188+ ldr r2, [r0]
19189+ orr r2, r2, r2, lsr #16
19190+ bic r2, r2, #0xFF000000
19191+ bic r2, r2, #0x00FF0000
19192+ orr r11, r11, r2
19193+
19194+ ldr r2, =0xFF
19195+ tst r11, r2
19196+ beq cbr3_next_test_burst_mode
19197+ tst r11, r2, lsl #8
19198+ beq cbr3_next_test_burst_mode
19199+/* CBRTest() end */
19200+
19201+cbr3_test_fail:
19202+ subs r10, r10, #1
19203+ bne cbr3_pattern_fail_retry
19204+ mov r9, #0x00
19205+ b cbr3_test_pattern_end @ CBRScan() return(0)
19206+
19207+cbr3_next_test_burst_mode:
19208+ add r1, r1, #1 @ increase the test mode index
19209+ cmp r1, #0x08 @ there are 8 modes
19210+ bne cbr3_test_burst_loop
19211+
19212+ ldr r1, =0xFF @ record the pass byte
19213+ tst r11, r1
19214+ andne r9, r9, #0x02 @ DQL fail
19215+ tst r11, r1, lsl #8
19216+ andne r9, r9, #0x01 @ DQH fail
19217+ cmp r9, #0x00
19218+ beq cbr3_test_pattern_end @ CBRScan() return(0)
19219+
19220+ add r5, r5, #0x04 @ increase the test pattern index
19221+ b cbr3_next_test_pattern
19222+
19223+CBR3_END:
19224+ ldr r0, =0x1e72000c @ check DQH margin
19225+ ldr r1, [r0]
19226+ mov r2, r1, lsr #8
19227+ and r2, r2, #0xFF @ get dllmax
19228+ and r1, r1, #0xFF @ get dllmin
19229+ subs r5, r2, r1 @ dllmax - dllmin
19230+ bmi CBR3_START @ no valid margin found, retry again
19231+ cmp r5, #10 @ (dllmax - dllmin) < 10
19232+ blt CBR3_START @ no enough margin found, retry again
19233+ add r2, r1, r2 @ (dllmin[1] + dllmax[1] + 1) >> 1
19234+ add r2, r2, #0x01
19235+ mov r1, r2, lsr #1
19236+ mov r3, r1, lsl #8
19237+ ldr r1, [r0] @ store the dll search result
19238+ bic r1, r1, #0xFF000000
19239+ bic r1, r1, #0x00FF0000
19240+ orr r1, r1, r3, lsl #8
19241+ str r1, [r0]
19242+
19243+ ldr r0, =0x1e720008 @ check DQL margin
19244+ ldr r1, [r0]
19245+ mov r2, r1, lsr #8
19246+ and r2, r2, #0xFF @ get dllmax
19247+ and r1, r1, #0xFF @ get dllmin
19248+ subs r5, r2, r1 @ dllmax - dllmin
19249+ bmi CBR3_START @ no valid margin found, retry again
19250+ cmp r5, #10 @ (dllmax - dllmin) < 10
19251+ blt CBR3_START @ no enough margin found, retry again
19252+ add r2, r1, r2 @ (dllmin[0] + dllmax[0] + 1) >> 1
19253+ add r2, r2, #0x01
19254+ mov r1, r2, lsr #1
19255+ ldr r2, [r0] @ store the dll search result
19256+ bic r2, r2, #0xFF000000
19257+ bic r2, r2, #0x00FF0000
19258+ orr r2, r2, r1, lsl #16
19259+ str r2, [r0]
19260+ orr r3, r3, r1
19261+
19262+ ldr r0, =0x1e6e0068 @ save the result dll value
19263+ ldr r1, [r0]
19264+ bic r1, r1, #0xFF000000
19265+ bic r1, r1, #0x00FF0000
19266+ orr r1, r1, r3, lsl #16
19267+ str r1, [r0]
19268+ b CBR4_START
19269+
19270+.LTORG
19271+
19272+/******************************************************************************
19273+ Search the DQS input mask margin
19274+ *****************************************************************************/
19275+CBR4_START:
19276+/* Debug - UART console message */
19277+ ldr r0, =0x1e784000
19278+ mov r1, #0x34 @ '4'
19279+ str r1, [r0]
19280+/* Debug - UART console message */
19281+
19282+ ldr r0, =0x1e6e0074 @ set the testing DRAM size = 4KB
19283+ ldr r1, =0x00000FFF
19284+ str r1, [r0]
19285+
19286+ mov r8, #0x00 @ init MCR18[4]
19287+ ldr r1, =0x000000ff
19288+ ldr r0, =0x1e7200b0 @ init MCR18[4]=0 max,min
19289+ str r1, [r0]
19290+ ldr r0, =0x1e7200b4 @ init MCR18[4]=1 max,min
19291+ str r1, [r0]
19292+
19293+ ldr r0, =0x1e6e0018
19294+ ldr r1, [r0]
19295+ bic r1, r1, #0x0000001F
19296+ str r1, [r0]
19297+
19298+ b cbr4_scan_start
19299+
19300+cbr4_next_maskdly:
19301+ add r8, r8, #0x01
19302+ and r2, r8, #0x01
19303+ ldr r0, =0x1e6e0018
19304+ ldr r1, [r0]
19305+ bic r1, r1, #0x0000001F
19306+ orr r1, r1, r2, lsl #4
19307+ str r1, [r0]
19308+ cmp r8, #0x02
19309+ bge CBR4_END
19310+
19311+cbr4_scan_start:
19312+ mov r6, #0x00 @ init pass count
19313+ mov r7, #0x00 @ init mask delay
19314+
19315+/****************************
19316+ DQS Mask delay margin test loop
19317+ ***************************/
19318+cbr4_next_parameter:
19319+ cmp r7, #0x10 @ max delay = 0xF
19320+ bge cbr4_next_maskdly
19321+ ldr r0, =0x1e6e0018 @ load MCR18 parameter
19322+ ldr r1, [r0]
19323+ bic r1, r1, #0x0000000F
19324+ orr r1, r1, r7
19325+ str r1, [r0]
19326+ add r7, r7, #0x01
19327+
19328+/* CBRScan3() start */
19329+ adrl r5, PATTERN_TABLE @ init pattern table index
19330+/****************************
19331+ Test pattern iteration loop
19332+ ***************************/
19333+cbr4_next_test_pattern:
19334+ mov r10, #2 @ set the retry loop = 2 of each pattern
19335+ ldr r1, [r5] @ load test pattern
19336+ ldr r0, =0x1e6e007c
19337+ str r1, [r0]
19338+ cmp r1, #0x00 @ the last data in pattern is 0x00
19339+ bne cbr4_test_burst
19340+
19341+ and r3, r7, #0xFF
19342+ sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1
19343+ add r6, r6, #0x01 @ increment pass count
19344+
19345+ ldr r0, =0x1e7200b0 @ record pass window
19346+ add r0, r0, r8, lsl #2
19347+ record_dll2_pass_range
19348+ mov r2, #0x01
19349+ add r1, r1, r2, lsl #16
19350+ str r1, [r0]
19351+ b cbr4_next_parameter
19352+
19353+cbr4_test_pattern_fail:
19354+ cmp r6, #5 @ passcnt >= 5
19355+ bge cbr4_next_maskdly
19356+ b cbr4_next_parameter
19357+
19358+/****************************
19359+ Test fail retry loop
19360+ ***************************/
19361+cbr4_pattern_fail_retry:
19362+
19363+/* CBRTest3() start */
19364+cbr4_test_burst:
19365+ ldr r0, =0x1e6e0070
19366+ ldr r1, =0x00000000
19367+ str r1, [r0]
19368+ ldr r1, =0x000000C1
19369+ str r1, [r0]
19370+ ldr r3, =0x3000
19371+cbr4_wait_engine_idle_0:
19372+ ldr r2, [r0]
19373+ tst r2, r3 @ D[12] = idle bit
19374+ beq cbr4_wait_engine_idle_0
19375+
19376+ ldr r2, [r0] @ read fail bit status
19377+ mov r1, #0x0
19378+ str r1, [r0]
19379+ mov r2, r2, lsr #13 @ D[13] = fail bit
19380+ cmp r2, #0x00
19381+ bne cbr4_test_fail
19382+
19383+cbr4_test_single:
19384+ ldr r0, =0x1e6e0070
19385+ ldr r1, =0x00000000
19386+ str r1, [r0]
19387+ ldr r1, =0x00000085
19388+ str r1, [r0]
19389+ ldr r3, =0x3000
19390+cbr4_wait_engine_idle_1:
19391+ ldr r2, [r0]
19392+ tst r2, r3 @ D[12] = idle bit
19393+ beq cbr4_wait_engine_idle_1
19394+
19395+ ldr r2, [r0] @ read fail bit status
19396+ mov r1, #0x0
19397+ str r1, [r0]
19398+ mov r2, r2, lsr #13 @ D[13] = fail bit
19399+ cmp r2, #0x00
19400+ beq cbr4_test_pass
19401+
19402+/* CBRTest3() end */
19403+
19404+cbr4_test_fail:
19405+ subs r10, r10, #1
19406+ bne cbr4_pattern_fail_retry
19407+ b cbr4_test_pattern_fail @ CBRScan3() return(0)
19408+
19409+cbr4_test_pass:
19410+ add r5, r5, #0x04 @ increase the test pattern index
19411+ b cbr4_next_test_pattern
19412+
19413+CBR4_END:
19414+ ldr r0, =0x1e7200b0 @ check mask margin
19415+ ldr r1, [r0]
19416+ add r0, r0, #0x04
19417+ ldr r2, [r0]
19418+ ands r6, r2, #0xFF @ get min of MCR18[4] = 1
19419+ bne cbr4_noset_delay
19420+ ands r5, r1, #0xFF @ get min of MCR18[4] = 0
19421+ bne cbr4_set_delay
19422+ mov r1, r1, lsr #8 @ get max of MCR18[4] = 0
19423+ and r1, r1, #0xFF
19424+ mov r2, r2, lsr #8 @ get max of MCR18[4] = 1
19425+ and r2, r2, #0xFF
19426+ sub r1, r1, r5
19427+ sub r2, r2, r6
19428+ cmp r1, r2
19429+ bge cbr4_noset_delay
19430+
19431+cbr4_set_delay:
19432+ ldr r0, =0x1e6e0018
19433+ ldr r1, [r0]
19434+ orr r1, r1, #0x10
19435+ str r1, [r0]
19436+
19437+cbr4_noset_delay:
19438+ ldr r0, =0x1e6e0070
19439+ ldr r1, =0x00000000
19440+ str r1, [r0]
19441+
19442+/******************************************************************************
19443+ CBR Finish
19444+ *****************************************************************************/
19445+/******************************************************************************
19446+ Check DRAM Size
19447+ *****************************************************************************/
19448+ ldr r0, =0x1e6e2070
19449+ ldr r1, [r0]
19450+ bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2
19451+ mov r2, r1, lsr #24
19452+ cmp r2, #0x01
19453+ beq check_ddr2_size
19454+
19455+ ldr r0, =0x1e6e0004
19456+ ldr r5, [r0]
19457+ bic r5, r5, #0x00000003 @ record MCR04
19458+ orr r1, r5, #0x3
19459+ str r1, [r0] @ set to 4Gbit
19460+ ldr r6, =0x003F2217
19461+#if defined(CONFIG_DRAM_336)
19462+ ldr r6, =0x00361C13
19463+#endif
19464+ b check_dram_size
19465+
19466+check_ddr2_size:
19467+ ldr r0, =0x1e6e0004
19468+ ldr r5, [r0]
19469+ bic r5, r5, #0x00000023 @ record MCR04
19470+ orr r1, r5, #0x23
19471+ str r1, [r0] @ set to 4Gbit
19472+ ldr r6, =0x3F2B1B16
19473+#if defined(CONFIG_DRAM_336)
19474+ ldr r6, =0x3B231612
19475+#endif
19476+
19477+ ldr r0, =0x40000000
19478+ ldr r1, =0x1817191A
19479+ str r1, [r0]
19480+ ldr r0, =0x40002000
19481+ ldr r1, =0x73616532
19482+ str r1, [r0]
19483+ ldr r0, =0x40000000
19484+ ldr r1, =0x1817191A
19485+ ldr r2, [r0]
19486+ cmp r1, r2
19487+ bne check_dram_size_end @ == 512Mbit
19488+ orr r5, r5, #0x20 @ >= 1Gbit
19489+ mov r6, r6, lsr #8
19490+
19491+check_dram_size:
19492+ ldr r0, =0x50100000
19493+ ldr r1, =0x41424344
19494+ str r1, [r0]
19495+ ldr r0, =0x48100000
19496+ ldr r1, =0x25262728
19497+ str r1, [r0]
19498+ ldr r0, =0x40100000
19499+ ldr r1, =0x191A1B1C
19500+ str r1, [r0]
19501+ ldr r0, =0x50100000
19502+ ldr r1, =0x41424344
19503+ ldr r2, [r0]
19504+ cmp r2, r1 @ == 4Gbit
19505+ orreq r5, r5, #0x03
19506+ moveq r6, r6, lsr #16
19507+ beq check_dram_size_end
19508+ ldr r0, =0x48100000
19509+ ldr r1, =0x25262728
19510+ ldr r2, [r0]
19511+ cmp r2, r1 @ == 2Gbit
19512+ orreq r5, r5, #0x02
19513+ moveq r6, r6, lsr #8
19514+ beq check_dram_size_end
19515+ orr r5, r5, #0x01 @ == 1Gbit
19516+
19517+check_dram_size_end:
19518+ ldr r0, =0x1e6e0004
19519+ str r5, [r0]
19520+ ldr r0, =0x1e6e0014
19521+ ldr r1, [r0]
19522+ bic r1, r1, #0x000000FF
19523+ and r6, r6, #0xFF
19524+ orr r1, r1, r6
19525+ str r1, [r0]
19526+
19527+ ldr r0, =0x1e6e0120 @ VGA Compatible Mode
19528+ ldr r1, =0x000050C0 @ 408 MHz
19529+#if defined(CONFIG_DRAM_336)
19530+ ldr r1, =0x00004DC0
19531+#endif
19532+ str r1, [r0]
19533+
19534+/******************************************************************************
19535+ Version Number
19536+ *****************************************************************************/
19537+ ldr r0, =0x1e7200a8
19538+ ldr r1, =0x20141229 @ released date
19539+ str r1, [r0]
19540+
19541+ add r0, r0, #4
19542+ ldr r1, =0x00000060 @ released SDK version
19543+ str r1, [r0]
19544+
19545+/******************************************************************************
19546+ Calibration Code End
19547+ ******************************************************************************/
19548+
19549+set_scratch:
19550+ /*Set Scratch register Bit 6 after ddr initial finished */
19551+ ldr r0, =0x1e6e2040
19552+ ldr r1, [r0]
19553+ orr r1, r1, #0x40
19554+ str r1, [r0]
19555+
19556+/* Debug - UART console message */
19557+ ldr r0, =0x1e784000
19558+ mov r1, #0x44 @ 'D'
19559+ str r1, [r0]
19560+ mov r1, #0x6F @ 'o'
19561+ str r1, [r0]
19562+ mov r1, #0x6E @ 'n'
19563+ str r1, [r0]
19564+ mov r1, #0x65 @ 'e'
19565+ str r1, [r0]
19566+ mov r1, #0x0D @ '\r'
19567+ str r1, [r0]
19568+ mov r1, #0x0A @ '\n'
19569+ str r1, [r0]
19570+/* Debug - UART console message */
19571+
19572+/******************************************************************************
19573+ Solve PCIe ASPM issue, only applied to AST2300 series
19574+ ******************************************************************************/
19575+ ldr r0, =0x1e6e207c @ Check bounding for AST1150 existence
19576+ ldr r1, [r0]
19577+ mov r2, r1, lsr #24
19578+ cmp r2, #0x01
19579+ bne platform_exit @ not match AST2300
19580+ bic r1, r1, #0xFFFFFCFF
19581+ mov r1, r1, lsr #8
19582+ cmp r1, #0x02
19583+ beq platform_exit @ match AST1050
19584+
19585+ ldr r0, =0x1e6e2004 @ Disable I2C controller reset
19586+ ldr r1, [r0]
19587+ orr r1, r1, #0x04
19588+ str r1, [r0]
19589+ bic r1, r1, #0x04
19590+ str r1, [r0]
19591+
19592+ ldr r0, =0x1e78a054 @ Check I2C bus state, if busy then quit
19593+ ldr r1, [r0]
19594+ mov r1, r1, lsr #17
19595+ and r1, r1, #0x03
19596+ cmp r1, #0x03
19597+ bne platform_exit
19598+
19599+ ldr r0, =0x1e78a040 @ Init I2C1 controller
19600+ mov r1, #0x01
19601+ orr r1, r1, r1, lsl #16
19602+ str r1, [r0]
19603+
19604+ ldr r0, =0x1e78a044
19605+ ldr r1, =0x77776704
19606+ str r1, [r0]
19607+
19608+ mov r1, #0x0
19609+ ldr r0, =0x1e78a048
19610+ str r1, [r0]
19611+ ldr r0, =0x1e78a04c
19612+ str r1, [r0]
19613+
19614+ ldr r0, =0x1e78a050
19615+ ldr r1, =0xFFFFFFFF
19616+ str r1, [r0]
19617+
19618+ ldr r0, =0x1e78a200 @ Set AST1150 I2C password
19619+ ldr r1, =0x00A88FA8
19620+ str r1, [r0]
19621+
19622+ ldr r0, =0x1e78a05c
19623+ ldr r1, =0x00000200 @ Enable buffer mode transfering 3 bytes
19624+ str r1, [r0]
19625+
19626+ ldr r0, =0x1e78a054
19627+ ldr r1, =0x00000063 @ Fire commmand
19628+ str r1, [r0]
19629+
19630+ ldr r0, =0x1e78a050
19631+i2c_wait_cmddone_1:
19632+ ldr r1, [r0]
19633+ tst r1, #0x38
19634+ beq i2c_wait_cmddone_1
19635+ tst r1, #0x2A @ transmit error
19636+ bne platform_exit2
19637+ ldr r1, =0xFFFFFFFF
19638+ str r1, [r0]
19639+
19640+ ldr r0, =0x1e78a200 @ Disable ASPM capability
19641+ ldr r1, =0x04005DA8
19642+ str r1, [r0]
19643+
19644+ ldr r0, =0x1e78a204
19645+ ldr r1, =0x00000024
19646+ str r1, [r0]
19647+
19648+ ldr r0, =0x1e78a05c
19649+ ldr r1, =0x00000200 @ Enable buffer mode transfering 3 bytes
19650+ str r1, [r0]
19651+
19652+ ldr r0, =0x1e78a054
19653+ ldr r1, =0x00000063 @ Fire commmand
19654+ str r1, [r0]
19655+
19656+ ldr r0, =0x1e78a050
19657+i2c_wait_cmddone_2:
19658+ ldr r1, [r0]
19659+ tst r1, #0x38
19660+ beq i2c_wait_cmddone_2
19661+ tst r1, #0x2A @ transmit error
19662+ bne platform_exit2
19663+ ldr r1, =0xFFFFFFFF
19664+ str r1, [r0]
19665+
19666+platform_exit2:
19667+ ldr r0, =0x1e78a040 @ Disable I2C1 controller
19668+ mov r1, #0x00
19669+ str r1, [r0]
19670+
19671+ b platform_exit
19672+.LTORG
19673+
19674+platform_exit:
19675+#ifdef CONFIG_DRAM_ECC
19676+ ldr r0, =0x1e6e0004
19677+ ldr r1, [r0]
19678+ orr r1, r1, #0x80
19679+ str r1, [r0]
19680+
19681+ ldr r0, =0x1e6e0054
19682+ ldr r1, =0x05000000 /* ECC protected memory size, default set at 80M */
19683+ str r1, [r0]
19684+
19685+ ldr r0, =0x1e6e007C
19686+ ldr r1, =0x00000000
19687+ str r1, [r0]
19688+ ldr r0, =0x1e6e0074
19689+ str r1, [r0]
19690+
19691+ ldr r0, =0x1e6e0070
19692+ ldr r1, =0x00000221
19693+ str r1, [r0]
19694+
19695+ ldr r0, =0x1e6e0070
19696+ ldr r2, =0x00001000
19697+ECC_Init_Flag:
19698+ ldr r1, [r0]
19699+ tst r1, r2 @ D[12] = 1, Done
19700+ beq ECC_Init_Flag
19701+
19702+ ldr r0, =0x1e6e0070
19703+ ldr r1, =0x00000000
19704+ str r1, [r0]
19705+
19706+ ldr r0, =0x1e6e0050
19707+ ldr r1, =0x80000000
19708+ str r1, [r0]
19709+
19710+ ldr r0, =0x1e6e0050
19711+ ldr r1, =0x00000000
19712+ str r1, [r0]
19713+
19714+ ldr r0, =0x1e6e0070
19715+ ldr r1, =0x00000400
19716+ str r1, [r0]
19717+#endif
19718+ ldr r0, =0x1e6e2008 @ Set Video ECLK phase
19719+ ldr r1, [r0]
19720+ ldr r2, =0xfffffff3
19721+ and r1, r1, r2
19722+ orr r1, r1, #0x08
19723+ str r1, [r0]
19724+
19725+ ldr r0, =0x1e6e2004
19726+ ldr r1, [r0]
19727+ ldr r2, =0xFFBFFFFF @ Enable JTAG Master, solve ARM stucked by JTAG issue
19728+ and r1, r1, r2
19729+ str r1, [r0]
19730+
19731+ ldr r0, =0x1e6e2048 @ Set MAC interface delay timing
19732+ ldr r1, =0x2255
19733+ str r1, [r0]
19734+
19735+ ldr r0, =0x1e6e2070 @ Set MAC AHB bus clock
19736+ ldr r1, [r0]
19737+ mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10
19738+ tst r1, #0xC0
19739+ movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6
19740+ ldr r0, =0x1e6e2008
19741+ ldr r1, [r0]
19742+ bic r1, r1, #0x00070000
19743+ orr r1, r1, r2, lsl #16
19744+ str r1, [r0]
19745+
19746+/* Test - DRAM initial time */
19747+ ldr r0, =0x1e782040
19748+ ldr r1, [r0]
19749+ ldr r0, =0xFFFFFFFF
19750+ sub r1, r0, r1
19751+ ldr r0, =0x1e72009c
19752+ str r1, [r0]
19753+ ldr r0, =0x1e7200a4
19754+ str r1, [r0]
19755+ ldr r0, =0x1e782030
19756+ ldr r1, [r0]
19757+ bic r1, r1, #0x0000F000
19758+ str r1, [r0]
19759+/* Test - DRAM initial time */
19760+
19761+/******************************************************************************
19762+ Reset GPIO registers when watchdog reset
19763+ ******************************************************************************/
19764+ ldr r0, =0x1e6e207c @ Check Revision ID
19765+ ldr r1, [r0]
19766+ mov r1, r1, lsr #24
19767+ cmp r1, #0x02
19768+ bne platform_exit3 @ not match AST2400
19769+
19770+ ldr r0, =0x1e6e203c @ Check watchdog reset event
19771+ ldr r1, [r0]
19772+ and r1, r1, #0x06
19773+ cmp r1, #0x0
19774+ beq platform_exit3 @ no watchdog reset event
19775+
19776+ ldr r0, =0x1e6e209c @ Check watchdog GPIO selection
19777+ ldr r1, [r0]
19778+ mov r1, r1, lsr #21
19779+ tst r1, #0x01
19780+ beq platform_exit3 @ no watchdog reset selection
19781+
19782+ ldr r1, =0x00000000 @ clear GPIO register reset by PRST_N
19783+ ldr r2, =0xFFFFFFFF
19784+ ldr r0, =0x1e780008
19785+ str r1, [r0]
19786+ ldr r0, =0x1e78000c
19787+ str r1, [r0]
19788+ ldr r0, =0x1e780010
19789+ str r1, [r0]
19790+ ldr r0, =0x1e780014
19791+ str r1, [r0]
19792+ ldr r0, =0x1e780018
19793+ str r2, [r0]
19794+ ldr r0, =0x1e780028
19795+ str r1, [r0]
19796+ ldr r0, =0x1e78002c
19797+ str r1, [r0]
19798+ ldr r0, =0x1e780030
19799+ str r1, [r0]
19800+ ldr r0, =0x1e780034
19801+ str r1, [r0]
19802+ ldr r0, =0x1e780038
19803+ str r2, [r0]
19804+ ldr r0, =0x1e780040
19805+ str r1, [r0]
19806+ ldr r0, =0x1e780044
19807+ str r1, [r0]
19808+ ldr r0, =0x1e780048
19809+ str r1, [r0]
19810+ ldr r0, =0x1e78004c
19811+ str r1, [r0]
19812+ ldr r0, =0x1e780050
19813+ str r1, [r0]
19814+ ldr r0, =0x1e780054
19815+ str r1, [r0]
19816+ ldr r0, =0x1e780058
19817+ str r1, [r0]
19818+ ldr r0, =0x1e780060
19819+ str r1, [r0]
19820+ ldr r0, =0x1e780064
19821+ str r1, [r0]
19822+ ldr r0, =0x1e780068
19823+ str r1, [r0]
19824+ ldr r0, =0x1e78006c
19825+ str r1, [r0]
19826+ ldr r0, =0x1e780090
19827+ str r1, [r0]
19828+ ldr r0, =0x1e780094
19829+ str r1, [r0]
19830+ ldr r0, =0x1e780098
19831+ str r1, [r0]
19832+ ldr r0, =0x1e78009c
19833+ str r1, [r0]
19834+ ldr r0, =0x1e7800a0
19835+ str r1, [r0]
19836+ ldr r0, =0x1e7800a4
19837+ str r1, [r0]
19838+ ldr r0, =0x1e7800a8
19839+ str r2, [r0]
19840+ ldr r0, =0x1e7800b0
19841+ str r1, [r0]
19842+ ldr r0, =0x1e7800b4
19843+ str r1, [r0]
19844+ ldr r0, =0x1e7800b8
19845+ str r1, [r0]
19846+ ldr r0, =0x1e7800e0
19847+ str r1, [r0]
19848+ ldr r0, =0x1e7800e4
19849+ str r1, [r0]
19850+ ldr r0, =0x1e7800e8
19851+ str r1, [r0]
19852+ ldr r0, =0x1e7800ec
19853+ str r1, [r0]
19854+ ldr r0, =0x1e7800f0
19855+ str r1, [r0]
19856+ ldr r0, =0x1e7800f4
19857+ str r1, [r0]
19858+ ldr r0, =0x1e7800f8
19859+ str r2, [r0]
19860+ ldr r0, =0x1e780100
19861+ str r1, [r0]
19862+ ldr r0, =0x1e780104
19863+ str r1, [r0]
19864+ ldr r0, =0x1e780108
19865+ str r1, [r0]
19866+ ldr r0, =0x1e780110
19867+ str r1, [r0]
19868+ ldr r0, =0x1e780114
19869+ str r1, [r0]
19870+ ldr r0, =0x1e780118
19871+ str r1, [r0]
19872+ ldr r0, =0x1e78011c
19873+ str r1, [r0]
19874+ ldr r0, =0x1e780120
19875+ str r1, [r0]
19876+ ldr r0, =0x1e780124
19877+ str r1, [r0]
19878+ ldr r0, =0x1e780128
19879+ str r2, [r0]
19880+ ldr r0, =0x1e780130
19881+ str r1, [r0]
19882+ ldr r0, =0x1e780134
19883+ str r1, [r0]
19884+ ldr r0, =0x1e780138
19885+ str r1, [r0]
19886+ ldr r0, =0x1e780140
19887+ str r1, [r0]
19888+ ldr r0, =0x1e780144
19889+ str r1, [r0]
19890+ ldr r0, =0x1e780148
19891+ str r1, [r0]
19892+ ldr r0, =0x1e78014c
19893+ str r1, [r0]
19894+ ldr r0, =0x1e780150
19895+ str r1, [r0]
19896+ ldr r0, =0x1e780154
19897+ str r1, [r0]
19898+ ldr r0, =0x1e780158
19899+ str r2, [r0]
19900+ ldr r0, =0x1e780160
19901+ str r1, [r0]
19902+ ldr r0, =0x1e780164
19903+ str r1, [r0]
19904+ ldr r0, =0x1e780168
19905+ str r1, [r0]
19906+ ldr r0, =0x1e780170
19907+ str r1, [r0]
19908+ ldr r0, =0x1e780174
19909+ str r1, [r0]
19910+ ldr r0, =0x1e780178
19911+ str r1, [r0]
19912+ ldr r0, =0x1e78017c
19913+ str r1, [r0]
19914+ ldr r0, =0x1e780180
19915+ str r1, [r0]
19916+ ldr r0, =0x1e780184
19917+ str r1, [r0]
19918+ ldr r0, =0x1e780188
19919+ str r2, [r0]
19920+ ldr r0, =0x1e780190
19921+ str r1, [r0]
19922+ ldr r0, =0x1e780194
19923+ str r1, [r0]
19924+ ldr r0, =0x1e780198
19925+ str r1, [r0]
19926+ ldr r0, =0x1e7801d0
19927+ str r1, [r0]
19928+ ldr r0, =0x1e7801d4
19929+ str r1, [r0]
19930+
19931+ ldr r0, =0x1e780204 @ clear SGPIOM register reset by PRST_N
19932+ str r1, [r0]
19933+ ldr r0, =0x1e780208
19934+ str r1, [r0]
19935+ ldr r0, =0x1e78020c
19936+ str r1, [r0]
19937+ ldr r0, =0x1e780210
19938+ str r1, [r0]
19939+ ldr r0, =0x1e780214
19940+ str r2, [r0]
19941+ ldr r0, =0x1e780220
19942+ str r1, [r0]
19943+ ldr r0, =0x1e780224
19944+ str r1, [r0]
19945+ ldr r0, =0x1e780228
19946+ str r1, [r0]
19947+ ldr r0, =0x1e78022c
19948+ str r1, [r0]
19949+ ldr r0, =0x1e780230
19950+ str r2, [r0]
19951+ ldr r0, =0x1e78023c
19952+ str r1, [r0]
19953+ ldr r0, =0x1e780240
19954+ str r1, [r0]
19955+ ldr r0, =0x1e780244
19956+ str r1, [r0]
19957+ ldr r0, =0x1e780248
19958+ str r1, [r0]
19959+ ldr r0, =0x1e78024c
19960+ str r2, [r0]
19961+ ldr r0, =0x1e780254
19962+ ldr r3, =0x01000040
19963+ str r3, [r0]
19964+ ldr r0, =0x1e780258
19965+ str r1, [r0]
19966+ ldr r0, =0x1e78025c
19967+ str r1, [r0]
19968+ ldr r0, =0x1e780260
19969+ str r1, [r0]
19970+
19971+ ldr r0, =0x1e780300 @ clear SGPIOS register reset by PRST_N
19972+ str r1, [r0]
19973+ ldr r0, =0x1e780304
19974+ str r1, [r0]
19975+ ldr r0, =0x1e780308
19976+ str r1, [r0]
19977+ ldr r0, =0x1e78030c
19978+ str r1, [r0]
19979+ ldr r0, =0x1e780310
19980+ str r1, [r0]
19981+ ldr r0, =0x1e780314
19982+ str r1, [r0]
19983+ ldr r0, =0x1e780318
19984+ str r2, [r0]
19985+ ldr r0, =0x1e78031c
19986+ str r2, [r0]
19987+ ldr r0, =0x1e780320
19988+ str r2, [r0]
19989+
19990+platform_exit3:
19991+
19992+/******************************************************************************
19993+ SPI Timing Calibration, not applicable to AST2300 series
19994+ ******************************************************************************/
19995+ ldr r0, =0x1e6e207c @ Check Revision ID
19996+ ldr r1, [r0]
19997+ mov r1, r1, lsr #24
19998+ cmp r1, #0x02
19999+ blt platform_exit4 @ not match AST2400 or later
20000+
20001+ ldr r0, =0x1e6e2070 @ Check SPI flash
20002+ ldr r1, [r0]
20003+ and r1, r1, #0x03
20004+ cmp r1, #0x02
20005+ bne platform_exit4
20006+
20007+ mov r2, #0x0
20008+ mov r6, #0x0
20009+ mov r7, #0x0
20010+ init_spi_checksum
20011+spi_checksum_wait_0:
20012+ ldr r1, [r0]
20013+ tst r1, r2
20014+ beq spi_checksum_wait_0
20015+ ldr r0, =0x1e620090
20016+ ldr r5, [r0] @ record golden checksum
20017+ ldr r0, =0x1e620080
20018+ mov r1, #0x0
20019+ str r1, [r0]
20020+
20021+ ldr r0, =0x1e620010 @ set to fast read mode
20022+ ldr r1, =0x000B0041
20023+ str r1, [r0]
20024+
20025+ ldr r6, =0x00F7E6D0 @ Init spiclk loop
20026+ mov r8, #0x0 @ Init delay record
20027+
20028+spi_cbr_next_clkrate:
20029+ mov r6, r6, lsr #0x4
20030+ cmp r6, #0x0
20031+ beq spi_cbr_end
20032+
20033+ mov r7, #0x0 @ Init delay loop
20034+ mov r8, r8, lsl #4
20035+
20036+spi_cbr_next_delay_s:
20037+ mov r2, #0x8
20038+ init_spi_checksum
20039+spi_checksum_wait_1:
20040+ ldr r1, [r0]
20041+ tst r1, r2
20042+ beq spi_checksum_wait_1
20043+ ldr r0, =0x1e620090
20044+ ldr r2, [r0] @ read checksum
20045+ ldr r0, =0x1e620080
20046+ mov r1, #0x0
20047+ str r1, [r0]
20048+ cmp r2, r5
20049+ bne spi_cbr_next_delay_e
20050+
20051+ mov r2, #0x0
20052+ init_spi_checksum
20053+spi_checksum_wait_2:
20054+ ldr r1, [r0]
20055+ tst r1, r2
20056+ beq spi_checksum_wait_2
20057+ ldr r0, =0x1e620090
20058+ ldr r2, [r0] @ read checksum
20059+ ldr r0, =0x1e620080
20060+ mov r1, #0x0
20061+ str r1, [r0]
20062+ cmp r2, r5
20063+ bne spi_cbr_next_delay_e
20064+
20065+ orr r8, r8, r7 @ record passed delay
20066+ b spi_cbr_next_clkrate
20067+
20068+spi_cbr_next_delay_e:
20069+ add r7, r7, #0x1
20070+ cmp r7, #0x6
20071+ blt spi_cbr_next_delay_s
20072+ b spi_cbr_next_clkrate
20073+
20074+spi_cbr_end:
20075+ ldr r0, =0x1e620094
20076+ str r8, [r0]
20077+ ldr r0, =0x1e620010
20078+ mov r1, #0x0
20079+ str r1, [r0]
20080+
20081+platform_exit4:
20082+
20083+ /* restore lr */
20084+ mov lr, r4
20085+
20086+ /* back to arch calling code */
20087+ mov pc, lr
20088diff --git a/board/aspeed/ast2300/rc4.c b/board/aspeed/ast2300/rc4.c
20089new file mode 100755
20090index 0000000..32e0ffa
20091--- /dev/null
20092+++ b/board/aspeed/ast2300/rc4.c
20093@@ -0,0 +1,68 @@
20094+/*
20095+ * This program is distributed in the hope that it will be useful,
20096+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20097+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20098+ * GNU General Public License for more details.
20099+ *
20100+ * You should have received a copy of the GNU General Public License
20101+ * along with this program; if not, write to the Free Software
20102+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20103+ */
20104+struct rc4_state
20105+{
20106+ int x, y, m[256];
20107+};
20108+
20109+void rc4_setup( struct rc4_state *s, unsigned char *key, int length )
20110+{
20111+ int i, j, k, *m, a;
20112+
20113+ s->x = 0;
20114+ s->y = 0;
20115+ m = s->m;
20116+
20117+ for( i = 0; i < 256; i++ )
20118+ {
20119+ m[i] = i;
20120+ }
20121+
20122+ j = k = 0;
20123+
20124+ for( i = 0; i < 256; i++ )
20125+ {
20126+ a = m[i];
20127+ j = (unsigned char) ( j + a + key[k] );
20128+ m[i] = m[j]; m[j] = a;
20129+ if( ++k >= length ) k = 0;
20130+ }
20131+}
20132+
20133+void rc4_crypt( struct rc4_state *s, unsigned char *data, int length )
20134+{
20135+ int i, x, y, *m, a, b;
20136+
20137+ x = s->x;
20138+ y = s->y;
20139+ m = s->m;
20140+
20141+ for( i = 0; i < length; i++ )
20142+ {
20143+ x = (unsigned char) ( x + 1 ); a = m[x];
20144+ y = (unsigned char) ( y + a );
20145+ m[x] = b = m[y];
20146+ m[y] = a;
20147+ data[i] ^= m[(unsigned char) ( a + b )];
20148+ }
20149+
20150+ s->x = x;
20151+ s->y = y;
20152+}
20153+
20154+void rc4_crypt_sw(unsigned char *data, int ulMsgLength, unsigned char *rc4_key, unsigned long ulKeyLength )
20155+{
20156+ struct rc4_state s;
20157+
20158+ rc4_setup( &s, rc4_key, ulKeyLength );
20159+
20160+ rc4_crypt( &s, data, ulMsgLength );
20161+}
20162diff --git a/board/aspeed/ast2300/regtest.c b/board/aspeed/ast2300/regtest.c
20163new file mode 100755
20164index 0000000..1cd75ae
20165--- /dev/null
20166+++ b/board/aspeed/ast2300/regtest.c
20167@@ -0,0 +1,91 @@
20168+/*
20169+ * This program is distributed in the hope that it will be useful,
20170+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20171+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20172+ * GNU General Public License for more details.
20173+ *
20174+ * You should have received a copy of the GNU General Public License
20175+ * along with this program; if not, write to the Free Software
20176+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20177+ * MA 02111-1307 USA
20178+ */
20179+
20180+/*
20181+ * Diagnostics support
20182+ */
20183+#include <common.h>
20184+#include <command.h>
20185+#include <post.h>
20186+#include "slt.h"
20187+
20188+#if ((CFG_CMD_SLT & CFG_CMD_REGTEST) && defined(CONFIG_SLT))
20189+#include "regtest.h"
20190+
20191+int do_regtest (void)
20192+{
20193+ _SOCRegTestInfo *pjSOCRegInfo;
20194+ _SOCRegTestTbl *pjRegTable;
20195+ unsigned long ulRegBase;
20196+ unsigned long ulIndex, ulBack, ulAND, ulMask, ulData, ulTemp;
20197+ unsigned long Flags = 0;
20198+
20199+ /* unlock reg */
20200+ *(unsigned long *) (0x1e600000) = 0xaeed1a03; /* AHBC */
20201+ *(unsigned long *) (0x1e6e0000) = 0xfc600309; /* MMC */
20202+ *(unsigned long *) (0x1e6e2000) = 0x1688a8a8; /* SCU */
20203+
20204+ /* SCU */
20205+
20206+ /* do test */
20207+ pjSOCRegInfo = SOCRegTestInfo;
20208+ while (strcmp(pjSOCRegInfo->jName, "END"))
20209+ {
20210+ /* Reg. Test Start */
20211+ ulRegBase = pjSOCRegInfo->ulRegOffset;
20212+ pjRegTable = pjSOCRegInfo->pjTblIndex;
20213+
20214+ while (pjRegTable->ulIndex != 0xFFFFFFFF)
20215+ {
20216+ ulIndex = ulRegBase + pjRegTable->ulIndex;
20217+
20218+ ulBack = *(unsigned long *) (ulIndex);
20219+
20220+ ulMask = pjRegTable->ulMask;
20221+ ulAND = ~pjRegTable->ulMask;
20222+
20223+ ulData = 0xFFFFFFFF & pjRegTable->ulMask;
20224+ *(unsigned long *) (ulIndex) = ulData;
20225+ ulTemp = *(volatile unsigned long *) (ulIndex) & pjRegTable->ulMask;
20226+ if (ulData != ulTemp)
20227+ {
20228+ Flags |= pjSOCRegInfo->ulFlags;
20229+ printf("[DBG] RegTest: Failed Index:%x, Data:%x, Temp:%x \n", ulIndex, ulData, ulTemp);
20230+ }
20231+
20232+ ulData = 0x00000000 & pjRegTable->ulMask;
20233+ *(unsigned long *) (ulIndex) = ulData;
20234+ ulTemp = *(volatile unsigned long *) (ulIndex) & pjRegTable->ulMask;
20235+ if (ulData != ulTemp)
20236+ {
20237+ Flags |= pjSOCRegInfo->ulFlags;
20238+ printf("[DBG] RegTest: Failed Index:%x, Data:%x, Temp:%x \n", ulIndex, ulData, ulTemp);
20239+ }
20240+
20241+ *(unsigned long *) (ulIndex) = ulBack;
20242+
20243+ pjRegTable++;
20244+
20245+ } /* Individual Reg. Test */
20246+
20247+ if (Flags & pjSOCRegInfo->ulFlags)
20248+ printf("[INFO] RegTest: %s Failed \n", pjSOCRegInfo->jName);
20249+
20250+ pjSOCRegInfo++;
20251+
20252+ } /* Reg. Test */
20253+
20254+ return Flags;
20255+
20256+}
20257+
20258+#endif /* CONFIG_SLT */
20259diff --git a/board/aspeed/ast2300/regtest.h b/board/aspeed/ast2300/regtest.h
20260new file mode 100755
20261index 0000000..49a360e
20262--- /dev/null
20263+++ b/board/aspeed/ast2300/regtest.h
20264@@ -0,0 +1,255 @@
20265+/*
20266+ * This program is distributed in the hope that it will be useful,
20267+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20268+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20269+ * GNU General Public License for more details.
20270+ *
20271+ * You should have received a copy of the GNU General Public License
20272+ * along with this program; if not, write to the Free Software
20273+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20274+ */
20275+typedef struct {
20276+ unsigned long ulIndex;
20277+ unsigned long ulMask;
20278+} _SOCRegTestTbl;
20279+
20280+typedef struct {
20281+ unsigned char jName[10];
20282+ unsigned long ulRegOffset;
20283+ _SOCRegTestTbl *pjTblIndex;
20284+ unsigned long ulFlags;
20285+} _SOCRegTestInfo;
20286+
20287+_SOCRegTestTbl SMCRegTestTbl[] = {
20288+ {0x00000000, 0x00001FF3},
20289+ {0x00000004, 0xFFFFFFFF},
20290+ {0x00000008, 0x0FFF17FF},
20291+ {0x0000000C, 0xFFFFFFFF},
20292+ {0x00000010, 0xFF5FFFF3},
20293+ {0x00000018, 0x0FFFFFFF},
20294+ {0xFFFFFFFF, 0xFFFFFFFF},
20295+};
20296+
20297+_SOCRegTestTbl AHBCRegTestTbl[] = {
20298+ {0x00000080, 0x0000FFFE},
20299+ {0x00000088, 0x01000000},
20300+ {0x0000008c, 0x00000031},
20301+ {0xFFFFFFFF, 0xFFFFFFFF},
20302+};
20303+
20304+_SOCRegTestTbl MICRegTestTbl[] = {
20305+/*
20306+ {0x00000000, 0x0FFFFFF8},
20307+ {0x00000004, 0x0FFFFFF8},
20308+ {0x00000008, 0x0000FFFF},
20309+ {0x0000000C, 0x0FFFF000},
20310+ {0x00000010, 0xFFFFFFFF},
20311+*/
20312+ {0xFFFFFFFF, 0xFFFFFFFF},
20313+};
20314+
20315+_SOCRegTestTbl MAC1RegTestTbl[] = {
20316+ {0xFFFFFFFF, 0xFFFFFFFF},
20317+};
20318+
20319+_SOCRegTestTbl MAC2RegTestTbl[] = {
20320+ {0xFFFFFFFF, 0xFFFFFFFF},
20321+};
20322+
20323+_SOCRegTestTbl USB2RegTestTbl[] = {
20324+ {0xFFFFFFFF, 0xFFFFFFFF},
20325+};
20326+
20327+_SOCRegTestTbl VICRegTestTbl[] = {
20328+ {0x0000000C, 0xFFFFFFFF},
20329+ {0x00000024, 0xFFFFFFFF},
20330+ {0x00000028, 0xFFFFFFFF},
20331+ {0x0000002C, 0xFFFFFFFF},
20332+ {0xFFFFFFFF, 0xFFFFFFFF},
20333+};
20334+
20335+_SOCRegTestTbl MMCRegTestTbl[] = {
20336+ {0xFFFFFFFF, 0xFFFFFFFF},
20337+};
20338+
20339+_SOCRegTestTbl USB11RegTestTbl[] = {
20340+ {0xFFFFFFFF, 0xFFFFFFFF},
20341+};
20342+
20343+_SOCRegTestTbl SCURegTestTbl[] = {
20344+ {0xFFFFFFFF, 0xFFFFFFFF},
20345+};
20346+
20347+_SOCRegTestTbl HASERegTestTbl[] = {
20348+ {0x00000000, 0x0FFFFFF8},
20349+ {0x00000004, 0x0FFFFFF8},
20350+ {0x00000008, 0x0FFFFFF8},
20351+ {0x0000000C, 0x0FFFFFF8},
20352+ //{0x00000010, 0x00001FFF},
20353+ {0x00000020, 0x0FFFFFF8},
20354+ {0x00000024, 0x0FFFFFF8},
20355+ {0x00000028, 0x0FFFFFc0},
20356+ {0x0000002C, 0x0FFFFFFF},
20357+ //{0x00000030, 0x000003FF},
20358+ {0xFFFFFFFF, 0xFFFFFFFF},
20359+};
20360+
20361+_SOCRegTestTbl I2SRegTestTbl[] = {
20362+ {0xFFFFFFFF, 0xFFFFFFFF},
20363+};
20364+
20365+_SOCRegTestTbl CRTRegTestTbl[] = {
20366+/*
20367+ {0x00000000, 0x001F3703},
20368+ {0x00000004, 0x0000FFC1},
20369+*/
20370+ {0x00000010, 0x0FFF0FFF},
20371+ {0x00000014, 0x0FFF0FFF},
20372+ {0x00000018, 0x07FF07FF},
20373+ {0x0000001C, 0x07FF07FF},
20374+ {0x00000020, 0x0FFFFFF8},
20375+ {0x00000024, 0x07FF3FF8},
20376+/*
20377+ {0x00000028, 0x003F003F},
20378+ {0x00000030, 0x003F003F},
20379+ {0x00000034, 0x0FFF0FFF},
20380+ {0x00000038, 0x0FFFFFF8},
20381+*/
20382+ {0x00000040, 0x0FFF0FFF},
20383+ {0x00000044, 0x07FF07FF},
20384+ {0x00000048, 0x0FFFFFF8},
20385+ {0x0000004C, 0x00FF07F8},
20386+ {0x00000050, 0x000F0F0F},
20387+/*
20388+ {0x00000060, 0x001F3703},
20389+ {0x00000064, 0x0000FFC1},
20390+*/
20391+ {0x00000070, 0x0FFF0FFF},
20392+ {0x00000074, 0x0FFF0FFF},
20393+ {0x00000078, 0x07FF07FF},
20394+ {0x0000007C, 0x07FF07FF},
20395+ {0x00000080, 0x0FFFFFF8},
20396+ {0x00000084, 0x07FF3FF8},
20397+/*
20398+ {0x00000088, 0x003F003F},
20399+ {0x00000090, 0x003F003F},
20400+ {0x00000094, 0x0FFF0FFF},
20401+ {0x00000098, 0x0FFFFFF8},
20402+*/
20403+ {0x000000A0, 0x0FFF0FFF},
20404+ {0x000000A4, 0x07FF07FF},
20405+ {0x000000A8, 0x0FFFFFF8},
20406+ {0x000000AC, 0x00FF07F8},
20407+ {0x000000B0, 0x000F0F0F},
20408+ {0xFFFFFFFF, 0xFFFFFFFF},
20409+};
20410+
20411+_SOCRegTestTbl VIDEORegTestTbl[] = {
20412+ {0xFFFFFFFF, 0xFFFFFFFF},
20413+};
20414+
20415+_SOCRegTestTbl A2PRegTestTbl[] = {
20416+ {0xFFFFFFFF, 0xFFFFFFFF},
20417+};
20418+
20419+_SOCRegTestTbl MDMARegTestTbl[] = {
20420+ {0xFFFFFFFF, 0xFFFFFFFF},
20421+};
20422+
20423+_SOCRegTestTbl M2DRegTestTbl[] = {
20424+ {0xFFFFFFFF, 0xFFFFFFFF},
20425+};
20426+
20427+_SOCRegTestTbl GPIORegTestTbl[] = {
20428+ {0xFFFFFFFF, 0xFFFFFFFF},
20429+};
20430+
20431+_SOCRegTestTbl RTCRegTestTbl[] = {
20432+ {0xFFFFFFFF, 0xFFFFFFFF},
20433+};
20434+
20435+_SOCRegTestTbl TIMERRegTestTbl[] = {
20436+ {0xFFFFFFFF, 0xFFFFFFFF},
20437+};
20438+
20439+_SOCRegTestTbl UART1RegTestTbl[] = {
20440+ {0xFFFFFFFF, 0xFFFFFFFF},
20441+};
20442+
20443+_SOCRegTestTbl UART2RegTestTbl[] = {
20444+ {0xFFFFFFFF, 0xFFFFFFFF},
20445+};
20446+
20447+_SOCRegTestTbl WDTRegTestTbl[] = {
20448+ {0xFFFFFFFF, 0xFFFFFFFF},
20449+};
20450+
20451+_SOCRegTestTbl PWMRegTestTbl[] = {
20452+ {0xFFFFFFFF, 0xFFFFFFFF},
20453+};
20454+
20455+_SOCRegTestTbl VUART1RegTestTbl[] = {
20456+ {0xFFFFFFFF, 0xFFFFFFFF},
20457+};
20458+
20459+_SOCRegTestTbl VUART2RegTestTbl[] = {
20460+ {0xFFFFFFFF, 0xFFFFFFFF},
20461+};
20462+
20463+_SOCRegTestTbl LPCRegTestTbl[] = {
20464+ {0xFFFFFFFF, 0xFFFFFFFF},
20465+};
20466+
20467+_SOCRegTestTbl I2CRegTestTbl[] = {
20468+ {0xFFFFFFFF, 0xFFFFFFFF},
20469+};
20470+
20471+_SOCRegTestTbl PECIRegTestTbl[] = {
20472+ {0xFFFFFFFF, 0xFFFFFFFF},
20473+};
20474+
20475+_SOCRegTestTbl PCIARegTestTbl[] = {
20476+ {0xFFFFFFFF, 0xFFFFFFFF},
20477+};
20478+
20479+_SOCRegTestTbl PCIRegTestTbl[] = {
20480+ {0xFFFFFFFF, 0xFFFFFFFF},
20481+};
20482+
20483+
20484+/* Test List */
20485+_SOCRegTestInfo SOCRegTestInfo[] = {
20486+ /* Test Name, Reg. Offset, Test Table, Error Code */
20487+ { "SMCREG", 0x16000000, SMCRegTestTbl, 0x00000001},
20488+ { "AHBCREG", 0x1e600000, AHBCRegTestTbl, 0x00000002},
20489+ { "MICREG", 0x1e640000, MICRegTestTbl, 0x00000004},
20490+ { "MAC1REG", 0x1e660000, MAC1RegTestTbl, 0x00000008},
20491+ { "MAC2REG", 0x1e680000, MAC2RegTestTbl, 0x00000010},
20492+ { "USB2REG", 0x1e6a0000, USB2RegTestTbl, 0x00000020},
20493+ { "VICREG", 0x1e6c0000, VICRegTestTbl, 0x00000040},
20494+ { "MMCREG", 0x1e6e0000, MMCRegTestTbl, 0x00000080},
20495+ { "USB11REG", 0x1e6e1000, USB11RegTestTbl, 0x00000100},
20496+ { "SCUREG", 0x1e6e2000, SCURegTestTbl, 0x00000200},
20497+ { "HASEREG", 0x1e6e3000, HASERegTestTbl, 0x00000400},
20498+ { "I2SREG", 0x1e6e5000, I2SRegTestTbl, 0x00000800},
20499+ { "CRTREG", 0x1e6e6000, CRTRegTestTbl, 0x00001000},
20500+ { "VIDEOREG", 0x1e700000, VIDEORegTestTbl, 0x00002000},
20501+ { "A2PREG", 0x1e720000, A2PRegTestTbl, 0x00004000},
20502+ { "MDMAREG", 0x1e740000, MDMARegTestTbl, 0x00008000},
20503+ { "2DREG", 0x1e760000, M2DRegTestTbl, 0x00010000},
20504+ { "GPIOREG", 0x1e780000, GPIORegTestTbl, 0x00020000},
20505+ { "RTCREG", 0x1e781000, RTCRegTestTbl, 0x00040000},
20506+ { "TIMERREG", 0x1e782000, TIMERRegTestTbl, 0x00080000},
20507+ { "UART1REG", 0x1e783000, UART1RegTestTbl, 0x00100000},
20508+ { "UART2REG", 0x1e784000, UART2RegTestTbl, 0x00200000},
20509+ { "WDTREG", 0x1e785000, WDTRegTestTbl, 0x00400000},
20510+ { "PWMREG", 0x1e786000, PWMRegTestTbl, 0x00800000},
20511+ {"VUART1REG", 0x1e787000, VUART1RegTestTbl, 0x01000000},
20512+ {"VUART2REG", 0x1e788000, VUART2RegTestTbl, 0x02000000},
20513+ { "LPCREG", 0x1e789000, LPCRegTestTbl, 0x04000000},
20514+ { "I2CREG", 0x1e78A000, I2CRegTestTbl, 0x08000000},
20515+ { "PECIREG", 0x1e78B000, PECIRegTestTbl, 0x10000000},
20516+ { "PCIAREG", 0x1e78C000, PCIARegTestTbl, 0x20000000},
20517+ { "PCIREG", 0x60000000, PCIRegTestTbl, 0x40000000},
20518+ { "END", 0xffffffff, NULL, 0xffffffff}
20519+};
20520diff --git a/board/aspeed/ast2300/slt.c b/board/aspeed/ast2300/slt.c
20521new file mode 100755
20522index 0000000..3283d34
20523--- /dev/null
20524+++ b/board/aspeed/ast2300/slt.c
20525@@ -0,0 +1,105 @@
20526+/*
20527+ * This program is distributed in the hope that it will be useful,
20528+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20529+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20530+ * GNU General Public License for more details.
20531+ *
20532+ * You should have received a copy of the GNU General Public License
20533+ * along with this program; if not, write to the Free Software
20534+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20535+ * MA 02111-1307 USA
20536+ */
20537+
20538+/*
20539+ * Diagnostics support
20540+ */
20541+#include <common.h>
20542+#include <command.h>
20543+#include <post.h>
20544+#include "slt.h"
20545+
20546+#if defined (CONFIG_SLT)
20547+
20548+int do_slt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
20549+{
20550+ int flags = 0;
20551+ int loop = 1;
20552+
20553+ if (argc > 1) {
20554+ loop = simple_strtoul(argv[1], NULL, 10);
20555+ }
20556+
20557+ do {
20558+
20559+do_slt_start:
20560+ /* Reg. Test */
20561+#if (CFG_CMD_SLT & CFG_CMD_REGTEST)
20562+ if (do_regtest())
20563+ {
20564+ flags |= FLAG_REGTEST_FAIL;
20565+ printf("[INFO] RegTest Failed \n");
20566+ }
20567+ else
20568+ printf("[INFO] RegTest Passed \n");
20569+#endif
20570+#if (CFG_CMD_SLT & CFG_CMD_MACTEST)
20571+ if (do_mactest())
20572+ {
20573+ flags |= FLAG_MACTEST_FAIL;
20574+ printf("[INFO] MACTest Failed \n");
20575+ }
20576+ else
20577+ printf("[INFO] MACTest Passed \n");
20578+#endif
20579+#if (CFG_CMD_SLT & CFG_CMD_VIDEOTEST)
20580+ if (do_videotest())
20581+ {
20582+ flags |= FLAG_VIDEOTEST_FAIL;
20583+ printf("[INFO] VideoTest Failed \n");
20584+ }
20585+ else
20586+ printf("[INFO] VideoTest Passed \n");
20587+#endif
20588+#if (CFG_CMD_SLT & CFG_CMD_HACTEST)
20589+ if (do_hactest())
20590+ {
20591+ flags |= FLAG_HACTEST_FAIL;
20592+ printf("[INFO] HACTest Failed \n");
20593+ }
20594+ else
20595+ printf("[INFO] HACTest Passed \n");
20596+#endif
20597+#if (CFG_CMD_SLT & CFG_CMD_MICTEST)
20598+ if (do_mictest())
20599+ {
20600+ flags |= FLAG_MICTEST_FAIL;
20601+ printf("[INFO] MICTest Failed \n");
20602+ }
20603+ else
20604+ printf("[INFO] MICTest Passed \n");
20605+#endif
20606+
20607+ /* Summary */
20608+ if (flags)
20609+ printf ("[INFO] SLT Test Failed!! \n");
20610+ else
20611+ printf ("[INFO] SLT Test Passed!! \n");
20612+
20613+ if (loop == 0) /* infinite */
20614+ goto do_slt_start;
20615+ else
20616+ loop--;
20617+
20618+ } while (loop);
20619+
20620+ return 0;
20621+}
20622+/***************************************************/
20623+
20624+U_BOOT_CMD(
20625+ slt, CONFIG_SYS_MAXARGS, 0, do_slt,
20626+ "slt - slt test program \n",
20627+ NULL
20628+);
20629+
20630+#endif /* CONFIG_SLT */
20631diff --git a/board/aspeed/ast2300/slt.h b/board/aspeed/ast2300/slt.h
20632new file mode 100755
20633index 0000000..4e650bc
20634--- /dev/null
20635+++ b/board/aspeed/ast2300/slt.h
20636@@ -0,0 +1,29 @@
20637+/*
20638+ * This program is distributed in the hope that it will be useful,
20639+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20640+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20641+ * GNU General Public License for more details.
20642+ *
20643+ * You should have received a copy of the GNU General Public License
20644+ * along with this program; if not, write to the Free Software
20645+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20646+ */
20647+#define CFG_CMD_REGTEST 0x00000001
20648+#define CFG_CMD_MACTEST 0x00000002
20649+#define CFG_CMD_VIDEOTEST 0x00000004
20650+#define CFG_CMD_HACTEST 0x00000008
20651+#define CFG_CMD_MICTEST 0x00000010
20652+#define CFG_CMD_OSDTEST 0x00000020
20653+#define CFG_CMD_2DTEST 0x00000040
20654+#define CFG_CMD_HWCTEST 0x00000080
20655+
20656+#define FLAG_REGTEST_FAIL 0x00000001
20657+#define FLAG_MACTEST_FAIL 0x00000002
20658+#define FLAG_VIDEOTEST_FAIL 0x00000004
20659+#define FLAG_HACTEST_FAIL 0x00000008
20660+#define FLAG_MICTEST_FAIL 0x00000010
20661+#define FLAG_OSDTEST_FAIL 0x00000020
20662+#define FLAG_2DTEST_FAIL 0x00000040
20663+#define FLAG_HWCTEST_FAIL 0x00000080
20664+
20665+
20666diff --git a/board/aspeed/ast2300/type.h b/board/aspeed/ast2300/type.h
20667new file mode 100755
20668index 0000000..f57ee5a
20669--- /dev/null
20670+++ b/board/aspeed/ast2300/type.h
20671@@ -0,0 +1,116 @@
20672+/*
20673+ * This program is distributed in the hope that it will be useful,
20674+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20675+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20676+ * GNU General Public License for more details.
20677+ *
20678+ * You should have received a copy of the GNU General Public License
20679+ * along with this program; if not, write to the Free Software
20680+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20681+ */
20682+#ifndef _TYPE_H_
20683+#define _TYPE_H_
20684+
20685+ typedef unsigned char BOOL;
20686+ typedef unsigned char UINT8;
20687+ typedef unsigned short UINT16;
20688+ typedef unsigned int UINT32;
20689+
20690+ #define FLONG unsigned long
20691+ #define BYTE unsigned char
20692+ #define INT int
20693+ #define VOID void
20694+ #define BOOLEAN unsigned short
20695+ #define ULONG unsigned long
20696+ #define USHORT unsigned short
20697+ #define UCHAR unsigned char
20698+ #define CHAR char
20699+ #define LONG long
20700+ #define PUCHAR UCHAR *
20701+ #define PULONG ULONG *
20702+
20703+ #define FAIL 1
20704+
20705+ #define intfunc int386
20706+
20707+ #define outdwport outpd
20708+ #define indwport inpd
20709+ #define outport outp
20710+ #define inport inp
20711+
20712+ //#define NULL ((void *)0)
20713+ #define FALSE 0
20714+ #define TRUE 1
20715+
20716+ #define ReadMemoryBYTE(baseaddress,offset) *(BYTE *)((ULONG)(baseaddress)+(ULONG)(offset))
20717+ #define ReadMemoryLong(baseaddress,offset) *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
20718+ #define ReadMemoryShort(baseaddress,offset) *(USHORT *)((ULONG)(baseaddress)+(ULONG)(offset))
20719+ #define WriteMemoryBYTE(baseaddress,offset,data) *(BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)
20720+ #define WriteMemoryLong(baseaddress,offset,data) *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
20721+ #define WriteMemoryShort(baseaddress,offset,data) *(USHORT *)((ULONG)(baseaddress)+(ULONG)(offset))=(USHORT)(data)
20722+ #define WriteMemoryLongWithANDData(baseaddress, offset, anddata, data) *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) & (ULONG)(anddata) | (ULONG)(data)
20723+
20724+ #define WriteMemoryLongWithMASK(baseaddress, offset, data, mask) \
20725+ *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = *(volatile ULONG *)(((ULONG)(baseaddress)+(ULONG)(offset)) & (ULONG)(~(mask))) | ((ULONG)(data) & (ULONG)(mask))
20726+
20727+ #define ReadMemoryLongHost(baseaddress,offset) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
20728+ #define WriteMemoryLongHost(baseaddress,offset,data) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
20729+ #define WriteMemoryBYTEHost(baseaddress,offset,data) *(volatile BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)
20730+#define WriteMemoryLongWithMASKHost(baseaddress, offset, data, mask) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = (((*(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)))&(~mask)) | (ULONG)((data)&(mask)))
20731+
20732+ #define ReadMemoryLongClient(baseaddress,offset) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
20733+ #define WriteMemoryLongClient(baseaddress,offset,data) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
20734+ #define WriteMemoryBYTEClient(baseaddress,offset,data) *(volatile BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)
20735+#define WriteMemoryLongWithMASKClient(baseaddress, offset, data, mask) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = (((*(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)))&(~mask)) | (ULONG)((data)&(mask)))
20736+
20737+#ifdef BUF_GLOBALS
20738+#define BUF_EXT
20739+#else
20740+#define BUF_EXT extern
20741+#endif
20742+
20743+BUF_EXT ULONG g_CAPTURE_VIDEO1_BUF1_ADDR; /* VIDEO1_BUF_1_ADDR*/
20744+BUF_EXT ULONG g_CAPTURE_VIDEO1_BUF2_ADDR; /* VIDEO1_BUF_2_ADDR*/
20745+BUF_EXT ULONG g_VIDEO1_COMPRESS_BUF_ADDR; /* Encode destination address */
20746+BUF_EXT ULONG g_VIDEO1_CRC_BUF_ADDR;
20747+BUF_EXT ULONG g_VIDEO1_FLAG_BUF_ADDR;
20748+BUF_EXT ULONG g_VIDEO1_RC4_BUF_ADDR;
20749+
20750+
20751+BUF_EXT ULONG g_CAPTURE_VIDEO2_BUF1_ADDR;
20752+BUF_EXT ULONG g_CAPTURE_VIDEO2_BUF2_ADDR;
20753+BUF_EXT ULONG g_VIDEO2_COMPRESS_BUF_ADDR;
20754+BUF_EXT ULONG g_VIDEO2_CRC_BUF_ADDR;
20755+BUF_EXT ULONG g_VIDEO2_FLAG_BUF_ADDR;
20756+BUF_EXT ULONG g_VIDEO2_RC4_BUF_ADDR;
20757+
20758+BUF_EXT ULONG g_VIDEO1_DECODE_BUF_1_ADDR;
20759+BUF_EXT ULONG g_VIDEO1_DECODE_BUF_2_ADDR;
20760+BUF_EXT ULONG g_VIDEO1_DECOMPRESS_BUF_ADDR;
20761+BUF_EXT ULONG g_VIDEO1_DECODE_RC4_BUF_ADDR;
20762+
20763+BUF_EXT ULONG g_VIDEO2_DECODE_BUF_1_ADDR;
20764+BUF_EXT ULONG g_VIDEO2_DECODE_BUF_2_ADDR;
20765+BUF_EXT ULONG g_VIDEO2_DECOMPRESS_BUF_ADDR;
20766+BUF_EXT ULONG g_VIDEO2_DECODE_RC4_BUF_ADDR;
20767+
20768+BUF_EXT ULONG g_CAPTURE_VIDEOM_BUF1_ADDR;
20769+BUF_EXT ULONG g_CAPTURE_VIDEOM_BUF2_ADDR;
20770+BUF_EXT ULONG g_VIDEOM_COMPRESS_BUF_ADDR;
20771+BUF_EXT ULONG g_VIDEOM_FLAG_BUF_ADDR;
20772+BUF_EXT ULONG g_VIDEOM_RC4_BUF_ADDR;
20773+
20774+BUF_EXT ULONG g_VIDEOM_DECODE_BUF_1_ADDR;
20775+BUF_EXT ULONG g_VIDEOM_DECODE_BUF_2_ADDR;
20776+BUF_EXT ULONG g_VIDEOM_DECOMPRESS_BUF_ADDR;
20777+BUF_EXT ULONG g_VIDEOM_DECODE_RC4_BUF_ADDR;
20778+
20779+#ifdef WIN_GLOBALS
20780+#define WIN_EXT
20781+#else
20782+#define WIN_EXT extern
20783+#endif
20784+
20785+WIN_EXT USHORT g_DefWidth, g_DefHeight;
20786+
20787+#endif
20788diff --git a/board/aspeed/ast2300/u-boot.lds b/board/aspeed/ast2300/u-boot.lds
20789new file mode 100755
20790index 0000000..b5a90ef
20791--- /dev/null
20792+++ b/board/aspeed/ast2300/u-boot.lds
20793@@ -0,0 +1,45 @@
20794+/*
20795+ * This program is distributed in the hope that it will be useful,
20796+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20797+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20798+ * GNU General Public License for more details.
20799+ *
20800+ * You should have received a copy of the GNU General Public License
20801+ * along with this program; if not, write to the Free Software
20802+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20803+ * MA 02111-1307 USA
20804+ */
20805+
20806+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
20807+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
20808+OUTPUT_ARCH(arm)
20809+ENTRY(_start)
20810+SECTIONS
20811+{
20812+ . = 0x00000000;
20813+
20814+ . = ALIGN(4);
20815+ .text :
20816+ {
20817+ cpu/arm926ejs/start.o (.text)
20818+ *(.text)
20819+ }
20820+
20821+ . = ALIGN(4);
20822+ .rodata : { *(.rodata) }
20823+
20824+ . = ALIGN(4);
20825+ .data : { *(.data) }
20826+
20827+ . = ALIGN(4);
20828+ .got : { *(.got) }
20829+
20830+ __u_boot_cmd_start = .;
20831+ .u_boot_cmd : { *(.u_boot_cmd) }
20832+ __u_boot_cmd_end = .;
20833+
20834+ . = ALIGN(4);
20835+ __bss_start = .;
20836+ .bss : { *(.bss) }
20837+ _end = .;
20838+}
20839diff --git a/board/aspeed/ast2300/vdef.h b/board/aspeed/ast2300/vdef.h
20840new file mode 100755
20841index 0000000..3c99b7e
20842--- /dev/null
20843+++ b/board/aspeed/ast2300/vdef.h
20844@@ -0,0 +1,500 @@
20845+/*
20846+ * This program is distributed in the hope that it will be useful,
20847+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
20848+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20849+ * GNU General Public License for more details.
20850+ *
20851+ * You should have received a copy of the GNU General Public License
20852+ * along with this program; if not, write to the Free Software
20853+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20854+ */
20855+#ifndef _VDEF_H_
20856+#define _VDEF_H_
20857+
20858+#define VIDEO1 0
20859+#define VIDEO1_ON 0x01
20860+#define VIDEO2 1
20861+#define VIDEO2_ON 0x02
20862+
20863+#define VIDEOM_ON 0x04
20864+#define VIDEOM 2
20865+
20866+#define CRT_1 0
20867+#define CRT_1_ON 0x01
20868+#define CRT_2 1
20869+#define CRT_2_ON 0x02
20870+
20871+#define SINGLE_CODEC_SINGLE_CAPTURE 0
20872+#define AUTO_CODEC_SINGLE_CAPTURE 2
20873+#define AUTO_CODEC_AUTO_CAPTURE 3
20874+
20875+#define MAC1_BASE 0x1E660000
20876+#define APB_BRIDGE_1_BASE 0x1E6E0000
20877+#define VIDEO_REG_BASE 0x1E700000
20878+#define APB_BRIDGE_2_BASE 0x1E780000
20879+
20880+#define DRAM_INIT_BASE 0x1E6E0000
20881+
20882+#define SDRAM_PROTECT_REG 0x00
20883+ #define SDRAM_WRITE_DISABLE 0
20884+ #define SDRAM_WRITE_ENABLE 1
20885+
20886+#define SCU_BASE 0x1E6E0000
20887+#define SCU_OFFSET 0x2000
20888+
20889+#define VIC_BASE 0x1E6C0000
20890+ #define VIDEO_INT_BIT 7
20891+
20892+#define IRQ_STATUS_REG 0x00
20893+#define RAW_INT_STATUS_REG 0x08
20894+#define INT_SEL_REG 0x0C
20895+ #define FIQ_INT 1
20896+ #define IRQ_INT 0
20897+#define INT_EN_REG 0x10
20898+#define INT_EN_CLEAR_REG 0x14
20899+#define INT_SOFT_REG 0x18
20900+#define INT_SOFT_CLEAR_REG 0x1C
20901+#define INT_SENSE_REG 0x24
20902+ #define LEVEL_SENSE 1
20903+ #define EDGE_SENSE 0
20904+#define INT_EVENT_REG 0x2C
20905+ #define HIGH_LEVEL_SENSE 1
20906+ #define LOW_LEVEL_SENSE 0
20907+
20908+#define SCU_HW_TRAPPING_REG 0x70 + SCU_OFFSET
20909+ #define CLIENT_MODE_EN_BIT 18
20910+ #define CLIENT_MODE_EN_MASK 0x00040000
20911+ #define BE_HOST_CHIP 0
20912+ #define BE_CLIENT_CHIP 1
20913+
20914+#define SCU_ULOCK_KEY 0x1688A8A8
20915+
20916+#define SCU_PROTECT_REG 0x00 + SCU_OFFSET
20917+ #define SCU_WRITE_DISABLE 0
20918+ #define SCU_WRITE_ENABLE 1
20919+
20920+#define SCU_CONTROL_REG 0x04 + SCU_OFFSET
20921+ #define VIDEO_ENGINE_RESET 0x00000040
20922+ #define VIDEO_ENGINE_RESET_BIT 6
20923+ #define VIDEO_ENGINE_RESET_MASK 0x00000040
20924+ #define VIDEO_RESET_EN 1
20925+ #define VIDEO_RESET_OFF 0
20926+
20927+#define SCU_CLOCK_SELECTION_REG 0x08 + SCU_OFFSET
20928+ #define PORTA_CLOCK_DELAY_MASK 7 << 8 //Video port A output clcok selection
20929+ #define PORTA_CLOCK_INV_DELAY_1NS 5 << 8 //Clock inversed and delay ~ 2ns
20930+ #define PORTA_CLOCK_INV_DELAY_2NS 6 << 8 //Clock inversed and delay ~ 3ns
20931+ #define PORTB_CLOCK_DELAY_MASK 7 << 12 //Video port B output clock delay
20932+ #define PORTB_CLOCK_INV_DELAY_1NS 5 << 12 //Clock inversed and delay ~ 3ns
20933+ #define PORTB_CLOCK_INV_DELAY_2NS 6 << 12 //Clock inversed and delay ~ 3ns
20934+ #define PORTB_CLOCK_SEL 1 << 15 //Video port B clock selection
20935+ #define PORTB_FROM_D1CLK 0 << 15
20936+ #define PORTB_FROM_D2CLK 1 << 15
20937+ #define ECLK_CLK_SEL_MASK (3 << 2)
20938+ #define ECLK_FROM_HPLL (1 << 2)
20939+
20940+ #define D2CLK_CLOCK_SELECTION 0x00020000
20941+ #define D2CLK_CLOCK_SELECTION_BIT 17
20942+ #define D2CLK_CLOCK_SELECTION_MASK 0x00060000
20943+ #define NORMAL_CRT1 0
20944+ #define V1CLK_VIDEO1 2
20945+ #define V1CLK_VIDEO2 3
20946+
20947+#define SCU_CLOCK_STOP_REG 0x0C + SCU_OFFSET
20948+ #define EN_ECLK 0 << 0 //Enable ECLK (For Video Engine)
20949+ #define STOP_ECLK_BIT 0
20950+ #define STOP_ECLK_MASK 1 << 0
20951+ #define EN_V1CLK 0 << 3 //Enable V1CLK (For Video Capture #1)
20952+ #define STOP_V1CLK_BIT 3
20953+ #define STOP_V1CLK_MASK 1 << 3
20954+ #define EN_D1CLK 0 << 10 //Enable D1CLK (For CRT1)
20955+ #define STOP_D1CLK_BIT 10
20956+ #define STOP_D1CLK_MASK 1 << 10
20957+ #define EN_D2CLK 0 << 11 //Stop D2CLK (For CRT2)
20958+ #define STOP_D2CLK (1 << 11)
20959+ #define STOP_D2CLK_BIT 11
20960+ #define STOP_D2CLK_MASK 1 << 11
20961+ #define EN_V2CLK 0 << 12 //Stop V2CLK (For Video Capture #2)
20962+ #define STOP_V2CLK_BIT 12
20963+ #define STOP_V2CLK_MASK 1 << 12
20964+ #define STOP_HACE_BIT 13
20965+ #define EN_HACE (0 << 13)
20966+ #define STOP_HACE_MASK (1 << 13)
20967+ #define EN_I2SCLK 0 << 18
20968+ #define STOP_I2SCLK_MASK 1 << 18
20969+
20970+#define SCU_PIN_CTRL1_REG 0x74 + SCU_OFFSET
20971+ #define I2C_5_PIN_EN 1 << 12 //Enable I2C #5 PIN
20972+ #define I2C_5_PIN_OFF 0 << 12 //Disable I2C #5 PIN
20973+ #define I2C_5_PIN_MASK 1 << 12
20974+ #define VGA_PIN_OFF 0 << 15 //Enable VGA pins
20975+ #define VGA_PIN_MASK 1 << 15
20976+ #define VIDEO_PORTA_EN 1 << 16 //Enable Video port A control pins
20977+ #define VIDEO_PORTA_MASK 1 << 16
20978+ #define VIDEO_PORTB_EN 1 << 17 //Enable Video port B control pins
20979+ #define VIDEO_PORTB_MASK 1 << 17
20980+ #define VIDEO_VP1_EN 1 << 22 //Enable VP[11:0]
20981+ #define VIDEO_VP1_MASK 1 << 22
20982+ #define VIDEO_VP2_EN 1 << 23 //Enable VP[23:12]
20983+ #define VIDEO_VP2_MASK 1 << 23
20984+ #define I2S_PIN_EN 1 << 29 //Enable I2S function pins
20985+ #define I2S_PIN_MASK 1 << 29
20986+
20987+#define SCU_PIN_CTRL2_REG 0x78 + SCU_OFFSET
20988+ #define VIDEO_PORTA_SINGLE_EDGE_MASK 1 << 0
20989+ #define VIDEO_PORTA_SINGLE_EDGE 1 << 0 //Enable Video port A single mode
20990+ #define VIDEO_PORTA_DUAL_EDGE 0 << 0
20991+ #define VIDEO_PORTB_SINGLE_EDGE_MASK 1 << 1
20992+ #define VIDEO_PORTB_DUAL_EDGE 0 << 1
20993+ #define VIDEO_PORTB_SINGLE_EDGE 1 << 1 //Enable Video port B single mode
20994+
20995+#define SCU_M_PLL_PARAM_REG 0x20 + SCU_OFFSET
20996+
20997+#define DRAM_BASE 0x40000000
20998+
20999+#define INPUT_BITCOUNT_YUV444 4
21000+#define INPUT_BITCOUNT_YUV420 2
21001+
21002+/* HW comment value */
21003+//PASSWORD
21004+#define VIDEO_UNLOCK_KEY 0x1A038AA8
21005+#define SCU_UNLOCK_KEY 0x1688A8A8
21006+#define SDRAM_UNLOCK_KEY 0xFC600309
21007+
21008+
21009+//#define SAMPLE_RATE 12000000.0
21010+#ifdef OSC_NEW
21011+ #define SAMPLE_RATE 24576000.0
21012+#else
21013+ #define SAMPLE_RATE 24000000.0
21014+#endif
21015+
21016+#define MODEDETECTION_VERTICAL_STABLE_MAXIMUM 0x4
21017+#define MODEDETECTION_HORIZONTAL_STABLE_MAXIMUM 0x4
21018+#define MODEDETECTION_VERTICAL_STABLE_THRESHOLD 0x4
21019+#define MODEDETECTION_HORIZONTAL_STABLE_THRESHOLD 0x8
21020+
21021+#define MODEDETECTION_EDGE_PIXEL_THRES_DIGITAL 2
21022+#define MODEDETECTION_EDGE_PIXEL_THRES_ANALOGE 0x0A
21023+
21024+#define MODEDETECTION_OK 0
21025+#define MODEDETECTION_ERROR 1
21026+#define JUDGE_MODE_ERROR 2
21027+
21028+//I2C Loop Count
21029+#define LOOP_COUNT 1000
21030+#define CAN_NOT_FIND_DEVICE 1
21031+#define SET_I2C_DONE 0
21032+#define I2C_BASE 0xA000
21033+#define AC_TIMING 0x77743355
21034+
21035+//I2C channel and Devices
21036+#define I2C_VIDEO1_EEPROM 0x2
21037+#define I2C_VIDEO2_EEPROM 0x5
21038+#define I2C_VIDEO2_9883 0x4
21039+/*
21040+ULONG CAPTURE1_ADDRESS = 0x1000000;
21041+ULONG CAPTURE2_ADDRESS = 0x3000000;
21042+ULONG PASS1_ENCODE_SOURCE_ADDRESS = 0x1000000;
21043+ULONG PASS1_ENCODE_DESTINATION_ADDRESS = 0x2000000;
21044+ULONG Buffer1_DECODE_SOURCE_ADDRESS = 0x1000000;
21045+ULONG Buffer2_DECODE_SOURCE_ADDRESS = 0x1400000;
21046+ULONG PASS1_DECODE_DESTINATION_ADDRESS = 0x600000;
21047+ULONG CAPTURE_2ND_ADDRESS = 0x1800000;
21048+ULONG PASS1_2ND_ENCODE_SOURCE_ADDRESS = 0x1800000;
21049+ULONG PASS1_2ND_ENCODE_DESTINATION_ADDRESS = 0x2800000;
21050+ULONG PASS1_2ND_DECODE_SOURCE_ADDRESS = 0x1000000;
21051+ULONG PASS1_2ND_DECODE_DESTINATION_ADDRESS = 0x600000;
21052+ULONG PASS2_ENCODE_SOURCE_ADDRESS = 0x000000;
21053+ULONG PASS2_ENCODE_DESTINATION_ADDRESS = 0xC00000;
21054+ULONG PASS2_DECODE_SOURCE_ADDRESS = 0xC00000;
21055+ULONG PASS2_DECODE_DESTINATION_ADDRESS = 0x600000;
21056+ULNG PASS2_DECODE_REFERENCE_ADDRESS = 0x600000;
21057+*/
21058+
21059+typedef struct _CTL_REG_G {
21060+ ULONG CompressMode:1;
21061+ ULONG SkipEmptyFrame:1;
21062+ ULONG MemBurstLen:2;
21063+ ULONG LineBufEn:2;
21064+ ULONG Unused:26;
21065+} CTL_REG_G;
21066+
21067+
21068+typedef union _U_CTL_G {
21069+ ULONG Value;
21070+ CTL_REG_G CtlReg;
21071+} U_CTL_G;
21072+
21073+typedef struct _MODE_DETECTION_PARAM_REG {
21074+ ULONG Unused1:8;
21075+ ULONG EdgePixelThres:8;
21076+ ULONG VerStableMax:4;
21077+ ULONG HorStableMax:4;
21078+ ULONG VerDiffMax:4;
21079+ ULONG HorDiffMax:4;
21080+} MODE_DETECTION_PARAM_REG;
21081+
21082+typedef struct _CRC_PRI_PARAM_REG {
21083+ ULONG Enable:1;
21084+ ULONG HighBitOnly:1;
21085+ ULONG SkipCountMax:6;
21086+ ULONG PolyLow:8;
21087+ ULONG PolyHigh:16;
21088+} CRC_PRI_PARAM_REG;
21089+
21090+typedef union _U_CRC_PRI_PARAM {
21091+ ULONG Value;
21092+ CRC_PRI_PARAM_REG CRCPriParam;
21093+} U_CRC_PRI_PARAM;
21094+
21095+typedef struct _CRC_SEC_PARAM_REG {
21096+ ULONG Unused1:8;
21097+ ULONG PolyLow:8;
21098+ ULONG PolyHigh:16;
21099+} CRC_SEC_PARAM_REG;
21100+
21101+typedef union _U_CRC_SEC_PARAM {
21102+ ULONG Value;
21103+ CRC_SEC_PARAM_REG CRCSecParam;
21104+} U_CRC_SEC_PARAM;
21105+
21106+typedef struct _GENERAL_INFO {
21107+ BYTE EnableVideoM;
21108+ BYTE CenterMode;
21109+ BYTE RC4NoResetFrame;
21110+ BYTE RC4TestMode;
21111+ U_CTL_G uCtlReg;
21112+ U_CRC_PRI_PARAM uCRCPriParam;
21113+ U_CRC_SEC_PARAM uCRCSecParam;
21114+} GENERAL_INFO, *PGENERAL_INFO;
21115+
21116+typedef struct _SEQ_CTL_REG {
21117+ ULONG Unused1:1;
21118+ ULONG Unused2:1;
21119+ ULONG Unused3:1;
21120+ ULONG CaptureAutoMode:1;
21121+ ULONG Unused4:1;
21122+ ULONG CodecAutoMode:1;
21123+ ULONG Unused5:1;
21124+ ULONG WatchDog:1;
21125+ ULONG CRTSel:1;
21126+ ULONG AntiTearing:1;
21127+ ULONG DataType:2;
21128+ ULONG Unused6:20;
21129+} SEQ_CTL_REG;
21130+
21131+typedef union _U_SEQ_CTL {
21132+ ULONG Value;
21133+ SEQ_CTL_REG SeqCtlReg;
21134+} U_SEQ_CTL;
21135+
21136+typedef struct _CTL_REG {
21137+ ULONG SrcHsync:1;
21138+ ULONG SrcVsync:1;
21139+ ULONG ExtSrc:1;
21140+ ULONG AnalongExtSrc:1;
21141+ ULONG IntTimingGen:1;
21142+ ULONG IntDataFrom:1;
21143+ ULONG WriteFmt:2;
21144+ ULONG VGACursor:1;
21145+ ULONG LinearMode:1;
21146+ ULONG ClockDelay:2;
21147+ ULONG CCIR656Src:1;
21148+ ULONG PortClock:1;
21149+ ULONG ExtPort:1;
21150+ ULONG Unused1:1;
21151+ ULONG FrameRate:8;
21152+ ULONG Unused2:8;
21153+} CTL_REG;
21154+
21155+typedef union _U_CTL {
21156+ ULONG Value;
21157+ CTL_REG CtlReg;
21158+} U_CTL_REG;
21159+
21160+typedef struct _TIMING_GEN_SETTING_H {
21161+ ULONG HDEEnd:13;
21162+ ULONG Unused1:3;
21163+ ULONG HDEStart:13;
21164+ ULONG Unused2:3;
21165+} TIMING_GEN_SETTING_H;
21166+
21167+typedef struct _TIMING_GEN_SETTING_V {
21168+ ULONG VDEEnd:13;
21169+ ULONG Unused1:3;
21170+ ULONG VDEStart:13;
21171+ ULONG Unused2:3;
21172+} TIMING_GEN_SETTING_V;
21173+
21174+typedef struct _BCD_CTL_REG {
21175+ ULONG Enable:1;
21176+ ULONG Unused1:15;
21177+ ULONG Tolerance:8;
21178+ ULONG Unused2:8;
21179+} BCD_CTL_REG;
21180+
21181+typedef union _U_BCD_CTL {
21182+ ULONG Value;
21183+ BCD_CTL_REG BCDCtlReg;
21184+} U_BCD_CTL;
21185+
21186+typedef struct _COMPRESS_WINDOW_REG {
21187+ ULONG VerLine:13;
21188+ ULONG Unused1:3;
21189+ ULONG HorPixel:13;
21190+ ULONG Unused2:3;
21191+} COMPRESS_WINDOW_REG;
21192+
21193+typedef struct _STREAM_BUF_SIZE {
21194+ ULONG PacketSize:3;
21195+ ULONG RingBufNum:2;
21196+ ULONG Unused1:11;
21197+ ULONG SkipHighMBThres:7;
21198+ ULONG SkipTestMode:2;
21199+ ULONG Unused2:7;
21200+} STREAM_BUF_SIZE;
21201+
21202+typedef union _U_STREAM_BUF {
21203+ ULONG Value;
21204+ STREAM_BUF_SIZE StreamBufSize;
21205+} U_STREAM_BUF;
21206+
21207+
21208+typedef struct _COMPRESS_CTL_REG {
21209+ ULONG JPEGOnly:1; /* True: Jpeg Only mode(Disable VQ), False:Jpeg and VQ mix mode */
21210+ ULONG En4VQ:1; /* True: 1, 2, 4 color mode, False: 1,2 color mode */
21211+ ULONG CodecMode:1; /* High and best Quantization encoding/decoding setting*/
21212+ ULONG DualQuality:1;
21213+ ULONG EnBest:1;
21214+ ULONG EnRC4:1;
21215+ ULONG NorChromaDCTTable:5;
21216+ ULONG NorLumaDCTTable:5;
21217+ ULONG EnHigh:1;
21218+ ULONG TestCtl:2;
21219+ ULONG UVFmt:1;
21220+ ULONG HufTable:2;
21221+ ULONG AlterValue1:5;
21222+ ULONG AlterValue2:5;
21223+} COMPRESS_CTL_REG;
21224+
21225+typedef union _U_COMPRESS_CTL {
21226+ ULONG Value;
21227+ COMPRESS_CTL_REG CompressCtlReg;
21228+} U_COMPRESS_CTL;
21229+
21230+typedef struct _QUANTI_TABLE_LOW_REG {
21231+ ULONG ChromaTable:5;
21232+ ULONG LumaTable:5;
21233+ ULONG Unused1:22;
21234+} QUANTI_TABLE_LOW_REG;
21235+
21236+typedef union _U_CQUANTI_TABLE_LOW {
21237+ ULONG Value;
21238+ QUANTI_TABLE_LOW_REG QTableLowReg;
21239+} U_QUANTI_TABLE_LOW;
21240+
21241+typedef struct _QUANTI_VALUE_REG {
21242+ ULONG High:15;
21243+ ULONG Unused1:1;
21244+ ULONG Best:15;
21245+ ULONG Unused2:1;
21246+} QUANTI_VALUE_REG;
21247+
21248+typedef union _U_QUANTI_VALUE {
21249+ ULONG Value;
21250+ QUANTI_VALUE_REG QValueReg;
21251+} U_QUANTI_VALUE;
21252+
21253+typedef struct _BSD_PARAM_REG {
21254+ ULONG HighThres:8;
21255+ ULONG LowThres:8;
21256+ ULONG HighCount:6;
21257+ ULONG Unused1:2;
21258+ ULONG LowCount:6;
21259+ ULONG Unused2:2;
21260+} BSD_PARAM_REG;
21261+
21262+typedef union _U_BSD_PARAM {
21263+ ULONG Value;
21264+ BSD_PARAM_REG BSDParamReg;
21265+} U_BSD_PARAM;
21266+
21267+typedef struct _VIDEO_INFO {
21268+ BYTE ExtADCAct; /* read from modection register */
21269+ BYTE EnableRC4;
21270+ BYTE DownScalingMethod;
21271+ USHORT AnalogDifferentialThreshold; /* BCD tolerance */
21272+ USHORT DigitalDifferentialThreshold; /* BCD tolerance */
21273+ USHORT DstWidth;
21274+ USHORT DstHeight;
21275+ USHORT SrcWidth;
21276+ USHORT SrcHeight;
21277+ BYTE HighLumaTable; /* if High and best Jpeg codec enable, use HighLumaTable and HighChromaTable, otherwise HighDeQuantiValue and BestDequantiValue*/
21278+ BYTE HighChromaTable;
21279+ BYTE HighDeQuantiValue;
21280+ BYTE BestDequantiValue;
21281+ U_SEQ_CTL uSeqCtlReg;
21282+ U_CTL_REG uCtlReg;
21283+ U_BCD_CTL uBCDCtlReg;
21284+ U_STREAM_BUF uStreamBufSize;
21285+ U_COMPRESS_CTL uCompressCtlReg;
21286+ U_QUANTI_TABLE_LOW uQTableLowReg;
21287+ U_QUANTI_VALUE uQValueReg;
21288+ U_BSD_PARAM uBSDParamReg;
21289+} VIDEO_INFO, *PVIDEO_INFO ;
21290+
21291+typedef struct _VIDEOM_SEQ_CTL_REG {
21292+ ULONG Unused1:1; //Bit 0
21293+ ULONG Unused2:1; //Bit 1
21294+ ULONG Unused3:1; //Bit 2
21295+ ULONG StreamMode:1; //Bit 3
21296+ ULONG Unused4:1; //Bit 4
21297+ ULONG CodecAutoMode:1; //Bit 5
21298+ ULONG Unused6:1; //Bit 6
21299+ ULONG Unused7:1; //Bit 7
21300+ ULONG SrcSel:1; //Bit 8
21301+ ULONG Unused9:1; //Bit 9
21302+ ULONG DataType:2; //Bit[11:10]
21303+ ULONG Unused12:20;
21304+} VIDEOM_SEQ_CTL_REG;
21305+
21306+typedef union _U_VIDEOM_SEQ_CTL {
21307+ ULONG Value;
21308+ VIDEOM_SEQ_CTL_REG SeqCtlReg;
21309+} U_VIDEOM_SEQ_CTL;
21310+
21311+typedef struct _VIDEOM_INFO {
21312+ BYTE DownScalingMethod;
21313+ USHORT AnalogDifferentialThreshold; /* BCD tolerance */
21314+ USHORT DigitalDifferentialThreshold; /* BCD tolerance */
21315+ USHORT DstWidth;
21316+ USHORT DstHeight;
21317+ USHORT SrcWidth;
21318+ USHORT SrcHeight;
21319+ BYTE HighLumaTable; /* if High and best Jpeg codec enable, use HighLumaTable and HighChromaTable, otherwise HighDeQuantiValue and BestDequantiValue*/
21320+ BYTE HighChromaTable;
21321+ BYTE HighDeQuantiValue;
21322+ BYTE BestDequantiValue;
21323+ BYTE PacketSize; //the same as video1 & video2
21324+ BYTE RingBufNum;
21325+ BYTE EnableRC4;
21326+ U_VIDEOM_SEQ_CTL uSeqCtlReg;
21327+ U_BCD_CTL uBCDCtlReg;
21328+ U_COMPRESS_CTL uCompressCtlReg;
21329+ U_QUANTI_TABLE_LOW uQTableLowReg;
21330+ U_QUANTI_VALUE uQValueReg;
21331+ U_BSD_PARAM uBSDParamReg;
21332+} VIDEOM_INFO, *PVIDEOM_INFO ;
21333+
21334+typedef struct _VIDEO_MODE_INFO
21335+{
21336+ USHORT X;
21337+ USHORT Y;
21338+ USHORT ColorDepth;
21339+ USHORT RefreshRate;
21340+ BYTE ModeIndex;
21341+} VIDEO_MODE_INFO, *PVIDEO_MODE_INFO;
21342+
21343+#endif
21344+
21345diff --git a/board/aspeed/ast2300/vesa.h b/board/aspeed/ast2300/vesa.h
21346new file mode 100755
21347index 0000000..69aba90
21348--- /dev/null
21349+++ b/board/aspeed/ast2300/vesa.h
21350@@ -0,0 +1,163 @@
21351+/*
21352+ * This program is distributed in the hope that it will be useful,
21353+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
21354+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21355+ * GNU General Public License for more details.
21356+ *
21357+ * You should have received a copy of the GNU General Public License
21358+ * along with this program; if not, write to the Free Software
21359+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21360+ */
21361+#ifndef _VESA_H_
21362+#define _VESA_H_
21363+
21364+typedef enum
21365+{
21366+ VCLK25_175 = 0x00,
21367+ VCLK28_322 = 0x01,
21368+ VCLK31_5 = 0x02,
21369+ VCLK31_574 = 0x03,
21370+ VCLK32_76 = 0x04,
21371+ VCLK33_154 = 0x05,
21372+ VCLK36 = 0x06,
21373+ VCLK40 = 0x07,
21374+ VCLK45_978 = 0x08,
21375+ VCLK49_5 = 0x09,
21376+ VCLK50 = 0x0A,
21377+ VCLK52_95 = 0x0B,
21378+ VCLK56_25 = 0x0C,
21379+ VCLK65 = 0x0D,
21380+ VCLK74_48 = 0x0E,
21381+ VCLK75 = 0x0F,
21382+ VCLK78_75 = 0x10,
21383+ VCLK79_373 = 0x11,
21384+ VCLK81_624 = 0x12,
21385+ VCLK83_462 = 0x13,
21386+ VCLK84_715 = 0x14,
21387+ VCLK94_5 = 0x15,
21388+ VCLK106_5 = 0x16,
21389+ VCLK108 = 0x17,
21390+ VCLK119 = 0x18,
21391+ VCLK135 = 0x19,
21392+ VCLK136_358 = 0x1A,
21393+ VCLK146_25 = 0x1B,
21394+ VCLK154 = 0x1C,
21395+ VCLK157_5 = 0x1D,
21396+ VCLK162 = 0x1E
21397+} ePIXEL_CLOCK;
21398+
21399+typedef struct {
21400+ USHORT HorizontalTotal;
21401+ USHORT VerticalTotal;
21402+ USHORT HorizontalActive;
21403+ USHORT VerticalActive;
21404+ BYTE RefreshRate;
21405+ double HorizontalFrequency;
21406+ USHORT HSyncTime;
21407+ USHORT HBackPorch;
21408+ USHORT VSyncTime;
21409+ USHORT VBackPorch;
21410+ USHORT HLeftBorder;
21411+ USHORT HRightBorder;
21412+ USHORT VBottomBorder;
21413+ USHORT VTopBorder;
21414+ USHORT PixelClock;
21415+ BOOL HorPolarity;
21416+ BOOL VerPolarity;
21417+ BYTE ADCIndex1;
21418+ BYTE ADCIndex2;
21419+ BYTE ADCIndex3;
21420+ BYTE ADCIndex5;
21421+ BYTE ADCIndex6;
21422+ BYTE ADCIndex7;
21423+ BYTE ADCIndex8;
21424+ BYTE ADCIndex9;
21425+ BYTE ADCIndexA;
21426+ BYTE ADCIndexF;
21427+ BYTE ADCIndex15;
21428+ int HorizontalShift;
21429+ int VerticalShift;
21430+} VESA_MODE;
21431+
21432+#define HOR_POSITIVE 0
21433+#define HOR_NEGATIVE 1
21434+#define VER_POSITIVE 0
21435+#define VER_NEGATIVE 1
21436+
21437+#ifdef VESA_GLOBALS
21438+
21439+// Note: Modified for modes which have border issue
21440+VESA_MODE vModeTable[] = {
21441+////////////////////////// 60Hz mode
21442+// 720x480 done
21443+ {1056, 497, 720, 480, 60, 29.900, 88, 104, 3, 13, 0, 0, 0, 0, VCLK31_574, HOR_NEGATIVE, VER_NEGATIVE, 0x41, 0xF0, 0x48, 0x05, 0x20, 0x58, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 2},
21444+// 848x480 done
21445+ {1064, 517, 848, 480, 60, 31.160, 88, 91, 3, 26, 0, 0, 0, 0, VCLK33_154, HOR_NEGATIVE, VER_NEGATIVE, 0x42, 0x70, 0x48, 0x05, 0x20, 0x58, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 2},
21446+ {800, 525, 640, 480, 60, 31.469, 96, 40, 2, 25, 1, 1, 8, 8, VCLK25_175, HOR_NEGATIVE, VER_NEGATIVE, 0x31, 0xF0, 0x48, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 2},
21447+// 720x576
21448+ {912, 597, 720, 576, 60, 35.920, 72, 88, 3, 17, 0, 0, 0, 0, VCLK32_76, HOR_NEGATIVE, VER_NEGATIVE, 0x38, 0xF0, 0x48, 0x05, 0x20, 0x48, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 2},
21449+// 960x600 GTF done
21450+ {1232, 622, 960, 600, 60, 37.320, 96, 136, 3, 18, 0, 0, 0, 0, VCLK45_978, HOR_NEGATIVE, VER_NEGATIVE, 0x4C, 0xF0, 0x60, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21451+ {1056, 628, 800, 600, 60, 37.879, 128, 88, 4, 23, 0, 0, 0, 0, VCLK40, HOR_POSITIVE, VER_POSITIVE, 0x41, 0xF0, 0x60, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21452+// 1088x612 GTF done
21453+ {1392, 634, 1088, 612, 60, 38.04, 112, 152, 3, 18, 0, 0, 0, 0, VCLK52_95, HOR_NEGATIVE, VER_NEGATIVE, 0x56, 0xF0, 0x60, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21454+// 1280x720 GTF done
21455+ {1664, 746, 1280, 720, 60, 44.760, 136, 192, 3, 22, 0, 0, 0, 0, VCLK74_48, HOR_NEGATIVE, VER_NEGATIVE, 0x67, 0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21456+// 1360x768 GTF done
21457+ {1776, 795, 1360, 768, 60, 47.700, 144, 208, 3, 23, 0, 0, 0, 0, VCLK84_715, HOR_NEGATIVE, VER_NEGATIVE, 0x6E, 0xF0, 0xA8, 0x05, 0x20, 0x90, 0x60, 0x60, 0x60, 0x5E, 0xFE, 7, 1},
21458+// 1280x768 done
21459+ {1664, 798, 1280, 768, 60, 47.700, 128, 184, 7, 20, 0, 0, 0, 0, VCLK79_373, HOR_NEGATIVE, VER_NEGATIVE, 0x67, 0xF0, 0xA8, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60, 0x5E, 0xFE, 7, 1},
21460+ {1344, 806, 1024, 768, 60, 48.363, 136, 160, 6, 29, 0, 0, 0, 0, VCLK65, HOR_NEGATIVE, VER_NEGATIVE, 0x53, 0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 7},
21461+// 1280x800 GTF done
21462+ {1680, 828, 1280, 800, 60, 49.680, 136, 200, 3, 24, 0, 0, 0, 0, VCLK83_462, HOR_NEGATIVE, VER_NEGATIVE, 0x68, 0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21463+// 1152x864 GTF done
21464+ {1520, 895, 1152, 864, 60, 53.700, 120, 184, 3, 27, 0, 0, 0, 0, VCLK81_624, HOR_NEGATIVE, VER_NEGATIVE, 0x5E, 0xF0, 0xA8, 0x05, 0x20, 0x78, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21465+// 1600x900 GTF done
21466+ {2128, 932, 1600, 900, 60, 55.920, 168, 264, 3, 28, 0, 0, 0, 0, VCLK119, HOR_NEGATIVE, VER_NEGATIVE, 0x84, 0xF0, 0xA8, 0x05, 0x20, 0xA8, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21467+// 1440X900 CVT done
21468+ {1904, 933, 1440, 900, 60, 55.935, 152, 232, 6, 25, 0, 0, 0, 0, VCLK106_5, HOR_NEGATIVE, VER_POSITIVE, 0x76, 0xF0, 0xA8, 0x05, 0x20, 0x96, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21469+ {1800, 1000, 1280, 960, 60, 60.000, 112, 312, 3, 36, 0, 0, 0, 0, VCLK108, HOR_POSITIVE, VER_POSITIVE, 0x70, 0x70, 0xA8, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21470+// 1600x1024 GTF done
21471+ {2144, 1060, 1600, 1024, 60, 63.600, 168, 272, 3, 32, 0, 0, 0, 0, VCLK136_358, HOR_NEGATIVE, VER_NEGATIVE, 0x85, 0xF0, 0xE8, 0x05, 0x20, 0xA8, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21472+ {1688, 1066, 1280, 1024, 60, 63.981, 112, 248, 3, 38, 0, 0, 0, 0, VCLK108, HOR_POSITIVE, VER_POSITIVE, 0x69, 0x70, 0xA8, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21473+// 1680X1050 CVT done Reduced Blanking
21474+ {1840, 1080, 1680, 1050, 60, 64.674, 32, 80, 6, 21, 0, 0, 0, 0, VCLK119, HOR_POSITIVE, VER_NEGATIVE, 0x72, 0xF0, 0xA8, 0x05, 0x20, 0x20, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21475+// 1920X1200 CVT done Reduced Blanking
21476+ {2080, 1235, 1920, 1200, 60, 74.038, 32, 80, 6, 26, 0, 0, 0, 0, VCLK154, HOR_POSITIVE, VER_NEGATIVE, 0x81, 0xF0, 0xA8, 0x05, 0x20, 0x20, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21477+ //{2160, 1250, 1600, 1200, 60,75.000, 192, 304, 3, 46, 0, 0, 0, 0, VCLK162, HOR_POSITIVE, VER_POSITIVE},
21478+ {2160, 1248, 1600, 1200, 60, 75.000, 192, 304, 3, 46, 0, 0, 0, 0, VCLK162, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xE8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21479+
21480+////////////////////// Not 60Hz mode
21481+ {900, 449, 720, 400, 70, 31.469, 108, 45, 2, 25, 1, 1, 8, 8, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x38, 0x30, 0x48, 0x05, 0x20, 0x6C, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 1},
21482+ {832, 520, 640, 480, 72, 37.861, 40, 120, 3, 20, 1, 1, 8, 8, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x33, 0xF0, 0x48, 0x05, 0x20, 0x28, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 3},
21483+ {840, 500, 640, 480, 75, 37.500, 64, 120, 3, 16, 0, 0, 0, 0, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x34, 0x70, 0x48, 0x05, 0x20, 0x40, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 3},
21484+ {832, 509, 640, 480, 85, 43.269, 56, 80, 3, 25, 0, 0, 0, 0, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x33, 0xF0, 0x48, 0x05, 0x20, 0x38, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 3},
21485+ {1024, 625, 800, 600, 56, 35.156, 72, 128, 2, 22, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x3F, 0xF0, 0x60, 0x05, 0x20, 0x48, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21486+ {1040, 666, 800, 600, 72, 48.077, 120, 64, 6, 23, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x40, 0xF0, 0x60, 0x05, 0x20, 0x78, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21487+ {1056, 625, 800, 600, 75, 46.875, 80, 160, 3, 21, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x41, 0xF0, 0x60, 0x05, 0x20, 0x50, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21488+ {1048, 631, 800, 600, 85, 53.674, 64, 152, 3, 27, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x41, 0x70, 0x60, 0x05, 0x20, 0x40, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21489+ {1328, 806, 1024, 768, 70, 56.476, 136, 144, 6, 29, 0, 0, 0, 0, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x52, 0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 7},
21490+ {1312, 800, 1024, 768, 75, 60.023, 96, 176, 3, 28, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x51, 0xF0, 0xA8, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 1},
21491+ {1376, 808, 1024, 768, 85, 68.677, 96, 208, 3, 36, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x55, 0xF0, 0xA8, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 1},
21492+ {1600, 900, 1152, 864, 75, 67.500, 128, 256, 3, 32, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x63, 0xF0, 0xA8, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21493+ {1728, 1011, 1280, 960, 85, 85.938, 160, 224, 3, 47, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x6B, 0xF0, 0xA8, 0x05, 0x20, 0xA0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21494+ {1688, 1066, 1280, 1024, 75, 79.976, 144, 248, 3, 38, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x69, 0x70, 0xE8, 0x05, 0x20, 0x90, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21495+ {1728, 1072, 1280, 1024, 85, 91.146, 160, 224, 3, 44, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x6B, 0xF0, 0xA8, 0x05, 0x20, 0xA0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21496+ {2160, 1250, 1600, 1200, 65, 81.250, 192, 304, 3, 46, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21497+ {2160, 1250, 1600, 1200, 70, 87.500, 192, 304, 3, 46, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21498+ {2160, 1250, 1600, 1200, 75, 93.750, 192, 304, 3, 46, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
21499+ {2160, 1250, 1600, 1200, 85, 106.250,192, 304, 3, 46, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0}
21500+};
21501+
21502+USHORT ModeNumberCount = sizeof (vModeTable) / sizeof (VESA_MODE);
21503+USHORT Mode60HZCount = 21;
21504+
21505+#else /* NOT VESA_GLOBALS */
21506+extern VESA_MODE vModeTable[];
21507+extern USHORT ModeNumberCount;
21508+extern USHORT Mode60HZCount;
21509+#endif
21510+
21511+#endif /* _VESA_H_ */
21512+
21513+
21514diff --git a/board/aspeed/ast2300/vfun.c b/board/aspeed/ast2300/vfun.c
21515new file mode 100755
21516index 0000000..f707e80
21517--- /dev/null
21518+++ b/board/aspeed/ast2300/vfun.c
21519@@ -0,0 +1,545 @@
21520+/*
21521+ * This program is distributed in the hope that it will be useful,
21522+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
21523+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21524+ * GNU General Public License for more details.
21525+ *
21526+ * You should have received a copy of the GNU General Public License
21527+ * along with this program; if not, write to the Free Software
21528+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21529+ */
21530+#define BUF_GLOBALS
21531+#include "type.h"
21532+#include "vdef.h"
21533+#include "vreg.h"
21534+#include "crt.h"
21535+#include "vfun.h"
21536+
21537+ULONG UnlockSCURegHost(ULONG MMIOBase, ULONG Key)
21538+{
21539+ WriteMemoryLongHost(SCU_BASE, SCU_PROTECT_REG, Key);
21540+ return ReadMemoryLongHost(SCU_BASE,SCU_PROTECT_REG);
21541+}
21542+
21543+void ResetVideoHost(void)
21544+{
21545+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, VIDEO_RESET_EN << VIDEO_ENGINE_RESET_BIT, VIDEO_ENGINE_RESET_MASK);
21546+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, VIDEO_RESET_OFF << VIDEO_ENGINE_RESET_BIT, VIDEO_ENGINE_RESET_MASK);
21547+}
21548+
21549+void StartModeDetectionTriggerHost(ULONG MMIOBase, ULONG offset)
21550+{
21551+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, MODE_DETECTION_TRIGGER);
21552+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, MODE_DETECTION_TRIGGER, MODE_DETECTION_TRIGGER);
21553+}
21554+
21555+BOOL ReadVideoInterruptHost(ULONG MMIOBase, ULONG value)
21556+{
21557+ return ((ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_READ_REG) & value) ? TRUE : FALSE);
21558+}
21559+
21560+ULONG UnlockVideoRegHost(ULONG MMIOBase, ULONG Key)
21561+{
21562+ WriteMemoryLongHost(VIDEO_REG_BASE, KEY_CONTROL_REG, Key);
21563+ return ReadMemoryLongHost(VIDEO_REG_BASE,KEY_CONTROL_REG);
21564+}
21565+
21566+void StartVideoCaptureTriggerHost(ULONG MMIOBase, ULONG offset)
21567+{
21568+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, VIDEO_CAPTURE_TRIGGER);
21569+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, VIDEO_CAPTURE_TRIGGER, VIDEO_CAPTURE_TRIGGER);
21570+}
21571+
21572+void StartVideoCodecTriggerHost(ULONG MMIOBase, ULONG offset)
21573+{
21574+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, VIDEO_CODEC_TRIGGER);
21575+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, VIDEO_CODEC_TRIGGER, VIDEO_CODEC_TRIGGER);
21576+}
21577+
21578+void StopModeDetectionTriggerHost(ULONG MMIOBase, ULONG offset)
21579+{
21580+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, MODE_DETECTION_TRIGGER);
21581+}
21582+
21583+void ClearVideoInterruptHost(ULONG MMIOBase, ULONG value)
21584+{
21585+ //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_CLEAR_REG, value, value);
21586+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_CLEAR_REG, value);
21587+}
21588+
21589+/* UnLock SCU Host and Reset Engine */
21590+BOOL CheckOnStartHost(void)
21591+{
21592+ int i=0, dwValue=0;
21593+
21594+ do
21595+ {
21596+ dwValue = UnlockSCURegHost(0, SCU_UNLOCK_KEY);
21597+ i++;
21598+ }
21599+ while ((SCU_WRITE_ENABLE != dwValue) && (i<10));
21600+
21601+ //Clear SCU Reset Register
21602+ WriteMemoryLongHost(SCU_BASE, SCU_CONTROL_REG, 0);
21603+
21604+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_ECLK | EN_V1CLK | EN_V2CLK), (STOP_ECLK_MASK | STOP_V1CLK_MASK | STOP_V2CLK_MASK));
21605+
21606+#if defined(CONFIG_AST2300)
21607+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x90 + SCU_OFFSET), 0x00000020, 0x00000030); //enable 24bits
21608+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x88 + SCU_OFFSET), 0x000fff00, 0x000fff00); //enable video multi-pins
21609+#else //AST2100
21610+ //WriteMemoryLongWithMASKHost(SCU_BASE, SCU_PIN_CTRL1_REG, (VIDEO_PORTA_EN | VIDEO_PORTB_EN | VIDEO_VP1_EN | VIDEO_VP2_EN) ,
21611+ // (VIDEO_PORTA_MASK | VIDEO_PORTB_MASK | VIDEO_VP1_MASK | VIDEO_VP2_MASK));
21612+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_PIN_CTRL2_REG, (VIDEO_PORTA_SINGLE_EDGE | VIDEO_PORTB_SINGLE_EDGE) ,
21613+ (VIDEO_PORTA_SINGLE_EDGE_MASK | VIDEO_PORTB_SINGLE_EDGE_MASK));
21614+#endif
21615+
21616+ ResetVideoHost();
21617+
21618+ return TRUE;
21619+}
21620+
21621+BOOL CheckOnStartClient(void)
21622+{
21623+ int i=0, dwValue=0;
21624+
21625+ do
21626+ {
21627+ dwValue = UnlockSCURegHost(0, SCU_UNLOCK_KEY);
21628+ i++;
21629+ }
21630+ while ((SCU_WRITE_ENABLE != dwValue) && (i<10));
21631+
21632+ //Clear SCU Reset Register
21633+ WriteMemoryLongClient(SCU_BASE, SCU_CONTROL_REG, 0);
21634+
21635+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_ECLK | EN_V1CLK | EN_D1CLK | EN_D2CLK | EN_V2CLK),
21636+ (STOP_ECLK_MASK | STOP_D1CLK_MASK | STOP_D2CLK_MASK | STOP_V1CLK_MASK | STOP_V2CLK_MASK));
21637+
21638+ //WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_SELECTION_REG, PORTB_FROM_D2CLK | PORTB_CLOCK_INV_DELAY_3NS | PORTA_CLOCK_INV_DELAY_3NS, PORTB_CLOCK_SEL | PORTB_CLOCK_DELAY_MASK | PORTA_CLOCK_DELAY_MASK);
21639+ //A1EVA
21640+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_SELECTION_REG, (PORTB_FROM_D2CLK | PORTB_CLOCK_INV_DELAY_1NS | PORTA_CLOCK_INV_DELAY_1NS), (PORTB_CLOCK_SEL | PORTB_CLOCK_DELAY_MASK | PORTA_CLOCK_DELAY_MASK));
21641+ WriteMemoryLongWithMASKClient(SCU_BASE, 0x202C, (0x03<<9), (0x03<<9));
21642+
21643+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL1_REG, (VIDEO_PORTA_EN | VIDEO_PORTB_EN | VIDEO_VP1_EN | VIDEO_VP2_EN),
21644+ (VIDEO_PORTA_MASK | VIDEO_PORTB_MASK | VIDEO_VP1_MASK | VIDEO_VP2_MASK));
21645+
21646+#if CONFIG_AST3000
21647+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL2_REG, (VIDEO_PORTA_DUAL_EDGE | VIDEO_PORTB_DUAL_EDGE),
21648+ (VIDEO_PORTA_SINGLE_EDGE_MASK | VIDEO_PORTB_SINGLE_EDGE_MASK));
21649+#else
21650+ //2100 is single edge
21651+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL2_REG, (VIDEO_PORTA_SINGLE_EDGE | VIDEO_PORTB_SINGLE_EDGE),
21652+ (VIDEO_PORTA_SINGLE_EDGE_MASK | VIDEO_PORTB_SINGLE_EDGE_MASK));
21653+#endif
21654+
21655+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_D1CLK | EN_D2CLK), (STOP_D1CLK_MASK | STOP_D2CLK_MASK));
21656+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL1_REG, VGA_PIN_OFF, VGA_PIN_MASK);
21657+
21658+ //ResetVideoHost();
21659+
21660+ return TRUE;
21661+}
21662+
21663+ULONG InitializeVideoEngineHost (ULONG MMIOBase,
21664+ int nVideo,
21665+ BOOL HorPolarity,
21666+ BOOL VerPolarity)
21667+{
21668+ //ULONG temp, temp1, temp2;
21669+ ULONG dwRegOffset = nVideo * 0x100;
21670+ ULONG dwValue;
21671+ int i;
21672+
21673+
21674+ /* General Video Control */
21675+ //LineBufEn 0
21676+ //dwValue = (COMPRESS_MODE << CODEC_DECOMPRESS_MODE_BIT) | DELAY_VSYNC_EN;
21677+ dwValue = 0;
21678+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CONTROL_REG, dwValue);
21679+ //Video Data Truncation Register
21680+ WriteMemoryLongHost(VIDEO_REG_BASE, 0x328, 0);
21681+
21682+ //D2CLK clock must config according to video's line buffer
21683+ if (VIDEO1 == nVideo)
21684+ dwValue = LINE_BUFFER_VIDEO1;
21685+ else
21686+ dwValue = LINE_BUFFER_VIDEO2;
21687+
21688+ //D2CLK clock must config according to video's line buffer
21689+ switch (dwValue)
21690+ {
21691+ case LINE_BUFFER_OFF:
21692+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, NORMAL_CRT1, D2CLK_CLOCK_SELECTION_MASK);
21693+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, STOP_D2CLK, STOP_D2CLK_MASK);
21694+ break;
21695+ case LINE_BUFFER_VIDEO1:
21696+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, V1CLK_VIDEO1 << D2CLK_CLOCK_SELECTION_BIT, D2CLK_CLOCK_SELECTION_MASK);
21697+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_D2CLK, STOP_D2CLK_MASK);
21698+ break;
21699+ case LINE_BUFFER_VIDEO2:
21700+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, V1CLK_VIDEO2 << D2CLK_CLOCK_SELECTION_BIT, D2CLK_CLOCK_SELECTION_MASK);
21701+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_D2CLK, STOP_D2CLK_MASK);
21702+ break;
21703+ case LINE_BUFFER_VIDEOM:
21704+ //If select this option, it will config at videoM INIT
21705+ break;
21706+ default:
21707+ break;
21708+ }
21709+
21710+ dwValue = 0;
21711+ //VR30 now is capture window in the compression
21712+ dwValue = g_DefHeight << CAPTURE_VER_LINE_BIT |
21713+ g_DefWidth << CAPTURE_HOR_PIXEL_BIT;
21714+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CAPTURE_WINDOWS_REG + dwRegOffset, dwValue);
21715+
21716+ dwValue = 0;
21717+ //VR34 now is destionation window in the compression
21718+ dwValue = g_DefHeight << COMPRESS_VER_LINE_BIT |
21719+ g_DefWidth << COMPRESS_HOR_PIXEL_BIT;
21720+
21721+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_WINDOWS_REG + dwRegOffset, dwValue);
21722+
21723+ //BitCOUNT according compress data format
21724+ dwValue = YUV444_MODE;
21725+ if (YUV444_MODE == dwValue)
21726+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV444, BUF_LINE_OFFSET_MASK);
21727+ else
21728+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV420, BUF_LINE_OFFSET_MASK);
21729+
21730+ // CRC
21731+ //Disable
21732+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_PRIMARY_REG, 0x0);
21733+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_SECOND_REG, 0x0);
21734+
21735+ /* Sequence Control register */
21736+ //Oonly Encoder need to set
21737+ /* Engine Sequence Contol Register */
21738+ dwValue = (WATCH_DOG_EN << WATCH_DOG_ENABLE_BIT) |
21739+ VIDEO_CAPTURE_AUTO_MODE |
21740+ VIDEO_CODEC_AUTO_MODE;
21741+
21742+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG + dwRegOffset, dwValue);
21743+
21744+ /* Control register */
21745+ dwValue = (HOR_NEGATIVE == HorPolarity) ? NO_INVERSE_POL : INVERSE_POL;
21746+ dwValue = (((VER_NEGATIVE == VerPolarity) ? NO_INVERSE_POL : INVERSE_POL) << VIDEO_VSYNC_POLARITY_BIT) | dwValue;
21747+
21748+ /* HW Recommand*/
21749+ //dwValue = (TILE_MODE << 9) | dwValue;
21750+ dwValue = (EXTERNAL_VGA_SOURCE << EXTERNAL_SOURCE_BIT) | dwValue;
21751+
21752+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG + dwRegOffset, dwValue);
21753+
21754+ /* BCD register */
21755+ //NO BCD
21756+ dwValue = 0;
21757+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BCD_CONTROL_REG + dwRegOffset, dwValue);
21758+
21759+ /* Stream Buffer Size register */
21760+ dwValue = (YUV_TEST << SKIP_TEST_MODE_BIT) |
21761+ (PACKET_SIZE_32KB << STREAM_PACKET_SIZE_BIT) |
21762+ (PACKETS_8 << RING_BUF_PACKET_NUM_BIT);
21763+ /* the same with Video1, Video2, and VideoM*/
21764+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_STREAM_BUF_SIZE, dwValue);
21765+
21766+ /* Comression control register */
21767+ dwValue = (USE_UV_CIR656 << UV_CIR656_FORMAT_BIT)|
21768+ (JPEG_MIX_MODE << JPEG_ONLY_BIT)|
21769+ (VQ_4_COLOR_MODE << VQ_4_COLOR_BIT)|
21770+ (QUANTI_CODEC_MODE << QUALITY_CODEC_SETTING_BIT)|
21771+ (7 << NORMAL_QUANTI_CHROMI_TABLE_BIT) |
21772+ (23 << NORMAL_QUANTI_LUMI_TABLE_BIT);
21773+
21774+ //Video2 have same value as video1
21775+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_CONTROL_REG, dwValue);
21776+
21777+ /* JPEG Quantization Table register */
21778+ dwValue = 0;
21779+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_TABLE_LOW_REG, dwValue);
21780+
21781+ /* Quantization value register */
21782+ //Video2 have same value as video1
21783+ dwValue = 0;
21784+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_VALUE_REG, dwValue);
21785+
21786+ //Video BSD Parameter Register
21787+ //Video2 have same value as video1
21788+ dwValue = 0;
21789+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BSD_PARA_REG, dwValue);
21790+
21791+ //no scale
21792+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_REG, 0x10001000);
21793+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER0_REG, 0x00200000);
21794+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER1_REG, 0x00200000);
21795+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER2_REG, 0x00200000);
21796+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER3_REG, 0x00200000);
21797+ return TRUE;
21798+}
21799+
21800+ULONG InitializeVideoEngineClient (ULONG MMIOBase,
21801+ int nVideo)
21802+{
21803+ //ULONG temp, temp1, temp2;
21804+ ULONG dwRegOffset = nVideo * 0x100;
21805+ ULONG dwValue;
21806+ int i;
21807+
21808+
21809+ /* General Video Control */
21810+ //LineBufEn 0
21811+ dwValue = (DECOMPRESS_MODE << CODEC_DECOMPRESS_MODE_BIT);
21812+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CONTROL_REG, dwValue);
21813+ //Video Data Truncation Register
21814+ WriteMemoryLongHost(VIDEO_REG_BASE, 0x328, 0);
21815+
21816+ //VR30 now is capture window in the compression
21817+ dwValue = g_DefHeight << CAPTURE_VER_LINE_BIT |
21818+ g_DefWidth << CAPTURE_HOR_PIXEL_BIT;
21819+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CAPTURE_WINDOWS_REG + dwRegOffset, dwValue, CAPTURE_VER_LINE_MASK | CAPTURE_HOR_PIXEL_MASK);
21820+
21821+ //VR34 now is destionation window in the compression
21822+ dwValue = g_DefHeight << COMPRESS_VER_LINE_BIT |
21823+ g_DefWidth << COMPRESS_HOR_PIXEL_BIT;
21824+
21825+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_WINDOWS_REG + dwRegOffset, dwValue, COMPRESS_VER_LINE_MASK | COMPRESS_HOR_PIXEL_MASK);
21826+
21827+ //BitCOUNT according compress data format
21828+ dwValue = YUV444_MODE;
21829+ if (YUV444_MODE == dwValue)
21830+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV444, BUF_LINE_OFFSET_MASK);
21831+ else
21832+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV420, BUF_LINE_OFFSET_MASK);
21833+
21834+ // CRC
21835+ //Disable
21836+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_PRIMARY_REG, 0x0);
21837+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_SECOND_REG, 0x0);
21838+
21839+ /* Sequence Control register */
21840+ //Oonly Encoder need to set
21841+ /* Engine Sequence Contol Register */
21842+ dwValue = VIDEO_CAPTURE_AUTO_MODE |
21843+ VIDEO_CODEC_AUTO_MODE;
21844+
21845+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG + dwRegOffset, dwValue);
21846+
21847+ /* Control register */
21848+ /* HW Recommand*/
21849+ dwValue = (TILE_MODE << 9);
21850+
21851+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG + dwRegOffset, dwValue);
21852+
21853+ /* BCD register */
21854+ //NO BCD
21855+ dwValue = 0;
21856+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BCD_CONTROL_REG + dwRegOffset, dwValue);
21857+
21858+ /* Stream Buffer Size register */
21859+ dwValue = (YUV_TEST << SKIP_TEST_MODE_BIT) |
21860+ (PACKET_SIZE_32KB << STREAM_PACKET_SIZE_BIT) |
21861+ (PACKETS_8 << RING_BUF_PACKET_NUM_BIT);
21862+ /* the same with Video1, Video2, and VideoM*/
21863+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_STREAM_BUF_SIZE, dwValue);
21864+
21865+
21866+ /* Comression control register */
21867+ dwValue = (USE_UV_CIR656 << UV_CIR656_FORMAT_BIT)|
21868+ (JPEG_MIX_MODE << JPEG_ONLY_BIT)|
21869+ (VQ_4_COLOR_MODE << VQ_4_COLOR_BIT)|
21870+ (QUANTI_CODEC_MODE << QUALITY_CODEC_SETTING_BIT)|
21871+ (7 << NORMAL_QUANTI_CHROMI_TABLE_BIT) |
21872+ (23 << NORMAL_QUANTI_LUMI_TABLE_BIT);
21873+
21874+ //Video2 have same value as video1
21875+ if (VIDEO1 == nVideo)
21876+ {
21877+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_CONTROL_REG, dwValue);
21878+ }
21879+ else
21880+ {
21881+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEOM_COMPRESS_CONTROL_REG, dwValue);
21882+ }
21883+
21884+ /* JPEG Quantization Table register */
21885+ dwValue = 0;
21886+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_TABLE_LOW_REG, dwValue);
21887+
21888+ /* Quantization value register */
21889+ //Video2 have same value as video1
21890+ dwValue = 0;
21891+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_VALUE_REG, dwValue);
21892+
21893+ //Video BSD Parameter Register
21894+ //Video2 have same value as video1
21895+ dwValue = 0;
21896+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BSD_PARA_REG, dwValue);
21897+
21898+ return TRUE;
21899+}
21900+
21901+BYTE GetI2CRegClient(ULONG MMIOBase,
21902+ BYTE DeviceSelect,
21903+ BYTE DeviceAddress,
21904+ BYTE RegisterIndex)
21905+{
21906+ BYTE Data;
21907+ ULONG Status;
21908+
21909+// Reset
21910+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 0);
21911+// Set AC Timing and Speed
21912+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x04, AC_TIMING);
21913+// Lower Speed
21914+// WriteMemoryLongWithANDData (VideoEngineInfo->VGAPCIInfo.ulMMIOBaseAddress, I2C_BASE + DeviceSelect * 0x40 + 0x04, 0, 0x33317805);
21915+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x08, 0);
21916+// Clear Interrupt
21917+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
21918+// Enable Master Mode
21919+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 1);
21920+// Enable Interrupt
21921+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0xAF);
21922+// BYTE I2C Mode
21923+// Start and Send Device Address
21924+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
21925+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
21926+// Wait TX ACK
21927+ do {
21928+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
21929+ } while (Status != 1);
21930+// Clear Interrupt
21931+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
21932+// Send Device Register Index
21933+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterIndex);
21934+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
21935+// Wait Tx ACK
21936+ do {
21937+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
21938+ } while (Status != 1);
21939+// Clear Interrupt
21940+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
21941+// Start, Send Device Address + 1(Read Mode), Receive Data
21942+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress + 1);
21943+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x1B);
21944+// Wait Rx Done
21945+ do {
21946+ Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x04) >> 2;
21947+ } while (Status != 1);
21948+// Clear Interrupt
21949+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
21950+
21951+// Enable STOP Interrupt
21952+ WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10, 0x10);
21953+// Issue STOP Command
21954+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x20);
21955+// Wait STOP
21956+ do {
21957+ Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x10) >> 4;
21958+ } while (Status != 1);
21959+// Disable STOP Interrupt
21960+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10);
21961+// Clear Interrupt
21962+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
21963+// Read Received Data
21964+ Data = (BYTE)((ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20) & 0xFF00) >> 8);
21965+
21966+ return Data;
21967+}
21968+
21969+ULONG SetI2CRegClient(ULONG MMIOBase,
21970+ BYTE DeviceSelect,
21971+ BYTE DeviceAddress,
21972+ BYTE RegisterIndex,
21973+ BYTE RegisterValue)
21974+{
21975+ ULONG Status;
21976+ ULONG Count = 0;
21977+
21978+// Reset
21979+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 0);
21980+// Set Speed
21981+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x04, AC_TIMING);
21982+// Lower Speed
21983+// WriteMemoryLongWithANDData (VideoEngineInfo->VGAPCIInfo.ulMMIOBaseAddress, I2C_BASE + DeviceSelect * 0x40 + 0x04, 0, 0x33317805);
21984+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x08, 0);
21985+// Clear Interrupt
21986+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
21987+// Enable Master Mode
21988+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 1);
21989+// Enable Interrupt
21990+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0xAF);
21991+// BYTE I2C Mode
21992+// Start and Send Device Address
21993+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
21994+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
21995+// Wait Tx ACK
21996+ do {
21997+ Count++;
21998+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
21999+
22000+ if (2 == Status)
22001+ {
22002+ //Clear Interrupt
22003+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
22004+ //Re-Send Start and Send Device Address while NACK return
22005+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
22006+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
22007+ }
22008+ //else
22009+ {
22010+ if (Count > LOOP_COUNT) {
22011+ return CAN_NOT_FIND_DEVICE;
22012+ }
22013+ }
22014+ } while (Status != 1);
22015+ Count = 0;
22016+// Clear Interrupt
22017+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
22018+// Send Device Register Index
22019+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterIndex);
22020+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
22021+// Wait Tx ACK
22022+ do {
22023+ Count++;
22024+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
22025+ if (Count > LOOP_COUNT) {
22026+ return CAN_NOT_FIND_DEVICE;
22027+ }
22028+ } while (Status != 1);
22029+ Count = 0;
22030+// Clear Interrupt
22031+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
22032+// Send Device Register Value and Stop
22033+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterValue);
22034+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
22035+// Wait Tx ACK
22036+ do {
22037+ Count++;
22038+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
22039+ if (Count > LOOP_COUNT) {
22040+ return CAN_NOT_FIND_DEVICE;
22041+ }
22042+ } while (Status != 1);
22043+ Count = 0;
22044+// Clear Interrupt
22045+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
22046+// Enable STOP Interrupt
22047+ WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10, 0x10);
22048+// Issue STOP Command
22049+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x20);
22050+// Wait STOP
22051+ do {
22052+ Count++;
22053+ Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x10) >> 4;
22054+ if (Count > LOOP_COUNT) {
22055+ return CAN_NOT_FIND_DEVICE;
22056+ }
22057+ } while (Status != 1);
22058+// Disable STOP Interrupt
22059+ WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0, 0x10);
22060+// Clear Interrupt
22061+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
22062+
22063+ return SET_I2C_DONE;
22064+}
22065diff --git a/board/aspeed/ast2300/vfun.h b/board/aspeed/ast2300/vfun.h
22066new file mode 100755
22067index 0000000..90f9ec4
22068--- /dev/null
22069+++ b/board/aspeed/ast2300/vfun.h
22070@@ -0,0 +1,79 @@
22071+/*
22072+ * This program is distributed in the hope that it will be useful,
22073+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
22074+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22075+ * GNU General Public License for more details.
22076+ *
22077+ * You should have received a copy of the GNU General Public License
22078+ * along with this program; if not, write to the Free Software
22079+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22080+ */
22081+#ifndef _VFUN_H_
22082+#define _VFUN_H_
22083+
22084+//#define vBufAlign(x) ((x + 0x0000007F) & 0xFFFFFF80) //128 byte alignment
22085+#define vBufAlign(x) ((x + 0x000003FF) & 0xFFFFFC00) //128 byte alignment
22086+#define vBufAlign2(x) ((x + 0x0000FFFF) & 0xFFFF0000) //128 byte alignment
22087+#define v16byteAlign(x) ((x + 0x0000000F) & 0xFFFFFFF0)
22088+#define vBuf_ALIGNMENT 128
22089+
22090+#define HOST_TOTAL_SIZE 0x8000000 /* 128M */
22091+#define STATION_TOTAL_SIZE 0xF800000 /* 120M */
22092+
22093+#define VIDEO_SOURCE_SIZE 0x200000 /* 800X600X4 = 0x1D4C00 */
22094+#define VIDEO_MAX_STREAM_SIZE 0x400000 /* 32X128K = 0x400000 */
22095+#define VIDEO_FLAG_SIZE 0x5000 /* 1920X1200/128 = 0x4650*/
22096+#define VIDEO_CRC_SIZE 0x50000 /* 1920/64X1200X8 = 0x46500*/
22097+
22098+#define VIDEO1_EN_TOTAL_SIZE (VIDEO_SOURCE_SIZE*2+VIDEO_MAX_STREAM_SIZE+VIDEO_FLAG_SIZE+VIDEO_CRC_SIZE) /* 0x1655000 = about 23M*/
22099+#define VIDEO2_EN_TOTAL_SIZE VIDEO1_EN_TOTAL_SIZE
22100+//#define VIDEOM_EN_TOTAL_SIZE (VIDEO_SOURCE_SIZE*2+VIDEO_MAX_STREAM_SIZE+VIDEO_FLAG_SIZE) /* 0x1605000 = about 22.7M */
22101+//#define VIDEO_HOST_SIZE (VIDEO1_EN_TOTAL_SIZE + VIDEO2_EN_TOTAL_SIZE + VIDEOM_EN_TOTAL_SIZE) /* 0x69922816 = about 70M */
22102+#define VIDEO_HOST_SIZE (VIDEO1_EN_TOTAL_SIZE + VIDEO2_EN_TOTAL_SIZE) /* NOT NEED VIDEOM */
22103+
22104+#define VIDEO1_EN_BASE 0x100000
22105+#define VIDEO2_EN_BASE (VIDEO1_EN_BASE + VIDEO1_EN_TOTAL_SIZE)
22106+#define VIDEOM_EN_BASE (VIDEO2_EN_BASE + VIDEO2_EN_TOTAL_SIZE)
22107+
22108+#define VIDEO1_DE_TOTAL_SIZE (VIDEO_MAX_STREAM_SIZE + VIDEO_SOURCE_SIZE) /* 0xD00000 = 13M*/
22109+#define VIDEO2_DE_TOTAL_SIZE (VIDEO1_DE_TOTAL_SIZE)
22110+#define VIDEO_STATION_SIZE (VIDEO1_DE_TOTAL_SIZE + VIDEO2_DE_TOTAL_SIZE) /* 26M */
22111+
22112+#define VIDEO1_DE_BASE VIDEO_HOST_SIZE
22113+#define VIDEO2_DE_BASE (VIDEO1_DE_BASE + VIDEO1_DE_TOTAL_SIZE)
22114+#define VIDEO_ALL_SIZE (VIDEO_HOST_SIZE + VIDEO_STATION_SIZE) //Host and Station
22115+
22116+#define OutdwmBankModeHost(offset,data) WriteMemoryLongHost(DRAM_BASE,offset,data)
22117+#define IndwmBankModeHost(offset) ReadMemoryLongHost(DRAM_BASE,offset)
22118+
22119+ULONG UnlockVideoRegHost(ULONG MMIOBase, ULONG Key);
22120+BOOL CheckOnStartHost(void);
22121+BOOL CheckOnStartClient(void);
22122+void StartVideoCaptureTriggerHost(ULONG MMIOBase, ULONG offset);
22123+void StartVideoCaptureTriggerHost(ULONG MMIOBase, ULONG offset);
22124+void StartVideoCodecTriggerHost(ULONG MMIOBase, ULONG offset);
22125+ULONG UnlockSCURegHost(ULONG MMIOBase, ULONG Key);
22126+ULONG UnlockSCURegHost(ULONG MMIOBase, ULONG Key);
22127+void StartModeDetectionTriggerHost(ULONG MMIOBase, ULONG offset);
22128+void ClearVideoInterruptHost(ULONG MMIOBase, ULONG value);
22129+BOOL ReadVideoInterruptHost(ULONG MMIOBase, ULONG value);
22130+void StopModeDetectionTriggerHost(ULONG MMIOBase, ULONG offset);
22131+void ResetVideoHost(void);
22132+ULONG InitializeVideoEngineHost (ULONG MMIOBase,
22133+ int nVideo,
22134+ BOOL HorPolarity,
22135+ BOOL VerPolarity);
22136+ULONG InitializeVideoEngineClient (ULONG MMIOBase,
22137+ int nVideo);
22138+BYTE GetI2CRegClient(ULONG MMIOBase,
22139+ BYTE DeviceSelect,
22140+ BYTE DeviceAddress,
22141+ BYTE RegisterIndex);
22142+
22143+ULONG SetI2CRegClient(ULONG MMIOBase,
22144+ BYTE DeviceSelect,
22145+ BYTE DeviceAddress,
22146+ BYTE RegisterIndex,
22147+ BYTE RegisterValue);
22148+#endif //_VFUN_H_
22149+
22150diff --git a/board/aspeed/ast2300/vgahw.h b/board/aspeed/ast2300/vgahw.h
22151new file mode 100755
22152index 0000000..7cbba0d
22153--- /dev/null
22154+++ b/board/aspeed/ast2300/vgahw.h
22155@@ -0,0 +1,175 @@
22156+/*
22157+ * This program is distributed in the hope that it will be useful,
22158+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
22159+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22160+ * GNU General Public License for more details.
22161+ *
22162+ * You should have received a copy of the GNU General Public License
22163+ * along with this program; if not, write to the Free Software
22164+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22165+ */
22166+/******************************************************************************
22167+ * Mode Stuff
22168+ ******************************************************************************/
22169+/* Default Settings */
22170+#define CRT_LOW_THRESHOLD_VALUE 0x12
22171+#define CRT_HIGH_THRESHOLD_VALUE 0x1E
22172+
22173+/* Output Selection */
22174+#define CRT1 0x00
22175+#define CRT2 0x01
22176+#define DVI1 0x10
22177+#define DVI2 0x11
22178+#define LVDS1 0x20
22179+#define LVDS2 0x21
22180+
22181+/* Mode Limitation */
22182+#define MAX_HResolution 1600
22183+#define MAX_VResolution 1200
22184+
22185+/* Std. Table Index Definition */
22186+#define TextModeIndex 0
22187+#define EGAModeIndex 1
22188+#define VGAModeIndex 2
22189+#define HiCModeIndex 3
22190+#define TrueCModeIndex 4
22191+
22192+/* DCLK Index */
22193+#define VCLK25_175 0x00
22194+#define VCLK28_322 0x01
22195+#define VCLK31_5 0x02
22196+#define VCLK36 0x03
22197+#define VCLK40 0x04
22198+#define VCLK49_5 0x05
22199+#define VCLK50 0x06
22200+#define VCLK56_25 0x07
22201+#define VCLK65 0x08
22202+#define VCLK75 0x09
22203+#define VCLK78_75 0x0A
22204+#define VCLK94_5 0x0B
22205+#define VCLK108 0x0C
22206+#define VCLK135 0x0D
22207+#define VCLK157_5 0x0E
22208+#define VCLK162 0x0F
22209+#define VCLK119 0x10
22210+
22211+/* Flags Definition */
22212+#define Charx8Dot 0x00000001
22213+#define HalfDCLK 0x00000002
22214+#define DoubleScanMode 0x00000004
22215+#define LineCompareOff 0x00000008
22216+#define SyncPP 0x00000000
22217+#define SyncPN 0x00000040
22218+#define SyncNP 0x00000080
22219+#define SyncNN 0x000000C0
22220+#define HBorder 0x00000020
22221+#define VBorder 0x00000010
22222+#define COLORINDEX 0x00000000
22223+#define MONOINDEX 0x00000100
22224+
22225+/* DAC Definition */
22226+#define DAC_NUM_TEXT 64
22227+#define DAC_NUM_EGA 64
22228+#define DAC_NUM_VGA 256
22229+
22230+/* AST3000 Reg. Definition */
22231+#define AST3000_VGAREG_BASE 0x1e6e6000
22232+#define AST3000_VGA1_CTLREG 0x00
22233+#define AST3000_VGA1_CTLREG2 0x04
22234+#define AST3000_VGA1_STATUSREG 0x08
22235+#define AST3000_VGA1_PLL 0x0C
22236+#define AST3000_VGA1_HTREG 0x10
22237+#define AST3000_VGA1_HRREG 0x14
22238+#define AST3000_VGA1_VTREG 0x18
22239+#define AST3000_VGA1_VRREG 0x1C
22240+#define AST3000_VGA1_STARTADDR 0x20
22241+#define AST3000_VGA1_OFFSETREG 0x24
22242+#define AST3000_VGA1_THRESHOLD 0x28
22243+#define AST3000_HWC1_OFFSET 0x30
22244+#define AST3000_HWC1_XY 0x34
22245+#define AST3000_HWC1_PBase 0x38
22246+#define AST3000_OSD1_H 0x40
22247+#define AST3000_OSD1_V 0x44
22248+#define AST3000_OSD1_PBase 0x48
22249+#define AST3000_OSD1_Offset 0x4C
22250+#define AST3000_OSD1_THRESHOLD 0x50
22251+
22252+#define AST3000_VGA2_CTLREG 0x60
22253+#define AST3000_VGA2_CTLREG2 0x64
22254+#define AST3000_VGA2_STATUSREG 0x68
22255+#define AST3000_VGA2_PLL 0x6C
22256+#define AST3000_VGA2_HTREG 0x70
22257+#define AST3000_VGA2_HRREG 0x74
22258+#define AST3000_VGA2_VTREG 0x78
22259+#define AST3000_VGA2_VRREG 0x7C
22260+#define AST3000_VGA2_STARTADDR 0x80
22261+#define AST3000_VGA2_OFFSETREG 0x84
22262+#define AST3000_VGA2_THRESHOLD 0x88
22263+#define AST3000_HWC2_OFFSET 0x90
22264+#define AST3000_HWC2_XY 0x94
22265+#define AST3000_HWC2_PBase 0x98
22266+#define AST3000_OSD2_H 0xA0
22267+#define AST3000_OSD2_V 0xA4
22268+#define AST3000_OSD2_PBase 0xA8
22269+#define AST3000_OSD2_Offset 0xAC
22270+#define AST3000_OSD2_THRESHOLD 0xB0
22271+
22272+/* Data Structure */
22273+typedef struct {
22274+ UCHAR ModeName[20];
22275+ USHORT usModeIndex;
22276+ USHORT usModeID;
22277+ USHORT usColorIndex;
22278+ USHORT usRefreshRateIndex;
22279+ USHORT usWidth;
22280+ USHORT usHeight;
22281+ USHORT usBitsPerPlane;
22282+ USHORT usRefreshRate;
22283+} ModeInfoStruct;
22284+
22285+typedef struct {
22286+
22287+ UCHAR MISC;
22288+ UCHAR SEQ[4];
22289+ UCHAR CRTC[25];
22290+ UCHAR AR[20];
22291+ UCHAR GR[9];
22292+
22293+} VBIOS_STDTABLE_STRUCT, *PVBIOS_STDTABLE_STRUCT;
22294+
22295+typedef struct {
22296+
22297+ ULONG HT;
22298+ ULONG HDE;
22299+ ULONG HFP;
22300+ ULONG HSYNC;
22301+ ULONG VT;
22302+ ULONG VDE;
22303+ ULONG VFP;
22304+ ULONG VSYNC;
22305+ ULONG DCLKIndex;
22306+ ULONG Flags;
22307+
22308+ ULONG ulRefreshRate;
22309+ ULONG ulRefreshRateIndex;
22310+ ULONG ulModeID;
22311+
22312+} VBIOS_ENHTABLE_STRUCT, *PVBIOS_ENHTABLE_STRUCT;
22313+
22314+typedef struct {
22315+ UCHAR Param1;
22316+ UCHAR Param2;
22317+ UCHAR Param3;
22318+} VBIOS_DCLK_INFO, *PVBIOS_DCLK_INFO;
22319+
22320+typedef struct {
22321+ UCHAR DACR;
22322+ UCHAR DACG;
22323+ UCHAR DACB;
22324+} VBIOS_DAC_INFO, *PVBIOS_DAC_INFO;
22325+
22326+typedef struct {
22327+ PVBIOS_STDTABLE_STRUCT pStdTableEntry;
22328+ PVBIOS_ENHTABLE_STRUCT pEnhTableEntry;
22329+
22330+} VBIOS_MODE_INFO, *PVBIOS_MODE_INFO;
22331diff --git a/board/aspeed/ast2300/vhace.c b/board/aspeed/ast2300/vhace.c
22332new file mode 100755
22333index 0000000..d045cbd
22334--- /dev/null
22335+++ b/board/aspeed/ast2300/vhace.c
22336@@ -0,0 +1,66 @@
22337+/*
22338+ * This program is distributed in the hope that it will be useful,
22339+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
22340+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22341+ * GNU General Public License for more details.
22342+ *
22343+ * You should have received a copy of the GNU General Public License
22344+ * along with this program; if not, write to the Free Software
22345+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22346+ */
22347+#define HASH_GLOBALS
22348+#include "type.h"
22349+#include "vdef.h"
22350+#include "vhace.h"
22351+#include "vfun.h"
22352+
22353+void HashAst3000(ULONG ulLength, ULONG *output, ULONG ulHashMode)
22354+{
22355+ ULONG i, ulTemp, ulCommand, ulDigestLength;
22356+ ULONG ulValue;
22357+
22358+ /* Get Info */
22359+ switch (ulHashMode)
22360+ {
22361+ case VHASHMODE_MD5:
22362+ ulCommand = VHASH_ALG_SELECT_MD5;
22363+ ulDigestLength = 16;
22364+ break;
22365+ case VHASHMODE_SHA1:
22366+ ulCommand = VHASH_ALG_SELECT_SHA1;
22367+ ulDigestLength = 20;
22368+ break;
22369+ case VHASHMODE_SHA256:
22370+ ulCommand = VHASH_ALG_SELECT_SHA256;
22371+ ulDigestLength = 32;
22372+ break;
22373+ case VHASHMODE_SHA224:
22374+ ulCommand = VHASH_ALG_SELECT_SHA224;
22375+ ulDigestLength = 28;
22376+ break;
22377+ }
22378+
22379+ /* Init. HW */
22380+ WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_SRC_BASE_OFFSET, g_HashSrcBuffer);
22381+ WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_DST_BASE_OFFSET, g_HashDstBuffer);
22382+ WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_LEN_OFFSET, ulLength);
22383+
22384+ /* write src */
22385+ //already fill in g_VIDEO1_COMPRESS_BUF_ADDR
22386+
22387+ /* fire cmd */
22388+ WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_CMD_OFFSET, ulCommand);
22389+
22390+ /* get digest */
22391+ do {
22392+ ulTemp = ReadMemoryLongHost(VHAC_REG_BASE, VREG_HASH_STATUS_OFFSET);
22393+ } while (ulTemp & VHASH_BUSY);
22394+
22395+ for (i=0; i<ulDigestLength/4; i++)
22396+ {
22397+ ulValue = *(((ULONG *)g_HashDstBuffer) + i);
22398+
22399+ //output is ULONG pointer
22400+ *(output + i) = ulValue;
22401+ }
22402+}
22403diff --git a/board/aspeed/ast2300/vhace.h b/board/aspeed/ast2300/vhace.h
22404new file mode 100755
22405index 0000000..460989b
22406--- /dev/null
22407+++ b/board/aspeed/ast2300/vhace.h
22408@@ -0,0 +1,58 @@
22409+/*
22410+ * This program is distributed in the hope that it will be useful,
22411+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
22412+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22413+ * GNU General Public License for more details.
22414+ *
22415+ * You should have received a copy of the GNU General Public License
22416+ * along with this program; if not, write to the Free Software
22417+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22418+ */
22419+#ifndef _VHACE_H_
22420+#define _VHACE_H_
22421+
22422+#define VHASHMODE_MD5 0x00
22423+#define VHASHMODE_SHA1 0x01
22424+#define VHASHMODE_SHA256 0x02
22425+#define VHASHMODE_SHA224 0x03
22426+
22427+#define VHASH_ALG_SELECT_MASK 0x70
22428+#define VHASH_ALG_SELECT_MD5 0x00
22429+#define VHASH_ALG_SELECT_SHA1 0x20
22430+#define VHASH_ALG_SELECT_SHA224 0x40
22431+#define VHASH_ALG_SELECT_SHA256 0x50
22432+
22433+#define VHASH_BUSY 0x01
22434+
22435+#define VHAC_REG_BASE 0x1e6e0000
22436+#define VHAC_REG_OFFSET 0x3000
22437+
22438+#define VREG_HASH_SRC_BASE_OFFSET (0x20+VHAC_REG_OFFSET)
22439+#define VREG_HASH_DST_BASE_OFFSET (0x24+VHAC_REG_OFFSET)
22440+#define VREG_HASH_KEY_BASE_OFFSET (0x28+VHAC_REG_OFFSET)
22441+#define VREG_HASH_LEN_OFFSET (0x2C+VHAC_REG_OFFSET)
22442+#define VREG_HASH_CMD_OFFSET (0x30+VHAC_REG_OFFSET)
22443+
22444+#define VREG_HASH_STATUS_OFFSET (0x1C+VHAC_REG_OFFSET)
22445+
22446+typedef struct
22447+{
22448+ int HashMode;
22449+ int DigestLen;
22450+} HASH_METHOD;
22451+
22452+
22453+#ifdef HASH_GLOBALS
22454+#define HASH_EXT
22455+#else
22456+#define HASH_EXT extern
22457+#endif
22458+
22459+HASH_EXT HASH_METHOD g_HashMethod;
22460+HASH_EXT BYTE g_DigestBuf[32];
22461+HASH_EXT ULONG g_HashSrcBuffer;
22462+HASH_EXT ULONG g_HashDstBuffer;
22463+
22464+void HashAst3000(ULONG ulLength, ULONG *output, ULONG ulHashMode);
22465+#endif
22466+
22467diff --git a/board/aspeed/ast2300/videotest.c b/board/aspeed/ast2300/videotest.c
22468new file mode 100755
22469index 0000000..f2e4953
22470--- /dev/null
22471+++ b/board/aspeed/ast2300/videotest.c
22472@@ -0,0 +1,779 @@
22473+/*
22474+ * This program is distributed in the hope that it will be useful,
22475+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
22476+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22477+ * GNU General Public License for more details.
22478+ *
22479+ * You should have received a copy of the GNU General Public License
22480+ * along with this program; if not, write to the Free Software
22481+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22482+ * MA 02111-1307 USA
22483+ */
22484+
22485+/*
22486+ * Diagnostics support
22487+ */
22488+#include <common.h>
22489+#include <command.h>
22490+#include <malloc.h>
22491+#include <post.h>
22492+
22493+#include "slt.h"
22494+#define WIN_GLOBALS
22495+#include "type.h"
22496+#include "vreg.h"
22497+#define VESA_GLOBALS
22498+#include "vesa.h"
22499+#include "vfun.h"
22500+#include "vdef.h"
22501+#include "vhace.h"
22502+#include "crt.h"
22503+#include "videotest.h"
22504+
22505+#define VHASH_ALIGNMENT 16
22506+#define VHASH_MAX_DST (32+VHASH_ALIGNMENT)
22507+
22508+
22509+#if ((CFG_CMD_SLT & CFG_CMD_VIDEOTEST) && defined(CONFIG_SLT))
22510+#include "videotest.h"
22511+
22512+#define RAND_MAX 32767 //2^16-1
22513+
22514+ULONG randSeed = 1;
22515+
22516+void srand(ULONG seed)
22517+{
22518+ randSeed = seed;
22519+}
22520+
22521+int rand(void)
22522+{
22523+ randSeed = randSeed * 214013 + 2531011;
22524+ return (int)(randSeed >> 17); //32 -15 = 17
22525+}
22526+
22527+//static unsigned char CaptureVideo1Buf1Addr[VIDEO_SOURCE_SIZE], CaptureVideo1Buf2Addr[VIDEO_SOURCE_SIZE], Video1CompressBufAddr[CRYPTO_MAX_CONTEXT];
22528+ULONG pCaptureVideo1Buf1Addr[VIDEO_SOURCE_SIZE/4], pCaptureVideo1Buf2Addr[VIDEO_SOURCE_SIZE/4], pVideo1CompressBufAddr[VIDEO_MAX_STREAM_SIZE/4], pVideo1FlagBufAddr[VIDEO_FLAG_SIZE];
22529+ULONG pCaptureVideo2Buf1Addr[VIDEO_SOURCE_SIZE/4], pCaptureVideo2Buf2Addr[VIDEO_SOURCE_SIZE/4], pVideo2CompressBufAddr[VIDEO_MAX_STREAM_SIZE/4], pVideo2FlagBufAddr[VIDEO_FLAG_SIZE];
22530+
22531+ULONG pVHashDstBuffer[VHASH_MAX_DST/4];
22532+
22533+ULONG pVideo1DecAddr[VIDEO_SOURCE_SIZE/4];
22534+ULONG pCrt1Addr[VIDEO_SOURCE_SIZE/4];
22535+//ULONG pCap1Addr[VIDEO_SOURCE_SIZE/4];
22536+
22537+BOOL AllocateEncodeBufHost(ULONG MMIOBase, int nVideo)
22538+{
22539+ //ULONG Addr;
22540+ //ULONG dwRegOffset = nVideo * 0x100;
22541+
22542+ if (VIDEO1 == nVideo)
22543+ {
22544+
22545+ //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
22546+ //pCaptureVideo1Buf1Addr = malloc(VIDEO_SOURCE_SIZE);
22547+
22548+ g_CAPTURE_VIDEO1_BUF1_ADDR = vBufAlign((ULONG)pCaptureVideo1Buf1Addr);
22549+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, g_CAPTURE_VIDEO1_BUF1_ADDR, BUF_1_ADDR_MASK);
22550+
22551+ //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
22552+ //pCaptureVideo1Buf2Addr = malloc(VIDEO_SOURCE_SIZE);
22553+
22554+ g_CAPTURE_VIDEO1_BUF2_ADDR = vBufAlign((ULONG)pCaptureVideo1Buf2Addr);
22555+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, g_CAPTURE_VIDEO1_BUF2_ADDR, BUF_2_ADDR_MASK);
22556+
22557+ //Addr = (ULONG)malloc(pVideoInfo->uStreamBufSize.StreamBufSize.RingBufNum * pVideoInfo->uStreamBufSize.StreamBufSize.PacketSize)
22558+ //pVideo1CompressBufAddr = malloc(VIDEO_MAX_STREAM_SIZE);
22559+ g_VIDEO1_COMPRESS_BUF_ADDR = vBufAlign((ULONG)pVideo1CompressBufAddr);
22560+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_ADDR_REG, g_VIDEO1_COMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
22561+
22562+ //Addr = (ULONG)malloc((pVideoInfo->SrcHeigh/64) * pVideoInfo->SrcWidth * 8);
22563+ //g_VIDEO1_CRC_BUF_ADDR = vBufAlign((ULONG)malloc(VIDEO_MAX_STREAM_SIZE));
22564+ //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, g_VIDEO1_CRC_BUF_ADDR, BUF_2_ADDR_MASK);
22565+
22566+
22567+ //Addr = (ULONG)malloc(pVideoInfo->SrcHeigh * pVideoInfo->SrcWidth / 128 (/64*4/8));
22568+ //pVideo1FlagBufAddr = malloc(VIDEO_FLAG_SIZE);
22569+ g_VIDEO1_FLAG_BUF_ADDR = vBufAlign((ULONG)pVideo1FlagBufAddr);
22570+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_FLAG_BUF_ADDR_REG, g_VIDEO1_FLAG_BUF_ADDR, BUF_2_ADDR_MASK);
22571+ }
22572+ else if (VIDEO2 == nVideo)
22573+ {
22574+ //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
22575+ //pCaptureVideo2Buf1Addr = malloc(VIDEO_SOURCE_SIZE);
22576+ g_CAPTURE_VIDEO2_BUF1_ADDR = vBufAlign((ULONG)pCaptureVideo2Buf1Addr);
22577+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_BUF_1_ADDR_REG, g_CAPTURE_VIDEO2_BUF1_ADDR, BUF_1_ADDR_MASK);
22578+
22579+ //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
22580+ //pCaptureVideo2Buf2Addr = malloc(VIDEO_SOURCE_SIZE);
22581+ g_CAPTURE_VIDEO2_BUF2_ADDR = vBufAlign((ULONG)pCaptureVideo2Buf2Addr);
22582+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_BUF_2_ADDR_REG, g_CAPTURE_VIDEO2_BUF2_ADDR, BUF_2_ADDR_MASK);
22583+
22584+ //Addr = (ULONG)malloc(pVideoInfo->uStreamBufSize.StreamBufSize.RingBufNum * pVideoInfo->uStreamBufSize.StreamBufSize.PacketSize)
22585+ //pVideo2CompressBufAddr = malloc(VIDEO_MAX_STREAM_SIZE);
22586+ g_VIDEO2_COMPRESS_BUF_ADDR = vBufAlign((ULONG)pVideo2CompressBufAddr);
22587+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_COMPRESS_BUF_ADDR_REG, g_VIDEO2_COMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
22588+
22589+ //Addr = (ULONG)malloc((pVideoInfo->SrcHeigh/64) * pVideoInfo->SrcWidth * 8);
22590+ //g_VIDEO1_CRC_BUF_ADDR = vBufAlign((ULONG)malloc(VIDEO_MAX_STREAM_SIZE));
22591+ //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, g_VIDEO1_CRC_BUF_ADDR, BUF_2_ADDR_MASK);
22592+
22593+
22594+ //Addr = (ULONG)malloc(pVideoInfo->SrcHeigh * pVideoInfo->SrcWidth / 128 (/64*4/8));
22595+ //pVideo2FlagBufAddr = malloc(VIDEO_FLAG_SIZE);
22596+ g_VIDEO2_FLAG_BUF_ADDR = vBufAlign((ULONG)pVideo2FlagBufAddr);
22597+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_FLAG_BUF_ADDR_REG, g_VIDEO2_FLAG_BUF_ADDR, BUF_2_ADDR_MASK);
22598+ }
22599+
22600+}
22601+
22602+/********************************************************/
22603+/* 1. product random data to encode */
22604+/* 2. use hash to verify encode function */
22605+/* 3. use encode stream to decompress original data */
22606+/********************************************************/
22607+int CodecTest(void)
22608+{
22609+ int num, i=0, j=0;
22610+ ULONG ulTemp = 0, ulTemp2;
22611+ int dwValue;
22612+ ULONG ulHWWp;
22613+ ULONG ulHWPt;
22614+
22615+ //max size
22616+ ULONG tArray[32/4];
22617+
22618+ //mode detection
22619+ BOOL bExternal = TRUE;
22620+ BOOL bAnalog = TRUE;
22621+ ULONG Status;
22622+
22623+#if defined(CONFIG_AST2300)
22624+ ULONG ulHashSha1[5] = {0x3f0c2ad6,0xc8eb7074,0xa9929352,0xfcd5b8b0,0x76fa8461};
22625+ ULONG aHashDecode[5] = {0xb23b62bb,0xd22a602b,0x113038a0,0x7217c6ab,0xcb156f06};
22626+#else
22627+ ULONG ulHashSha1[5] = {0x2a19e99f,0x99b1bb2d,0x9ac82862,0x49205e43,0x6bc4b4d7};
22628+ ULONG aHashDecode[5] = {0x2907a827,0xaf337079,0x47817f1f,0xb0b7cd68,0x8d33bd2};
22629+#endif
22630+
22631+ //Load pattern to src1 & src2 buffer
22632+ srand(1);
22633+
22634+ //Total size : DefWidth*DeHeight*4
22635+ //rand function: 16 bits one time is equal to 2 bytes
22636+ //OutdwmBankMode: 32 bits one time is equal to 4 bytes
22637+ for (i=0; i<g_DefWidth*g_DefHeight*2; i++)
22638+ {
22639+ if (i%2)
22640+ {
22641+ ulTemp2 = rand();
22642+ ulTemp = (ulTemp2 << 16) | ulTemp;
22643+ //WriteMemoryLongHost(DRAM_BASE, g_CAPTURE_VIDEO1_BUF1_ADDR + ((i-1)/2)*4, ulTemp);
22644+ *(((ULONG *)g_CAPTURE_VIDEO1_BUF1_ADDR) + (i-1)/2) = ulTemp;
22645+ ulTemp = 0;
22646+ }
22647+ else
22648+ {
22649+ ulTemp = rand();
22650+ }
22651+ }
22652+
22653+ /* init encoder engine */
22654+ InitializeVideoEngineHost (0,
22655+ VIDEO1,
22656+ vModeTable[2].HorPolarity,
22657+ vModeTable[2].VerPolarity);
22658+
22659+ /* reset offset pointer register*/
22660+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, VIDEO_CODEC_TRIGGER | VIDEO_CAPTURE_TRIGGER);
22661+
22662+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_READ_OFFSET_REG, 0, COMPRESS_BUF_READ_OFFSET_MASK);
22663+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ, 0, BUF_CODEC_OFFSET_MASK);
22664+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG, 0, COMPRESS_BUF_PROCESS_OFFSET_MASK);
22665+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_FRAME_END_READ, 0, COMPRESS_FRAME_END_READ_MASK);
22666+
22667+ /* start compress stream */
22668+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, MODE_DETECTION_TRIGGER, MODE_DETECTION_TRIGGER);
22669+ //Stream mode: set CODEC trigger first
22670+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, VIDEO_CODEC_TRIGGER, VIDEO_CODEC_TRIGGER);
22671+
22672+ //Stream mode: start trigger (only trigger capture bit)
22673+ StartVideoCaptureTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
22674+
22675+ //stop engine
22676+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, 0xFF);
22677+#if defined(CONFIG_AST2300)
22678+ do { /* wait compress engine idle */
22679+ ulTemp = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
22680+ } while (!(ulTemp & 0x40000));
22681+#endif
22682+
22683+ //read 30 times to get HW write pointer
22684+ for (i=0; i<30000; i++)
22685+ ulHWWp = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ);
22686+
22687+ g_HashSrcBuffer = g_VIDEO1_COMPRESS_BUF_ADDR + 128; //skip encode data 128 byte
22688+ g_HashDstBuffer = v16byteAlign((unsigned long)pVHashDstBuffer);
22689+ ulTemp = 300;
22690+
22691+ //Enable hash clock
22692+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_HACE, STOP_HACE_MASK);
22693+ g_HashMethod.HashMode = VHASHMODE_SHA1;
22694+ g_HashMethod.DigestLen = 20;
22695+ HashAst3000(ulTemp, tArray, g_HashMethod.HashMode);
22696+
22697+ if (strncmp((const char *)tArray, (const char *)ulHashSha1, g_HashMethod.DigestLen))
22698+ {
22699+ printf("[VIDEO] Encoder Test: Wrong\n");
22700+ //ExitVideoTest();
22701+ return VIDEO_ENCODE_FAIL;
22702+ }
22703+ else
22704+ {
22705+ printf("[VIDEO] Encoder Test: Pass\n");
22706+ }
22707+
22708+#if 0
22709+ /******** prepare for next decoding test at the same chip ***********/
22710+ ResetVideoHost();
22711+
22712+ dwValue=0;
22713+
22714+ do
22715+ {
22716+ dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
22717+ i++;
22718+ }
22719+ while ((VIDEO_UNLOCK != dwValue) && (i<10));
22720+
22721+ if (VIDEO_UNLOCK != dwValue)
22722+ {
22723+ printf("[VIDEO] Video register is locked");
22724+ return VIDEO_UNLOCK_FAIL;
22725+ }
22726+
22727+ // allocate decoding buffer
22728+ //Use Compress buffer last time, and Don't need to allocate
22729+ g_VIDEO1_DECODE_BUF_1_ADDR = g_VIDEO1_COMPRESS_BUF_ADDR;
22730+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, g_VIDEO1_DECODE_BUF_1_ADDR, BUF_1_ADDR_MASK);
22731+
22732+ // pVideo1DecAddr = malloc(VIDEO_SOURCE_SIZE);
22733+ g_VIDEO1_DECOMPRESS_BUF_ADDR = vBufAlign((unsigned long)pVideo1DecAddr);
22734+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_ADDR_REG, g_VIDEO1_DECOMPRESS_BUF_ADDR, COMPRESS_BUF_ADDR_MASK);
22735+
22736+ //Addr = (ULONG)malloc(256);
22737+ //g_VIDEO1_RC4_BUF_ADDR = Addr;
22738+ //g_VIDEO1_DECODE_RC4_BUF_ADDR = g_VIDEO1_DECOMPRESS_BUF_ADDR + 0x800000; //assume video size is 8MB for umcompressed buf;
22739+ //WriteMemoryLongWithMASKClient(VIDEO_REG_BASE, VIDEO1_RC4_TABLE_ADDR, g_VIDEO1_DECODE_RC4_BUF_ADDR, RC4_TABLE_ADDR_MASK);
22740+
22741+ //HW recommanded value
22742+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, g_VIDEO1_DECOMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
22743+ //WriteMemoryLongWithMASKClient(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, 0, BUF_2_ADDR_MASK);
22744+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, 0, BUF_2_ADDR_MASK);
22745+
22746+ /* init encoder engine */
22747+ InitializeVideoEngineClient (0, VIDEO1);
22748+
22749+ /* reset offset pointer register*/
22750+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, VIDEO_CODEC_TRIGGER | VIDEO_CAPTURE_TRIGGER);
22751+
22752+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_READ_OFFSET_REG, 0, COMPRESS_BUF_READ_OFFSET_MASK);
22753+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ, 0, BUF_CODEC_OFFSET_MASK);
22754+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG, 0, COMPRESS_BUF_PROCESS_OFFSET_MASK);
22755+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_FRAME_END_READ, 0, COMPRESS_FRAME_END_READ_MASK);
22756+
22757+ StartVideoCodecTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
22758+
22759+ //wrtie SW write pointer
22760+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_DECOMPRESS_BUF_PROCESS_OFFSET_REG, ulHWWp, COMPRESS_BUF_READ_OFFSET_MASK);
22761+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_DECOMPRESS_BUF_WRITE_OFFSET_REG, ulHWWp, COMPRESS_BUF_READ_OFFSET_MASK);
22762+
22763+ i = 0;
22764+
22765+ do
22766+ {
22767+ ulHWPt = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ);
22768+ i++;
22769+ }while((ulHWPt != ulHWWp) && (i<10000));
22770+
22771+ if (10000 > i)
22772+ {
22773+ printf("[VIDEO] Decoder Pointer cannot move!!! /n");
22774+ //ExitVideoTest();
22775+ return VIDEO_DECODE_FAIL;
22776+ }
22777+
22778+ //8*8 YUVA block
22779+ for (i=24; i<g_DefWidth*g_DefHeight; i=i+32)
22780+ {
22781+ *(((ULONG *)g_VIDEO1_DECOMPRESS_BUF_ADDR) + i) = 0x0;
22782+ *(((ULONG *)g_VIDEO1_DECOMPRESS_BUF_ADDR) + i+1) = 0x0;
22783+ }
22784+
22785+ g_HashSrcBuffer = g_VIDEO1_DECOMPRESS_BUF_ADDR;
22786+ //g_HashDstBuffer = VIDEO1_EN_BASE + VIDEO_ALL_SIZE; //config forward
22787+
22788+ ulTemp = 300;
22789+
22790+ //Enable hash clock
22791+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_HACE, STOP_HACE_MASK);
22792+ g_HashMethod.HashMode = VHASHMODE_SHA1;
22793+ g_HashMethod.DigestLen = 20;
22794+ HashAst3000(ulTemp, tArray, g_HashMethod.HashMode);
22795+
22796+ if (strncmp((const char *)tArray, (const char *)aHashDecode, g_HashMethod.DigestLen))
22797+ {
22798+ printf("[VIDEO] Decoder Test: Wrong\n");
22799+ //ExitVideoTest();
22800+ return VIDEO_DECODE_FAIL;
22801+ }
22802+ else
22803+ {
22804+ printf("[VIDEO] Decoder Test: Pass\n");
22805+ }
22806+#endif
22807+
22808+ return VIDEO_TEST_OK;
22809+}
22810+
22811+/********************************************************/
22812+/* Only used in the host */
22813+/* test function: Mode detection and Capture pattern */
22814+/********************************************************/
22815+int CapTest(void)
22816+{
22817+ ULONG dwValue, Status;
22818+ int i;
22819+ BOOL bAnalog;
22820+ ULONG HStart, HEnd, VStart, VEnd;
22821+ USHORT usCRTHor, usCRTVer;
22822+ ULONG ulHor, ulVer;
22823+ ULONG ulVGABaseAddr, ulCapAddr;
22824+ ULONG ulFlag;
22825+
22826+ printf("\n --------- Mode Detection Test --------- \n");
22827+ //clear clear register
22828+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG, 0);
22829+ dwValue = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG);
22830+
22831+ // Note: Current mode detection procedure has to set signal input 1st
22832+ //Note: Clear and enable interrupt Encode
22833+ ClearVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_CLEAR);
22834+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_EN_REG, VIDEO1_MODE_DETECTION_READY_INT_EN, VIDEO1_MODE_DETECTION_READY_INT_EN);
22835+ // Set input signal
22836+ dwValue |= EXTERNAL_VGA_SOURCE;
22837+
22838+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG, (dwValue <<EXTERNAL_SOURCE_BIT), EXTERNAL_SOURCE_MASK);
22839+
22840+// Set H/V stable maximum
22841+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_VERTICAL_STABLE_MAXIMUM << VER_STABLE_MAX_BIT), 0x000F0000);
22842+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_HORIZONTAL_STABLE_MAXIMUM << HOR_STABLE_MAX_BIT), HOR_STABLE_MAX_BIT_MASK);
22843+// Set H/V stable threshold
22844+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_VERTICAL_STABLE_THRESHOLD << VER_STABLE_THRES_BIT), VER_STABLE_THRES_BIT_MASK);
22845+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_HORIZONTAL_STABLE_THRESHOLD << HOR_STABLE_THRES_BIT), HOR_STABLE_THRES_BIT_MASK);
22846+
22847+ //Trigger mode detection
22848+ // turn off WATCH_DOG first
22849+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, (WATCH_DOG_OFF << WATCH_DOG_ENABLE_BIT), WATCH_DOG_EN_MASK);
22850+
22851+ // Note: Clear mode detection ready interrupt
22852+ //ClearVideoInterrupt(MMIOBase, MODE_DETECTION_READY_CLEAR);
22853+ StartModeDetectionTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
22854+
22855+
22856+// Note: Polling mode detection ready interrupt
22857+ //it sometime take a long time, especially during change mode,
22858+ //so the loop count must be big, or you can't pull it by timer
22859+ i = 0;
22860+ do {
22861+
22862+ Status = ReadVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_READ);
22863+ i++;
22864+ } while ((!Status) & (i<500000));
22865+
22866+ if (!Status)
22867+ {
22868+ printf("[VIDEO] Mode detection error\n");
22869+ //ExitVideoTest();
22870+ return VIDEO_TEST_FAIL;
22871+ }
22872+
22873+ HStart = (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_H_REG) & LEFT_EDGE_LOCATION_MASK) >> LEFT_EDGE_LOCATION_BIT;
22874+ HEnd = (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_H_REG) & RIGHT_EDGE_LOCATION_MASK) >> RIGHT_EDGE_LOCATION_BIT;
22875+
22876+ VStart = (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_V_REG) & TOP_EDGE_LOCATION_MASK) >> TOP_EDGE_LOCATION_BIT;
22877+ VEnd = (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_V_REG) & BOTTOM_EDGE_LOCATION_MASK) >> BOTTOM_EDGE_LOCATION_BIT;
22878+
22879+ ulHor = HEnd-HStart+1;
22880+ ulVer = VEnd-VStart+1;
22881+
22882+ printf("[VIDEO] Resolution: H[%d] * V[%d]\n", ulHor, ulVer);
22883+
22884+ if ((g_DefWidth == ulHor) & (g_DefHeight == ulVer))
22885+ {
22886+ printf("[VIDEO] Mode detection PASS\n");
22887+ }
22888+ else
22889+ {
22890+ printf("[VIDEO] Mode detection FAIL\n");
22891+ return VIDEO_TEST_FAIL;
22892+ }
22893+
22894+ if(!((ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_MODE_DETECTION_STATUS_READ_REG) & ANALONG_DIGITAL_READ) >> ANALONG_DIGITAL_READ_BIT))
22895+ bAnalog = FALSE;
22896+ else
22897+ bAnalog = TRUE;
22898+
22899+ // Note: Clear mode detection ready interrupt
22900+ ClearVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_CLEAR);
22901+
22902+ printf("\n --------- Capture Test --------- \n");
22903+
22904+ //capture engine
22905+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, (HEnd << VIDEO_HDE_END_BIT), VIDEO_HDE_END_MASK);
22906+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, (HStart << VIDEO_HDE_START_BIT), VIDEO_HDE_START_MASK);
22907+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_V_REG, (VEnd << VIDEO_VDE_END_BIT), VIDEO_VDE_END_MASK);
22908+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_V_REG, (VStart << VIDEO_VDE_START_BIT), VIDEO_VDE_START_MASK);
22909+
22910+ ulCapAddr = vBufAlign2((ULONG)pCaptureVideo1Buf1Addr);
22911+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, ulCapAddr, BUF_1_ADDR_MASK);
22912+
22913+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, 0, BUF_2_ADDR_MASK);
22914+
22915+ InitializeVideoEngineHost (0,
22916+ VIDEO1,
22917+ vModeTable[2].HorPolarity,
22918+ vModeTable[2].VerPolarity);
22919+
22920+ WriteMemoryLongHost(VIDEO_REG_BASE, 0x04, 0x01);
22921+ WriteMemoryLongHost(VIDEO_REG_BASE, 0x300, 0x0);
22922+#if defined(CONFIG_AST2300)
22923+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0x0880, 0x0ec0);
22924+#elif defined(CONFIG_AST3000)
22925+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0x2800, 0x2800);
22926+#else
22927+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0xa00, 0x2a80); //tile mode
22928+#endif
22929+
22930+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, 0xa0000000, 0xa0000000);
22931+
22932+ //only trigger capture, in source buffer (vr44), the front of data is correct.
22933+ //StartVideoCaptureTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
22934+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, VIDEO_CAPTURE_TRIGGER);
22935+
22936+ i = 0;
22937+ do {
22938+ Status = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG) & CAPTURE_READY_MASK;
22939+ i++;
22940+ } while ((!Status) & (i<500000));
22941+
22942+ if (!Status)
22943+ {
22944+ printf("[VIDEO] Capture is not READY\n");
22945+ return VIDEO_TEST_FAIL;
22946+ }
22947+
22948+#if !defined(CONFIG_AST2300)
22949+ ulVGABaseAddr = ulCapAddr + 0x1000;
22950+
22951+ /* check pattern */
22952+ ulFlag = 0; //no 0 is error
22953+
22954+ for (i=0; i<100; i++)
22955+ {
22956+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32);
22957+ if (0x32323232 != dwValue)
22958+ {
22959+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
22960+ printf("[VIDEO]1 i=%d value=%x\n", i, dwValue);
22961+ ulFlag = 1;
22962+ break;
22963+ }
22964+
22965+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 4);
22966+ if (0x32323232 != dwValue)
22967+ {
22968+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
22969+ printf("[VIDEO]2 i=%d value=%x\n", i, dwValue);
22970+ ulFlag = 1;
22971+ break;
22972+ }
22973+
22974+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 8);
22975+ if (0x80808080 != dwValue)
22976+ {
22977+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
22978+ printf("[VIDEO]3 i=%d value=%x\n", i, dwValue);
22979+ ulFlag = 1;
22980+ break;
22981+ }
22982+
22983+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 12);
22984+ if (0x80808080 != dwValue)
22985+ {
22986+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
22987+ printf("4 i=%d value=%x\n", i, dwValue);
22988+ ulFlag = 1;
22989+ break;
22990+ }
22991+
22992+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 16);
22993+ if (0x80808080 != dwValue)
22994+ {
22995+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
22996+ printf("5 i=%d value=%x\n", i, dwValue);
22997+ ulFlag = 1;
22998+ break;
22999+ }
23000+
23001+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 20);
23002+ if (0x80808080 != dwValue)
23003+ {
23004+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
23005+ printf("6 i=%d value=%x\n", i, dwValue);
23006+ ulFlag = 1;
23007+ break;
23008+ }
23009+ }
23010+#endif
23011+
23012+ if (!ulFlag)
23013+ {
23014+ printf("[VIDEO] Capture Test OK\n");
23015+ }
23016+ else
23017+ {
23018+ printf("[VIDEO] Capture Test FAIL\n");
23019+ return VIDEO_TEST_FAIL;
23020+ }
23021+
23022+ return VIDEO_TEST_OK;
23023+}
23024+
23025+/********************************************************/
23026+/* Only used in the station */
23027+/********************************************************/
23028+int CRTTest(void)
23029+{
23030+ ULONG ulVGABaseAddr;
23031+ BYTE btCRTCenterMode, btCRTColorFmt;
23032+ USHORT usCRTHor, usCRTVer;
23033+ ULONG ulData;
23034+
23035+ int i,j;
23036+
23037+ //printf("\n --------- Turn on CRT --------- \n");
23038+
23039+ //Enable CRT1 first
23040+ ulVGABaseAddr = vBufAlign((unsigned long)pCrt1Addr);
23041+
23042+ btCRTCenterMode = 0;
23043+ btCRTColorFmt = YUV_444;
23044+ usCRTHor = g_DefWidth;
23045+ usCRTVer = g_DefHeight;
23046+
23047+ CheckOnStartClient();
23048+
23049+ /* Fill Pattern */
23050+ for (i=0; i<usCRTHor; i++)
23051+ {
23052+ for (j=0; j<usCRTVer/8; j++)
23053+ {
23054+ //Y
23055+ //ulData = 0x10101010;
23056+ ulData = 0x32323232;
23057+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32)) = ulData;
23058+ //ulData = 0x10101010;
23059+ ulData = 0x32323232;
23060+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +4) = ulData;
23061+ //U
23062+ ulData = 0x80808080;
23063+ //ulData = 0x77777777;
23064+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +8) = ulData;
23065+ ulData = 0x80808080;
23066+ //ulData = 0x77777777;
23067+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +12) = ulData;
23068+ //V
23069+ ulData = 0x80808080;
23070+ //ulData = 0x11111111;
23071+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +16) = ulData;
23072+ ulData = 0x80808080;
23073+ //ulData = 0x11111111;
23074+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +20) = ulData;
23075+ //A
23076+ ulData = 0xFFFFFFFFF;
23077+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +24) = ulData;
23078+ ulData = 0xFFFFFFFFF;
23079+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +28) = ulData;
23080+ }
23081+ } /* ~Fill Pattern */
23082+
23083+#if defined(CONFIG_AST2300)
23084+ if(!ASTSetModeV (0, CRT_2, ulVGABaseAddr, usCRTHor, usCRTVer, btCRTColorFmt, btCRTCenterMode))
23085+#else
23086+ if(!ASTSetModeV (0, CRT_1, ulVGABaseAddr, usCRTHor, usCRTVer, btCRTColorFmt, btCRTCenterMode))
23087+#endif
23088+ {
23089+ printf("[VIDEO] The resolution is not in mode table list\n");
23090+ return CRT_FAIL;
23091+ }
23092+
23093+ //printf("[VIDEO] CRT turn on\n");
23094+
23095+ return VIDEO_TEST_OK;
23096+}
23097+
23098+int do_videotest (void)
23099+{
23100+ int dwValue=0;
23101+ int i = 0;
23102+ int iRet;
23103+ ULONG ulRestore1, ulTemp;
23104+ BOOL bClient;
23105+
23106+
23107+ //InitVideoTest();
23108+ g_DefWidth = 640;
23109+ g_DefHeight= 480;
23110+
23111+ printf("\n --------- Codec Test --------- \n");
23112+
23113+#if defined(CONFIG_AST2300)
23114+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, 0x00002000, 0x00002000);
23115+#endif
23116+
23117+ CheckOnStartHost();
23118+
23119+ do
23120+ {
23121+ dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
23122+ i++;
23123+ }
23124+ while ((VIDEO_UNLOCK != dwValue) && (i<1000));
23125+
23126+ if (VIDEO_UNLOCK != dwValue)
23127+ {
23128+ printf("[VIDEO] Video register is locked \n");
23129+ return VIDEO_TEST_FAIL;
23130+ }
23131+ AllocateEncodeBufHost(0, VIDEO1);
23132+
23133+ iRet = CodecTest();
23134+ if (iRet)
23135+ return VIDEO_TEST_FAIL;
23136+
23137+#if defined(CONFIG_AST2300)
23138+ /* Init SCU */
23139+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x2c + SCU_OFFSET), 0x00040000, 0x00040010); /* Enable D2-PLL */
23140+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, 0, 0x00000400); /* Enable D2CLK */
23141+ udelay(10);
23142+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, 0, 0x00002000);
23143+
23144+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x90 + SCU_OFFSET), 0x20, 0x00000030); /* enable video mode single edge */
23145+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x84 + SCU_OFFSET), 0xfffe0000, 0xfffe0000); /* multi-pins */
23146+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x88 + SCU_OFFSET), 0x000fffff, 0x000fffff); /* multi-pins */
23147+
23148+ iRet = CRTTest();
23149+ if (iRet)
23150+ {
23151+ printf("[VIDEO] CRT Test Failed \n");
23152+ return VIDEO_TEST_FAIL;
23153+ }
23154+
23155+ iRet = CapTest();
23156+ if (iRet)
23157+ {
23158+ printf("[VIDEO] Capture Test Failed \n");
23159+ return VIDEO_TEST_FAIL;
23160+ }
23161+#else
23162+ //Host or Client
23163+ bClient = ((ReadMemoryLong(SCU_BASE, SCU_HW_TRAPPING_REG) & CLIENT_MODE_EN_MASK)?TRUE:FALSE);
23164+ //reset video for another testing
23165+ ResetVideoHost();
23166+ dwValue=0;
23167+ i = 0;
23168+ do
23169+ {
23170+ dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
23171+ i++;
23172+ }
23173+ while ((VIDEO_UNLOCK != dwValue) && (i<10));
23174+
23175+ if (VIDEO_UNLOCK != dwValue)
23176+ {
23177+ printf("[VIDEO] Video register is locked");
23178+ return VIDEO_UNLOCK_FAIL;
23179+ }
23180+
23181+ //check if 1e6e0008[3,0] is 0
23182+ ulRestore1 = ReadMemoryLongHost(0x1e6e0000, 8);
23183+ dwValue = ReadMemoryLongHost(0x1e6e0000, 8)&0xF;
23184+
23185+ //set 1e6e0008[3,0] to 0
23186+ if (dwValue)
23187+ {
23188+ WriteMemoryLongHost(0x1e6e0000, 0, 0xfc600309);
23189+
23190+ i=0;
23191+ do
23192+ {
23193+ i++;
23194+ dwValue = ReadMemoryLongHost(0x1e6e0000,0);
23195+ }while((1 != dwValue)&& (i<10));
23196+
23197+ if (1 != dwValue)
23198+ {
23199+ printf("0x1e6e0000 is locked");
23200+ return VIDEO_UNLOCK_FAIL;
23201+ }
23202+ }
23203+
23204+ //only clear 1e6e0008[3,0]
23205+ WriteMemoryLongWithMASKHost(0x1e6e0000, 8, 0, 0xf);
23206+
23207+ bClient = 0;
23208+ if (!bClient)
23209+ {
23210+ //To turn on crt, must be the client mode
23211+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_CLIENT_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
23212+
23213+ iRet = CRTTest();
23214+
23215+ if (iRet)
23216+ {
23217+ //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
23218+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
23219+ //restore value
23220+ WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
23221+ //lock register
23222+ WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678);
23223+ return VIDEO_TEST_FAIL;
23224+ }
23225+
23226+ iRet = CapTest();
23227+
23228+ if (iRet)
23229+ {
23230+ //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
23231+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
23232+ //restore value
23233+ WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
23234+ //lock register
23235+ WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678);
23236+
23237+ return VIDEO_TEST_FAIL;
23238+ }
23239+ //WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
23240+ }
23241+ //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
23242+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
23243+ //restore value
23244+ WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
23245+ //lock register
23246+ WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678);
23247+#endif
23248+
23249+ return VIDEO_TEST_OK;
23250+}
23251+#endif /* CONFIG_SLT */
23252diff --git a/board/aspeed/ast2300/videotest.h b/board/aspeed/ast2300/videotest.h
23253new file mode 100755
23254index 0000000..79b8dd9
23255--- /dev/null
23256+++ b/board/aspeed/ast2300/videotest.h
23257@@ -0,0 +1,24 @@
23258+/*
23259+ * This program is distributed in the hope that it will be useful,
23260+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
23261+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23262+ * GNU General Public License for more details.
23263+ *
23264+ * You should have received a copy of the GNU General Public License
23265+ * along with this program; if not, write to the Free Software
23266+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23267+ */
23268+/* VideoTest.h */
23269+#ifndef _VIDEOTEST_H_
23270+#define _VIDEOTEST_H_
23271+
23272+#define VIDEO_TEST_OK 0
23273+#define VIDEO_TEST_FAIL 1
23274+
23275+#define VIDEO_UNLOCK_FAIL 1
23276+#define VIDEO_ENCODE_FAIL 2
23277+#define VIDEO_DECODE_FAIL 3
23278+#define CRT_FAIL 4
23279+
23280+#endif /* _VIDEOTEST_H_ */
23281+
23282diff --git a/board/aspeed/ast2300/vreg.h b/board/aspeed/ast2300/vreg.h
23283new file mode 100755
23284index 0000000..9738548
23285--- /dev/null
23286+++ b/board/aspeed/ast2300/vreg.h
23287@@ -0,0 +1,845 @@
23288+/*
23289+ * This program is distributed in the hope that it will be useful,
23290+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
23291+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23292+ * GNU General Public License for more details.
23293+ *
23294+ * You should have received a copy of the GNU General Public License
23295+ * along with this program; if not, write to the Free Software
23296+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23297+ */
23298+#ifndef _VREG_H_
23299+#define _VREG_H_
23300+
23301+/********************************************************/
23302+/* CRT register */
23303+/********************************************************/
23304+#define CRT_BASE_ADDRESS 0x000400
23305+#define VGA_GRAPH_BASE_ADDRESS 0x600000
23306+#define VGA_CURSOR_BASE_ADDRESS 0x300000
23307+#define VGA_OSD_BASE_ADDRESS 0x300000
23308+#define RGB_565 0x0
23309+#define RGB_888 0x1
23310+#define YUV_444 0x2
23311+#define NO_SUPPORTED_CRT_FMT 0x3
23312+#define CRT_LOW_THRESHOLD_VALUE 0x12
23313+#define CRT_HIGH_THRESHOLD_VALUE 0x1E
23314+
23315+// AST3000's Registers
23316+#ifdef Watcom
23317+#define VIDEOBASE_OFFSET 0x10000
23318+#else
23319+#define VIDEOBASE_OFFSET 0x0
23320+#endif
23321+
23322+#define KEY_CONTROL_REG 0x00 + VIDEOBASE_OFFSET
23323+ #define VIDEO_LOCKED 0
23324+ #define VIDEO_UNLOCK 1
23325+
23326+// Registers for video1 and video2
23327+#define VIDEO1_ENGINE_SEQUENCE_CONTROL_REG 0x04 + VIDEOBASE_OFFSET
23328+#define VIDEO2_ENGINE_SEQUENCE_CONTROL_REG 0x104 + VIDEOBASE_OFFSET
23329+ #define MODE_DETECTION_TRIGGER 0x00000001 //Bit[0] trigger HW auto mode detection
23330+ #define VIDEO_CAPTURE_TRIGGER 0x00000002 //Bit[1] trigger HW to capture video
23331+ #define FORCE_HW_IDLE_MASK (1<<2) //Bit[2] Force engine into ready(idle) state
23332+ #define ENGINE_RESET (0<<2)
23333+ #define ENGINE_IDLE (1<<2)
23334+ #define VIDEO_CAPTURE_AUTO_MODE 0x00000008 //Bit[3]
23335+ #define CAPTURE_FRAME_MODE 0
23336+ #define CAPTURE_AUTO_MODE 1
23337+ #define CAPTURE_AUTO_MODE_BIT 3
23338+ #define CAPTURE_AUTO_MODE_MASK 0x00000008
23339+ #define VIDEO_CODEC_TRIGGER 0x00000010 //Bit[4] trigger HW to compress or decompress video
23340+ #define CODEC_TRIGGER_BIT 4
23341+ #define CODEC_TRIGGER_MASK 0x00000010
23342+ #define CLEAR_CODEC_TRIGGER 0
23343+ #define EN_CODEC_TRIGGER 1
23344+ #define VIDEO_CODEC_AUTO_MODE 0x00000020 //Bit[5]
23345+ #define CODEC_FRAME_MODE 0
23346+ #define CODEC_AUTO_MODE 1
23347+ #define CODEC_AUTO_MODE_BIT 5
23348+ #define CODEC_AUTO_MODE_MASK 0x00000020
23349+ #define INSERT_FULL_FRAME_MASK (1<<6) //Bit[6] Insert full frame compression
23350+ #define INSERT_FULL_FRAME_EN (1<<6)
23351+ #define INSERT_FULL_FRAME_OFF (0<<6)
23352+ #define WATCH_DOG_ENABLE 0x00000080 //Bit[7] Video Enable watch dog for mode change detection
23353+ #define WATCH_DOG_ENABLE_BIT 7
23354+ #define WATCH_DOG_OFF 0
23355+ #define WATCH_DOG_EN 1
23356+ #define WATCH_DOG_EN_MASK 0x00000080
23357+ #define VIDEO_CRT_SELECTION 0x00000100 //Bit[8]
23358+ #define CRT1 0
23359+ #define CRT2 1
23360+ #define ANTI_TEARING_ENABLE 0x00000200 //Bit[9] Anti-tearing mode enable for decoding
23361+ #define ANTI_TEARING_EN 1
23362+ #define STREAM_DATA_MODE 0x00000400 //Bit[11:10] Buffer and Stream Data type
23363+ #define STREAM_DATA_MODE_BIT 10
23364+ #define STREAM_DATA_MODE_MASK 0x00000C00
23365+ #define YUV444_MODE 0
23366+ #define YUV420_MODE 1
23367+ #define YUV420_MODE_WITH_AST2000 2 //AST2000 compatible
23368+ #define VIDEO_CAPTURE_READY 0x00010000 //Bit[16] Video capture ready status read back(read only)
23369+ #define CAPTURE_READY_MASK 0x00010000
23370+ #define HW_BUSY 0
23371+ #define HW_IDLE 1
23372+ #define VIDEO_CODEC_READY 0x00040000 //Bit[18] Video codec ready status read back(read only)
23373+ #define CODEC_READY_MASK 0x00040000
23374+ //#define HW_BUSY 0
23375+ //#define HW_IDLE 1
23376+
23377+#define VIDEO1_CONTROL_REG 0x08 + VIDEOBASE_OFFSET
23378+#define VIDEO2_CONTROL_REG 0x108 + VIDEOBASE_OFFSET
23379+ #define VIDEO_HSYNC_POLARITY 0x00000001 //Bit[0] Video source hsync polarity
23380+ #define VIDEO_HSYNC_POLARITY_BIT 0
23381+ #define NO_INVERSE_POL 0
23382+ #define INVERSE_POL 1
23383+ #define VIDEO_VSYNC_POLARITY 0x00000002 //Bit[1] Video source vsync polarity
23384+ #define VIDEO_VSYNC_POLARITY_BIT 1
23385+ //Setting defination the same as VIDEO_HSYNC_POLARITY
23386+ #define VIDEO_EXTERNAL_SOURCE 0x00000004 //Bit[2] Video external source
23387+ #define EXTERNAL_SOURCE_BIT 2
23388+ #define INTERNAL_VGA_SOURCE 0
23389+ #define EXTERNAL_VGA_SOURCE 1
23390+ #define EXTERNAL_SOURCE_MASK 0x00000004
23391+ #define VIDEO_ANALONG_EXTERNAL_SOURCE 0x00000008 //Bit[3] Video Analog external source
23392+ #define ANALONG_EXTERNAL_SOURCE_BIT 3
23393+ #define DVI_SOURCE 0
23394+ #define ANALOG_RGB_SOURCE 1
23395+ #define VIDEO_INTERNAL_TIMING_GEN 0x00000010 //Bit[4] Video Use internal timing generator
23396+ #define INTERNAL_TIMING_GEN_BIT 4
23397+ #define EXTERNAL_DE_SIGNAL 0 //DVI only
23398+ #define VR0C_VR10_DE_SINGAL 1 //use VR0C and VR10 for generate VDE signal
23399+ /****** Video2 Only from DAC ******/
23400+ #define VIDEO1_CAPTURE_FROM 0x00000020 //Bit[5] Video1 capture data direct from VGA frame buffer(internal VGA only)
23401+ #define FROM_DAC_PORT 0
23402+ #define FROM_FRAME_BUFFER 1
23403+ #define WRITE_DATA_FORMAT 0x00000040 //Bit[7:6] Write data format
23404+ #define WRITE_DATA_FORMAT_BIT 6
23405+ #define WRTIE_DATA_FORMAT_MASK 0x000000C0
23406+ #define CCIR601_2_YUV_FORMAT 0
23407+ #define FULL_YUV_FORMAT 1
23408+ #define RGB_FORMAT 2
23409+ #define VGA_CURSOR_DISABLE 0x00000100 //Bit[8] External video port slection
23410+ #define VGA_CURSOR_NORMAL 0
23411+ #define VGA_CURSOR_OFF 1
23412+ #define VIDEO_CAPTURE_LINEAR_MODE 0x00000200 //Bit[9] VIDEO_CAPTURE_LINEAR_MODE
23413+ #define LINEAR_MODE 0
23414+ #define TILE_MODE 1
23415+ #define VIDEO_CLOCK_DELAY 0x00000400 //Bit[11:10] Video clock delay control
23416+ #define VIDEO_CLOCK_DELAY_BIT 10
23417+ #define VIDEO_CLOCK_DELAY_MASK 0x00000C00
23418+ #define DELAY_0_NS 0
23419+ #define DELAY_1_NS 1
23420+ #define INV_AND_DELAY_0_NS 2
23421+ #define INV_AND_DELAY_1_NS 3
23422+ #define VIDEO_CCIR656_SOURCE_MODE 0x00001000 //Bit[12] Video CCIR656 source mode
23423+ #define RGB_SOURCE_MODE 0
23424+ #define CCIR656_SOURCE_MODE 1
23425+ #define SOURCE_PORT_CLOCK_MODE 0x00002000 //Bit[13] Video Source port clock mode
23426+ #define SINGLE_EDGE_MODE 0
23427+ #define DUAL_EDGE_MODE 1
23428+ #define EXTERNAL_PORT_SELECTION 0x00004000 //Bit[14] External video port slection
23429+ #define VIDEO_PORT_A 0
23430+ #define VIDEO_PORT_B 1
23431+ #define VIDEO_CAPTURE_FRAME_RATE 0x00010000 //Bit[23:16] Video capture frame rate control
23432+ #define VIDEO_CAPTURE_FRAME_RATE_BIT 16
23433+ #define VIDEO_CAPTURE_FRAME_RATE_MASK 0x00FF0000 //Maximum frame rate = XX * SourceFPS / 60
23434+
23435+#define VIDEO1_TIMEING_GEN_HOR_REG 0x0C + VIDEOBASE_OFFSET
23436+#define VIDEO2_TIMEING_GEN_HOR_REG 0x10C + VIDEOBASE_OFFSET
23437+ #define VIDEO_HDE_END 0x00000000 //Bit[12:0] Video HDE End timing generator
23438+ #define VIDEO_HDE_END_BIT 0 //Number of pixels from rising edge of Hsync for first active pixel
23439+ #define VIDEO_HDE_END_MASK 0x00001FFF
23440+ #define VIDEO_HDE_START 0x00010000 //Bit[28:16] Video HDE Start timing generator
23441+ #define VIDEO_HDE_START_BIT 16 //Number of pixels from rising edge of Hsync for last active pixel
23442+ #define VIDEO_HDE_START_MASK 0x1FFF0000
23443+ #define FRAME_RATE_OFF 0
23444+
23445+#define VIDEO1_TIMEING_GEN_V_REG 0x10 + VIDEOBASE_OFFSET
23446+#define VIDEO2_TIMEING_GEN_V_REG 0x110 + VIDEOBASE_OFFSET
23447+ #define VIDEO_VDE_END 0x00000001 //Bit[11:0] Video VDE End timing generator
23448+ #define VIDEO_VDE_END_BIT 0 //Number of pixels from rising edge of Vsync for first active pixel
23449+ #define VIDEO_VDE_END_MASK 0x00000FFF
23450+ #define VIDEO_VDE_START 0x00010000 //Bit[27:16] Video VDE Start timing generator
23451+ #define VIDEO_VDE_START_BIT 16 //Number of pixels from rising edge of Vsync for last active pixel
23452+ #define VIDEO_VDE_START_MASK 0x0FFF0000
23453+
23454+#define VIDEO1_SCALE_FACTOR_REG 0x14 + VIDEOBASE_OFFSET
23455+#define VIDEO2_SCALE_FACTOR_REG 0x114 + VIDEOBASE_OFFSET
23456+ #define HOR_SCALING_FACTOR 0x00000001 //Bit[15:0] Video Horizontal scaling factor
23457+ #define HOR_SCALING_FACTOR_BIT 0 //The formula=4096/(Horizontal scaling facotr)
23458+ #define HOR_SCALING_FACTOR_MASK 0x0000FFFF
23459+ #define VER_SCALING_FACTOR 0x00000000 //Bit[31:16] Video Vertical scaling factor
23460+ #define VER_SCALING_FACTOR_BIT 16 //The formula=4096/(Vertical scaling facotr)
23461+ #define VER_SCALING_FACTOR_MASK 0xFFFF0000
23462+
23463+#define VIDEO1_SCALE_FACTOR_PARAMETER0_REG 0x18 + VIDEOBASE_OFFSET //Scaling Parameters F00, F01, F02, F03
23464+#define VIDEO2_SCALE_FACTOR_PARAMETER0_REG 0x118 + VIDEOBASE_OFFSET
23465+
23466+#define VIDEO1_SCALE_FACTOR_PARAMETER1_REG 0x1C + VIDEOBASE_OFFSET //Scaling Parameters F10, F11, F12, F13
23467+#define VIDEO2_SCALE_FACTOR_PARAMETER1_REG 0x11C + VIDEOBASE_OFFSET
23468+
23469+#define VIDEO1_SCALE_FACTOR_PARAMETER2_REG 0x20 + VIDEOBASE_OFFSET //Scaling Parameters F20, F21, F22, F23
23470+#define VIDEO2_SCALE_FACTOR_PARAMETER2_REG 0x120 + VIDEOBASE_OFFSET
23471+
23472+#define VIDEO1_SCALE_FACTOR_PARAMETER3_REG 0x24 + VIDEOBASE_OFFSET //Scaling Parameters F30, F31, F32, F33
23473+#define VIDEO2_SCALE_FACTOR_PARAMETER3_REG 0x124 + VIDEOBASE_OFFSET
23474+
23475+#define VIDEO1_BCD_CONTROL_REG 0x2C + VIDEOBASE_OFFSET
23476+#define VIDEO2_BCD_CONTROL_REG 0x12C + VIDEOBASE_OFFSET
23477+ #define BCD_ENABLE 0x00000001 //Bit[0] Enable block change detection(BCD)
23478+ #define BCD_ENABLE_BIT 0
23479+ #define BCD_ENABLE_MASK 0x00000001
23480+ #define BCD_TOLERANCE 0x00010000 //Bit[23:16]
23481+ #define BCD_TOLERANCE_BIT 16 //flag as changed block when the video data difference greater
23482+ #define BCD_TOLERANCE_MASK 0x00FF0000
23483+
23484+#define VIDEO1_CAPTURE_WINDOWS_REG 0x30 + VIDEOBASE_OFFSET
23485+#define VIDEO2_CAPTURE_WINDOWS_REG 0x130 + VIDEOBASE_OFFSET
23486+ #define CAPTURE_VER_LINE 0x00000001 //Bit[10:0] Video compression vertical line total
23487+ #define CAPTURE_VER_LINE_BIT 0
23488+ #define CAPTURE_VER_LINE_MASK 0x000007FF
23489+ #define CAPTURE_HOR_PIXEL 0x00010000 //Bit[26:16] Video compression vertical line total
23490+ #define CAPTURE_HOR_PIXEL_BIT 16
23491+ #define CAPTURE_HOR_PIXEL_MASK 0x07FF0000
23492+
23493+#define VIDEO1_COMPRESS_WINDOWS_REG 0x34 + VIDEOBASE_OFFSET
23494+#define VIDEO2_COMPRESS_WINDOWS_REG 0x134 + VIDEOBASE_OFFSET
23495+ #define COMPRESS_VER_LINE 0x00000001 //Bit[10:0] Video compression vertical line total
23496+ #define COMPRESS_VER_LINE_BIT 0
23497+ #define COMPRESS_VER_LINE_MASK 0x000007FF
23498+ #define COMPRESS_HOR_PIXEL 0x00010000 //Bit[26:16] Video compression vertical line total
23499+ #define COMPRESS_HOR_PIXEL_BIT 16
23500+ #define COMPRESS_HOR_PIXEL_MASK 0x07FF0000
23501+
23502+#define VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG 0x38
23503+#define VIDEO2_COMPRESS_BUF_PROCESS_OFFSET_REG 0x138
23504+ #define COMPRESS_BUF_PROCESS_OFFSET_ALIGN 127 //128 byte alignment
23505+ #define COMPRESS_BUF_PROCESS_OFFSET_MASK 0xFFFFFF
23506+
23507+#define VIDEO1_DECOMPRESS_BUF_PROCESS_OFFSET_REG 0x38
23508+#define VIDEO2_DECOMPRESS_BUF_PROCESS_OFFSET_REG 0x138
23509+ #define DECOMPRESS_BUF_PROCESS_OFFSET_ALIGN 127 //128 byte alignment
23510+ #define DECOMPRESS_BUF_PROCESS_OFFSET_MASK 0xFFFFFF
23511+
23512+
23513+//For Compression
23514+#define VIDEO1_COMPRESS_BUF_READ_OFFSET_REG 0x3C + VIDEOBASE_OFFSET //For stream mode
23515+#define VIDEO2_COMPRESS_BUF_READ_OFFSET_REG 0x13C + VIDEOBASE_OFFSET
23516+ #define COMPRESS_BUF_READ_OFFSET_ALIGN 127 //128 byte alignment
23517+ #define COMPRESS_BUF_READ_OFFSET_MASK 0x00FFFFFF
23518+//For Decompression
23519+#define VIDEO1_DECOMPRESS_BUF_WRITE_OFFSET_REG 0x3C + VIDEOBASE_OFFSET //For stream mode
23520+#define VIDEO2_DECOMPRESS_BUF_WRITE_OFFSET_REG 0x13C + VIDEOBASE_OFFSET
23521+ #define DECOMPRESS_BUF_WRITE_OFFSET_ALIGN 127 //128 byte alignment
23522+ #define DECOMPRESS_BUF_WRITE_OFFSET_MASK 0x00FFFFFF
23523+
23524+#define VIDEO1_CRC_BUF_ADDR_REG 0x40 + VIDEOBASE_OFFSET
23525+#define VIDEO2_CRC_BUF_ADDR_REG 0x140 + VIDEOBASE_OFFSET
23526+ #define CRC_BUF_ADDR_ALIGN 7 //8 byte alignment
23527+ #define CRC_BUF_ADDR_MASK 0x0FFFFFFF
23528+
23529+#define VIDEO1_BUF_1_ADDR_REG 0x44 + VIDEOBASE_OFFSET //For Source Buffer in frame mode
23530+#define VIDEO2_BUF_1_ADDR_REG 0x144 + VIDEOBASE_OFFSET
23531+ #define BUF_1_ADDR_ALIGN 255 //256 byte alignment
23532+ #define BUF_1_ADDR_MASK 0x1FFFFFFF
23533+
23534+#define VIDEO1_BUF_LINE_OFFSET_REG 0x48 + VIDEOBASE_OFFSET //Must set both in Frame/Stream mode
23535+#define VIDEO2_BUF_LINE_OFFSET_REG 0x148 + VIDEOBASE_OFFSET
23536+ #define BUF_LINE_OFFSET_ALIGN 7 //8 byte alignment
23537+ #define BUF_LINE_OFFSET_MASK 0x00003FFF
23538+
23539+#define VIDEO1_BUF_2_ADDR_REG 0x4C + VIDEOBASE_OFFSET //For BCD Buffer in frame mode
23540+#define VIDEO2_BUF_2_ADDR_REG 0x14C + VIDEOBASE_OFFSET
23541+ #define BUF_2_ADDR_ALIGN 255 //256 byte alignment
23542+ #define BUF_2_ADDR_MASK 0x1FFFFFFF
23543+
23544+#define VIDEO1_FLAG_BUF_ADDR_REG 0x50 + VIDEOBASE_OFFSET //For block change flag buffer
23545+#define VIDEO2_FLAG_BUF_ADDR_REG 0x150 + VIDEOBASE_OFFSET
23546+ #define FLAG_BUF_ADDR_ALIGN 7 //8 byte alignment
23547+ #define FLAG_BUF_ADDR_MASK 0x1FFFFFFF
23548+
23549+#define VIDEO1_COMPRESS_BUF_ADDR_REG 0x54 + VIDEOBASE_OFFSET //For stream mode
23550+#define VIDEO2_COMPRESS_BUF_ADDR_REG 0x154 + VIDEOBASE_OFFSET
23551+ #define COMPRESS_BUF_ADDR_ALIGN 127 //128 byte alignment
23552+ #define COMPRESS_BUF_ADDR_MASK 0x1FFFFFFF
23553+
23554+#define VIDEO1_STREAM_BUF_SIZE 0x58 + VIDEOBASE_OFFSET //For stream mode
23555+#define VIDEO2_STREAM_BUF_SIZE 0x158 + VIDEOBASE_OFFSET
23556+ #define STREAM_PACKET_SIZE 0x00000001
23557+ #define STREAM_PACKET_SIZE_BIT 0
23558+ #define STREAM_PACKET_SIZE_MASK 0x00000007
23559+ #define PACKET_SIZE_1KB 0
23560+ #define PACKET_SIZE_2KB 1
23561+ #define PACKET_SIZE_4KB 2
23562+ #define PACKET_SIZE_8KB 3
23563+ #define PACKET_SIZE_16KB 4
23564+ #define PACKET_SIZE_32KB 5
23565+ #define PACKET_SIZE_64KB 6
23566+ #define PACKET_SIZE_128KB 7
23567+ #define RING_BUF_PACKET_NUM 0x00000008
23568+ #define RING_BUF_PACKET_NUM_BIT 3
23569+ #define RING_BUF_PACKET_NUM_MASK 0x00000018
23570+ #define PACKETS_4 0
23571+ #define PACKETS_8 1
23572+ #define PACKETS_16 2
23573+ #define PACKETS_32 3
23574+ #define SKIP_HIGH_MB_THRES 0x00010000 //Bit[22:16] Skip high quality macro block threshold
23575+ #define SKIP_HIGH_MB_THRES_BIT 16
23576+ #define SKIP_HIGH_MB_THRES_MASK 0x007F0000
23577+ #define SKIP_TEST_MODE 0x00800000 //Bit[24:23] Skip test mode
23578+ #define SKIP_TEST_MODE_BIT 23
23579+ #define SKIP_TEST_MODE_MASK 0x01800000
23580+ #define YUV_TEST 2 //recommend
23581+
23582+#define VIDEO1_BUF_CODEC_OFFSET_READ 0x5C + VIDEOBASE_OFFSET //For stream mode,
23583+#define VIDEO2_BUF_CODEC_OFFSET_READ 0x15C + VIDEOBASE_OFFSET //Video stream buffer offset read back(HW)
23584+ #define BUF_CODEC_OFFSET_ALIGN 255 //256 byte alignment
23585+ #define BUF_CODEC_OFFSET_MASK 0x00FFFFFF
23586+
23587+#define VIDEO1_COMPRESS_CONTROL_REG 0x60 + VIDEOBASE_OFFSET
23588+#define VIDEO2_COMPRESS_CONTROL_REG 0x160 + VIDEOBASE_OFFSET
23589+ #define JPEG_ONLY_ENCODE 0x00000001 //Bit[0] JPEG only encoding
23590+ #define JPEG_ONLY_BIT 0
23591+ #define JPEG_MIX_MODE 0 //Enable JPEG/VQ mix mode encoding
23592+ #define JPEG_ONLY_MODE 1 //JPEG encoding mode only
23593+ #define VQ_4_COLOR_ENCODE 0x00000002 //Bit[1] Enable 4 color VQ encoding
23594+ #define VQ_4_COLOR_BIT 1
23595+ #define VQ_1_2_COLOR_MODE 0 //1 and 2 color mode VQ encoding
23596+ #define VQ_4_COLOR_MODE 1 //1, 2 and 4 color VQ encoding
23597+ #define QUALITY_CODEC_SETTING 0x00000004 //Bit[2] High and best video quality codec mode setting
23598+ #define QUALITY_CODEC_SETTING_BIT 2
23599+ #define JPEG_CODEC_MODE 0 //not supported in best video quality mode
23600+ #define QUANTI_CODEC_MODE 1
23601+ #define JPEG_DUAL_QUALITY_EN 0x00000008 //Bit[3] JPEG dual quality mode
23602+ #define EN_JPEG_DUAL_QUALITY 1 //enable(only for normal video quality mode)
23603+ #define BEST_QUALITY_EN 0x00000010 //Bit[4] Best quality video mode enable
23604+ #define BEST_QUALITY_EN_BIT 4
23605+ #define EN_BEST_QUALITY 1 //enable(only for quantization codec mode)
23606+ #define RC4_CRYPT_EN 0x00000020 //Bit[5] Enable RC4 encryption/decryption
23607+ #define RC4_CRYPT_EN_BIT 5
23608+ #define RC4_CRYPT_EN_MASK 0x00000020
23609+ #define RC4_CRYPT_ON 1 //enable
23610+ #define NORMAL_QUANTI_CHROMI_TABLE 0x00000040 //Bit[10:6] Normal video quality mode JPEG DCT chromi quantination table
23611+ #define NORMAL_QUANTI_CHROMI_TABLE_BIT 6
23612+ #define NORMAL_QUANTI_CHROMI_TABLE_MASK 0x000007C0
23613+ #define NORMAL_QUANTI_LUMI_TABLE 0x00000800 //Bit[15:11] Normal video quality mode JPEG DCT lumi quantination table
23614+ #define NORMAL_QUANTI_LUMI_TABLE_BIT 11
23615+ #define NORMAL_QUANTI_LUMI_TABLE_MASK 0x0000F800
23616+ #define HIGH_QUALITY_EN 0x00010000 //Bit[16] High video quality mode enable
23617+ #define HIGH_QUALITY_EN_BIT 16
23618+ #define EN_HIGH_QUALITY 1 //Enable
23619+ #define UV_CIR656_FORMAT 0x00080000 //Bit[19] UV fromat
23620+ #define UV_CIR656_FORMAT_BIT 19
23621+ #define USE_UV_CIR656 1 //recommand
23622+ #define HUFFMAN_TABLE_SELECT 0x00100000 //Bit[20] JPEG Huffman table combination
23623+ #define DUAL_TABLE 0 //Dual Y, UV table
23624+ #define SINGLE_TABLE 1 //Single Y table
23625+ #define SINGLE_UV_TABLE 0x00200000 //1x: Single UV table
23626+ #define HIGH_QUANTI_CHROMI_TABLE 0x00400000 //Bit[26:22] High quality JPEG DCT chromi quantization table
23627+ #define HIGH_QUANTI_CHROMI_TABLE_BIT 22
23628+ #define HIGH_QUANTI_CHROMI_TABLE_MASK 0x07C00000
23629+ #define HIGH_DEQUANTI_VALUE 0x00400000 //Bit[26:22] High quality de-quantization value
23630+ #define HIGH_DEQUANTI_VALUE_BIT 22
23631+ #define HIGH_DEQUANTI_VALUE_MASK 0x07C00000
23632+ #define HIGH_QUANTI_LUMI_TABLE 0x08000000 //Bit[31:27] High quality JPEG DCT lumi quantization table
23633+ #define HIGH_QUANTI_LUMI_TABLE_BIT 27
23634+ #define HIGH_QUANTI_LUMI_TABLE_MASK 0xF8000000
23635+ #define BEST_DEQUANTI_VALUE 0x08000000 //Bit[31:27] Best quality de-quantization value
23636+ #define BEST_DEQUANTI_VALUE_BIT 27
23637+ #define BEST_DEQUANTI_VALUE_MASK 0xF8000000
23638+
23639+
23640+#define VIDEO1_QUANTI_TABLE_LOW_REG 0x64 + VIDEOBASE_OFFSET //Match with 0x60 Bit[10:6], Bit[15:11]
23641+#define VIDEO2_QUANTI_TABLE_LOW_REG 0x164 + VIDEOBASE_OFFSET
23642+ #define QUANTI_CHROMI_TABLE_LOW 0x00000001 //Bit[4:0] Normal video low quality block chromi quantization table
23643+ #define QUANTI_CHROMI_TABLE_LOW_BIT 0
23644+ #define QUANTI_CHROMI_TABLE_LOW_MASK 0x0000001F
23645+ #define QUANTI_LUMI_TABLE_LOW 0x00000020 //Bit[9:5] Normal video low quality block lumi quantization table
23646+ #define QUANTI_LUMI_TABLE_LOW_BIT 5
23647+ #define QUANTI_LUMI_TABLE_LOW_MASK 0x000003E0
23648+
23649+#define VIDEO1_QUANTI_VALUE_REG 0x68 + VIDEOBASE_OFFSET //Match with 0x60 Bit[26:22],Bit[31:27]
23650+#define VIDEO2_QUANTI_VALUE_REG 0x168 + VIDEOBASE_OFFSET
23651+ #define HIGH_QUANTI_VALUE 0x00000001 //Bit[14:0] High quality quantization value. Format is 1.14
23652+ #define HIGH_QUANTI_VALUE_BIT 0
23653+ #define HIGH_QUANTI_VALUE_MASK 0x00007FFF
23654+ #define BEST_QUANTI_VALUE 0x00010000 //Bit[30:16] Best quality quantization value. Format is 1.14
23655+ #define BEST_QUANTI_VALUE_BIT 16
23656+ #define BEST_QUANTI_VALUE_MASK 0x7FFF0000
23657+
23658+#define VIDEO1_BSD_PARA_REG 0x6C + VIDEOBASE_OFFSET //Video BSD Parameters Register
23659+#define VIDEO2_BSD_PARA_REG 0x16C + VIDEOBASE_OFFSET
23660+ #define BSD_HIGH_THRES 0x00000001 //Bit[7:0] Block sharpness detection high threshold
23661+ #define BSD_HIGH_THRES_BIT 0
23662+ #define BSD_HIGH_THRES_MASK 0x000000FF
23663+ #define BSD_LOW_THRES 0x00000100 //Bit[15:8] Block shaprpness detection low threshold
23664+ #define BSD_LOW_THRES_BIT 8
23665+ #define BSD_LOW_THRES_MASK 0x0000FF00
23666+ #define BSD_HIGH_COUNTS 0x00010000 //Bit[21:16] Block sharpness detection high counts threshold
23667+ #define BSD_HIGH_COUNTS_BIT 16
23668+ #define BSD_HIGH_COUNTS_MASK 0x003F0000
23669+ #define BSD_LOW_COUNTS 0x00400000 //Bit[27:22] Block sharpness detection low counts threshold
23670+ #define BSD_LOW_COUNTS_BIT 22
23671+ #define BSD_LOW_COUNTS_MASK 0x0FC00000
23672+
23673+#define VIDEO1_COMPRESS_FRAME_SIZE_REG 0x70 + VIDEOBASE_OFFSET
23674+#define VIDEO2_COMPRESS_FRAME_SIZE_REG 0x170 + VIDEOBASE_OFFSET
23675+ #define COMPRESS_FRAME_SIZE_READ 0x00000001 //Bit[19:0] Video compression frame size read back(number of DW)
23676+ #define COMPRESS_FRAME_SIZE_READ_BIT 0
23677+ #define COMPRESS_FRAME_SIZE_READ_MASK 0x003FFFFF
23678+
23679+#define VIDEO1_COMPRESS_BLOCK_COUNT_REG 0x74 + VIDEOBASE_OFFSET
23680+#define VIDEO2_COMPRESS_BLOCK_COUNT_REG 0x174 + VIDEOBASE_OFFSET
23681+ #define PROCESS_BLOCK_COUNT_READ_BIT 0
23682+ #define PROCESS_BLOCK_COUNT_READ_MASK 0x00003FFF //Bit[13:0] Video processed total block counter read back(number of blocks)
23683+ #define COMPRESS_BLOCK_COUNT_READ_BIT 16
23684+ #define COMPRESS_BLOCK_COUNT_READ_MASK 0xFFFF0000 //Bit[29:16] Video processed total block counter read back(number of blocks)
23685+
23686+#define VIDEO1_COMPRESS_FRAME_END_READ 0x78 + VIDEOBASE_OFFSET //Video compression stream frame end pointer
23687+#define VIDEO2_COMPRESS_FRAME_END_READ 0x178 + VIDEOBASE_OFFSET
23688+ #define COMPRESS_FRAME_END_READ_ALIGN 7
23689+ #define COMPRESS_FRAME_END_READ_MASK 0x00FFFFFF
23690+
23691+#define VIDEO1_COMPRESS_FRAME_COUNT_READ 0x7C + VIDEOBASE_OFFSET
23692+#define VIDEO2_COMPRESS_FRAME_COUNT_READ 0x17C + VIDEOBASE_OFFSET
23693+ #define COMPRESS_FRAME_COUNT_READ 0x00000001 //Bit[15:0] Video compression frame count read back(number of frame)
23694+ #define COMPRESS_FRAME_COUNT_READ_BIT 0
23695+ #define COMPRESS_FRAME_COUNT_READ_MASK 0xFFFFFFFF
23696+
23697+#define VIDEO1_USER_DEFINE_HEADER 0x80 + VIDEOBASE_OFFSET
23698+#define VIDEO2_USER_DEFINE_HEADER 0x180 + VIDEOBASE_OFFSET
23699+ #define USER_DEFINE_HEADER 0x00000001 //Bit[15:0] Video user defined header parameter
23700+ #define USER_DEFINE_HEADER_BIT 0
23701+ #define USER_DEFINE_HEADER_MASK 0x0000FFFF
23702+
23703+#define VIDE1_MODE_DETECTION_EDGE_H_REG 0x90 + VIDEOBASE_OFFSET
23704+#define VIDE2_MODE_DETECTION_EDGE_H_REG 0x190 + VIDEOBASE_OFFSET
23705+ #define LEFT_EDGE_LOCATION 0x00000001 //Bit[11:0] Video source left edge location from sync rising edge
23706+ #define LEFT_EDGE_LOCATION_BIT 0
23707+ #define LEFT_EDGE_LOCATION_MASK 0x00000FFF
23708+ #define NO_VER_SYNC (1 << 12) //Bit[12] No Vertical sync detected
23709+ #define NO_HOR_SYNC (1 << 13) //Bit[13] No horizontal sync detected
23710+ #define NO_ACTIVE_DISP (1 << 14) //Bit[14] No active display detected
23711+ #define NO_DISP_CLOCK (1 << 15)
23712+ #define RIGHT_EDGE_LOCATION 0x00010000 //Bit[27:16] Video source right edge location from sync rising edge
23713+ #define RIGHT_EDGE_LOCATION_BIT 16
23714+ #define RIGHT_EDGE_LOCATION_MASK 0x0FFF0000
23715+
23716+#define VIDE1_MODE_DETECTION_EDGE_V_REG 0x94 + VIDEOBASE_OFFSET
23717+#define VIDE2_MODE_DETECTION_EDGE_V_REG 0x194 + VIDEOBASE_OFFSET
23718+ #define TOP_EDGE_LOCATION 0x00000001 //Bit[11:0] Video source top edge location from sync rising edge
23719+ #define TOP_EDGE_LOCATION_BIT 0
23720+ #define TOP_EDGE_LOCATION_MASK 0x00000FFF
23721+ #define BOTTOM_EDGE_LOCATION 0x00010000 //Bit[27:16] Video source bottom edge location from sync rising edge
23722+ #define BOTTOM_EDGE_LOCATION_BIT 16
23723+ #define BOTTOM_EDGE_LOCATION_MASK 0x0FFF0000
23724+
23725+#define VIDEO1_MODE_DETECTION_STATUS_READ_REG 0x98 + VIDEOBASE_OFFSET
23726+#define VIDEO2_MODE_DETECTION_STATUS_READ_REG 0x198 + VIDEOBASE_OFFSET
23727+ #define MODE_DETECTION_HOR_TIME_READ 0x00000001 //Bit[11:0] Mode detection Horizontal time read back (read only)
23728+ #define MODE_DETECTION_HOR_TIME_READ_BIT 0
23729+ #define MODE_DETECTION_HOR_TIME_READ_MASK 0x00000FFF
23730+ #define ANALONG_DIGITAL_READ 0x00001000 //Bit[12] Auto detection for external analog or digital source read back
23731+ #define ANALONG_DIGITAL_READ_BIT 12
23732+ #define DVI_SIGNAL 0
23733+ #define ADC_SIGNAL 1
23734+ #define MODE_DETECTION_HOR_STABLE_READ 0x00002000 //Bit[13] Mode detection horizontal stable read back
23735+ #define HOR_STABLE 1
23736+ #define MODE_DETECTION_VER_STABLE_READ 0x00004000 //Bit[14] Mode detection vertical stable read back
23737+ #define VER_STABLE 1
23738+ #define OUT_LOCK_READ 0x00008000 //Bit[15] Mode detection out of lock read back
23739+ #define SIGNAL_OUT_LOCK 1
23740+ #define MODE_DETECTION_VER_LINE_READ 0x00010000 //Bit[27:16] Mode detection Vertical lines read back
23741+ #define MODE_DETECTION_VER_LINE_READ_BIT 16
23742+ #define MODE_DETECTION_VER_LINE_READ_MASK 0x0FFF0000
23743+ #define VSYNC_POLARITY_READ 0x10000000 //Bit[28] Vsync polarity read back
23744+ #define HSYNC_POLARITY_READ 0x20000000 //Bit[29] Hsync polarity read back
23745+ #define MODE_DETECTION_VSYNC_READY 0x40000000 //Bit[30] Mode detection Vsync ready
23746+ #define MODE_DETECTION_HSYNC_READY 0x80000000 //Bit[31] Mode detection Hsync ready
23747+
23748+/****** VIDEO MEMAGER SETTING ******/
23749+#define VIDEOM_ENGINE_SEQUENCE_CONTROL_REG 0x204 + VIDEOBASE_OFFSET
23750+ #define VIDEOM_CAPTURE_TRIGGER 0x00000002 //Bit[1] trigger HW to capture video
23751+ #define VIDEOM_AUTO_MODE 0x00000008 //Bit[3]
23752+ #define DISABLE_AUTO_MODE 0
23753+ #define AUTO_COMPRESS 1
23754+ #define VIDEOM_CODEC_TRIGGER 0x00000010 //Bit[4] trigger HW to compress or decompress video
23755+ #define VIDEOM_SOURCE_SELECTION 0x00000100 //Bit[8]
23756+ #define VIDEO1 0
23757+ #define VIDEO2 1
23758+ //#define STREAM_DATA_MODE 0x00000400 //Bit[11:10] Buffer and Stream Data type
23759+ // #define STREAM_DATA_MODE_BIT 10
23760+ // #define STREAM_DATA_MODE_MASK 0x00000C00
23761+ // #define YUV444_MODE 0
23762+ // #define YUV420_MODE 1
23763+ // #define YUV420_MODE_WITH_AST2000 2 //AST2000 compatible
23764+ #define VIDEOM_CAPTURE_READY 0x00010000 //Bit[16] Video capture ready status read back(read only)
23765+ //#define HW_BUSY 0
23766+ //#define HW_IDLE 1
23767+ #define VIDEOM_CODEC_READY 0x00040000 //Bit[18] Video codec ready status read back(read only)
23768+ //#define HW_BUSY 0
23769+ //#define HW_IDLE 1
23770+
23771+#define VIDEOM_SCALE_FACTOR_REG 0x214 + VIDEOBASE_OFFSET
23772+// #define HOR_SCALING_FACTOR 0x00000001 //Bit[15:0] Video Horizontal scaling factor
23773+// #define HOR_SCALING_FACTOR_BIT 0 //The formula=4096/(Horizontal scaling facotr)
23774+// #define HOR_SCALING_FACTOR_MASK 0x0000FFFF
23775+// #define VER_SCALING_FACTOR 0x00000000 //Bit[31:16] Video Vertical scaling factor
23776+// #define VER_SCALING_FACTOR_BIT 16 //The formula=4096/(Vertical scaling facotr)
23777+// #define VER_SCALING_FACTOR_MASK 0xFFFF0000
23778+
23779+#define VIDEOM_SCALE_FACTOR_PARAMETER0_REG 0x218 + VIDEOBASE_OFFSET //Scaling Parameters F00, F01, F02, F03
23780+
23781+#define VIDEOM_SCALE_FACTOR_PARAMETER1_REG 0x21C + VIDEOBASE_OFFSET //Scaling Parameters F10, F11, F12, F13
23782+
23783+#define VIDEOM_SCALE_FACTOR_PARAMETER2_REG 0x220 + VIDEOBASE_OFFSET //Scaling Parameters F20, F21, F22, F23
23784+
23785+#define VIDEOM_SCALE_FACTOR_PARAMETER3_REG 0x224 + VIDEOBASE_OFFSET //Scaling Parameters F30, F31, F32, F33
23786+
23787+#define VIDEOM_BCD_CONTROL_REG 0x22C + VIDEOBASE_OFFSET
23788+ //#define BCD_ENABLE 0x00000001 //Bit[0] Enable block change detection(BCD)
23789+ //#define BCD_TOLERANCE 0x00010000 //Bit[23:16]
23790+ // #define BCD_TOLERANCE_BIT 16 //flag as changed block when the video data difference greater
23791+ // #define BCD_TOLERANCE_MASK 0x00FF0000
23792+
23793+#define VIDEOM_CAPTURE_WINDOWS_REG 0x230 + VIDEOBASE_OFFSET
23794+ //#define RC4_TABLE_ADDR_ALIGN 7 //8 byte alignment
23795+ //#define RC4_TABLE_ADDR_MASK 0x0FFFFFFF
23796+
23797+#define VIDEOM_COMPRESS_WINDOWS_REG 0x234 + VIDEOBASE_OFFSET
23798+ //#define COMPRESS_VER_LINE 0x00000001 //Bit[12:0] Video compression vertical line total
23799+ //#define COMPRESS_VER_LINE_BIT 0
23800+ //#define COMPRESS_VER_LINE_MASK 0x00001FFF
23801+ //#define COMPRESS_HOR_PIXEL 0x00010000 //Bit[12:0] Video compression vertical line total
23802+ //#define COMPRESS_HOR_PIXEL_BIT 16
23803+ //#define COMPRESS_HOR_PIXEL_MASK 0x1FFF0000
23804+
23805+#define VIDEOM_COMPRESS_BUF_PROCESS_OFFSET_REG 0x238
23806+ //#define COMPRESS_BUF_PROCESS_OFFSET_ALIGN 127 //128 byte alignment
23807+ //#define COMPRESS_BUF_PROCESS_OFFSET_MASK 0x3FFFFF
23808+
23809+
23810+//For Compression
23811+#define VIDEOM_COMPRESS_BUF_READ_OFFSET_REG 0x23C + VIDEOBASE_OFFSET //For stream mode
23812+ //#define COMPRESS_BUF_READ_OFFSET_ALIGN 127 //128 byte alignment
23813+ //#define COMPRESS_BUF_READ_OFFSET_MASK 0x003FFFFF
23814+//For Decompression
23815+#define VIDEOM_DECOMPRESS_BUF_WRITE_OFFSET_REG 0x23C + VIDEOBASE_OFFSET //For stream mode
23816+ //#define DECOMPRESS_BUF_WRITE_OFFSET_ALIGN 127 //128 byte alignment
23817+ //#define DECOMPRESS_BUF_WRITE_OFFSET_MASK 0x003FFFFF
23818+
23819+#define VIDEOM_BUF_1_ADDR_REG 0x244 + VIDEOBASE_OFFSET //For Source Buffer in frame mode
23820+ //#define BUF_1_ADDR_ALIGN 255 //256 byte alignment
23821+ //#define BUF_1_ADDR_MASK 0x0FFFFFFF
23822+
23823+#define VIDEOM_BUF_LINE_OFFSET_REG 0x248 + VIDEOBASE_OFFSET //Must set both in Frame/Stream mode
23824+ //#define BUF_LINE_OFFSET_ALIGN 7 //8 byte alignment
23825+ //#define BUF_LINE_OFFSET_MASK 0x00003FFF
23826+
23827+#define VIDEOM_BUF_2_ADDR_REG 0x24C + VIDEOBASE_OFFSET //For BCD Buffer in frame mode
23828+ //#define BUF_2_ADDR_ALIGN 255 //256 byte alignment
23829+ //#define BUF_2_ADDR_MASK 0x0FFFFFFF
23830+
23831+#define VIDEOM_FLAG_BUF_ADDR_REG 0x250 + VIDEOBASE_OFFSET //For block change flag buffer
23832+ //#define FLAG_BUF_ADDR_ALIGN 7 //8 byte alignment
23833+ //#define FLAG_BUF_ADDR_MASK 0x0FFFFFFF
23834+
23835+#define VIDEOM_COMPRESS_BUF_ADDR_REG 0x254 + VIDEOBASE_OFFSET //For stream mode
23836+ //#define FLAG_BUF_ADDR_ALIGN 7 //8 byte alignment
23837+ //#define FLAG_BUF_ADDR_MASK 0x0FFFFFFF
23838+
23839+#define VIDEOM_BUF_CODEC_OFFSET_READ 0x25C + VIDEOBASE_OFFSET //For stream mode,
23840+ //#define BUF_CODEC_OFFSET_ALIGN 255 //256 byte alignment
23841+ //#define BUF_CODEC_OFFSET_MASK 0x003FFFFF
23842+
23843+#define VIDEOM_COMPRESS_CONTROL_REG 0x260 + VIDEOBASE_OFFSET
23844+ //#define JPEG_ONLY_ENCODE 0x00000001 //Bit[0] JPEG only encoding
23845+ // #define JPEG_MIX_MODE 0 //Enable JPEG/VQ mix mode encoding
23846+ // #define JPEG_ONLY_MODE 1 //JPEG encoding mode only
23847+ //#define VQ_4_COLOR_ENCODE 0x00000002 //Bit[1] Enable 4 color VQ encoding
23848+ // #define VQ_1_2_COLOR_MODE 0 //1 and 2 color mode VQ encoding
23849+ // #define VQ_4_COLOR_MODE 1 //1, 2 and 4 color VQ encoding
23850+ //#define QUALITY_CODEC_SETTING 0x00000004 //Bit[2] High and best video quality codec mode setting
23851+ // #define JPEG_CODEC_MODE 0 //not supported in best video quality mode
23852+ // #define QUANTI_CODEC_MODE 1
23853+ //#define JPEG_DUAL_QUALITY_EN 0x00000008 //Bit[3] JPEG dual quality mode
23854+ // #define EN_JPEG_DUAL_QUALITY 1 //enable(only for normal video quality mode)
23855+ //#define BEST_QUALITY_EN 0x00000010 //Bit[4] Best quality video mode enable
23856+ // #define EN_BEST_QUALITY 1 //enable(only for quantization codec mode)
23857+ //#define RC4_CRYPT_EN 0x00000020 //Bit[5] Enable RC4 encryption/decryption
23858+ // #define EN_RC4_CRYPT 1 //enable
23859+ //#define NORMAL_QUANTI_CHROMI_TABLE 0x00000040 //Bit[10:6] Normal video quality mode JPEG DCT chromi quantination table
23860+ // #define NORMAL_QUANTI_CHROMI_TABLE_BIT 6
23861+ // #define NORMAL_QUANTI_CHROMI_TABLE_MASK 0x000007C0
23862+ //#define NORMAL_QUANTI_LUMI_TABLE 0x00000800 //Bit[15:11] Normal video quality mode JPEG DCT lumi quantination table
23863+ // #define NORMAL_QUANTI_LUMI_TABLE_BIT 11
23864+ // #define NORMAL_QUANTI_LUMI_TABLE_MASK 0x0000F800
23865+ //#define HIGH_QUALITY_EN 0x00010000 //Bit[16] High video quality mode enable
23866+ // #define EN_HIGH_QUALITY 1 //Enable
23867+ //#define UV_CIR656_FORMAT 0x00080000 //Bit[19] UV fromat
23868+ // #define USE_UV_CIR656 1 //recommand
23869+ //#define HUFFMAN_TABLE_SELECT 0x00100000 //Bit[20] JPEG Huffman table combination
23870+ // #define DUAL_TABLE 0 //Dual Y, UV table
23871+ // #define SINGLE_TABLE 1 //Single Y table
23872+ // #define SINGLE_UV_TABLE 0x00200000 //1x: Single UV table
23873+ //#define HIGH_QUANTI_CHROMI_TABLE 0x00400000 //Bit[26:22] High quality JPEG DCT chromi quantization table
23874+ // #define HIGH_QUANTI_CHROMI_TABLE_BIT 22
23875+ // #define HIGH_QUANTI_CHROMI_TABLE_MASK 0x07C00000
23876+ //#define HIGH_DEQUANTI_VALUE 0x00400000 //Bit[26:22] High quality de-quantization value
23877+ // #define HIGH_DEQUANTI_VALUE_BIT 22
23878+ // #define HIGH_DEQUANTI_VALUE_MASK 0x07C00000
23879+ //#define HIGH_QUANTI_LUMI_TABLE 0x08000000 //Bit[31:27] High quality JPEG DCT lumi quantization table
23880+ // #define HIGH_QUANTI_LUMI_TABLE_BIT 27
23881+ // #define HIGH_QUANTI_LUMI_TABLE_MASK 0xF8000000
23882+ //#define BEST_DEQUANTI_VALUE 0x08000000 //Bit[31:27] Best quality de-quantization value
23883+ // #define BEST_QUANTI_VALUE_BIT 27
23884+ // #define BEST_QUANTI_VALUE_MASK 0xF8000000
23885+
23886+#define VIDEOM_QUANTI_TABLE_LOW_REG 0x264 + VIDEOBASE_OFFSET //Match with 0x60 Bit[10:6], Bit[15:11]
23887+// #define QUANTI_CHROMI_TABLE_LOW 0x00000001 //Bit[4:0] Normal video low quality block chromi quantization table
23888+// #define QUANTI_CHROMI_TABLE_LOW_BIT 0
23889+// #define QUANTI_CHROMI_TABLE_LOW_MASK 0x0000001F
23890+// #define QUANTI_LUMI_TABLE_LOW 0x00000020 //Bit[9:5] Normal video low quality block lumi quantization table
23891+// #define QUANTI_CHROMI_TABLE_LOW_BIT 5
23892+// #define QUANTI_CHROMI_TABLE_LOW_MASK 0x000003E0
23893+
23894+#define VIDEOM_QUANTI_VALUE_REG 0x268 + VIDEOBASE_OFFSET //Match with 0x60 Bit[26:22],Bit[31:27]
23895+// #define HIGH_QUANTI_VALUE 0x00000001 //Bit[14:0] High quality quantization value. Format is 1.14
23896+// #define HIGH_QUANTI_VALUE_BIT 0
23897+// #define HIGH_QUANTI_VALUE_MASK 0x00007FFF
23898+// #define BEST_QUANTI_VALUE 0x00010000 //Bit[30:16] Best quality quantization value. Format is 1.14
23899+// #define BEST_QUANTI_VALUE_BIT 16
23900+// #define BEST_QUANTI_VALUE_MASK 0x7FFF0000
23901+
23902+#define VIDEOM_BSD_PARA_REG 0x26C + VIDEOBASE_OFFSET //Video BSD Parameters Register
23903+// #define BSD_HIGH_THRES 0x00000001 //Bit[7:0] Block sharpness detection high threshold
23904+// #define BSD_HIGH_THRES_BIT 0
23905+// #define BSD_HIGH_THRES_MASK 0x000000FF
23906+// #define BSD_LOW_THRES 0x00000100 //Bit[15:8] Block shaprpness detection low threshold
23907+// #define BSD_LOW_THRES_BIT 8
23908+// #define BSD_LOW_THRES_MASK 0x0000FF00
23909+// #define BSD_HIGH_COUNTS 0x00010000 //Bit[21:16] Block sharpness detection high counts threshold
23910+// #define BSD_HIGH_COUNTS_BIT 16
23911+// #define BSD_HIGH_COUNTS_MASK 0x003F0000
23912+// #define BSD_LOW_COUNTS 0x01000000 //Bit[27:24] Block sharpness detection low counts threshold
23913+// #define BSD_LOW_COUNTS_BIT 24
23914+// #define BSD_LOW_COUNTS_MASK 0x3F000000
23915+
23916+#define VIDEOM_COMPRESS_FRAME_SIZE_REG 0x270 + VIDEOBASE_OFFSET
23917+// #define COMPRESS_FRAME_SIZE_READ 0x00000001 //Bit[19:0] Video compression frame size read back(number of DW)
23918+// #define COMPRESS_FRAME_SIZE_READ_BIT 0
23919+// #define COMPRESS_FRAME_SIZE_READ_MASK 0x000FFFFF
23920+
23921+#define VIDEOM_COMPRESS_BLOCK_COUNT_REG 0x274 + VIDEOBASE_OFFSET
23922+// #define COMPRESS_BLOCK_COUNT_READ 0x00000001 //Bit[15:0] Video compress block counter read back(number of blocks)
23923+// #define COMPRESS_BLOCK_COUNT_READ_BIT 0
23924+// #define COMPRESS_BLOCK_COUNT_READ_MASK 0x0000FFFF
23925+
23926+#define VIDEOM_COMPRESS_FRAME_END_READ 0x278 + VIDEOBASE_OFFSET //Video compression stream frame end pointer
23927+ //#define COMPRESS_FRAME_END_READ_ALIGN 7
23928+ //#define COMPRESS_FRAME_END_READ_MASK 0x003FFFFF
23929+
23930+#define VIDEOM_USER_DEFINE_HEADER_REG 0x280 + VIDEOBASE_OFFSET
23931+// #define USER_DEFINE_HEADER 0x00000001 //Bit[15:0] Video user defined header parameter
23932+// #define USER_DEFINE_HEADER_BIT 0
23933+// #define USER_DEFINE_HEADER_MASK 0x0000FFFF
23934+
23935+/****** VR300-VR3FC: General Control registers *****/
23936+#define VIDEO_CONTROL_REG 0x300 + VIDEOBASE_OFFSET
23937+ #define CODEC_DECOMPRESS_MODE 0x00000001 //Bit[0] Codec in de-compression mode
23938+ #define CODEC_DECOMPRESS_MODE_BIT 0
23939+ #define CODEC_DECOMPRESS_MODE_MASK 0x00000001
23940+ #define COMPRESS_MODE 0
23941+ #define DECOMPRESS_MODE 1
23942+ #define VIDEO_SAFE_MODE 0x00000002 //Bit[1] VIDEO SAFE MODE
23943+ #define VIDEO_SAFE_MODE_BIT 1
23944+ #define VIDEO_SAFE_MODE_OFF 0
23945+ #define VIDEO_SAFE_MODE_ON 1
23946+ #define DELAY_VSYNC 0x00000004 //Bit[2] Delay Internal VSYNC
23947+ #define DELAY_VSYNC_BIT 2
23948+ #define DELAY_VSYNC_MASK (1<<2)
23949+ #define DELAY_VSYNC_OFF (0<<2)
23950+ #define DELAY_VSYNC_EN (1<<2)
23951+ #define VER_DOWNSCALING_LINE_BUFFER_EN 0x00000010 //Bit[5:4] Video vertical downscaling line buffer enable
23952+ #define VER_LINE_BUFFER_MASK (3<<4)
23953+ #define LINE_BUFFER_OFF (0<<4)
23954+ #define LINE_BUFFER_VIDEO1 1
23955+ #define LINE_BUFFER_VIDEO2 2
23956+ #define LINE_BUFFER_VIDEOM 3
23957+ #define RC4_KEY_BUFFER_SELECTION (1UL<<6) //Bit[7:6] RC4 Key Buffer Selection
23958+ #define RC4_KEY_BUFFER_SELECTION_BIT 6
23959+ #define RC4_KEY_BUFFER_SELECTION_MASK (3UL<<6)
23960+ #define RC4_KEY_BUFFER_VIDEO1 0
23961+ #define RC4_KEY_BUFFER_VIDEO2 1
23962+ #define RC4_KEY_BUFFER_VIDEOM 2
23963+ #define RC4_INIT_RESET (1UL<<8) //Bit[8] RC4 initial reset
23964+ #define RC4_INIT_RESET_BIT 8
23965+ #define RC4_INIT_RESET_MASK (1UL<<8)
23966+ #define RC4_NORMAL_MODE 0
23967+ #define RC4_RESET_COUNTER 1
23968+ #define RC4_TEST_MODE (1UL<<9) //Bit[9] RC4 test mode
23969+ #define RC4_TEST_MODE_BIT 9
23970+ #define RC4_TEST_OFF 0
23971+ #define RC4_TEST_ON 1
23972+ #define RC4_SAVE_MODE (1UL<<14) //Bit[14] RC4 save mode
23973+ #define RC4_SAVE_MODE_BIT 14
23974+ #define RC4_SAVE_MODE_MASK (1UL<<14)
23975+ #define RC4_SAVE_MODE_OFF 0
23976+ #define RC4_SAVE_MODE_ON 1
23977+ #define RC4_NO_RESET_FRAME (1UL<<15) //Bit[15] RC4 no reset when frame completed
23978+ #define RC4_NO_RESET_FRAME_BIT 15
23979+ #define RC4_NO_RESET_FRAME_MASK (1UL<<15)
23980+ #define RC4_NO_RESET_FRAME_OFF 0 //Always reset
23981+ #define RC4_NO_RESET_FRAME_ON 1
23982+
23983+#define VIDEO_INT_CONTROL_EN_REG 0x304 + VIDEOBASE_OFFSET
23984+ #define VIDEO1_WATCH_DOG_INT_EN 0x00000001 //Bit[0] Enable Video1 mode detection watch dog out of lock interrupt
23985+ #define VIDEO1_INPUT_COMPLETE_INT_EN 0x00000002 //Bit[1] Enable Video1 video input complete interrupt (frame complete only for frame mode)
23986+ #define VIDEO1_PACKET_READY_INT_EN 0x00000004 //Bit[2] Enable Video1 packet ready interrupt
23987+ #define VIDEO1_COMPRESS_COMPLETE_INT_EN 0x00000008 //Bit[3] Enable Video1 compression complete interrupt
23988+ #define VIDEO1_MODE_DETECTION_READY_INT_EN 0x00000010 //Bit[4] Enable video1 mode detection ready interrupt
23989+ #define VIDEO1_FRAME_COMPLETE_INT_EN 0x00000020 //Bit[5] Enable Video1 frame complete interrupt (only for stream mode)
23990+ #define VIDEO1_STREAM_ERR_INT_EN 0x00000040 //Bit[6] Enable Video1 decode stream error interrupt
23991+ #define VIDEO2_WATCH_DOG_INT_EN 0x00000100 //Bit[8] Enable Video2 mode detection watch dog out of lock interrupt
23992+ #define VIDEO2_INPUT_COMPLETE_INT_EN 0x00000200 //Bit[9] Enable Video2 video input complete interrupt (frame complete only for frame mode)
23993+ #define VIDEO2_PACKET_READY_INT_EN 0x00000400 //Bit[10] Enable Video2 packet ready interrupt
23994+ #define VIDEO2_COMPRESS_COMPLETE_INT_EN 0x00000800 //Bit[11] Enable Video2 compression complete interrupt
23995+ #define VIDEO2_MODE_DETECTION_READY_INT_EN 0x00001000 //Bit[12] Enable video2 mode detection ready interrupt
23996+ #define VIDEO2_FRAME_COMPLETE_INT_EN 0x00002000 //Bit[13] Enable Video2 frame complete interrupt (only for stream mode)
23997+ #define VIDEO2_STREAM_ERR_INT_EN 0x00004000 //Bit[14] Enable Video2 decode stream error interrupt
23998+ #define VIDEOM_INPUT_COMPLETE_INT_EN 0x00010000 //Bit[16] Enable VideoM video input complete interrupt
23999+ #define VIDEOM_COMPRESS_COMPLETE_INT_EN 0x00020000 //Bit[17] Enable VideoM compression complete interrupt
24000+ #define VIDEOM_PACKET_READY_INT_EN 0x00040000 //Bit[18] Enable VideoM packet ready interrupt
24001+ #define VIDEOM_FRAME_COMPLETE_INT_EN 0x00080000 //Bit[19] Enable VideoM frame complete interrupt (only for stream mode)
24002+
24003+#define VIDEO_INT_CONTROL_READ_REG 0x308 + VIDEOBASE_OFFSET //Clear when write 1
24004+ #define VIDEO1_WATCH_DOG_READ 0x00000001 //Bit[0] Video1 mode detection watch dog out of lock interrupt status read back
24005+ #define VIDEO1_WATCH_DOG_BIT 0
24006+ #define VIDEO1_WATCH_DOG_MASK 0x00000001
24007+ #define VIDEO1_INPUT_COMPLETE_READ 0x00000002 //Bit[1] Video1 video input complete interrupt status read back (frame complete only for frame mode)
24008+ #define VIDEO1_INPUT_COMPLETE_BIT 1
24009+ #define VIDEO1_INPUT_COMPLETE_MASK 0x00000002
24010+ #define VIDEO1_PACKET_READY_READ 0x00000004 //Bit[2] Video1 packet ready interrupt status read back
24011+ #define VIDEO1_PACKET_READY_BIT 2
24012+ #define VIDEO1_PACKET_READY_MASK 0x00000004
24013+ #define VIDEO1_COMPRESS_COMPLETE_READ 0x00000008 //Bit[3] Video1 compression complete interrupt status read back
24014+ #define VIDEO1_COMPRESS_COMPLETE_BIT 3
24015+ #define VIDEO1_COMPRESS_COMPLETE_MASK 0x00000008
24016+ #define VIDEO1_MODE_DETECTION_READY_READ 0x00000010 //Bit[4] Video1 mode detection ready interrupt status read back
24017+ #define VIDEO1_MODE_DETECTION_READY_BIT 4
24018+ #define VIDEO1_FRAME_COMPLETE_READ 0x00000020 //Bit[5] Video1 frame complete interrupt status read back
24019+ #define VIDEO1_FRAME_COMPLETE_BIT 5
24020+ #define VIDEO1_FRAME_COMPLETE_MASK 0x00000020
24021+ #define VIDEO1_STREAM_ERR_READ 0x00000040 //Bit[6] Video1 decode stream error interrupt status read back
24022+ #define VIDEO1_STREAM_ERR_BIT 6
24023+ #define VIDEO1_STREAM_ERR_MASK 0x00000040
24024+ #define VIDEO2_WATCH_DOG_READ 0x00000100 //Bit[8] Video2 mode detection watch dog out of lock interrupt status read back
24025+ #define VIDEO2_WATCH_DOG_BIT 8
24026+ #define VIDEO2_WATCH_DOG_MASK 0x00000100
24027+ #define VIDEO2_INPUT_COMPLETE_READ 0x00000200 //Bit[9] Video2 video input complete interrupt status read back (frame complete only for frame mode)
24028+ #define VIDEO2_INPUT_COMPLETE_BIT 9
24029+ #define VIDEO2_INPUT_COMPLETE_MASK 0x00000200
24030+ #define VIDEO2_PACKET_READY_READ 0x00000400 //Bit[10] Video2 packet ready interrupt status read back
24031+ #define VIDEO2_PACKET_READY_BIT 10
24032+ #define VIDEO2_PACKET_READY_MASK 0x00000400
24033+ #define VIDEO2_COMPRESS_COMPLETE_READ 0x00000800 //Bit[11] Video2 compression complete interrupt status read back
24034+ #define VIDEO2_COMPRESS_COMPLETE_BIT 11
24035+ #define VIDEO2_COMPRESS_COMPLETE_MASK 0x00000800
24036+ #define VIDEO2_MODE_DETECTION_READY_READ 0x00001000 //Bit[12] Video2 mode detection ready interrupt status read back
24037+ #define VIDEO2_MODE_DETECTION_READY_BIT 12
24038+ #define VIDEO2_FRAME_COMPLETE_READ 0x00002000 //Bit[13] Video2 frame complete interrupt status read back
24039+ #define VIDEO2_FRAME_COMPLETE_BIT 13
24040+ #define VIDEO2_FRAME_COMPLETE_MASK 0x00002000
24041+ #define VIDEO2_STREAM_ERR_READ 0x00004000 //Bit[14] Video2 decode stream error interrupt status read back
24042+ #define VIDEO2_STREAM_ERR_BIT 14
24043+ #define VIDEO2_STREAM_ERR_MASK 0x00004000
24044+ //need check spec
24045+ #define VIDEOM_INPUT_COMPLETE_READ 0x00010000 //Bit[16] VideoM video input complete interrupt status read back
24046+ #define VIDEOM_INPUT_COMPLETE_BIT 16
24047+ #define VIDEOM_INPUT_COMPLETE_MASK 0x00010000
24048+ #define VIDEOM_COMPRESS_COMPLETE_READ 0x00020000 //Bit[17] VideoM compression complete interrupt status read back
24049+ #define VIDEOM_COMPRESS_COMPLETE_BIT 17
24050+ #define VIDEOM_COMPRESS_COMPLETE_MASK 0x00020000
24051+ #define VIDEOM_PACKET_READY_READ 0x00040000 //Bit[18] Clear Packet ready interrupt when write 1
24052+ #define VIDEOM_PACKET_READY_BIT 18
24053+ #define VIDEOM_PACKET_READY_MASK 0x00040000
24054+ #define VIDEOM_FRAME_COMPLETE_READ 0x00080000 //Bit[19] Clear Frame complete interrupt when write 1
24055+ #define VIDEOM_FRAME_COMPLETE_BIT 19
24056+ #define VIDEOM_FRAME_COMPLETE_MASK 0x00080000
24057+
24058+#define VIDEO_INT_CONTROL_CLEAR_REG 0x308 + VIDEOBASE_OFFSET //Clear when write 1
24059+ //Clear when write 1
24060+ #define VIDEO1_WATCH_DOG_CLEAR 0x00000001 //Bit[0] Clear mode detection watch dog out of lock interrupt when write 1
24061+ #define VIDEO1_INPUT_COMPLETE_CLEAR 0x00000002 //Bit[1] Clear video input complete interrupt when write 1 (frame complete only for frame mode)
24062+ #define VIDEO1_PACKET_READY_CLEAR 0x00000004 //Bit[2] Clear Packet ready interrupt when write 1
24063+ #define VIDEO1_PACKET_READY_CLEAR_BIT 2
24064+ #define VIDEO1_PACKET_READY_CLEAR_MASK 0x00000004
24065+ #define VIDEO1_COMPRESS_COMPLETE_CLEAR 0x00000008 //Bit[3] Clear video compression interrupt when write 1
24066+ #define VIDEO1_MODE_DETECTION_READY_CLEAR 0x00000010 //Bit[4] Clear Video1 Mode detection ready interrupt when write 1
24067+ #define VIDEO1_FRAME_COMPLETE_CLEAR 0x00000020 //Bit[5] Clear Frame complete interrupt when write 1
24068+ #define VIDEO1_FRAME_COMPLETE_CLEAR_BIT 5
24069+ #define VIDEO1_FRAME_COMPLETE_CLEAR_MASK 0x00000020
24070+ #define VIDEO1_STREAM_ERR_CLEAR 0x00000040 //Bit[6] Clear decode stream error interrupt when write 1
24071+ #define VIDEO2_WATCH_DOG_CLEAR 0x00000100 //Bit[8] Clear Mode detection interrupt when write 1
24072+ #define VIDEO2_INPUT_COMPLETE_CLEAR 0x00000200 //Bit[9] Clear video input complete interrupt when write 1
24073+ #define VIDEO2_PACKET_READY_CLEAR 0x00000400 //Bit[10] Clear packet ready interrupt when write 1
24074+ #define VIDEO2_COMPRESS_COMPLETE_CLEAR 0x00000800 //Bit[11] Clear video compression complete interrupt when write 1
24075+ #define VIDEO2_MODE_DETECTION_READY_CLEAR 0x00001000 //Bit[12] Clear Video2 Mode detection ready interrupt when write 1
24076+ #define VIDEO2_FRAME_COMPLETE_CLEAR 0x00002000 //Bit[13] Clear Frame complete interrupt when write 1 (frame complete only for frame mode)
24077+ #define VIDEO2_STREAM_ERR_CLEAR 0x00004000 //Bit[14] Clear Decode stream error interrupt when write 1
24078+ //need check spec
24079+ #define VIDEOM_INPUT_COMPLETE_CLEAR 0x00010000 //Bit[16] Clear video input complete interrupt when write 1
24080+ #define VIDEOM_COMPRESS_COMPLETE_CLEAR 0x00020000 //Bit[17] Clear compression complete interrupt when write 1
24081+ #define VIDEOM_COMPRESS_COMPLETE_CLEAR_BIT 17
24082+ #define VIDEOM_COMPRESS_COMPLETE_CLEAR_MASK 0x00020000
24083+ #define VIDEOM_PACKET_READY_CLEAR 0x00040000 //Bit[18] Clear compression complete interrupt when write 1
24084+ #define VIDEOM_PACKET_READY_CLEAR_BIT 18
24085+ #define VIDEOM_PACKET_READY_CLEAR_MASK 0x00040000
24086+ #define VIDEOM_FRAME_COMPLETE_CLEAR 0x00100000 //Bit[20] Clear Frame complete interrupt when write 1
24087+ #define VIDEOM_FRAME_COMPLETE_CLEAR_BIT 20
24088+ #define VIDEOM_FRAME_COMPLETE_CLEAR_MASK 0x00100000
24089+ #define VIDEOM_STREAM_ERR_CLEAR 0x00200000 //Bit[21] Clear decode stream error interrupt when write 1
24090+
24091+#define VIDEO_MODE_DETECTION_PARAM_REG 0x30C + VIDEOBASE_OFFSET
24092+ #define EDGE_PIXEL_THRES_BIT 8 //Bit[15:8] Mode detection edge pixel threshold
24093+ #define EDGE_PIXEL_THRES_MASK 0x0000FF00
24094+ #define VER_STABLE_MAX_BIT 16 //Bit[19:16] Mode detection vertical stable maximum
24095+ #define VER_STABLE_MAX_BIT_MASK 0x000F0000
24096+ #define HOR_STABLE_MAX_BIT 20 //Bit[23:20] Mode detection horizontal stable maximum
24097+ #define HOR_STABLE_MAX_BIT_MASK 0x00F00000
24098+ #define VER_STABLE_THRES_BIT 24 //Bit[27:24] Mode detection vertical stable threshold
24099+ #define VER_STABLE_THRES_BIT_MASK 0x0F000000
24100+ #define HOR_STABLE_THRES_BIT 28 //Bit[31:28] Mode detection horizontal stable threshold
24101+ #define HOR_STABLE_THRES_BIT_MASK 0xF0000000
24102+
24103+#define VIDEO_CRC_PRIMARY_REG 0x320 + VIDEOBASE_OFFSET
24104+ #define CRC_CHECK_EN 0x00000001 //Bit[0] Video port 1/2 Enable video capture write CRC check
24105+ #define CRC_CHECK_EN_BIT 0
24106+ #define CRC_CHECK_HIGH 0x00000002 //Bit[1] Video port 1/2 CRC check high bit only
24107+ #define CRC_CHECK_HIGH_BIT 1
24108+ #define SKIP_COUNT_MAX 0x00000004 //Bit[7:2] Video port 1/2 Max capture write skip count
24109+ #define SKIP_COUNT_MAX_BIT 2
24110+ #define SKIP_COUNT_MAX_MASK 0x000000FC
24111+ #define CRC_PRIMARY_POLY_LOW 0x00000100 //Bit[15:8] Primary CRC low 8-bit polynomial
24112+ #define CRC_RIMARY_POLY_LOW_BIT 8
24113+ #define CRC_RIMARY_POLY_LOW_MASK 0x0000FF00
24114+ #define CRC_PRIMARY_POLY_HIGH 0x00010000 //Bit[31:16] Primary CRC high 8-bit polynomial
24115+ #define CRC_RIMARY_POLY_HIGH_BIT 16
24116+ #define CRC_RIMARY_POLY_HIGH_MASK 0xFFFF0000
24117+
24118+
24119+#define VIDEO_CRC_SECOND_REG 0x324 + VIDEOBASE_OFFSET
24120+ #define CRC_SECOND_POLY_LOW 0x00000100 //Bit[15:8] Secondary CRC low 8-bit polynomial
24121+ #define CRC_SECOND_POLY_LOW_BIT 8
24122+ #define CRC_SECOND_POLY_LOW_MASK 0x0000FF00
24123+ #define CRC_SECOND_POLY_HIGH 0x00010000 //Bit[31:16] Secondary CRC high 8-bit polynomial
24124+ #define CRC_SECOND_POLY_HIGH_BIT 16
24125+ #define CRC_SECOND_POLY_HIGH_MASK 0xFFFF0000
24126+
24127+#define VIDEO1_RC4_KEYS_REG 0x400 + VIDEOBASE_OFFSET //Total Video1 RC4 Keys
24128+#define VIDEO2_RC4_KEYS_REG 0x500 + VIDEOBASE_OFFSET //Total Video2 RC4 Keys
24129+#define VIDEOM_RC4_KEYS_REG 0x600 + VIDEOBASE_OFFSET //Total VideoM RC4 Keys
24130+
24131+#endif /* end of _VREG_H_ */
24132+
24133diff --git a/board/aspeed/ast2400/Makefile b/board/aspeed/ast2400/Makefile
24134new file mode 100644
24135index 0000000..1970ea1
24136--- /dev/null
24137+++ b/board/aspeed/ast2400/Makefile
24138@@ -0,0 +1,44 @@
24139+# This program is distributed in the hope that it will be useful,
24140+# but WITHOUT ANY WARRANTY; without even the implied warranty of
24141+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24142+# GNU General Public License for more details.
24143+#
24144+# You should have received a copy of the GNU General Public License
24145+# along with this program; if not, write to the Free Software
24146+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24147+# MA 02111-1307 USA
24148+#
24149+
24150+include $(TOPDIR)/config.mk
24151+
24152+LIB = $(obj)lib$(BOARD).a
24153+
24154+COBJS := ast2400.o flash.o flash_spi.o pci.o crc32.o slt.o regtest.o vfun.o vhace.o crt.o videotest.o mactest.o hactest.o mictest.o
24155+
24156+ifeq ($(CONFIG_FPGA_ASPEED),y)
24157+SOBJS := platform_fpga.o
24158+else ifeq ($(CONFIG_SLT_ASPEED),y)
24159+SOBJS := platform_slt.o
24160+else
24161+SOBJS := platform.o
24162+endif
24163+
24164+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
24165+OBJS := $(addprefix $(obj),$(COBJS))
24166+SOBJS := $(addprefix $(obj),$(SOBJS))
24167+
24168+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
24169+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
24170+
24171+clean:
24172+ rm -f $(SOBJS) $(OBJS)
24173+
24174+distclean: clean
24175+ rm -f $(LIB) core *.bak $(obj).depend
24176+
24177+# defines $(obj).depend target
24178+include $(SRCTREE)/rules.mk
24179+
24180+sinclude .depend
24181+
24182+#########################################################################
24183diff --git a/board/aspeed/ast2400/aes.c b/board/aspeed/ast2400/aes.c
24184new file mode 100755
24185index 0000000..76262e7
24186--- /dev/null
24187+++ b/board/aspeed/ast2400/aes.c
24188@@ -0,0 +1,579 @@
24189+/*
24190+ * AES implementation
24191+ *
24192+ * This program is free software; you can redistribute it and/or modify
24193+ * it under the terms of the GNU General Public License as published by
24194+ * the Free Software Foundation; either version 2 of the License, or
24195+ * (at your option) any later version.
24196+ *
24197+ * This program is distributed in the hope that it will be useful,
24198+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
24199+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24200+ * GNU General Public License for more details.
24201+ *
24202+ * You should have received a copy of the GNU General Public License
24203+ * along with this program; if not, write to the Free Software
24204+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24205+ */
24206+
24207+/* uncomment the following line to run the test suite */
24208+
24209+/* #define TEST */
24210+
24211+/* uncomment the following line to use pre-computed tables */
24212+/* otherwise the tables will be generated at the first run */
24213+
24214+#define FIXED_TABLES
24215+
24216+#ifndef FIXED_TABLES
24217+
24218+/* forward S-box & tables */
24219+
24220+uint32 FSb[256];
24221+uint32 FT0[256];
24222+uint32 FT1[256];
24223+uint32 FT2[256];
24224+uint32 FT3[256];
24225+
24226+/* reverse S-box & tables */
24227+
24228+uint32 RSb[256];
24229+uint32 RT0[256];
24230+uint32 RT1[256];
24231+uint32 RT2[256];
24232+uint32 RT3[256];
24233+
24234+/* round constants */
24235+
24236+uint32 RCON[10];
24237+
24238+/* tables generation flag */
24239+
24240+int do_init = 1;
24241+
24242+/* tables generation routine */
24243+
24244+#define ROTR8(x) ( ( ( x << 24 ) & 0xFFFFFFFF ) | \
24245+ ( ( x & 0xFFFFFFFF ) >> 8 ) )
24246+
24247+#define XTIME(x) ( ( x << 1 ) ^ ( ( x & 0x80 ) ? 0x1B : 0x00 ) )
24248+#define MUL(x,y) ( ( x && y ) ? pow[(log[x] + log[y]) % 255] : 0 )
24249+
24250+void aes_gen_tables( void )
24251+{
24252+ int i;
24253+ uint8 x, y;
24254+ uint8 pow[256];
24255+ uint8 log[256];
24256+
24257+ /* compute pow and log tables over GF(2^8) */
24258+
24259+ for( i = 0, x = 1; i < 256; i++, x ^= XTIME( x ) )
24260+ {
24261+ pow[i] = x;
24262+ log[x] = i;
24263+ }
24264+
24265+ /* calculate the round constants */
24266+
24267+ for( i = 0, x = 1; i < 10; i++, x = XTIME( x ) )
24268+ {
24269+ RCON[i] = (uint32) x << 24;
24270+ }
24271+
24272+ /* generate the forward and reverse S-boxes */
24273+
24274+ FSb[0x00] = 0x63;
24275+ RSb[0x63] = 0x00;
24276+
24277+ for( i = 1; i < 256; i++ )
24278+ {
24279+ x = pow[255 - log[i]];
24280+
24281+ y = x; y = ( y << 1 ) | ( y >> 7 );
24282+ x ^= y; y = ( y << 1 ) | ( y >> 7 );
24283+ x ^= y; y = ( y << 1 ) | ( y >> 7 );
24284+ x ^= y; y = ( y << 1 ) | ( y >> 7 );
24285+ x ^= y ^ 0x63;
24286+
24287+ FSb[i] = x;
24288+ RSb[x] = i;
24289+ }
24290+
24291+ /* generate the forward and reverse tables */
24292+
24293+ for( i = 0; i < 256; i++ )
24294+ {
24295+ x = (unsigned char) FSb[i]; y = XTIME( x );
24296+
24297+ FT0[i] = (uint32) ( x ^ y ) ^
24298+ ( (uint32) x << 8 ) ^
24299+ ( (uint32) x << 16 ) ^
24300+ ( (uint32) y << 24 );
24301+
24302+ FT0[i] &= 0xFFFFFFFF;
24303+
24304+ FT1[i] = ROTR8( FT0[i] );
24305+ FT2[i] = ROTR8( FT1[i] );
24306+ FT3[i] = ROTR8( FT2[i] );
24307+
24308+ y = (unsigned char) RSb[i];
24309+
24310+ RT0[i] = ( (uint32) MUL( 0x0B, y ) ) ^
24311+ ( (uint32) MUL( 0x0D, y ) << 8 ) ^
24312+ ( (uint32) MUL( 0x09, y ) << 16 ) ^
24313+ ( (uint32) MUL( 0x0E, y ) << 24 );
24314+
24315+ RT0[i] &= 0xFFFFFFFF;
24316+
24317+ RT1[i] = ROTR8( RT0[i] );
24318+ RT2[i] = ROTR8( RT1[i] );
24319+ RT3[i] = ROTR8( RT2[i] );
24320+ }
24321+}
24322+
24323+#else
24324+
24325+/* forward S-box */
24326+
24327+static const uint32 FSb[256] =
24328+{
24329+ 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5,
24330+ 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
24331+ 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
24332+ 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
24333+ 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC,
24334+ 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
24335+ 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A,
24336+ 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
24337+ 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0,
24338+ 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
24339+ 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B,
24340+ 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
24341+ 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85,
24342+ 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
24343+ 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5,
24344+ 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
24345+ 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17,
24346+ 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
24347+ 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88,
24348+ 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
24349+ 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C,
24350+ 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
24351+ 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9,
24352+ 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
24353+ 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6,
24354+ 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
24355+ 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E,
24356+ 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
24357+ 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94,
24358+ 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
24359+ 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68,
24360+ 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
24361+};
24362+
24363+/* forward tables */
24364+
24365+#define FT \
24366+\
24367+ V(C6,63,63,A5), V(F8,7C,7C,84), V(EE,77,77,99), V(F6,7B,7B,8D), \
24368+ V(FF,F2,F2,0D), V(D6,6B,6B,BD), V(DE,6F,6F,B1), V(91,C5,C5,54), \
24369+ V(60,30,30,50), V(02,01,01,03), V(CE,67,67,A9), V(56,2B,2B,7D), \
24370+ V(E7,FE,FE,19), V(B5,D7,D7,62), V(4D,AB,AB,E6), V(EC,76,76,9A), \
24371+ V(8F,CA,CA,45), V(1F,82,82,9D), V(89,C9,C9,40), V(FA,7D,7D,87), \
24372+ V(EF,FA,FA,15), V(B2,59,59,EB), V(8E,47,47,C9), V(FB,F0,F0,0B), \
24373+ V(41,AD,AD,EC), V(B3,D4,D4,67), V(5F,A2,A2,FD), V(45,AF,AF,EA), \
24374+ V(23,9C,9C,BF), V(53,A4,A4,F7), V(E4,72,72,96), V(9B,C0,C0,5B), \
24375+ V(75,B7,B7,C2), V(E1,FD,FD,1C), V(3D,93,93,AE), V(4C,26,26,6A), \
24376+ V(6C,36,36,5A), V(7E,3F,3F,41), V(F5,F7,F7,02), V(83,CC,CC,4F), \
24377+ V(68,34,34,5C), V(51,A5,A5,F4), V(D1,E5,E5,34), V(F9,F1,F1,08), \
24378+ V(E2,71,71,93), V(AB,D8,D8,73), V(62,31,31,53), V(2A,15,15,3F), \
24379+ V(08,04,04,0C), V(95,C7,C7,52), V(46,23,23,65), V(9D,C3,C3,5E), \
24380+ V(30,18,18,28), V(37,96,96,A1), V(0A,05,05,0F), V(2F,9A,9A,B5), \
24381+ V(0E,07,07,09), V(24,12,12,36), V(1B,80,80,9B), V(DF,E2,E2,3D), \
24382+ V(CD,EB,EB,26), V(4E,27,27,69), V(7F,B2,B2,CD), V(EA,75,75,9F), \
24383+ V(12,09,09,1B), V(1D,83,83,9E), V(58,2C,2C,74), V(34,1A,1A,2E), \
24384+ V(36,1B,1B,2D), V(DC,6E,6E,B2), V(B4,5A,5A,EE), V(5B,A0,A0,FB), \
24385+ V(A4,52,52,F6), V(76,3B,3B,4D), V(B7,D6,D6,61), V(7D,B3,B3,CE), \
24386+ V(52,29,29,7B), V(DD,E3,E3,3E), V(5E,2F,2F,71), V(13,84,84,97), \
24387+ V(A6,53,53,F5), V(B9,D1,D1,68), V(00,00,00,00), V(C1,ED,ED,2C), \
24388+ V(40,20,20,60), V(E3,FC,FC,1F), V(79,B1,B1,C8), V(B6,5B,5B,ED), \
24389+ V(D4,6A,6A,BE), V(8D,CB,CB,46), V(67,BE,BE,D9), V(72,39,39,4B), \
24390+ V(94,4A,4A,DE), V(98,4C,4C,D4), V(B0,58,58,E8), V(85,CF,CF,4A), \
24391+ V(BB,D0,D0,6B), V(C5,EF,EF,2A), V(4F,AA,AA,E5), V(ED,FB,FB,16), \
24392+ V(86,43,43,C5), V(9A,4D,4D,D7), V(66,33,33,55), V(11,85,85,94), \
24393+ V(8A,45,45,CF), V(E9,F9,F9,10), V(04,02,02,06), V(FE,7F,7F,81), \
24394+ V(A0,50,50,F0), V(78,3C,3C,44), V(25,9F,9F,BA), V(4B,A8,A8,E3), \
24395+ V(A2,51,51,F3), V(5D,A3,A3,FE), V(80,40,40,C0), V(05,8F,8F,8A), \
24396+ V(3F,92,92,AD), V(21,9D,9D,BC), V(70,38,38,48), V(F1,F5,F5,04), \
24397+ V(63,BC,BC,DF), V(77,B6,B6,C1), V(AF,DA,DA,75), V(42,21,21,63), \
24398+ V(20,10,10,30), V(E5,FF,FF,1A), V(FD,F3,F3,0E), V(BF,D2,D2,6D), \
24399+ V(81,CD,CD,4C), V(18,0C,0C,14), V(26,13,13,35), V(C3,EC,EC,2F), \
24400+ V(BE,5F,5F,E1), V(35,97,97,A2), V(88,44,44,CC), V(2E,17,17,39), \
24401+ V(93,C4,C4,57), V(55,A7,A7,F2), V(FC,7E,7E,82), V(7A,3D,3D,47), \
24402+ V(C8,64,64,AC), V(BA,5D,5D,E7), V(32,19,19,2B), V(E6,73,73,95), \
24403+ V(C0,60,60,A0), V(19,81,81,98), V(9E,4F,4F,D1), V(A3,DC,DC,7F), \
24404+ V(44,22,22,66), V(54,2A,2A,7E), V(3B,90,90,AB), V(0B,88,88,83), \
24405+ V(8C,46,46,CA), V(C7,EE,EE,29), V(6B,B8,B8,D3), V(28,14,14,3C), \
24406+ V(A7,DE,DE,79), V(BC,5E,5E,E2), V(16,0B,0B,1D), V(AD,DB,DB,76), \
24407+ V(DB,E0,E0,3B), V(64,32,32,56), V(74,3A,3A,4E), V(14,0A,0A,1E), \
24408+ V(92,49,49,DB), V(0C,06,06,0A), V(48,24,24,6C), V(B8,5C,5C,E4), \
24409+ V(9F,C2,C2,5D), V(BD,D3,D3,6E), V(43,AC,AC,EF), V(C4,62,62,A6), \
24410+ V(39,91,91,A8), V(31,95,95,A4), V(D3,E4,E4,37), V(F2,79,79,8B), \
24411+ V(D5,E7,E7,32), V(8B,C8,C8,43), V(6E,37,37,59), V(DA,6D,6D,B7), \
24412+ V(01,8D,8D,8C), V(B1,D5,D5,64), V(9C,4E,4E,D2), V(49,A9,A9,E0), \
24413+ V(D8,6C,6C,B4), V(AC,56,56,FA), V(F3,F4,F4,07), V(CF,EA,EA,25), \
24414+ V(CA,65,65,AF), V(F4,7A,7A,8E), V(47,AE,AE,E9), V(10,08,08,18), \
24415+ V(6F,BA,BA,D5), V(F0,78,78,88), V(4A,25,25,6F), V(5C,2E,2E,72), \
24416+ V(38,1C,1C,24), V(57,A6,A6,F1), V(73,B4,B4,C7), V(97,C6,C6,51), \
24417+ V(CB,E8,E8,23), V(A1,DD,DD,7C), V(E8,74,74,9C), V(3E,1F,1F,21), \
24418+ V(96,4B,4B,DD), V(61,BD,BD,DC), V(0D,8B,8B,86), V(0F,8A,8A,85), \
24419+ V(E0,70,70,90), V(7C,3E,3E,42), V(71,B5,B5,C4), V(CC,66,66,AA), \
24420+ V(90,48,48,D8), V(06,03,03,05), V(F7,F6,F6,01), V(1C,0E,0E,12), \
24421+ V(C2,61,61,A3), V(6A,35,35,5F), V(AE,57,57,F9), V(69,B9,B9,D0), \
24422+ V(17,86,86,91), V(99,C1,C1,58), V(3A,1D,1D,27), V(27,9E,9E,B9), \
24423+ V(D9,E1,E1,38), V(EB,F8,F8,13), V(2B,98,98,B3), V(22,11,11,33), \
24424+ V(D2,69,69,BB), V(A9,D9,D9,70), V(07,8E,8E,89), V(33,94,94,A7), \
24425+ V(2D,9B,9B,B6), V(3C,1E,1E,22), V(15,87,87,92), V(C9,E9,E9,20), \
24426+ V(87,CE,CE,49), V(AA,55,55,FF), V(50,28,28,78), V(A5,DF,DF,7A), \
24427+ V(03,8C,8C,8F), V(59,A1,A1,F8), V(09,89,89,80), V(1A,0D,0D,17), \
24428+ V(65,BF,BF,DA), V(D7,E6,E6,31), V(84,42,42,C6), V(D0,68,68,B8), \
24429+ V(82,41,41,C3), V(29,99,99,B0), V(5A,2D,2D,77), V(1E,0F,0F,11), \
24430+ V(7B,B0,B0,CB), V(A8,54,54,FC), V(6D,BB,BB,D6), V(2C,16,16,3A)
24431+
24432+#define V(a,b,c,d) 0x##a##b##c##d
24433+static const uint32 FT0[256] = { FT };
24434+#undef V
24435+
24436+#define V(a,b,c,d) 0x##d##a##b##c
24437+static const uint32 FT1[256] = { FT };
24438+#undef V
24439+
24440+#define V(a,b,c,d) 0x##c##d##a##b
24441+static const uint32 FT2[256] = { FT };
24442+#undef V
24443+
24444+#define V(a,b,c,d) 0x##b##c##d##a
24445+static const uint32 FT3[256] = { FT };
24446+#undef V
24447+
24448+#undef FT
24449+
24450+/* reverse S-box */
24451+
24452+static const uint32 RSb[256] =
24453+{
24454+ 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38,
24455+ 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB,
24456+ 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87,
24457+ 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB,
24458+ 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D,
24459+ 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E,
24460+ 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2,
24461+ 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25,
24462+ 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16,
24463+ 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92,
24464+ 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA,
24465+ 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84,
24466+ 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A,
24467+ 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06,
24468+ 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02,
24469+ 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B,
24470+ 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA,
24471+ 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73,
24472+ 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85,
24473+ 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E,
24474+ 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89,
24475+ 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B,
24476+ 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20,
24477+ 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4,
24478+ 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31,
24479+ 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F,
24480+ 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D,
24481+ 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF,
24482+ 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0,
24483+ 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61,
24484+ 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26,
24485+ 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D
24486+};
24487+
24488+/* reverse tables */
24489+
24490+#define RT \
24491+\
24492+ V(51,F4,A7,50), V(7E,41,65,53), V(1A,17,A4,C3), V(3A,27,5E,96), \
24493+ V(3B,AB,6B,CB), V(1F,9D,45,F1), V(AC,FA,58,AB), V(4B,E3,03,93), \
24494+ V(20,30,FA,55), V(AD,76,6D,F6), V(88,CC,76,91), V(F5,02,4C,25), \
24495+ V(4F,E5,D7,FC), V(C5,2A,CB,D7), V(26,35,44,80), V(B5,62,A3,8F), \
24496+ V(DE,B1,5A,49), V(25,BA,1B,67), V(45,EA,0E,98), V(5D,FE,C0,E1), \
24497+ V(C3,2F,75,02), V(81,4C,F0,12), V(8D,46,97,A3), V(6B,D3,F9,C6), \
24498+ V(03,8F,5F,E7), V(15,92,9C,95), V(BF,6D,7A,EB), V(95,52,59,DA), \
24499+ V(D4,BE,83,2D), V(58,74,21,D3), V(49,E0,69,29), V(8E,C9,C8,44), \
24500+ V(75,C2,89,6A), V(F4,8E,79,78), V(99,58,3E,6B), V(27,B9,71,DD), \
24501+ V(BE,E1,4F,B6), V(F0,88,AD,17), V(C9,20,AC,66), V(7D,CE,3A,B4), \
24502+ V(63,DF,4A,18), V(E5,1A,31,82), V(97,51,33,60), V(62,53,7F,45), \
24503+ V(B1,64,77,E0), V(BB,6B,AE,84), V(FE,81,A0,1C), V(F9,08,2B,94), \
24504+ V(70,48,68,58), V(8F,45,FD,19), V(94,DE,6C,87), V(52,7B,F8,B7), \
24505+ V(AB,73,D3,23), V(72,4B,02,E2), V(E3,1F,8F,57), V(66,55,AB,2A), \
24506+ V(B2,EB,28,07), V(2F,B5,C2,03), V(86,C5,7B,9A), V(D3,37,08,A5), \
24507+ V(30,28,87,F2), V(23,BF,A5,B2), V(02,03,6A,BA), V(ED,16,82,5C), \
24508+ V(8A,CF,1C,2B), V(A7,79,B4,92), V(F3,07,F2,F0), V(4E,69,E2,A1), \
24509+ V(65,DA,F4,CD), V(06,05,BE,D5), V(D1,34,62,1F), V(C4,A6,FE,8A), \
24510+ V(34,2E,53,9D), V(A2,F3,55,A0), V(05,8A,E1,32), V(A4,F6,EB,75), \
24511+ V(0B,83,EC,39), V(40,60,EF,AA), V(5E,71,9F,06), V(BD,6E,10,51), \
24512+ V(3E,21,8A,F9), V(96,DD,06,3D), V(DD,3E,05,AE), V(4D,E6,BD,46), \
24513+ V(91,54,8D,B5), V(71,C4,5D,05), V(04,06,D4,6F), V(60,50,15,FF), \
24514+ V(19,98,FB,24), V(D6,BD,E9,97), V(89,40,43,CC), V(67,D9,9E,77), \
24515+ V(B0,E8,42,BD), V(07,89,8B,88), V(E7,19,5B,38), V(79,C8,EE,DB), \
24516+ V(A1,7C,0A,47), V(7C,42,0F,E9), V(F8,84,1E,C9), V(00,00,00,00), \
24517+ V(09,80,86,83), V(32,2B,ED,48), V(1E,11,70,AC), V(6C,5A,72,4E), \
24518+ V(FD,0E,FF,FB), V(0F,85,38,56), V(3D,AE,D5,1E), V(36,2D,39,27), \
24519+ V(0A,0F,D9,64), V(68,5C,A6,21), V(9B,5B,54,D1), V(24,36,2E,3A), \
24520+ V(0C,0A,67,B1), V(93,57,E7,0F), V(B4,EE,96,D2), V(1B,9B,91,9E), \
24521+ V(80,C0,C5,4F), V(61,DC,20,A2), V(5A,77,4B,69), V(1C,12,1A,16), \
24522+ V(E2,93,BA,0A), V(C0,A0,2A,E5), V(3C,22,E0,43), V(12,1B,17,1D), \
24523+ V(0E,09,0D,0B), V(F2,8B,C7,AD), V(2D,B6,A8,B9), V(14,1E,A9,C8), \
24524+ V(57,F1,19,85), V(AF,75,07,4C), V(EE,99,DD,BB), V(A3,7F,60,FD), \
24525+ V(F7,01,26,9F), V(5C,72,F5,BC), V(44,66,3B,C5), V(5B,FB,7E,34), \
24526+ V(8B,43,29,76), V(CB,23,C6,DC), V(B6,ED,FC,68), V(B8,E4,F1,63), \
24527+ V(D7,31,DC,CA), V(42,63,85,10), V(13,97,22,40), V(84,C6,11,20), \
24528+ V(85,4A,24,7D), V(D2,BB,3D,F8), V(AE,F9,32,11), V(C7,29,A1,6D), \
24529+ V(1D,9E,2F,4B), V(DC,B2,30,F3), V(0D,86,52,EC), V(77,C1,E3,D0), \
24530+ V(2B,B3,16,6C), V(A9,70,B9,99), V(11,94,48,FA), V(47,E9,64,22), \
24531+ V(A8,FC,8C,C4), V(A0,F0,3F,1A), V(56,7D,2C,D8), V(22,33,90,EF), \
24532+ V(87,49,4E,C7), V(D9,38,D1,C1), V(8C,CA,A2,FE), V(98,D4,0B,36), \
24533+ V(A6,F5,81,CF), V(A5,7A,DE,28), V(DA,B7,8E,26), V(3F,AD,BF,A4), \
24534+ V(2C,3A,9D,E4), V(50,78,92,0D), V(6A,5F,CC,9B), V(54,7E,46,62), \
24535+ V(F6,8D,13,C2), V(90,D8,B8,E8), V(2E,39,F7,5E), V(82,C3,AF,F5), \
24536+ V(9F,5D,80,BE), V(69,D0,93,7C), V(6F,D5,2D,A9), V(CF,25,12,B3), \
24537+ V(C8,AC,99,3B), V(10,18,7D,A7), V(E8,9C,63,6E), V(DB,3B,BB,7B), \
24538+ V(CD,26,78,09), V(6E,59,18,F4), V(EC,9A,B7,01), V(83,4F,9A,A8), \
24539+ V(E6,95,6E,65), V(AA,FF,E6,7E), V(21,BC,CF,08), V(EF,15,E8,E6), \
24540+ V(BA,E7,9B,D9), V(4A,6F,36,CE), V(EA,9F,09,D4), V(29,B0,7C,D6), \
24541+ V(31,A4,B2,AF), V(2A,3F,23,31), V(C6,A5,94,30), V(35,A2,66,C0), \
24542+ V(74,4E,BC,37), V(FC,82,CA,A6), V(E0,90,D0,B0), V(33,A7,D8,15), \
24543+ V(F1,04,98,4A), V(41,EC,DA,F7), V(7F,CD,50,0E), V(17,91,F6,2F), \
24544+ V(76,4D,D6,8D), V(43,EF,B0,4D), V(CC,AA,4D,54), V(E4,96,04,DF), \
24545+ V(9E,D1,B5,E3), V(4C,6A,88,1B), V(C1,2C,1F,B8), V(46,65,51,7F), \
24546+ V(9D,5E,EA,04), V(01,8C,35,5D), V(FA,87,74,73), V(FB,0B,41,2E), \
24547+ V(B3,67,1D,5A), V(92,DB,D2,52), V(E9,10,56,33), V(6D,D6,47,13), \
24548+ V(9A,D7,61,8C), V(37,A1,0C,7A), V(59,F8,14,8E), V(EB,13,3C,89), \
24549+ V(CE,A9,27,EE), V(B7,61,C9,35), V(E1,1C,E5,ED), V(7A,47,B1,3C), \
24550+ V(9C,D2,DF,59), V(55,F2,73,3F), V(18,14,CE,79), V(73,C7,37,BF), \
24551+ V(53,F7,CD,EA), V(5F,FD,AA,5B), V(DF,3D,6F,14), V(78,44,DB,86), \
24552+ V(CA,AF,F3,81), V(B9,68,C4,3E), V(38,24,34,2C), V(C2,A3,40,5F), \
24553+ V(16,1D,C3,72), V(BC,E2,25,0C), V(28,3C,49,8B), V(FF,0D,95,41), \
24554+ V(39,A8,01,71), V(08,0C,B3,DE), V(D8,B4,E4,9C), V(64,56,C1,90), \
24555+ V(7B,CB,84,61), V(D5,32,B6,70), V(48,6C,5C,74), V(D0,B8,57,42)
24556+
24557+#define V(a,b,c,d) 0x##a##b##c##d
24558+static const uint32 RT0[256] = { RT };
24559+#undef V
24560+
24561+#define V(a,b,c,d) 0x##d##a##b##c
24562+static const uint32 RT1[256] = { RT };
24563+#undef V
24564+
24565+#define V(a,b,c,d) 0x##c##d##a##b
24566+static const uint32 RT2[256] = { RT };
24567+#undef V
24568+
24569+#define V(a,b,c,d) 0x##b##c##d##a
24570+static const uint32 RT3[256] = { RT };
24571+#undef V
24572+
24573+#undef RT
24574+
24575+/* round constants */
24576+
24577+static const uint32 RCON[10] =
24578+{
24579+ 0x01000000, 0x02000000, 0x04000000, 0x08000000,
24580+ 0x10000000, 0x20000000, 0x40000000, 0x80000000,
24581+ 0x1B000000, 0x36000000
24582+};
24583+
24584+int do_init = 0;
24585+
24586+void aes_gen_tables( void )
24587+{
24588+}
24589+
24590+#endif
24591+
24592+/* platform-independant 32-bit integer manipulation macros */
24593+
24594+#define GET_UINT32_aes(n,b,i) \
24595+{ \
24596+ (n) = ( (uint32) (b)[(i) ] << 24 ) \
24597+ | ( (uint32) (b)[(i) + 1] << 16 ) \
24598+ | ( (uint32) (b)[(i) + 2] << 8 ) \
24599+ | ( (uint32) (b)[(i) + 3] ); \
24600+}
24601+
24602+#define PUT_UINT32_aes(n,b,i) \
24603+{ \
24604+ (b)[(i) ] = (uint8) ( (n) >> 24 ); \
24605+ (b)[(i) + 1] = (uint8) ( (n) >> 16 ); \
24606+ (b)[(i) + 2] = (uint8) ( (n) >> 8 ); \
24607+ (b)[(i) + 3] = (uint8) ( (n) ); \
24608+}
24609+
24610+/* decryption key schedule tables */
24611+
24612+int KT_init = 1;
24613+
24614+uint32 KT0[256];
24615+uint32 KT1[256];
24616+uint32 KT2[256];
24617+uint32 KT3[256];
24618+
24619+/* AES key scheduling routine */
24620+int aes_set_key( aes_context *ctx, uint8 *key, int nbits )
24621+{
24622+ int i;
24623+ uint32 *RK, *SK;
24624+
24625+ if( do_init )
24626+ {
24627+ aes_gen_tables();
24628+
24629+ do_init = 0;
24630+ }
24631+
24632+ switch( nbits )
24633+ {
24634+ case 128: ctx->nr = 10; break;
24635+ case 192: ctx->nr = 12; break;
24636+ case 256: ctx->nr = 14; break;
24637+ default : return( 1 );
24638+ }
24639+
24640+ RK = ctx->erk;
24641+
24642+ for( i = 0; i < (nbits >> 5); i++ )
24643+ {
24644+ GET_UINT32_aes( RK[i], key, i * 4 );
24645+ }
24646+
24647+ /* setup encryption round keys */
24648+
24649+ switch( nbits )
24650+ {
24651+ case 128:
24652+
24653+ for( i = 0; i < 10; i++, RK += 4 )
24654+ {
24655+ RK[4] = RK[0] ^ RCON[i] ^
24656+ ( FSb[ (uint8) ( RK[3] >> 16 ) ] << 24 ) ^
24657+ ( FSb[ (uint8) ( RK[3] >> 8 ) ] << 16 ) ^
24658+ ( FSb[ (uint8) ( RK[3] ) ] << 8 ) ^
24659+ ( FSb[ (uint8) ( RK[3] >> 24 ) ] );
24660+
24661+ RK[5] = RK[1] ^ RK[4];
24662+ RK[6] = RK[2] ^ RK[5];
24663+ RK[7] = RK[3] ^ RK[6];
24664+ }
24665+ break;
24666+
24667+ case 192:
24668+
24669+ for( i = 0; i < 8; i++, RK += 6 )
24670+ {
24671+ RK[6] = RK[0] ^ RCON[i] ^
24672+ ( FSb[ (uint8) ( RK[5] >> 16 ) ] << 24 ) ^
24673+ ( FSb[ (uint8) ( RK[5] >> 8 ) ] << 16 ) ^
24674+ ( FSb[ (uint8) ( RK[5] ) ] << 8 ) ^
24675+ ( FSb[ (uint8) ( RK[5] >> 24 ) ] );
24676+
24677+ RK[7] = RK[1] ^ RK[6];
24678+ RK[8] = RK[2] ^ RK[7];
24679+ RK[9] = RK[3] ^ RK[8];
24680+ RK[10] = RK[4] ^ RK[9];
24681+ RK[11] = RK[5] ^ RK[10];
24682+ }
24683+ break;
24684+
24685+ case 256:
24686+
24687+ for( i = 0; i < 7; i++, RK += 8 )
24688+ {
24689+ RK[8] = RK[0] ^ RCON[i] ^
24690+ ( FSb[ (uint8) ( RK[7] >> 16 ) ] << 24 ) ^
24691+ ( FSb[ (uint8) ( RK[7] >> 8 ) ] << 16 ) ^
24692+ ( FSb[ (uint8) ( RK[7] ) ] << 8 ) ^
24693+ ( FSb[ (uint8) ( RK[7] >> 24 ) ] );
24694+
24695+ RK[9] = RK[1] ^ RK[8];
24696+ RK[10] = RK[2] ^ RK[9];
24697+ RK[11] = RK[3] ^ RK[10];
24698+
24699+ RK[12] = RK[4] ^
24700+ ( FSb[ (uint8) ( RK[11] >> 24 ) ] << 24 ) ^
24701+ ( FSb[ (uint8) ( RK[11] >> 16 ) ] << 16 ) ^
24702+ ( FSb[ (uint8) ( RK[11] >> 8 ) ] << 8 ) ^
24703+ ( FSb[ (uint8) ( RK[11] ) ] );
24704+
24705+ RK[13] = RK[5] ^ RK[12];
24706+ RK[14] = RK[6] ^ RK[13];
24707+ RK[15] = RK[7] ^ RK[14];
24708+ }
24709+ break;
24710+ }
24711+
24712+ /* setup decryption round keys */
24713+
24714+ if( KT_init )
24715+ {
24716+ for( i = 0; i < 256; i++ )
24717+ {
24718+ KT0[i] = RT0[ FSb[i] ];
24719+ KT1[i] = RT1[ FSb[i] ];
24720+ KT2[i] = RT2[ FSb[i] ];
24721+ KT3[i] = RT3[ FSb[i] ];
24722+ }
24723+
24724+ KT_init = 0;
24725+ }
24726+
24727+ SK = ctx->drk;
24728+
24729+ *SK++ = *RK++;
24730+ *SK++ = *RK++;
24731+ *SK++ = *RK++;
24732+ *SK++ = *RK++;
24733+
24734+ for( i = 1; i < ctx->nr; i++ )
24735+ {
24736+ RK -= 8;
24737+
24738+ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
24739+ KT1[ (uint8) ( *RK >> 16 ) ] ^
24740+ KT2[ (uint8) ( *RK >> 8 ) ] ^
24741+ KT3[ (uint8) ( *RK ) ]; RK++;
24742+
24743+ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
24744+ KT1[ (uint8) ( *RK >> 16 ) ] ^
24745+ KT2[ (uint8) ( *RK >> 8 ) ] ^
24746+ KT3[ (uint8) ( *RK ) ]; RK++;
24747+
24748+ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
24749+ KT1[ (uint8) ( *RK >> 16 ) ] ^
24750+ KT2[ (uint8) ( *RK >> 8 ) ] ^
24751+ KT3[ (uint8) ( *RK ) ]; RK++;
24752+
24753+ *SK++ = KT0[ (uint8) ( *RK >> 24 ) ] ^
24754+ KT1[ (uint8) ( *RK >> 16 ) ] ^
24755+ KT2[ (uint8) ( *RK >> 8 ) ] ^
24756+ KT3[ (uint8) ( *RK ) ]; RK++;
24757+ }
24758+
24759+ RK -= 8;
24760+
24761+ *SK++ = *RK++;
24762+ *SK++ = *RK++;
24763+ *SK++ = *RK++;
24764+ *SK++ = *RK++;
24765+
24766+ return( 0 );
24767+}
24768diff --git a/board/aspeed/ast2400/ast2400.c b/board/aspeed/ast2400/ast2400.c
24769new file mode 100644
24770index 0000000..65bccbe
24771--- /dev/null
24772+++ b/board/aspeed/ast2400/ast2400.c
24773@@ -0,0 +1,304 @@
24774+/*
24775+ * This program is distributed in the hope that it will be useful,
24776+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
24777+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24778+ * GNU General Public License for more details.
24779+ *
24780+ * You should have received a copy of the GNU General Public License
24781+ * along with this program; if not, write to the Free Software
24782+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24783+ */
24784+
24785+#include <common.h>
24786+#include <command.h>
24787+#include <pci.h>
24788+
24789+int board_init (void)
24790+{
24791+ DECLARE_GLOBAL_DATA_PTR;
24792+ unsigned char data;
24793+ unsigned long gpio;
24794+ unsigned long reg;
24795+
24796+ /* AHB Controller */
24797+ *((volatile ulong*) 0x1E600000) = 0xAEED1A03; /* unlock AHB controller */
24798+ *((volatile ulong*) 0x1E60008C) |= 0x01; /* map DRAM to 0x00000000 */
24799+
24800+ /* Flash Controller */
24801+#ifdef CONFIG_FLASH_AST2300
24802+ *((volatile ulong*) 0x1e620000) |= 0x800f0000; /* enable Flash Write */
24803+#else
24804+ *((volatile ulong*) 0x16000000) |= 0x00001c00; /* enable Flash Write */
24805+#endif
24806+
24807+ /* SCU */
24808+ *((volatile ulong*) 0x1e6e2000) = 0x1688A8A8; /* unlock SCU */
24809+ reg = *((volatile ulong*) 0x1e6e2008);
24810+ reg &= 0x1c0fffff;
24811+ reg |= 0x61800000; /* PCLK = HPLL/8 */
24812+#ifdef CONFIG_AST1070
24813+ //check lpc or lpc+ mode
24814+////////////////////////////////////////////////////////////////////////
24815+ gpio = *((volatile ulong*) 0x1e780070); /* mode check */
24816+ if(gpio & 0x2)
24817+ reg |= 0x100000; /* LHCLK = HPLL/4 */
24818+ else
24819+ reg |= 0x300000; /* LHCLK = HPLL/8 */
24820+
24821+ reg |= 0x80000; /* enable LPC Host Clock */
24822+
24823+ *((volatile ulong*) 0x1e6e2008) = reg;
24824+
24825+ reg = *((volatile ulong*) 0x1e6e200c); /* enable LPC clock */
24826+ *((volatile ulong*) 0x1e6e200c) &= ~(1 << 28);
24827+
24828+ if(gpio & 0x2) {
24829+
24830+ //use LPC+ for sys clk
24831+ // set OSCCLK = VPLL1
24832+ *((volatile ulong*) 0x1e6e2010) = 0x18;
24833+
24834+ // enable OSCCLK
24835+ reg = *((volatile ulong*) 0x1e6e202c);
24836+ reg |= 0x00000002;
24837+ *((volatile ulong*) 0x1e6e202c) = reg;
24838+ } else {
24839+ // USE LPC use D2 clk
24840+ /*set VPPL1 */
24841+ *((volatile ulong*) 0x1e6e201c) = 0x6420;
24842+
24843+ // set d2-pll & enable d2-pll D[21:20], D[4]
24844+ reg = *((volatile ulong*) 0x1e6e202c);
24845+ reg &= 0xffcfffef;
24846+ reg |= 0x00200010;
24847+ *((volatile ulong*) 0x1e6e202c) = reg;
24848+
24849+ // set OSCCLK = VPLL1
24850+ *((volatile ulong*) 0x1e6e2010) = 0x8;
24851+
24852+ // enable OSCCLK
24853+ reg = *((volatile ulong*) 0x1e6e202c);
24854+ reg &= 0xfffffffd;
24855+ reg |= 0x00000002;
24856+ *((volatile ulong*) 0x1e6e202c) = reg;
24857+ }
24858+#else
24859+ *((volatile ulong*) 0x1e6e2008) = reg;
24860+#endif
24861+ reg = *((volatile ulong*) 0x1e6e200c); /* enable 2D Clk */
24862+ *((volatile ulong*) 0x1e6e200c) &= 0xFFFFFFFD;
24863+/* enable wide screen. If your video driver does not support wide screen, don't
24864+enable this bit 0x1e6e2040 D[0]*/
24865+ reg = *((volatile ulong*) 0x1e6e2040);
24866+ *((volatile ulong*) 0x1e6e2040) |= 0x01;
24867+
24868+ /* arch number */
24869+ gd->bd->bi_arch_number = MACH_TYPE_ASPEED;
24870+
24871+ /* adress of boot parameters */
24872+ gd->bd->bi_boot_params = 0x40000100;
24873+
24874+ return 0;
24875+}
24876+
24877+int dram_init (void)
24878+{
24879+ DECLARE_GLOBAL_DATA_PTR;
24880+
24881+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
24882+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
24883+
24884+ return 0;
24885+}
24886+
24887+/*
24888+SCU7C: Silicon Revision ID Register
24889+D[31:24]: Chip ID
24890+0: AST2050/AST2100/AST2150/AST2200/AST3000
24891+1: AST2300
24892+
24893+D[23:16] Silicon revision ID for AST2300 generation and later
24894+0: A0
24895+1: A1
24896+2: A2
24897+.
24898+.
24899+.
24900+FPGA revision starts from 0x80
24901+
24902+
24903+D[11:8] Bounding option
24904+
24905+D[7:0] Silicon revision ID for AST2050/AST2100 generation (for software compatible)
24906+0: A0
24907+1: A1
24908+2: A2
24909+3: A3
24910+.
24911+.
24912+FPGA revision starts from 0x08, 8~10 means A0, 11+ means A1, AST2300 should be assigned to 3
24913+*/
24914+int wait_calibration_done()
24915+{
24916+ DECLARE_GLOBAL_DATA_PTR;
24917+ unsigned char data;
24918+ unsigned long reg, count = 0;
24919+
24920+ do {
24921+ udelay(1000);
24922+ count++;
24923+ if (count >= 1000) {
24924+
24925+ return 1;
24926+ }
24927+ } while ((*(volatile ulong*) 0x1e6ec000) & 0xf00);
24928+
24929+// printf ("count = %d\n", count);
24930+
24931+ return 0;
24932+}
24933+
24934+/* AST1070 Calibration
24935+Program 0x101 to 0x1e6ec000
24936+Wait till 1e6ec000 [8] = 0
24937+Check 0x1e6ec004 = 0x5a5a5a5a
24938+*/
24939+int ast1070_calibration()
24940+{
24941+ DECLARE_GLOBAL_DATA_PTR;
24942+ unsigned char data;
24943+ unsigned long reg, i, j;
24944+
24945+ //only for 2 chip
24946+ for (i = 0; i < 2; i++) {
24947+ for (j = 0; j < 4; j++) {
24948+// printf ("chip = %d, delay = %d\n", i, j);
24949+ *((volatile ulong*) 0x1e6ec000) = (j << (12 + i * 2)) + (1 << (8 + i)) + 0x01;
24950+// printf ("1e6ec000 = %x\n", *(volatile ulong*)0x1e6ec000);
24951+ if (!wait_calibration_done()) {
24952+ if ((*(volatile ulong*) 0x1e6ec004) == 0x5a5a5a5a) {
24953+// printf ("calibration result: chip %d pass, timing = %d\n", i, j);
24954+ break;
24955+ }
24956+ else {
24957+// printf ("calibration result: chip %d fail, timing = %d\n", i, j);
24958+ }
24959+ }
24960+ }
24961+ }
24962+
24963+ return 0;
24964+}
24965+
24966+int misc_init_r(void)
24967+{
24968+ unsigned int reg, reg1, revision, chip_id, lpc_plus;
24969+
24970+#ifdef CONFIG_AST1070
24971+ //Reset AST1070 and AST2400 engine [bit 23:15]
24972+ reg = *((volatile ulong*) 0x1e7890a0);
24973+ reg &= ~0x808000;
24974+ *((volatile ulong*) 0x1e7890a0) = reg;
24975+
24976+ udelay(5000);
24977+
24978+ lpc_plus = (*((volatile ulong*) 0x1e780070)) & 0x2;
24979+
24980+ reg = *((volatile ulong*) 0x1e7890a0);
24981+ reg |= 0x800000;
24982+ *((volatile ulong*) 0x1e7890a0) = reg;
24983+
24984+ udelay(1000);
24985+
24986+ reg = *((volatile ulong*) 0x1e7890a0);
24987+ reg |= 0x008000;
24988+ *((volatile ulong*) 0x1e7890a0) = reg;
24989+
24990+
24991+ if(lpc_plus) {
24992+ *((volatile ulong*) 0x1E60008C) |= 0x011; /* map DRAM to 0x00000000 and LPC+ 0x70000000*/
24993+
24994+ //SCU multi-Function pin
24995+ reg = *((volatile ulong*) 0x1e6e2090);
24996+ reg |= (1 << 30);
24997+ *((volatile ulong*) 0x1e6e2090) = reg;
24998+ //LPC+ Engine Enable
24999+ reg = *((volatile ulong*) 0x1e6ec000);
25000+ reg |= 1;
25001+ *((volatile ulong*) 0x1e6ec000) = reg;
25002+
25003+ ast1070_calibration();
25004+
25005+ } else {
25006+ // enable AST1050's LPC master
25007+ reg = *((volatile ulong*) 0x1e7890a0);
25008+ *((volatile ulong*) 0x1e7890a0) |= 0x11;
25009+
25010+ }
25011+
25012+#endif
25013+ /* Show H/W Version */
25014+ reg1 = (unsigned int) (*((ulong*) 0x1e6e207c));
25015+ chip_id = (reg1 & 0xff000000) >> 24;
25016+ revision = (reg1 & 0xff0000) >> 16;
25017+
25018+ puts ("H/W: ");
25019+ if (chip_id == 1) {
25020+ if (revision >= 0x80) {
25021+ printf("AST2300 series FPGA Rev. %02x \n", revision);
25022+ }
25023+ else {
25024+ printf("AST2300 series chip Rev. %02x \n", revision);
25025+ }
25026+ }
25027+ else if (chip_id == 2) {
25028+ printf("AST2400 series chip Rev. %02x \n", revision);
25029+ }
25030+ else if (chip_id == 0) {
25031+ printf("AST2050/AST2150 series chip\n");
25032+ }
25033+
25034+#ifdef CONFIG_AST1070
25035+ if(lpc_plus) {
25036+ puts ("C/C: LPC+ :");
25037+ revision = (unsigned int) (*((ulong*) 0x70002034));
25038+ printf("AST1070 ID [%08x] ", revision);
25039+
25040+ if((*((volatile ulong*) 0x1e780070)) & 0x4) {
25041+ if((unsigned int) (*((ulong*) 0x70012034)) == 0x10700001)
25042+ printf(", 2nd : AST1070 ID [%08x] \n", (unsigned int) (*((ulong*) 0x70012034)));
25043+ else
25044+ printf("\n");
25045+ } else {
25046+ printf("\n");
25047+ }
25048+ } else {
25049+ puts ("C/C: LPC :");
25050+ revision = (unsigned int) (*((ulong*) 0x60002034));
25051+ printf("LPC : AST1070 ID [%08x] \n", revision);
25052+
25053+ }
25054+#endif
25055+
25056+#ifdef CONFIG_PCI
25057+ pci_init ();
25058+#endif
25059+
25060+ if (getenv ("verify") == NULL) {
25061+ setenv ("verify", "n");
25062+ }
25063+ if (getenv ("eeprom") == NULL) {
25064+ setenv ("eeprom", "y");
25065+ }
25066+}
25067+
25068+#ifdef CONFIG_PCI
25069+static struct pci_controller hose;
25070+
25071+extern void aspeed_init_pci (struct pci_controller *hose);
25072+
25073+void pci_init_board(void)
25074+{
25075+ aspeed_init_pci(&hose);
25076+}
25077+#endif
25078diff --git a/board/aspeed/ast2400/config.mk b/board/aspeed/ast2400/config.mk
25079new file mode 100755
25080index 0000000..24ca09b
25081--- /dev/null
25082+++ b/board/aspeed/ast2400/config.mk
25083@@ -0,0 +1,18 @@
25084+# This program is distributed in the hope that it will be useful,
25085+# but WITHOUT ANY WARRANTY; without even the implied warranty of
25086+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25087+# GNU General Public License for more details.
25088+#
25089+# You should have received a copy of the GNU General Public License
25090+# along with this program; if not, write to the Free Software
25091+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25092+# MA 02111-1307 USA
25093+#
25094+
25095+# ROM version
25096+#TEXT_BASE = 0xBFC00000
25097+
25098+# RAM version
25099+TEXT_BASE = 0x40500000
25100+#TEXT_BASE = 0x00000000
25101+#TEXT_BASE = 0x00400000
25102diff --git a/board/aspeed/ast2400/crc32.c b/board/aspeed/ast2400/crc32.c
25103new file mode 100755
25104index 0000000..cc8d2ac
25105--- /dev/null
25106+++ b/board/aspeed/ast2400/crc32.c
25107@@ -0,0 +1,127 @@
25108+/*
25109+ * This program is distributed in the hope that it will be useful,
25110+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
25111+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25112+ * GNU General Public License for more details.
25113+ *
25114+ * You should have received a copy of the GNU General Public License
25115+ * along with this program; if not, write to the Free Software
25116+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25117+ */
25118+#include <common.h>
25119+#include <asm/processor.h>
25120+#include <asm/byteorder.h>
25121+#include <environment.h>
25122+
25123+#ifdef CONFIG_2SPIFLASH
25124+
25125+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
25126+
25127+/* ========================================================================
25128+ * Table of CRC-32's of all single-byte values (made by make_aspeed_crc_table)
25129+ */
25130+unsigned long aspeed_crc_table[256] = {
25131+ 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
25132+ 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
25133+ 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
25134+ 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
25135+ 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
25136+ 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
25137+ 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
25138+ 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
25139+ 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
25140+ 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
25141+ 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
25142+ 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
25143+ 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
25144+ 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
25145+ 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
25146+ 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
25147+ 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
25148+ 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
25149+ 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
25150+ 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
25151+ 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
25152+ 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
25153+ 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
25154+ 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
25155+ 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
25156+ 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
25157+ 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
25158+ 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
25159+ 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
25160+ 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
25161+ 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
25162+ 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
25163+ 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
25164+ 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
25165+ 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
25166+ 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
25167+ 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
25168+ 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
25169+ 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
25170+ 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
25171+ 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
25172+ 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
25173+ 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
25174+ 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
25175+ 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
25176+ 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
25177+ 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
25178+ 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
25179+ 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
25180+ 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
25181+ 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
25182+ 0x2d02ef8dL
25183+};
25184+
25185+/* ========================================================================= */
25186+#define ASPEED_DO1(buf) crc = aspeed_crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
25187+#define ASPEED_DO2(buf) ASPEED_DO1(buf); ASPEED_DO1(buf);
25188+#define ASPEED_DO4(buf) ASPEED_DO2(buf); ASPEED_DO2(buf);
25189+#define ASPEED_DO8(buf) ASPEED_DO4(buf); ASPEED_DO4(buf);
25190+
25191+/* ========================================================================= */
25192+unsigned long spi2_crc32(crc, buf, len)
25193+ unsigned long crc;
25194+ unsigned char *buf;
25195+ unsigned long len;
25196+{
25197+
25198+ size_t len1, len2;
25199+ char *s;
25200+
25201+ len1 = len2 = 0;
25202+ if ( (ulong)(buf) <= (flash_info[0].start[0] + flash_info[0].size) )
25203+ len1 = (flash_info[0].start[0] + flash_info[0].size) - (ulong)(buf);
25204+
25205+ len1 = (len < len1) ? len:len1;
25206+ len2 = (len < len1) ? 0: (len - len1);
25207+
25208+ crc = crc ^ 0xffffffffL;
25209+ while (len1 >= 8)
25210+ {
25211+ ASPEED_DO8(buf);
25212+ len1 -= 8;
25213+ }
25214+ if (len1) do {
25215+ ASPEED_DO1(buf);
25216+ } while (--len1);
25217+
25218+ //s = (char *) flash_info[1].start[0];
25219+ s= (char *) flash_make_addr (&flash_info[1], 0, 0);
25220+ while (len2 >= 8)
25221+ {
25222+ ASPEED_DO8(s);
25223+ len2 -= 8;
25224+ }
25225+ if (len2) do {
25226+ ASPEED_DO1(s);
25227+ } while (--len2);
25228+
25229+ return crc ^ 0xffffffffL;
25230+
25231+}
25232+
25233+#endif /* CONFIG_2SPIFLASH */
25234+
25235diff --git a/board/aspeed/ast2400/crt.c b/board/aspeed/ast2400/crt.c
25236new file mode 100755
25237index 0000000..b67f669
25238--- /dev/null
25239+++ b/board/aspeed/ast2400/crt.c
25240@@ -0,0 +1,322 @@
25241+/*
25242+ * This program is distributed in the hope that it will be useful,
25243+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
25244+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25245+ * GNU General Public License for more details.
25246+ *
25247+ * You should have received a copy of the GNU General Public License
25248+ * along with this program; if not, write to the Free Software
25249+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25250+ */
25251+#include <common.h>
25252+#include <command.h>
25253+
25254+#include "type.h"
25255+#include "vesa.h"
25256+#include "vdef.h"
25257+#include "vfun.h"
25258+#include "vreg.h"
25259+#include "crt.h"
25260+
25261+ULONG AST3000DCLKTableV [] = {
25262+ 0x00046515, /* 00: VCLK25_175 */
25263+ 0x00047255, /* 01: VCLK28_322 */
25264+ 0x0004682a, /* 02: VCLK31_5 */
25265+ 0x0004672a, /* 03: VCLK36 */
25266+ 0x00046c50, /* 04: VCLK40 */
25267+ 0x00046842, /* 05: VCLK49_5 */
25268+ 0x00006c32, /* 06: VCLK50 */
25269+ 0x00006a2f, /* 07: VCLK56_25 */
25270+ 0x00006c41, /* 08: VCLK65 */
25271+ 0x00006832, /* 09: VCLK75 */
25272+ 0x0000672e, /* 0A: VCLK78_75 */
25273+ 0x0000683f, /* 0B: VCLK94_5 */
25274+ 0x00004824, /* 0C: VCLK108 */
25275+ 0x00004723, /* 0D: VCLK119 */
25276+ 0x0000482d, /* 0E: VCLK135 */
25277+ 0x00004B37, /* 0F: VCLK146_25 */
25278+ 0x0000472e, /* 10: VCLK157_5 */
25279+ 0x00004836, /* 11: VCLK162 */
25280+
25281+};
25282+
25283+BOOL CheckDAC(int nCRTIndex)
25284+{
25285+ BYTE btValue;
25286+ BOOL bValue;
25287+
25288+ BYTE btDeviceSelect;
25289+
25290+ switch (nCRTIndex)
25291+ {
25292+ case CRT_1:
25293+ btDeviceSelect = DEVICE_ADDRESS_CH7301_CRT1;
25294+ break;
25295+ case CRT_2:
25296+ btDeviceSelect = DEVICE_ADDRESS_CH7301_CRT2;
25297+ break;
25298+ default:
25299+ printf("CRTIndex is not 1 or 2");
25300+ return FALSE;
25301+ break;
25302+ }
25303+
25304+ //Enable all DAC's and set register 21h[0] = '0'
25305+ //DVIP and DVIL disable for DAC
25306+ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_PM_REG, 0x00);
25307+
25308+ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_DC_REG);
25309+ btValue = btValue & 0xFE;
25310+ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_DC_REG, btValue);
25311+
25312+ //Set SENSE bit to 1
25313+ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG);
25314+ btValue = btValue | 0x01;
25315+ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG, btValue);
25316+
25317+ //Reset SENSE bit to 0
25318+ btValue = GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG);
25319+ btValue = btValue & 0xFE;
25320+ SetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG, btValue);
25321+
25322+ bValue = (GetI2CRegClient(0, DEVICE_SELECT_CH7301, btDeviceSelect, CH7301_CD_REG) & CD_DACT) ? TRUE : FALSE;
25323+
25324+ return bValue;
25325+}
25326+
25327+VOID SetCH7301C(ULONG MMIOBase,
25328+ int nCRTIndex,
25329+ int inFreqRange,
25330+ int inOperating)
25331+{
25332+ BYTE btDeviceSelect;
25333+ BYTE btValue;
25334+
25335+//#ifdef EVB_CLIENT
25336+ //output RGB doesn't need to set CH7301
25337+ //if (1 == inOperating)
25338+ // return;
25339+//#endif
25340+
25341+ switch (nCRTIndex)
25342+ {
25343+ case CRT_1:
25344+ btDeviceSelect = 0xEA;
25345+
25346+ break;
25347+ case CRT_2:
25348+ btDeviceSelect = 0xEC;
25349+
25350+ break;
25351+ default:
25352+ printf("CRTIndex is not 1 or 2");
25353+ return;
25354+ break;
25355+ }
25356+
25357+ if (inFreqRange <= VCLK65)
25358+ {
25359+ printf("ch7301: low f \n");
25360+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x33, 0x08);
25361+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x34, 0x16);
25362+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x36, 0x60);
25363+ }
25364+ else
25365+ {
25366+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x33, 0x06);
25367+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x34, 0x26);
25368+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x36, 0xA0);
25369+ }
25370+
25371+ switch (inOperating)
25372+ {
25373+ case 0:
25374+ //DVI is normal function
25375+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x49, 0xC0);
25376+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1D, 0x47);
25377+ break;
25378+ case 1:
25379+ //RGB
25380+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x48, 0x18);
25381+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x49, 0x0);
25382+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x56, 0x0);
25383+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x21, 0x9);
25384+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1D, 0x48);
25385+ SetI2CRegClient(MMIOBase, 0x3, btDeviceSelect, 0x1C, 0x00);
25386+ break;
25387+ default:
25388+ break;
25389+ };
25390+}
25391+
25392+void SetASTModeTiming (ULONG MMIOBase, int nCRTIndex, BYTE ModeIndex, BYTE ColorDepth)
25393+{
25394+ ULONG temp, RetraceStart, RetraceEnd, DisplayOffset, TerminalCount, bpp;
25395+
25396+// Access CRT Engine
25397+ // SetPolarity
25398+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, ((vModeTable[ModeIndex].HorPolarity << HOR_SYNC_SELECT_BIT) | (vModeTable[ModeIndex].VerPolarity << VER_SYNC_SELECT_BIT)), (HOR_SYNC_SELECT_MASK|VER_SYNC_SELECT_MASK));
25399+
25400+#if CONFIG_AST3000
25401+ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0xc0);
25402+#else
25403+ //2100 is single edge
25404+ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0x80);
25405+#endif
25406+ // Horizontal Timing
25407+ temp = 0;
25408+ temp = ((vModeTable[ModeIndex].HorizontalActive - 1) << HOR_ENABLE_END_BIT) | ((vModeTable[ModeIndex].HorizontalTotal - 1) << HOR_TOTAL_BIT);
25409+ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_TOTAL_END_REG + nCRTIndex*0x60, temp);
25410+
25411+ RetraceStart = vModeTable[ModeIndex].HorizontalTotal - vModeTable[ModeIndex].HBackPorch - vModeTable[ModeIndex].HSyncTime - vModeTable[ModeIndex].HLeftBorder - 1;
25412+ RetraceEnd = (RetraceStart + vModeTable[ModeIndex].HSyncTime);
25413+ temp = 0;
25414+ temp = (RetraceEnd << HOR_RETRACE_END_BIT) | (RetraceStart << HOR_RETRACE_START_BIT);
25415+ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_RETRACE_REG + nCRTIndex*0x60, temp);
25416+
25417+ // Vertical Timing
25418+ temp = 0;
25419+ temp = ((vModeTable[ModeIndex].VerticalActive - 1) << VER_ENABLE_END_BIT) | ((vModeTable[ModeIndex].VerticalTotal - 1) << VER_TOTAL_BIT);
25420+ WriteMemoryLongClient(SCU_BASE, CRT1_VER_TOTAL_END_REG + nCRTIndex*0x60, temp);
25421+
25422+ temp = 0;
25423+ RetraceStart = vModeTable[ModeIndex].VerticalTotal - vModeTable[ModeIndex].VBackPorch - vModeTable[ModeIndex].VSyncTime - vModeTable[ModeIndex].VTopBorder - 1;
25424+ RetraceEnd = (RetraceStart + vModeTable[ModeIndex].VSyncTime);
25425+ temp = (RetraceEnd << VER_RETRACE_END_BIT) | (RetraceStart << VER_RETRACE_START_BIT);
25426+ WriteMemoryLongClient(SCU_BASE, CRT1_VER_RETRACE_REG + nCRTIndex*0x60, temp);
25427+
25428+ // Set CRT Display Offset and Terminal Count
25429+ if (ColorDepth == RGB_565) {
25430+ bpp = 16;
25431+ }
25432+ else {
25433+ bpp = 32;
25434+ }
25435+
25436+ DisplayOffset = vModeTable[ModeIndex].HorizontalActive * bpp / 8;
25437+ TerminalCount = vModeTable[ModeIndex].HorizontalActive * bpp / 64;
25438+ if (ColorDepth == YUV_444) {
25439+ TerminalCount = TerminalCount * 3 / 4;
25440+ }
25441+ if (((vModeTable[ModeIndex].HorizontalActive * bpp) % 64) != 0) {
25442+ TerminalCount++;
25443+ }
25444+
25445+ WriteMemoryLongClient(SCU_BASE, CRT1_DISPLAY_OFFSET + nCRTIndex*0x60, ((TerminalCount << TERMINAL_COUNT_BIT) | DisplayOffset));
25446+
25447+ // Set Color Format
25448+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (ColorDepth << FORMAT_SELECT_BIT), FORMAT_SELECT_MASK);
25449+
25450+ // Set Threshold
25451+ temp = 0;
25452+ temp = (CRT_HIGH_THRESHOLD_VALUE << THRES_HIGHT_BIT) | (CRT_LOW_THRESHOLD_VALUE << THRES_LOW_BIT);
25453+ WriteMemoryLongClient(SCU_BASE, CRT1_THRESHOLD_REG + nCRTIndex*0x60, temp);
25454+
25455+ WriteMemoryLongClient(SCU_BASE, CRT1_VIDEO_PLL_REG + nCRTIndex*0x60, AST3000DCLKTableV[vModeTable[ModeIndex].PixelClock]);
25456+}
25457+
25458+void SetASTCenter1024ModeTiming (ULONG MMIOBase, int nCRTIndex, BYTE ModeIndex, BYTE ColorDepth)
25459+{
25460+ ULONG temp, RetraceStart, RetraceEnd, DisplayOffset, TerminalCount, bpp;
25461+
25462+ // Access CRT Engine
25463+ // SetPolarity
25464+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (HOR_NEGATIVE << HOR_SYNC_SELECT_BIT) | (VER_NEGATIVE << VER_SYNC_SELECT_BIT), HOR_SYNC_SELECT_MASK|VER_SYNC_SELECT_MASK);
25465+
25466+ WriteMemoryLongClient(SCU_BASE, CRT1_CONTROL2_REG + nCRTIndex*0x60, 0xC0);
25467+
25468+ // Horizontal Timing
25469+ temp = 0;
25470+ temp = ((vModeTable[ModeIndex].HorizontalActive - 1) << HOR_ENABLE_END_BIT) | ((vModeTable[10].HorizontalTotal - 1) << HOR_TOTAL_BIT);
25471+ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_TOTAL_END_REG + nCRTIndex*0x60, temp);
25472+
25473+ RetraceStart = vModeTable[10].HorizontalTotal - vModeTable[10].HBackPorch - vModeTable[10].HSyncTime - vModeTable[10].HLeftBorder - 1;
25474+ RetraceStart = RetraceStart - (vModeTable[10].HorizontalActive - vModeTable[ModeIndex].HorizontalActive) / 2 - 1;
25475+ RetraceEnd = (RetraceStart + vModeTable[10].HSyncTime);
25476+ temp = 0;
25477+ temp = (RetraceEnd << HOR_RETRACE_END_BIT) | (RetraceStart << HOR_RETRACE_START_BIT);
25478+ WriteMemoryLongClient(SCU_BASE, CRT1_HOR_RETRACE_REG + nCRTIndex*0x60, temp);
25479+
25480+ // Vertical Timing
25481+ temp = 0;
25482+ temp = ((vModeTable[ModeIndex].VerticalActive - 1) << VER_ENABLE_END_BIT) | ((vModeTable[10].VerticalTotal - 1) << VER_TOTAL_BIT);
25483+ WriteMemoryLongClient(SCU_BASE, CRT1_VER_TOTAL_END_REG + nCRTIndex*0x60, temp);
25484+
25485+ RetraceStart = vModeTable[10].VerticalTotal - vModeTable[10].VBackPorch - vModeTable[10].VSyncTime - vModeTable[10].VTopBorder - 1;
25486+ RetraceStart = RetraceStart - (vModeTable[10].VerticalActive - vModeTable[ModeIndex].VerticalActive) / 2 - 1;
25487+ RetraceEnd = (RetraceStart + vModeTable[10].VSyncTime);
25488+ temp = (RetraceEnd << VER_RETRACE_END_BIT) | (RetraceStart << VER_RETRACE_START_BIT);
25489+ WriteMemoryLongClient(SCU_BASE, CRT1_VER_RETRACE_REG + nCRTIndex*0x60, temp);
25490+
25491+ // Set CRT Display Offset and Terminal Count
25492+ if (ColorDepth == RGB_565) {
25493+ bpp = 16;
25494+ }
25495+ else {
25496+ bpp = 32;
25497+ }
25498+ DisplayOffset = vModeTable[ModeIndex].HorizontalActive * bpp / 8;
25499+ TerminalCount = vModeTable[ModeIndex].HorizontalActive * bpp / 64;
25500+ if (ColorDepth == YUV_444) {
25501+ TerminalCount = TerminalCount * 3 / 4;
25502+ }
25503+ if (((vModeTable[ModeIndex].HorizontalActive * bpp) % 64) != 0) {
25504+ TerminalCount++;
25505+ }
25506+
25507+ WriteMemoryLongClient(SCU_BASE, CRT1_DISPLAY_OFFSET + nCRTIndex*0x60, (TerminalCount << TERMINAL_COUNT_BIT) | DisplayOffset);
25508+
25509+ // Set Color Format
25510+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + nCRTIndex*0x60, (ColorDepth << FORMAT_SELECT_BIT), FORMAT_SELECT_MASK);
25511+
25512+ // Set Threshold
25513+ temp = 0;
25514+ temp = (CRT_HIGH_THRESHOLD_VALUE << THRES_HIGHT_BIT) | (CRT_LOW_THRESHOLD_VALUE << THRES_LOW_BIT);
25515+ WriteMemoryLongClient(SCU_BASE, CRT1_THRESHOLD_REG + nCRTIndex*0x60, temp);
25516+
25517+ // Set DCLK
25518+ WriteMemoryLongClient(SCU_BASE, CRT1_VIDEO_PLL_REG + nCRTIndex*0x60, AST3000DCLKTableV[vModeTable[ModeIndex].PixelClock]);
25519+
25520+}
25521+
25522+BOOL ASTSetModeV (ULONG MMIOBase, int nCRTIndex, ULONG VGABaseAddr, USHORT Horizontal, USHORT Vertical, BYTE ColorFormat, BYTE CenterMode)
25523+{
25524+ BYTE i, ModeIndex;
25525+ BOOL bDAC;
25526+ ULONG ulTemp;
25527+
25528+ // Access CRT Engine
25529+ //Enable CRT1 graph
25530+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_CONTROL_REG + 0x60*nCRTIndex, GRAPH_DISPLAY_ON, GRAPH_DISPLAY_MASK);
25531+
25532+ // Set CRT Display Start Address
25533+ WriteMemoryLongWithMASKClient(SCU_BASE, CRT1_DISPLAY_ADDRESS + 0x60*nCRTIndex, VGABaseAddr, DISPLAY_ADDRESS_MASK);
25534+
25535+ for (i = 0; i < Mode60HZCount; i++) {
25536+ if ((vModeTable[i].HorizontalActive == Horizontal) && (vModeTable[i].VerticalActive == Vertical)) {
25537+
25538+ ModeIndex = i;
25539+
25540+ if (CenterMode != 1) {
25541+ SetASTModeTiming(MMIOBase, nCRTIndex, i, ColorFormat);
25542+ }
25543+ else {
25544+ SetASTCenter1024ModeTiming (MMIOBase, nCRTIndex, i, ColorFormat);
25545+ }
25546+
25547+ //use internal video out sigal and don't need use 7301
25548+ /*
25549+ bDAC = CheckDAC(nCRTIndex);
25550+
25551+ SetCH7301C(0,
25552+ nCRTIndex,
25553+ vModeTable[ModeIndex].PixelClock,
25554+ bDAC); //For RGB
25555+ */
25556+ return TRUE;
25557+ }
25558+ }
25559+
25560+ return FALSE;
25561+}
25562+
25563diff --git a/board/aspeed/ast2400/crt.h b/board/aspeed/ast2400/crt.h
25564new file mode 100755
25565index 0000000..e7483be
25566--- /dev/null
25567+++ b/board/aspeed/ast2400/crt.h
25568@@ -0,0 +1,121 @@
25569+/*
25570+ * This program is distributed in the hope that it will be useful,
25571+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
25572+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25573+ * GNU General Public License for more details.
25574+ *
25575+ * You should have received a copy of the GNU General Public License
25576+ * along with this program; if not, write to the Free Software
25577+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25578+ */
25579+#ifndef _CRT_H_
25580+#define _CRT_H_
25581+
25582+#ifdef Watcom
25583+#define CRT_REMAP_OFFSET 0x10000
25584+#else
25585+#define CRT_REMAP_OFFSET 0x0
25586+#endif
25587+
25588+/********************************************************/
25589+/* CRT register */
25590+/********************************************************/
25591+#define CRT_BASE_OFFSET 0x6000+CRT_REMAP_OFFSET
25592+
25593+#define CRT1_CONTROL_REG 0x00 + CRT_BASE_OFFSET
25594+ #define GRAPH_DISPLAY_BIT 0
25595+ #define GRAPH_DISPLAY_MASK (1<<0)
25596+ #define GRAPH_DISPLAY_ON 1
25597+ #define GRAPH_DISPLAY_OFF 0
25598+ #define FORMAT_SELECT_BIT 8
25599+ #define FORMAT_SELECT_MASK (3<<8)
25600+ #define HOR_SYNC_SELECT_BIT 16
25601+ #define HOR_SYNC_SELECT_MASK (1<<16)
25602+ #define HOR_NEGATIVE 1
25603+ #define HOR_POSITIVE 0
25604+ #define VER_SYNC_SELECT_BIT 17
25605+ #define VER_SYNC_SELECT_MASK (1<<17)
25606+ #define VER_NEGATIVE 1
25607+ #define VER_POSITIVE 0
25608+
25609+#define CRT1_CONTROL2_REG 0x04 + CRT_BASE_OFFSET
25610+
25611+#define CRT1_VIDEO_PLL_REG 0x0C + CRT_BASE_OFFSET
25612+ #define POST_DIV_BIT 18
25613+ #define POST_DIV_MASK 3<<18
25614+ #define DIV_1_1 0
25615+ //#define DIV_1_2 1
25616+ #define DIV_1_2 2
25617+ #define DIV_1_4 3
25618+
25619+#define CRT1_HOR_TOTAL_END_REG 0x10 + CRT_BASE_OFFSET
25620+ #define HOR_TOTAL_BIT 0
25621+ #define HOR_ENABLE_END_BIT 16
25622+
25623+#define CRT1_HOR_RETRACE_REG 0x14 + CRT_BASE_OFFSET
25624+ #define HOR_RETRACE_START_BIT 0
25625+ #define HOR_RETRACE_END_BIT 16
25626+
25627+#define CRT1_VER_TOTAL_END_REG 0x18 + CRT_BASE_OFFSET
25628+ #define VER_TOTAL_BIT 0
25629+ #define VER_ENABLE_END_BIT 16
25630+
25631+#define CRT1_VER_RETRACE_REG 0x1C + CRT_BASE_OFFSET
25632+ #define VER_RETRACE_START_BIT 0
25633+ #define VER_RETRACE_END_BIT 16
25634+
25635+#define CRT1_DISPLAY_ADDRESS 0x20 + CRT_BASE_OFFSET
25636+ #define DISPLAY_ADDRESS_MASK 0x0FFFFFFF
25637+
25638+#define CRT1_DISPLAY_OFFSET 0x24 + CRT_BASE_OFFSET
25639+ #define DISPLAY_OFFSET_ALIGN 7 /* 8 byte alignment*/
25640+ #define TERMINAL_COUNT_BIT 16
25641+
25642+#define CRT1_THRESHOLD_REG 0x28 + CRT_BASE_OFFSET
25643+ #define THRES_LOW_BIT 0
25644+ #define THRES_HIGHT_BIT 8
25645+
25646+#define CURSOR_POSITION 0x30 + OFFSET
25647+#define CURSOR_OFFSET 0x34 + OFFSET
25648+#define CURSOR_PATTERN 0x38 + OFFSET
25649+#define OSD_HORIZONTAL 0x40 + OFFSET
25650+#define OSD_VERTICAL 0x44 + OFFSET
25651+#define OSD_PATTERN 0x48 + OFFSET
25652+#define OSD_OFFSET 0x4C + OFFSET
25653+#define OSD_THRESHOLD 0x50 + OFFSET
25654+
25655+//Ch7301c
25656+#define DEVICE_ADDRESS_CH7301_CRT1 0xEA
25657+#define DEVICE_ADDRESS_CH7301_CRT2 0xEC
25658+
25659+
25660+#define DEVICE_SELECT_CH7301 0x3
25661+
25662+/* CH7301 Register Definition */
25663+#define CH7301_CD_REG 0x20
25664+ #define CD_DACT 0x0E
25665+ #define CD_DVIT 1 << 5
25666+#define CH7301_DC_REG 0x21
25667+#define CH7301_PM_REG 0x49
25668+
25669+BOOL CheckHotPlug(int nCRTIndex);
25670+BOOL CheckDAC(int nCRTIndex);
25671+
25672+BOOL ASTSetModeV (ULONG MMIOBase,
25673+ int nCRTIndex,
25674+ ULONG VGABaseAddr,
25675+ USHORT Horizontal,
25676+ USHORT Vertical,
25677+ BYTE ColorFormat,
25678+ BYTE CenterMode);
25679+
25680+BOOL SelCRTClock(ULONG MMIOBase,
25681+ int nCRTIndex,
25682+ USHORT Horizontal,
25683+ USHORT Vertical);
25684+
25685+void DisableCRT(ULONG MMIOBase, int nCRTIndex);
25686+void ClearCRTWithBlack(ULONG ulCRTAddr, int iWidth, int iHeight);
25687+
25688+#endif /* _CRT_H_ */
25689+
25690diff --git a/board/aspeed/ast2400/flash.c b/board/aspeed/ast2400/flash.c
25691new file mode 100755
25692index 0000000..d611d0d
25693--- /dev/null
25694+++ b/board/aspeed/ast2400/flash.c
25695@@ -0,0 +1,1651 @@
25696+/*
25697+ * This program is distributed in the hope that it will be useful,
25698+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
25699+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25700+ * GNU General Public License for more details.
25701+ *
25702+ * You should have received a copy of the GNU General Public License
25703+ * along with this program; if not, write to the Free Software
25704+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25705+ * MA 02111-1307 USA
25706+ *
25707+ * History
25708+ * 01/20/2004 - combined variants of original driver.
25709+ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
25710+ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
25711+ * 01/27/2004 - Little endian support Ed Okerson
25712+ *
25713+ * Tested Architectures
25714+ * Port Width Chip Width # of banks Flash Chip Board
25715+ * 32 16 1 28F128J3 seranoa/eagle
25716+ * 64 16 1 28F128J3 seranoa/falcon
25717+ */
25718+// (Sun) This CFI driver is written for fixed-width flash chips.
25719+// It was not designed for flexible 8-bit/16-bit chips, which are the norm.
25720+// When those chips are connected to a bus in 8-bit mode, the address wires
25721+// right-shifted by 1.
25722+//FIXME: Fix the driver to auto-detect "16-bit flash wired in 8-bit mode".
25723+// Left-shift CFI offsets by 1 bit instead of doubling the #define values.
25724+
25725+/* The DEBUG define must be before common to enable debugging */
25726+// (Sun) Changed to DEBUG_FLASH because flash debug()s are too numerous.
25727+// #define DEBUG
25728+
25729+#include <common.h>
25730+#include <asm/processor.h>
25731+#include <asm/byteorder.h>
25732+#include <environment.h>
25733+#ifdef CONFIG_SYS_FLASH_CFI
25734+
25735+/*
25736+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
25737+ * The width of the port and the width of the chips are determined at initialization.
25738+ * These widths are used to calculate the address for access CFI data structures.
25739+ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
25740+ *
25741+ * References
25742+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
25743+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
25744+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
25745+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
25746+ *
25747+ * TODO
25748+ *
25749+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
25750+ * Table (ALT) to determine if protection is available
25751+ *
25752+ * Add support for other command sets Use the PRI and ALT to determine command set
25753+ * Verify erase and program timeouts.
25754+ */
25755+
25756+#ifndef CONFIG_FLASH_BANKS_LIST
25757+#define CONFIG_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
25758+#endif
25759+
25760+#define FLASH_CMD_CFI 0x98
25761+#define FLASH_CMD_READ_ID 0x90
25762+#define FLASH_CMD_RESET 0xff
25763+#define FLASH_CMD_BLOCK_ERASE 0x20
25764+#define FLASH_CMD_ERASE_CONFIRM 0xD0
25765+#define FLASH_CMD_WRITE 0x40
25766+#define FLASH_CMD_PROTECT 0x60
25767+#define FLASH_CMD_PROTECT_SET 0x01
25768+#define FLASH_CMD_PROTECT_CLEAR 0xD0
25769+#define FLASH_CMD_CLEAR_STATUS 0x50
25770+#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
25771+#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
25772+
25773+#define FLASH_STATUS_DONE 0x80
25774+#define FLASH_STATUS_ESS 0x40
25775+#define FLASH_STATUS_ECLBS 0x20
25776+#define FLASH_STATUS_PSLBS 0x10
25777+#define FLASH_STATUS_VPENS 0x08
25778+#define FLASH_STATUS_PSS 0x04
25779+#define FLASH_STATUS_DPS 0x02
25780+#define FLASH_STATUS_R 0x01
25781+#define FLASH_STATUS_PROTECT 0x01
25782+
25783+#define AMD_CMD_RESET 0xF0
25784+#define AMD_CMD_WRITE 0xA0
25785+#define AMD_CMD_ERASE_START 0x80
25786+#define AMD_CMD_ERASE_SECTOR 0x30
25787+#define AMD_CMD_UNLOCK_START 0xAA
25788+#define AMD_CMD_UNLOCK_ACK 0x55
25789+#define AMD_CMD_WRITE_TO_BUFFER 0x25
25790+#define AMD_CMD_BUFFER_TO_FLASH 0x29
25791+
25792+#define AMD_STATUS_TOGGLE 0x40
25793+#define AMD_STATUS_ERROR 0x20
25794+//FIXME: These 3 were also changed for 8-bit/16-bit flash chips.
25795+#define AMD_ADDR_ERASE_START (0xAAA/info->portwidth)
25796+#define AMD_ADDR_START (0xAAA/info->portwidth)
25797+#define AMD_ADDR_ACK (0x555/info->portwidth)
25798+
25799+//FIXME: Fix the driver to auto-detect "16-bit flash wired in 8-bit mode".
25800+// Left-shift CFI offsets by 1 bit instead of doubling the #define values.
25801+#define FLASH_OFFSET_CFI (0xAA/info->portwidth)
25802+#define FLASH_OFFSET_CFI_RESP (0x20/info->portwidth)
25803+#define FLASH_OFFSET_CFI_RESP1 (0x22/info->portwidth)
25804+#define FLASH_OFFSET_CFI_RESP2 (0x24/info->portwidth)
25805+#define FLASH_OFFSET_PRIMARY_VENDOR (0x26/info->portwidth)
25806+#define FLASH_OFFSET_WTOUT (0x3E/info->portwidth)
25807+#define FLASH_OFFSET_WBTOUT (0x40/info->portwidth)
25808+#define FLASH_OFFSET_ETOUT (0x42/info->portwidth)
25809+#define FLASH_OFFSET_CETOUT (0x44/info->portwidth)
25810+#define FLASH_OFFSET_WMAX_TOUT (0x46/info->portwidth)
25811+#define FLASH_OFFSET_WBMAX_TOUT (0x48/info->portwidth)
25812+#define FLASH_OFFSET_EMAX_TOUT (0x4A/info->portwidth)
25813+#define FLASH_OFFSET_CEMAX_TOUT (0x4C/info->portwidth)
25814+#define FLASH_OFFSET_SIZE (0x4E/info->portwidth)
25815+#define FLASH_OFFSET_INTERFACE (0x50/info->portwidth)
25816+#define FLASH_OFFSET_BUFFER_SIZE (0x54/info->portwidth)
25817+#define FLASH_OFFSET_NUM_ERASE_REGIONS (0x58/info->portwidth)
25818+#define FLASH_OFFSET_ERASE_REGIONS (0x5A/info->portwidth)
25819+#define FLASH_OFFSET_PROTECT (0x02/info->portwidth)
25820+#define FLASH_OFFSET_USER_PROTECTION (0x85/info->portwidth)
25821+#define FLASH_OFFSET_INTEL_PROTECTION (0x81/info->portwidth)
25822+
25823+#define MAX_NUM_ERASE_REGIONS 4
25824+
25825+#define FLASH_MAN_CFI 0x01000000
25826+
25827+#define CFI_CMDSET_NONE 0
25828+#define CFI_CMDSET_INTEL_EXTENDED 1
25829+#define CFI_CMDSET_AMD_STANDARD 2
25830+#define CFI_CMDSET_INTEL_STANDARD 3
25831+#define CFI_CMDSET_AMD_EXTENDED 4
25832+#define CFI_CMDSET_MITSU_STANDARD 256
25833+#define CFI_CMDSET_MITSU_EXTENDED 257
25834+#define CFI_CMDSET_SST 258
25835+
25836+
25837+#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
25838+# undef FLASH_CMD_RESET
25839+# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
25840+#endif
25841+
25842+
25843+typedef union {
25844+ unsigned char c;
25845+ unsigned short w;
25846+ unsigned long l;
25847+ unsigned long long ll;
25848+} cfiword_t;
25849+
25850+typedef union {
25851+ volatile unsigned char *cp;
25852+ volatile unsigned short *wp;
25853+ volatile unsigned long *lp;
25854+ volatile unsigned long long *llp;
25855+} cfiptr_t;
25856+
25857+/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
25858+#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
25859+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS_DETECT] = CONFIG_FLASH_BANKS_LIST;
25860+flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
25861+#else
25862+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_FLASH_BANKS_LIST;
25863+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
25864+#endif
25865+
25866+
25867+/*-----------------------------------------------------------------------
25868+ * Functions
25869+ */
25870+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
25871+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
25872+static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
25873+static void flash_write_cmd_nodbg (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
25874+static void flash_write_cmd_int (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd, int noDebug);
25875+static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
25876+static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
25877+static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
25878+static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
25879+static int flash_detect_cfi (flash_info_t * info);
25880+ulong flash_get_size (ulong base, int banknum);
25881+static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
25882+static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
25883+ ulong tout, char *prompt);
25884+static void write_buffer_abort_reset(flash_info_t * info, flash_sect_t sector);
25885+#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
25886+static flash_info_t *flash_get_info(ulong base);
25887+#endif
25888+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
25889+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
25890+static int flash_write_cfibuffer_amd (flash_info_t * info, ulong dest, uchar * cp, int len);
25891+#endif
25892+
25893+/*-----------------------------------------------------------------------
25894+ * create an address based on the offset and the port width
25895+ */
25896+inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
25897+{
25898+ return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
25899+}
25900+
25901+/*-----------------------------------------------------------------------
25902+ * Debug support
25903+ */
25904+#ifdef DEBUG_FLASH
25905+static void print_longlong (char *str, unsigned long long data)
25906+{
25907+ int i;
25908+ char *cp;
25909+
25910+ cp = (unsigned char *) &data;
25911+ for (i = 0; i < 8; i++)
25912+ sprintf (&str[i * 2], "%2.2x", *cp++);
25913+}
25914+#endif
25915+
25916+#if defined(DEBUG_FLASH)
25917+static void flash_printqry (flash_info_t * info, flash_sect_t sect)
25918+{
25919+ cfiptr_t cptr;
25920+ int x, y;
25921+
25922+ for (x = 0; x < 0x40; x += 16U / info->portwidth) {
25923+ cptr.cp =
25924+ flash_make_addr (info, sect,
25925+ x + FLASH_OFFSET_CFI_RESP);
25926+ debug ("%p : ", cptr.cp);
25927+ for (y = 0; y < 16; y++) {
25928+ debug ("%2.2x ", cptr.cp[y]);
25929+ }
25930+ debug (" ");
25931+ for (y = 0; y < 16; y++) {
25932+ if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
25933+ debug ("%c", cptr.cp[y]);
25934+ } else {
25935+ debug (".");
25936+ }
25937+ }
25938+ debug ("\n");
25939+ }
25940+}
25941+#endif
25942+
25943+/*-----------------------------------------------------------------------
25944+ * read a character at a port width address
25945+ */
25946+inline uchar flash_read_uchar (flash_info_t * info, uint offset)
25947+{
25948+ uchar *cp;
25949+
25950+ cp = flash_make_addr (info, 0, offset);
25951+#if defined(__LITTLE_ENDIAN)
25952+ return (cp[0]);
25953+#else
25954+ return (cp[info->portwidth - 1]);
25955+#endif
25956+}
25957+
25958+/*-----------------------------------------------------------------------
25959+ * read a short word by swapping for ppc format.
25960+ */
25961+#if 0
25962+static ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
25963+{
25964+ uchar *addr;
25965+ ushort retval;
25966+
25967+#ifdef DEBUG_FLASH
25968+ int x;
25969+#endif
25970+ addr = flash_make_addr (info, sect, offset);
25971+
25972+#ifdef DEBUG_FLASH
25973+ debug ("ushort addr is at %p info->portwidth = %d\n", addr,
25974+ info->portwidth);
25975+ for (x = 0; x < 2 * info->portwidth; x++) {
25976+ debug ("addr[%x] = 0x%x\n", x, addr[x]);
25977+ }
25978+#endif
25979+#if defined(__LITTLE_ENDIAN)
25980+ if (info->interface == FLASH_CFI_X8X16) {
25981+ retval = (addr[0] | (addr[2] << 8));
25982+ } else {
25983+ retval = (addr[0] | (addr[(info->portwidth)] << 8));
25984+ }
25985+#else
25986+ retval = ((addr[(2 * info->portwidth) - 1] << 8) |
25987+ addr[info->portwidth - 1]);
25988+#endif
25989+
25990+ debug ("retval = 0x%x\n", retval);
25991+ return retval;
25992+}
25993+#endif
25994+
25995+/*-----------------------------------------------------------------------
25996+ * read a long word by picking the least significant byte of each maximum
25997+ * port size word. Swap for ppc format.
25998+ */
25999+static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
26000+{
26001+ uchar *addr;
26002+ ulong retval;
26003+#ifdef DEBUG_FLASH
26004+ int x;
26005+#endif
26006+#if 0
26007+ switch (info->interface) {
26008+ case FLASH_CFI_X8:
26009+ case FLASH_CFI_X16:
26010+ break;
26011+ case FLASH_CFI_X8X16:
26012+ offset <<= 1;
26013+ }
26014+#endif
26015+ // flash_make_addr() multiplies offset by info->portwidth.
26016+ addr = flash_make_addr (info, sect, offset);
26017+
26018+#ifdef DEBUG_FLASH
26019+ debug ("long addr is at %p info->portwidth = %d\n", addr,
26020+ info->portwidth);
26021+ for (x = 0; x < 4 * info->portwidth; x++) {
26022+ debug ("addr[%x] = 0x%x\n", x, addr[x]);
26023+ }
26024+#endif
26025+#if defined(__LITTLE_ENDIAN)
26026+ if (info->interface == FLASH_CFI_X8X16) {
26027+ retval = (addr[0] | (addr[2] << 8) | (addr[4] << 16) | (addr[6] << 24));
26028+ } else {
26029+ retval = (addr[0] | (addr[(info->portwidth)] << 8) |
26030+ (addr[(2 * info->portwidth)] << 16) |
26031+ (addr[(3 * info->portwidth)] << 24));
26032+ }
26033+#else
26034+ //FIXME: This undocumented code appears to match broken bus wiring.
26035+ retval = (addr[(2 * info->portwidth) - 1] << 24) |
26036+ (addr[(info->portwidth) - 1] << 16) |
26037+ (addr[(4 * info->portwidth) - 1] << 8) |
26038+ addr[(3 * info->portwidth) - 1];
26039+#endif
26040+ return retval;
26041+}
26042+
26043+/*-----------------------------------------------------------------------
26044+ */
26045+unsigned long flash_init (void)
26046+{
26047+ unsigned long size = 0;
26048+ int i;
26049+
26050+ /* Init: no FLASHes known */
26051+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
26052+ flash_info[i].flash_id = FLASH_UNKNOWN;
26053+ size += flash_info[i].size = flash_get_size (bank_base[i], i);
26054+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
26055+#ifndef CFG_FLASH_QUIET_TEST
26056+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
26057+ i, flash_info[i].size, flash_info[i].size << 20);
26058+#endif /* CFG_FLASH_QUIET_TEST */
26059+ }
26060+ }
26061+
26062+ /* Monitor protection ON by default */
26063+#if (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
26064+ flash_protect (FLAG_PROTECT_SET,
26065+ CONFIG_MONITOR_BASE,
26066+ CONFIG_MONITOR_BASE + monitor_flash_len - 1,
26067+ flash_get_info(CONFIG_MONITOR_BASE));
26068+#endif
26069+
26070+ /* Environment protection ON by default */
26071+#ifdef CONFIG_ENV_IS_IN_FLASH
26072+ flash_protect (FLAG_PROTECT_SET,
26073+ CONFIG_ENV_ADDR,
26074+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
26075+ flash_get_info(CONFIG_ENV_ADDR));
26076+#endif
26077+
26078+ /* Redundant environment protection ON by default */
26079+#ifdef CONFIG_ENV_ADDR_REDUND
26080+ flash_protect (FLAG_PROTECT_SET,
26081+ CONFIG_ENV_ADDR_REDUND,
26082+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
26083+ flash_get_info(CONFIG_ENV_ADDR_REDUND));
26084+#endif
26085+ return (size);
26086+}
26087+
26088+/*-----------------------------------------------------------------------
26089+ */
26090+#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
26091+static flash_info_t *flash_get_info(ulong base)
26092+{
26093+ int i;
26094+ flash_info_t * info = 0;
26095+
26096+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
26097+ info = & flash_info[i];
26098+ if (info->size && info->start[0] <= base &&
26099+ base <= info->start[0] + info->size - 1)
26100+ break;
26101+ }
26102+
26103+ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
26104+}
26105+#endif
26106+
26107+/*-----------------------------------------------------------------------
26108+ */
26109+int flash_erase (flash_info_t * info, int s_first, int s_last)
26110+{
26111+ int rcode = 0;
26112+ int prot;
26113+ flash_sect_t sect;
26114+ uchar ch;
26115+ uchar *addr;
26116+
26117+ if (info->flash_id != FLASH_MAN_CFI) {
26118+ puts ("Can't erase unknown flash type - aborted\n");
26119+ return 1;
26120+ }
26121+ if ((s_first < 0) || (s_first > s_last)) {
26122+ puts ("- no sectors to erase\n");
26123+ return 1;
26124+ }
26125+
26126+ prot = 0;
26127+ for (sect = s_first; sect <= s_last; ++sect) {
26128+ if (info->protect[sect]) {
26129+ prot++;
26130+ }
26131+ }
26132+ if (prot) {
26133+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
26134+ } else {
26135+ putc ('\n');
26136+ }
26137+
26138+
26139+ for (sect = s_first; sect <= s_last; sect++) {
26140+ if (info->protect[sect] == 0) { /* not protected */
26141+ switch (info->vendor) {
26142+ case CFI_CMDSET_INTEL_STANDARD:
26143+ case CFI_CMDSET_INTEL_EXTENDED:
26144+ flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
26145+ flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
26146+ flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
26147+ break;
26148+ case CFI_CMDSET_AMD_STANDARD:
26149+ case CFI_CMDSET_AMD_EXTENDED:
26150+ flash_unlock_seq (info, sect);
26151+ flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
26152+ AMD_CMD_ERASE_START);
26153+ flash_unlock_seq (info, sect);
26154+ flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
26155+
26156+ /* toggle */
26157+ addr = flash_make_addr (info, sect, 0);
26158+ do {
26159+ ch = *(volatile uchar *)(addr);
26160+ } while ( ((ch & 0x80) == 0) || (ch != 0xFF) );
26161+ break;
26162+ default:
26163+ debug ("Unkown flash vendor %d\n",
26164+ info->vendor);
26165+ break;
26166+ }
26167+
26168+ if (flash_full_status_check
26169+ (info, sect, info->erase_blk_tout, "erase")) {
26170+ rcode = 1;
26171+ } else
26172+ putc ('.');
26173+ }
26174+ }
26175+ puts (" done\n");
26176+ return rcode;
26177+}
26178+
26179+/*-----------------------------------------------------------------------
26180+ */
26181+void flash_print_info (flash_info_t * info)
26182+{
26183+ int i;
26184+
26185+ if (info->flash_id != FLASH_MAN_CFI) {
26186+ puts ("missing or unknown FLASH type\n");
26187+ return;
26188+ }
26189+
26190+ printf ("CFI conformant FLASH (%d x %d)",
26191+ (info->portwidth << 3), (info->chipwidth << 3));
26192+ printf (" Size: %ld MB in %d Sectors\n",
26193+ info->size >> 20, info->sector_count);
26194+ printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
26195+ info->erase_blk_tout,
26196+ info->write_tout,
26197+ info->buffer_write_tout,
26198+ info->buffer_size);
26199+
26200+ puts (" Sector Start Addresses:");
26201+ for (i = 0; i < info->sector_count; ++i) {
26202+#ifdef CFG_FLASH_EMPTY_INFO
26203+ int k;
26204+ int size;
26205+ int erased;
26206+ volatile unsigned long *flash;
26207+
26208+ /*
26209+ * Check if whole sector is erased
26210+ */
26211+ if (i != (info->sector_count - 1))
26212+ size = info->start[i + 1] - info->start[i];
26213+ else
26214+ size = info->start[0] + info->size - info->start[i];
26215+ erased = 1;
26216+ flash = (volatile unsigned long *) info->start[i];
26217+ size = size >> 2; /* divide by 4 for longword access */
26218+ for (k = 0; k < size; k++) {
26219+ if (*flash++ != 0xffffffff) {
26220+ erased = 0;
26221+ break;
26222+ }
26223+ }
26224+
26225+ if ((i % 5) == 0)
26226+ printf ("\n");
26227+ /* print empty and read-only info */
26228+ printf (" %08lX%s%s",
26229+ info->start[i],
26230+ erased ? " E" : " ",
26231+ info->protect[i] ? "RO " : " ");
26232+#else /* ! CFG_FLASH_EMPTY_INFO */
26233+ if ((i % 5) == 0)
26234+ printf ("\n ");
26235+ printf (" %08lX%s",
26236+ info->start[i], info->protect[i] ? " (RO)" : " ");
26237+#endif
26238+ }
26239+ putc ('\n');
26240+ return;
26241+}
26242+
26243+/*-----------------------------------------------------------------------
26244+ * Copy memory to flash, returns:
26245+ * 0 - OK
26246+ * 1 - write timeout
26247+ * 2 - Flash not erased
26248+ */
26249+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
26250+{
26251+ ulong wp;
26252+ ulong cp;
26253+ int aln;
26254+ cfiword_t cword;
26255+ int i, rc;
26256+
26257+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
26258+ unsigned char pat[] = {'|', '-', '/', '\\'};
26259+ int patcnt = 0;
26260+ int buffered_size;
26261+#endif
26262+ /* get lower aligned address */
26263+ /* get lower aligned address */
26264+ wp = (addr & ~(info->portwidth - 1));
26265+
26266+ /* handle unaligned start */
26267+ if ((aln = addr - wp) != 0) {
26268+ cword.l = 0;
26269+ cp = wp;
26270+ for (i = 0; i < aln; ++i, ++cp)
26271+ flash_add_byte (info, &cword, (*(uchar *) cp));
26272+
26273+ for (; (i < info->portwidth) && (cnt > 0); i++) {
26274+ flash_add_byte (info, &cword, *src++);
26275+ cnt--;
26276+ cp++;
26277+ }
26278+ for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
26279+ flash_add_byte (info, &cword, (*(uchar *) cp));
26280+ if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
26281+ return rc;
26282+ wp = cp;
26283+ }
26284+
26285+ /* handle the aligned part */
26286+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
26287+ buffered_size = (info->portwidth / info->chipwidth);
26288+ buffered_size *= info->buffer_size;
26289+ while (cnt >= info->portwidth) {
26290+ /* Show processing */
26291+ if ((++patcnt % 256) == 0)
26292+ printf("%c\b", pat[(patcnt / 256) & 0x03]);
26293+
26294+ i = buffered_size > cnt ? cnt : buffered_size;
26295+ if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
26296+ return rc;
26297+ i -= i & (info->portwidth - 1);
26298+ wp += i;
26299+ src += i;
26300+ cnt -= i;
26301+ }
26302+#else
26303+ while (cnt >= info->portwidth) {
26304+ cword.l = 0;
26305+ for (i = 0; i < info->portwidth; i++) {
26306+ flash_add_byte (info, &cword, *src++);
26307+ }
26308+ if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
26309+ return rc;
26310+ wp += info->portwidth;
26311+ cnt -= info->portwidth;
26312+ }
26313+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
26314+ if (cnt == 0) {
26315+ return (0);
26316+ }
26317+
26318+ /*
26319+ * handle unaligned tail bytes
26320+ */
26321+ cword.l = 0;
26322+ for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
26323+ flash_add_byte (info, &cword, *src++);
26324+ --cnt;
26325+ }
26326+ for (; i < info->portwidth; ++i, ++cp) {
26327+ flash_add_byte (info, &cword, (*(uchar *) cp));
26328+ }
26329+
26330+ return flash_write_cfiword (info, wp, cword);
26331+}
26332+
26333+/*-----------------------------------------------------------------------
26334+ */
26335+#ifdef CFG_FLASH_PROTECTION
26336+
26337+int flash_real_protect (flash_info_t * info, long sector, int prot)
26338+{
26339+ int retcode = 0;
26340+
26341+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
26342+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
26343+ if (prot)
26344+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
26345+ else
26346+ flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
26347+
26348+ if ((retcode =
26349+ flash_full_status_check (info, sector, info->erase_blk_tout,
26350+ prot ? "protect" : "unprotect")) == 0) {
26351+
26352+ info->protect[sector] = prot;
26353+ /* Intel's unprotect unprotects all locking */
26354+ if (prot == 0) {
26355+ flash_sect_t i;
26356+
26357+ for (i = 0; i < info->sector_count; i++) {
26358+ if (info->protect[i])
26359+ flash_real_protect (info, i, 1);
26360+ }
26361+ }
26362+ }
26363+ return retcode;
26364+}
26365+
26366+/*-----------------------------------------------------------------------
26367+ * flash_read_user_serial - read the OneTimeProgramming cells
26368+ */
26369+void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
26370+ int len)
26371+{
26372+ uchar *src;
26373+ uchar *dst;
26374+
26375+ dst = buffer;
26376+ src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
26377+ flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
26378+ memcpy (dst, src + offset, len);
26379+ flash_write_cmd (info, 0, 0, info->cmd_reset);
26380+}
26381+
26382+/*
26383+ * flash_read_factory_serial - read the device Id from the protection area
26384+ */
26385+void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
26386+ int len)
26387+{
26388+ uchar *src;
26389+
26390+ src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
26391+ flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
26392+ memcpy (buffer, src + offset, len);
26393+ flash_write_cmd (info, 0, 0, info->cmd_reset);
26394+}
26395+
26396+#endif /* CFG_FLASH_PROTECTION */
26397+
26398+/*
26399+ * flash_is_busy - check to see if the flash is busy
26400+ * This routine checks the status of the chip and returns true if the chip is busy
26401+ */
26402+static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
26403+{
26404+ int retval;
26405+
26406+ switch (info->vendor) {
26407+ case CFI_CMDSET_INTEL_STANDARD:
26408+ case CFI_CMDSET_INTEL_EXTENDED:
26409+ retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
26410+ break;
26411+ case CFI_CMDSET_AMD_STANDARD:
26412+ case CFI_CMDSET_AMD_EXTENDED:
26413+ retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
26414+ break;
26415+ default:
26416+ retval = 0;
26417+ }
26418+#ifdef DEBUG_FLASH
26419+ if (retval)
26420+ debug ("flash_is_busy: %d\n", retval);
26421+#endif
26422+ return retval;
26423+}
26424+
26425+/*-----------------------------------------------------------------------
26426+ * wait for XSR.7 to be set. Time out with an error if it does not.
26427+ * This routine does not set the flash to read-array mode.
26428+ */
26429+static int flash_status_check (flash_info_t * info, flash_sect_t sector,
26430+ ulong tout, char *prompt)
26431+{
26432+ ulong start, now;
26433+
26434+ /* Wait for command completion */
26435+ // (Sun) Fix order of checking time so it works when the CPU is very
26436+ // slow, e.g., single-stepping or emulation.
26437+ start = get_timer (0);
26438+ while (now = get_timer(start),
26439+ flash_is_busy (info, sector))
26440+ {
26441+ if (now > info->erase_blk_tout) {
26442+ printf ("Flash %s timeout at address %lx data %lx\n",
26443+ prompt, info->start[sector],
26444+ flash_read_long (info, sector, 0));
26445+ flash_write_cmd (info, sector, 0, info->cmd_reset);
26446+ return ERR_TIMOUT;
26447+ }
26448+ }
26449+ return ERR_OK;
26450+}
26451+
26452+/*-----------------------------------------------------------------------
26453+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
26454+ * This routine sets the flash to read-array mode.
26455+ */
26456+static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
26457+ ulong tout, char *prompt)
26458+{
26459+ int retcode;
26460+
26461+ retcode = flash_status_check (info, sector, tout, prompt);
26462+ switch (info->vendor) {
26463+ case CFI_CMDSET_INTEL_EXTENDED:
26464+ case CFI_CMDSET_INTEL_STANDARD:
26465+ if ((retcode != ERR_OK)
26466+ && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
26467+ retcode = ERR_INVAL;
26468+ printf ("Flash %s error at address %lx\n", prompt,
26469+ info->start[sector]);
26470+ if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
26471+ puts ("Command Sequence Error.\n");
26472+ } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
26473+ puts ("Block Erase Error.\n");
26474+ retcode = ERR_NOT_ERASED;
26475+ } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
26476+ puts ("Locking Error\n");
26477+ }
26478+ if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
26479+ puts ("Block locked.\n");
26480+ retcode = ERR_PROTECTED;
26481+ }
26482+ if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
26483+ puts ("Vpp Low Error.\n");
26484+ }
26485+ flash_write_cmd (info, sector, 0, info->cmd_reset);
26486+ break;
26487+ default:
26488+ break;
26489+ }
26490+ return retcode;
26491+}
26492+
26493+static void write_buffer_abort_reset(flash_info_t * info, flash_sect_t sector)
26494+{
26495+ flash_write_cmd (info, sector, 0xaaa, 0xaa);
26496+ flash_write_cmd (info, sector, 0x555, 0x55);
26497+ flash_write_cmd (info, sector, 0xaaa, 0xf0);
26498+}
26499+
26500+/*-----------------------------------------------------------------------
26501+ */
26502+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
26503+{
26504+#if defined(__LITTLE_ENDIAN)
26505+ unsigned short w;
26506+ unsigned int l;
26507+ unsigned long long ll;
26508+#endif
26509+
26510+ switch (info->portwidth) {
26511+ case FLASH_CFI_8BIT:
26512+ cword->c = c;
26513+ break;
26514+ case FLASH_CFI_16BIT:
26515+#if defined(__LITTLE_ENDIAN)
26516+ w = c;
26517+ w <<= 8;
26518+ cword->w = (cword->w >> 8) | w;
26519+#else
26520+ cword->w = (cword->w << 8) | c;
26521+#endif
26522+ break;
26523+ case FLASH_CFI_32BIT:
26524+#if defined(__LITTLE_ENDIAN)
26525+ l = c;
26526+ l <<= 24;
26527+ cword->l = (cword->l >> 8) | l;
26528+#else
26529+ cword->l = (cword->l << 8) | c;
26530+#endif
26531+ break;
26532+ case FLASH_CFI_64BIT:
26533+#if defined(__LITTLE_ENDIAN)
26534+ ll = c;
26535+ ll <<= 56;
26536+ cword->ll = (cword->ll >> 8) | ll;
26537+#else
26538+ cword->ll = (cword->ll << 8) | c;
26539+#endif
26540+ break;
26541+ }
26542+}
26543+
26544+
26545+/*-----------------------------------------------------------------------
26546+ * make a proper sized command based on the port and chip widths
26547+ */
26548+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
26549+{
26550+ int i;
26551+ uchar *cp = (uchar *) cmdbuf;
26552+
26553+#if defined(__LITTLE_ENDIAN)
26554+ for (i = info->portwidth; i > 0; i--)
26555+#else
26556+ for (i = 1; i <= info->portwidth; i++)
26557+#endif
26558+ *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
26559+}
26560+
26561+/*
26562+ * Write a proper sized command to the correct address
26563+ */
26564+static void
26565+flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset,
26566+ uchar cmd)
26567+{
26568+#ifdef DEBUG_FLASH
26569+ const int noDebug = 0;
26570+#else
26571+ const int noDebug = 1;
26572+#endif
26573+ return flash_write_cmd_int(info, sect, offset, cmd, noDebug);
26574+}
26575+static void
26576+flash_write_cmd_nodbg (flash_info_t * info, flash_sect_t sect, uint offset,
26577+ uchar cmd)
26578+{
26579+ return flash_write_cmd_int(info, sect, offset, cmd, 1);
26580+}
26581+
26582+static void
26583+flash_write_cmd_int (flash_info_t * info, flash_sect_t sect, uint offset,
26584+ uchar cmd, int noDebug)
26585+{
26586+
26587+ volatile cfiptr_t addr;
26588+ cfiword_t cword;
26589+
26590+ addr.cp = flash_make_addr (info, sect, offset);
26591+ flash_make_cmd (info, cmd, &cword);
26592+ switch (info->portwidth) {
26593+ case FLASH_CFI_8BIT:
26594+ if (noDebug == 0)
26595+ debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
26596+ cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
26597+ *addr.cp = cword.c;
26598+ break;
26599+ case FLASH_CFI_16BIT:
26600+ if (noDebug == 0)
26601+ debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
26602+ cmd, cword.w,
26603+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
26604+ *addr.wp = cword.w;
26605+ break;
26606+ case FLASH_CFI_32BIT:
26607+ if (noDebug == 0)
26608+ debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
26609+ cmd, cword.l,
26610+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
26611+ *addr.lp = cword.l;
26612+ break;
26613+ case FLASH_CFI_64BIT:
26614+#ifdef DEBUG_FLASH
26615+ if (noDebug == 0)
26616+ {
26617+ char str[20];
26618+
26619+ print_longlong (str, cword.ll);
26620+
26621+ debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
26622+ addr.llp, cmd, str,
26623+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
26624+ }
26625+#endif
26626+ *addr.llp = cword.ll;
26627+ break;
26628+ }
26629+}
26630+
26631+static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
26632+{
26633+ flash_write_cmd_nodbg (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
26634+ flash_write_cmd_nodbg (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
26635+}
26636+
26637+/*-----------------------------------------------------------------------
26638+ */
26639+static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
26640+{
26641+ cfiptr_t cptr;
26642+ cfiword_t cword;
26643+ int retval;
26644+#ifdef DEBUG_FLASH
26645+ const int dbg = 1;
26646+#else
26647+ const int dbg = 0;
26648+#endif
26649+ cptr.cp = flash_make_addr (info, sect, offset);
26650+ flash_make_cmd (info, cmd, &cword);
26651+
26652+ if (dbg)
26653+ debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
26654+ switch (info->portwidth) {
26655+ case FLASH_CFI_8BIT:
26656+ if (dbg)
26657+ debug ("is= %x %x\n", cptr.cp[0], cword.c);
26658+ retval = (cptr.cp[0] == cword.c);
26659+ break;
26660+ case FLASH_CFI_16BIT:
26661+ if (dbg)
26662+ debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
26663+ retval = (cptr.wp[0] == cword.w);
26664+ break;
26665+ case FLASH_CFI_32BIT:
26666+ if (dbg)
26667+ debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
26668+ retval = (cptr.lp[0] == cword.l);
26669+ break;
26670+ case FLASH_CFI_64BIT:
26671+#ifdef DEBUG_FLASH
26672+ {
26673+ char str1[20];
26674+ char str2[20];
26675+
26676+ print_longlong (str1, cptr.llp[0]);
26677+ print_longlong (str2, cword.ll);
26678+ debug ("is= %s %s\n", str1, str2);
26679+ }
26680+#endif
26681+ retval = (cptr.llp[0] == cword.ll);
26682+ break;
26683+ default:
26684+ retval = 0;
26685+ break;
26686+ }
26687+ return retval;
26688+}
26689+
26690+/*-----------------------------------------------------------------------
26691+ */
26692+static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
26693+{
26694+ cfiptr_t cptr;
26695+ cfiword_t cword;
26696+ int retval;
26697+
26698+ cptr.cp = flash_make_addr (info, sect, offset);
26699+ flash_make_cmd (info, cmd, &cword);
26700+ switch (info->portwidth) {
26701+ case FLASH_CFI_8BIT:
26702+ retval = ((cptr.cp[0] & cword.c) == cword.c);
26703+ break;
26704+ case FLASH_CFI_16BIT:
26705+ retval = ((cptr.wp[0] & cword.w) == cword.w);
26706+ break;
26707+ case FLASH_CFI_32BIT:
26708+ retval = ((cptr.lp[0] & cword.l) == cword.l);
26709+ break;
26710+ case FLASH_CFI_64BIT:
26711+ retval = ((cptr.llp[0] & cword.ll) == cword.ll);
26712+ break;
26713+ default:
26714+ retval = 0;
26715+ break;
26716+ }
26717+ return retval;
26718+}
26719+
26720+/*-----------------------------------------------------------------------
26721+ */
26722+static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
26723+{
26724+ cfiptr_t cptr;
26725+ cfiword_t cword;
26726+ int retval;
26727+
26728+ cptr.cp = flash_make_addr (info, sect, offset);
26729+ flash_make_cmd (info, cmd, &cword);
26730+ switch (info->portwidth) {
26731+ case FLASH_CFI_8BIT:
26732+ retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
26733+ break;
26734+ case FLASH_CFI_16BIT:
26735+ retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
26736+ break;
26737+ case FLASH_CFI_32BIT:
26738+ retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
26739+ break;
26740+ case FLASH_CFI_64BIT:
26741+ retval = ((cptr.llp[0] & cword.ll) !=
26742+ (cptr.llp[0] & cword.ll));
26743+ break;
26744+ default:
26745+ retval = 0;
26746+ break;
26747+ }
26748+ return retval;
26749+}
26750+
26751+/*-----------------------------------------------------------------------
26752+ * detect if flash is compatible with the Common Flash Interface (CFI)
26753+ * http://www.jedec.org/download/search/jesd68.pdf
26754+ *
26755+*/
26756+static int flash_detect_cfi (flash_info_t * info)
26757+{
26758+ ulong data;
26759+
26760+ debug ("flash_detect_cfi()... ");
26761+
26762+#if defined(CONFIG_FLASH_AST2300)
26763+ data = *(ulong *)(0x1e6e2070); /* hardware traping */
26764+ if (data & 0x10) /* D[4]: 0/1 (8/16) */
26765+ info->portwidth = FLASH_CFI_16BIT;
26766+ else
26767+ info->portwidth = FLASH_CFI_8BIT;
26768+#else
26769+ info->portwidth = FLASH_CFI_8BIT;
26770+#endif
26771+
26772+ {
26773+ for (info->chipwidth = FLASH_CFI_BY8;
26774+ info->chipwidth <= info->portwidth;
26775+ info->chipwidth <<= 1) {
26776+ flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
26777+ flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
26778+ if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
26779+ //FIXME: Next 3 lines were changed for 8-bit/16-bit flash chips.
26780+ && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP1, 'R')
26781+ && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP2, 'Y')) {
26782+ info->interface = flash_read_uchar (info, FLASH_OFFSET_INTERFACE);
26783+ debug ("device interface is %d\n",
26784+ info->interface);
26785+ debug ("found port %d chip %d ",
26786+ info->portwidth, info->chipwidth);
26787+ debug ("port %d bits chip %d bits\n",
26788+ info->portwidth << CFI_FLASH_SHIFT_WIDTH,
26789+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
26790+ return 1;
26791+ }
26792+ }
26793+ }
26794+ debug ("not found\n");
26795+ return 0;
26796+}
26797+
26798+/*
26799+ * The following code cannot be run from FLASH!
26800+ *
26801+ */
26802+ulong flash_get_size (ulong base, int banknum)
26803+{
26804+ flash_info_t *info = &flash_info[banknum];
26805+ int i, j;
26806+ flash_sect_t sect_cnt;
26807+ unsigned long sector;
26808+ unsigned long tmp;
26809+ int size_ratio;
26810+ uchar num_erase_regions;
26811+ int erase_region_size;
26812+ int erase_region_count;
26813+
26814+ info->start[0] = base;
26815+
26816+ if (flash_detect_cfi (info)) {
26817+ info->vendor = flash_read_uchar (info, FLASH_OFFSET_PRIMARY_VENDOR);
26818+#if defined(DEBUG_FLASH)
26819+ flash_printqry (info, 0);
26820+#endif
26821+ switch (info->vendor) {
26822+ case CFI_CMDSET_INTEL_STANDARD:
26823+ case CFI_CMDSET_INTEL_EXTENDED:
26824+ default:
26825+ info->cmd_reset = FLASH_CMD_RESET;
26826+ break;
26827+ case CFI_CMDSET_AMD_STANDARD:
26828+ case CFI_CMDSET_AMD_EXTENDED:
26829+ info->cmd_reset = AMD_CMD_RESET;
26830+ break;
26831+ }
26832+
26833+ debugX(2, "manufacturer is %d\n", info->vendor);
26834+ size_ratio = info->portwidth / info->chipwidth;
26835+ /* if the chip is x8/x16 reduce the ratio by half */
26836+#if 0
26837+ if ((info->interface == FLASH_CFI_X8X16)
26838+ && (info->chipwidth == FLASH_CFI_BY8)) {
26839+ size_ratio >>= 1;
26840+ }
26841+#endif
26842+ num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
26843+ debugX(2, "size_ratio %d port %d bits chip %d bits\n",
26844+ size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
26845+ info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
26846+ debugX(2, "found %d erase regions\n", num_erase_regions);
26847+ sect_cnt = 0;
26848+ sector = base;
26849+ for (i = 0; i < num_erase_regions; i++) {
26850+ if (i > MAX_NUM_ERASE_REGIONS) {
26851+ printf ("%d erase regions found, only %d used\n",
26852+ num_erase_regions, MAX_NUM_ERASE_REGIONS);
26853+ break;
26854+ }
26855+ // CFI Erase Block Region Information:
26856+ // Bits[31:16] = sect_size/256, 0 means 128-byte
26857+ // Bits[15:0] = num_sectors - 1
26858+ tmp = flash_read_long(info, 0,
26859+ FLASH_OFFSET_ERASE_REGIONS + i * 4);
26860+ debug("CFI erase block region info[%d]: 0x%08x, ",
26861+ i, tmp);
26862+ erase_region_count = (tmp & 0xffff) + 1;
26863+ tmp >>= 16;
26864+ erase_region_size = (tmp ? tmp * 256 : 128);
26865+ debug ("erase_region_count=%d erase_region_size=%d\n",
26866+ erase_region_count, erase_region_size);
26867+#if 0
26868+ erase_region_size = CFG_FLASH_SECTOR_SIZE; // Commented out
26869+ erase_region_count = CFG_FLASH_SECTOR_COUNT; // Commented out
26870+#endif
26871+ if (sect_cnt + erase_region_count > CONFIG_SYS_MAX_FLASH_SECT) {
26872+ printf("Warning: Erase region %d adds too many flash sectors"
26873+ " %d+%d; reducing to fit total limit of %d\n",
26874+ i, sect_cnt, erase_region_count, CONFIG_SYS_MAX_FLASH_SECT);
26875+ erase_region_count = CONFIG_SYS_MAX_FLASH_SECT - sect_cnt;
26876+ }
26877+ for (j = 0; j < erase_region_count; j++) {
26878+ info->start[sect_cnt] = sector;
26879+ sector += (erase_region_size * size_ratio);
26880+
26881+ /*
26882+ * Only read protection status from supported devices (intel...)
26883+ */
26884+ switch (info->vendor) {
26885+ case CFI_CMDSET_INTEL_EXTENDED:
26886+ case CFI_CMDSET_INTEL_STANDARD:
26887+ info->protect[sect_cnt] =
26888+ flash_isset (info, sect_cnt,
26889+ FLASH_OFFSET_PROTECT,
26890+ FLASH_STATUS_PROTECT);
26891+ break;
26892+ default:
26893+ info->protect[sect_cnt] = 0; /* default: not protected */
26894+ }
26895+
26896+ sect_cnt++;
26897+ }
26898+ }
26899+
26900+ info->sector_count = sect_cnt;
26901+ /* multiply the size by the number of chips */
26902+ // info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
26903+ // Use only the sectors that fit within the flash_info array size.
26904+ info->size = sector - base;
26905+ printf("Flash bank %d at %08x has 0x%x bytes in %d sectors"
26906+ " (chipSize 1<<%d, size_ratio %d).\n",
26907+ banknum, base, info->size, info->sector_count,
26908+ flash_read_uchar(info, FLASH_OFFSET_SIZE), size_ratio);
26909+
26910+ info->buffer_size = (1 << flash_read_uchar (info, FLASH_OFFSET_BUFFER_SIZE));
26911+ /* Limit the buffer size to 32bytes to meet most of AMD-styles flash's minimum requirement */
26912+ if (info->buffer_size > 32)
26913+ info->buffer_size = 32;
26914+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
26915+ info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
26916+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
26917+ info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
26918+ tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
26919+ info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
26920+ info->flash_id = FLASH_MAN_CFI;
26921+#if 0
26922+ if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
26923+ info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
26924+ }
26925+#endif
26926+ }
26927+
26928+ flash_write_cmd (info, 0, 0, info->cmd_reset);
26929+ return (info->size);
26930+}
26931+
26932+
26933+/*-----------------------------------------------------------------------
26934+ */
26935+static int flash_write_cfiword (flash_info_t * info, ulong dest,
26936+ cfiword_t cword)
26937+{
26938+
26939+ cfiptr_t ctladdr;
26940+ cfiptr_t cptr;
26941+ int flag;
26942+
26943+ ctladdr.cp = flash_make_addr (info, 0, 0);
26944+ cptr.cp = (uchar *) dest;
26945+
26946+
26947+ /* Check if Flash is (sufficiently) erased */
26948+ switch (info->portwidth) {
26949+ case FLASH_CFI_8BIT:
26950+ flag = ((cptr.cp[0] & cword.c) == cword.c);
26951+ break;
26952+ case FLASH_CFI_16BIT:
26953+ flag = ((cptr.wp[0] & cword.w) == cword.w);
26954+ break;
26955+ case FLASH_CFI_32BIT:
26956+ flag = ((cptr.lp[0] & cword.l) == cword.l);
26957+ break;
26958+ case FLASH_CFI_64BIT:
26959+ flag = ((cptr.llp[0] & cword.ll) == cword.ll);
26960+ break;
26961+ default:
26962+ return 2;
26963+ }
26964+ if (!flag)
26965+ return 2;
26966+
26967+ /* Disable interrupts which might cause a timeout here */
26968+ flag = disable_interrupts ();
26969+
26970+ switch (info->vendor) {
26971+ case CFI_CMDSET_INTEL_EXTENDED:
26972+ case CFI_CMDSET_INTEL_STANDARD:
26973+ flash_write_cmd_nodbg (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
26974+ flash_write_cmd_nodbg (info, 0, 0, FLASH_CMD_WRITE);
26975+ break;
26976+ case CFI_CMDSET_AMD_EXTENDED:
26977+ case CFI_CMDSET_AMD_STANDARD:
26978+ flash_unlock_seq (info, 0);
26979+ flash_write_cmd_nodbg (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
26980+ break;
26981+ }
26982+
26983+ switch (info->portwidth) {
26984+ case FLASH_CFI_8BIT:
26985+ cptr.cp[0] = cword.c;
26986+ break;
26987+ case FLASH_CFI_16BIT:
26988+ cptr.wp[0] = cword.w;
26989+ break;
26990+ case FLASH_CFI_32BIT:
26991+ cptr.lp[0] = cword.l;
26992+ break;
26993+ case FLASH_CFI_64BIT:
26994+ cptr.llp[0] = cword.ll;
26995+ break;
26996+ }
26997+
26998+ /* re-enable interrupts if necessary */
26999+ if (flag)
27000+ enable_interrupts ();
27001+
27002+ return flash_full_status_check (info, 0, info->write_tout, "write");
27003+}
27004+
27005+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
27006+
27007+/* loop through the sectors from the highest address
27008+ * when the passed address is greater or equal to the sector address
27009+ * we have a match
27010+ */
27011+static flash_sect_t find_sector (flash_info_t * info, ulong addr)
27012+{
27013+ flash_sect_t sector;
27014+
27015+ for (sector = info->sector_count - 1; sector >= 0; sector--) {
27016+ if (addr >= info->start[sector])
27017+ break;
27018+ }
27019+ return sector;
27020+}
27021+
27022+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
27023+ int len)
27024+{
27025+ flash_sect_t sector;
27026+ int cnt;
27027+ int retcode;
27028+ volatile cfiptr_t src;
27029+ volatile cfiptr_t dst;
27030+
27031+/* Add AMD write buffer mode support, ycchen@102006 */
27032+#if 0
27033+ /* buffered writes in the AMD chip set is not supported yet */
27034+ if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
27035+ (info->vendor == CFI_CMDSET_AMD_EXTENDED))
27036+ return ERR_INVAL;
27037+#endif
27038+ if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
27039+ (info->vendor == CFI_CMDSET_AMD_EXTENDED))
27040+ {
27041+ retcode = flash_write_cfibuffer_amd(info, dest, cp, len);
27042+ return retcode;
27043+ }
27044+
27045+ src.cp = cp;
27046+ dst.cp = (uchar *) dest;
27047+ sector = find_sector (info, dest);
27048+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
27049+ flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
27050+ if ((retcode =
27051+ flash_status_check (info, sector, info->buffer_write_tout,
27052+ "write to buffer")) == ERR_OK) {
27053+ /* reduce the number of loops by the width of the port */
27054+ switch (info->portwidth) {
27055+ case FLASH_CFI_8BIT:
27056+ cnt = len;
27057+ break;
27058+ case FLASH_CFI_16BIT:
27059+ cnt = len >> 1;
27060+ break;
27061+ case FLASH_CFI_32BIT:
27062+ cnt = len >> 2;
27063+ break;
27064+ case FLASH_CFI_64BIT:
27065+ cnt = len >> 3;
27066+ break;
27067+ default:
27068+ return ERR_INVAL;
27069+ break;
27070+ }
27071+ flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
27072+ while (cnt-- > 0) {
27073+ switch (info->portwidth) {
27074+ case FLASH_CFI_8BIT:
27075+ *dst.cp++ = *src.cp++;
27076+ break;
27077+ case FLASH_CFI_16BIT:
27078+ *dst.wp++ = *src.wp++;
27079+ break;
27080+ case FLASH_CFI_32BIT:
27081+ *dst.lp++ = *src.lp++;
27082+ break;
27083+ case FLASH_CFI_64BIT:
27084+ *dst.llp++ = *src.llp++;
27085+ break;
27086+ default:
27087+ return ERR_INVAL;
27088+ break;
27089+ }
27090+ }
27091+ flash_write_cmd (info, sector, 0,
27092+ FLASH_CMD_WRITE_BUFFER_CONFIRM);
27093+ retcode =
27094+ flash_full_status_check (info, sector,
27095+ info->buffer_write_tout,
27096+ "buffer write");
27097+ }
27098+ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
27099+ return retcode;
27100+}
27101+
27102+
27103+static int flash_write_cfibuffer_amd (flash_info_t * info, ulong dest, uchar * cp,
27104+ int len)
27105+{
27106+ flash_sect_t sector;
27107+ int cnt;
27108+ int retcode;
27109+ volatile cfiptr_t src;
27110+ volatile cfiptr_t dst;
27111+ volatile cfiword_t tmpsrc, tmpdst;
27112+
27113+ src.cp = cp;
27114+ dst.cp = (uchar *) dest;
27115+ sector = find_sector (info, dest);
27116+ flash_unlock_seq (info, 0);
27117+ if ((retcode =
27118+ flash_status_check (info, sector, info->buffer_write_tout,
27119+ "write to buffer")) == ERR_OK) {
27120+ /* reduce the number of loops by the width of the port */
27121+ switch (info->portwidth) {
27122+ case FLASH_CFI_8BIT:
27123+ cnt = len;
27124+ *dst.cp = (uchar) (AMD_CMD_WRITE_TO_BUFFER);
27125+ *dst.cp = (uchar) (cnt -1);
27126+ break;
27127+ case FLASH_CFI_16BIT:
27128+ cnt = len >> 1;
27129+ *dst.wp = (unsigned short) (AMD_CMD_WRITE_TO_BUFFER);
27130+ *dst.wp = (unsigned short) (cnt -1);
27131+ break;
27132+ case FLASH_CFI_32BIT:
27133+ cnt = len >> 2;
27134+ *dst.lp = (unsigned long) (AMD_CMD_WRITE_TO_BUFFER);
27135+ *dst.lp = (unsigned long) (cnt -1);
27136+ break;
27137+ case FLASH_CFI_64BIT:
27138+ cnt = len >> 3;
27139+ *dst.llp = (unsigned long long) (AMD_CMD_WRITE_TO_BUFFER);
27140+ *dst.llp = (unsigned long long) (cnt -1);
27141+ break;
27142+ default:
27143+ return ERR_INVAL;
27144+ break;
27145+ }
27146+ while (cnt-- > 0) {
27147+ switch (info->portwidth) {
27148+ case FLASH_CFI_8BIT:
27149+ *dst.cp++ = *src.cp++;
27150+ break;
27151+ case FLASH_CFI_16BIT:
27152+ *dst.wp++ = *src.wp++;
27153+ break;
27154+ case FLASH_CFI_32BIT:
27155+ *dst.lp++ = *src.lp++;
27156+ break;
27157+ case FLASH_CFI_64BIT:
27158+ *dst.llp++ = *src.llp++;
27159+ break;
27160+ default:
27161+ return ERR_INVAL;
27162+ break;
27163+ }
27164+ }
27165+ switch (info->portwidth) {
27166+ case FLASH_CFI_8BIT:
27167+ src.cp--;
27168+ dst.cp--;
27169+ *dst.cp = (unsigned char) (AMD_CMD_BUFFER_TO_FLASH);
27170+ tmpsrc.c = *src.cp & 0x80;
27171+
27172+ do {
27173+ tmpdst.c = *(volatile uchar *)(dst.cp);
27174+
27175+ if (tmpdst.c & 0x20) { /* toggle DQ5 */
27176+ tmpdst.c = *(volatile uchar *)(dst.cp);
27177+ if ((tmpdst.c & 0x80) != tmpsrc.c)
27178+ {
27179+ printf("program error occurred\n");
27180+ flash_write_cmd (info, sector, 0, info->cmd_reset);
27181+ return ERR_PROG_ERROR;
27182+ }
27183+ }
27184+ else if (tmpdst.c & 0x02) { /* toggle DQ1 */
27185+ tmpdst.c = *(volatile uchar *)(dst.cp);
27186+ if ((tmpdst.c & 0x80) != tmpsrc.c)
27187+ {
27188+ printf("write buffer error occurred \n");
27189+ write_buffer_abort_reset(info, sector);
27190+ return ERR_PROG_ERROR;
27191+ }
27192+ }
27193+
27194+ } while ((tmpdst.c & 0x80) != tmpsrc.c);
27195+
27196+ break;
27197+ case FLASH_CFI_16BIT:
27198+ src.wp--;
27199+ dst.wp--;
27200+ *dst.wp = (unsigned short) (AMD_CMD_BUFFER_TO_FLASH);
27201+ tmpsrc.w = *src.wp & 0x80;
27202+
27203+ do {
27204+ tmpdst.w = *(volatile short *)(dst.wp);
27205+
27206+ if (tmpdst.w & 0x20) { /* toggle DQ5 */
27207+ tmpdst.w = *(volatile ushort *)(dst.wp);
27208+ if ((tmpdst.w & 0x80) != tmpsrc.w)
27209+ {
27210+ printf("program error occurred\n");
27211+ flash_write_cmd (info, sector, 0, info->cmd_reset);
27212+ return ERR_PROG_ERROR;
27213+ }
27214+ }
27215+ else if (tmpdst.w & 0x02) { /* toggle DQ1 */
27216+ tmpdst.w = *(volatile ushort *)(dst.wp);
27217+ if ((tmpdst.w & 0x80) != tmpsrc.w)
27218+ {
27219+ printf("write buffer error occurred \n");
27220+ write_buffer_abort_reset(info, sector);
27221+ return ERR_PROG_ERROR;
27222+ }
27223+ }
27224+
27225+ } while ((tmpdst.w & 0x80) != tmpsrc.w);
27226+
27227+ break;
27228+ case FLASH_CFI_32BIT:
27229+ src.lp--;
27230+ dst.lp--;
27231+ *dst.lp = (unsigned long) (AMD_CMD_BUFFER_TO_FLASH);
27232+ tmpsrc.l = *src.lp & 0x80;
27233+
27234+ do {
27235+ tmpdst.l = *(volatile ulong *)(dst.lp);
27236+
27237+ if (tmpdst.l & 0x20) { /* toggle DQ5 */
27238+ tmpdst.l = *(volatile ulong *)(dst.lp);
27239+ if ((tmpdst.l & 0x80) != tmpsrc.l)
27240+ {
27241+ printf("program error occurred\n");
27242+ flash_write_cmd (info, sector, 0, info->cmd_reset);
27243+ return ERR_PROG_ERROR;
27244+ }
27245+ }
27246+ else if (tmpdst.l & 0x02) { /* toggle DQ1 */
27247+ tmpdst.l = *(volatile ulong *)(dst.lp);
27248+ if ((tmpdst.l & 0x80) != tmpsrc.l)
27249+ {
27250+ printf("write buffer error occurred \n");
27251+ write_buffer_abort_reset(info, sector);
27252+ return ERR_PROG_ERROR;
27253+ }
27254+ }
27255+
27256+ } while ((tmpdst.l & 0x80) != tmpsrc.l);
27257+
27258+ break;
27259+ case FLASH_CFI_64BIT:
27260+ src.llp--;
27261+ dst.llp--;
27262+ *dst.llp = (unsigned long long) (AMD_CMD_BUFFER_TO_FLASH);
27263+ tmpsrc.ll = *src.llp & 0x80;
27264+
27265+ do {
27266+ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
27267+
27268+ if (tmpdst.ll & 0x20) { /* toggle DQ5 */
27269+ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
27270+ if ((tmpdst.ll & 0x80) != tmpsrc.ll)
27271+ {
27272+ printf("program error occurred\n");
27273+ flash_write_cmd (info, sector, 0, info->cmd_reset);
27274+ return ERR_PROG_ERROR;
27275+ }
27276+ }
27277+ else if (tmpdst.ll & 0x02) { /* toggle DQ1 */
27278+ tmpdst.ll = *(volatile unsigned long long *)(dst.llp);
27279+ if ((tmpdst.ll & 0x80) != tmpsrc.ll)
27280+ {
27281+ printf("write buffer error occurred \n");
27282+ write_buffer_abort_reset(info, sector);
27283+ return ERR_PROG_ERROR;
27284+ }
27285+ }
27286+
27287+ } while ((tmpdst.ll & 0x80) != tmpsrc.ll);
27288+
27289+ break;
27290+ default:
27291+ return ERR_INVAL;
27292+ break;
27293+ }
27294+
27295+ retcode =
27296+ flash_full_status_check (info, sector,
27297+ info->buffer_write_tout,
27298+ "buffer write");
27299+ }
27300+
27301+ return retcode;
27302+}
27303+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
27304+
27305+#ifdef CONFIG_FLASH_AST2300_DMA
27306+#define STCBaseAddress 0x1e620000
27307+
27308+/* for DMA */
27309+#define REG_FLASH_INTERRUPT_STATUS 0x08
27310+#define REG_FLASH_DMA_CONTROL 0x80
27311+#define REG_FLASH_DMA_FLASH_BASE 0x84
27312+#define REG_FLASH_DMA_DRAM_BASE 0x88
27313+#define REG_FLASH_DMA_LENGTH 0x8c
27314+
27315+#define FLASH_STATUS_DMA_BUSY 0x0000
27316+#define FLASH_STATUS_DMA_READY 0x0800
27317+#define FLASH_STATUS_DMA_CLEAR 0x0800
27318+
27319+#define FLASH_DMA_ENABLE 0x01
27320+
27321+void * memmove_dma(void * dest,const void *src,size_t count)
27322+{
27323+ ulong count_align, poll_time, data;
27324+
27325+ count_align = (count + 3) & 0xFFFFFFFC; /* 4-bytes align */
27326+ poll_time = 100; /* set 100 us as default */
27327+
27328+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE);
27329+
27330+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_FLASH_BASE) = (ulong *) (src);
27331+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_DRAM_BASE) = (ulong *) (dest);
27332+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_LENGTH) = (ulong) (count_align);
27333+ udelay(10);
27334+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE);
27335+
27336+ /* wait poll */
27337+ do {
27338+ udelay(poll_time);
27339+ data = *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS);
27340+ } while (!(data & FLASH_STATUS_DMA_READY));
27341+
27342+ /* clear status */
27343+ *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR;
27344+}
27345+#endif
27346+#endif /* CFG_FLASH_CFI */
27347diff --git a/board/aspeed/ast2400/flash_spi.c b/board/aspeed/ast2400/flash_spi.c
27348new file mode 100755
27349index 0000000..ad89254
27350--- /dev/null
27351+++ b/board/aspeed/ast2400/flash_spi.c
27352@@ -0,0 +1,1634 @@
27353+/*
27354+ * This program is distributed in the hope that it will be useful,
27355+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
27356+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27357+ * GNU General Public License for more details.
27358+ *
27359+ * You should have received a copy of the GNU General Public License
27360+ * along with this program; if not, write to the Free Software
27361+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27362+ * MA 02111-1307 USA
27363+ *
27364+ * History
27365+ * 01/20/2004 - combined variants of original driver.
27366+ * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
27367+ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
27368+ * 01/27/2004 - Little endian support Ed Okerson
27369+ *
27370+ * Tested Architectures
27371+ * Port Width Chip Width # of banks Flash Chip Board
27372+ * 32 16 1 28F128J3 seranoa/eagle
27373+ * 64 16 1 28F128J3 seranoa/falcon
27374+ *
27375+ */
27376+
27377+/* The DEBUG define must be before common to enable debugging */
27378+/* #define DEBUG */
27379+
27380+#include <common.h>
27381+#include <asm/processor.h>
27382+#include <asm/byteorder.h>
27383+#include <environment.h>
27384+#ifdef CONFIG_FLASH_SPI
27385+
27386+/*
27387+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
27388+ * The width of the port and the width of the chips are determined at initialization.
27389+ * These widths are used to calculate the address for access CFI data structures.
27390+ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
27391+ *
27392+ * References
27393+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
27394+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
27395+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
27396+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
27397+ *
27398+ * TODO
27399+ *
27400+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
27401+ * Table (ALT) to determine if protection is available
27402+ *
27403+ * Add support for other command sets Use the PRI and ALT to determine command set
27404+ * Verify erase and program timeouts.
27405+ */
27406+
27407+#ifndef CONFIG_FLASH_BANKS_LIST
27408+#define CONFIG_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
27409+#endif
27410+
27411+/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
27412+#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
27413+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS_DETECT] = CONFIG_FLASH_BANKS_LIST;
27414+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
27415+#else
27416+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_FLASH_BANKS_LIST;
27417+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
27418+#endif
27419+
27420+/* Support Flash ID */
27421+#define STM25P64 0x172020
27422+#define STM25P128 0x182020
27423+#define N25Q256 0x19ba20
27424+#define N25Q512 0x20ba20
27425+#define S25FL064A 0x160201
27426+#define S25FL128P 0x182001
27427+#define S25FL256S 0x190201
27428+#define W25X16 0x1530ef
27429+#define W25X64 0x1730ef
27430+#define W25Q64BV 0x1740ef
27431+#define W25Q128BV 0x1840ef
27432+#define W25Q256FV 0x1940ef
27433+#define MX25L1605D 0x1520C2
27434+#define MX25L12805D 0x1820C2
27435+#define MX25L25635E 0x1920C2
27436+#define SST25VF016B 0x4125bf
27437+#define SST25VF064C 0x4b25bf
27438+#define AT25DF161 0x02461F
27439+#define AT25DF321 0x01471F
27440+
27441+/* SPI Define */
27442+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
27443+#if defined(CONFIG_AST1300)
27444+#define STCBaseAddress 0x00620000
27445+#else
27446+#define STCBaseAddress 0x1e620000
27447+#endif
27448+#define SCU_REVISION_REGISTER 0x1e6e207c
27449+#define SCU_CACHE_CTRL_REGISTER 0x1e6e2118
27450+
27451+#define SPICtrlRegOffset 0x10
27452+#define SPICtrlRegOffset2 0x14
27453+
27454+#define SPIMiscCtrlRegOffset 0x54
27455+
27456+/* for DMA */
27457+#define REG_FLASH_INTERRUPT_STATUS 0x08
27458+#define REG_FLASH_DMA_CONTROL 0x80
27459+#define REG_FLASH_DMA_FLASH_BASE 0x84
27460+#define REG_FLASH_DMA_DRAM_BASE 0x88
27461+#define REG_FLASH_DMA_LENGTH 0x8c
27462+
27463+#define FLASH_STATUS_DMA_BUSY 0x0000
27464+#define FLASH_STATUS_DMA_READY 0x0800
27465+#define FLASH_STATUS_DMA_CLEAR 0x0800
27466+
27467+#define FLASH_DMA_ENABLE 0x01
27468+#else
27469+#define STCBaseAddress 0x16000000
27470+
27471+#define SPICtrlRegOffset 0x04
27472+#define SPICtrlRegOffset2 0x0C
27473+#endif /* CONFIG_FLASH_AST2300 */
27474+
27475+#define CMD_MASK 0xFFFFFFF8
27476+
27477+#define NORMALREAD 0x00
27478+#define FASTREAD 0x01
27479+#define NORMALWRITE 0x02
27480+#define USERMODE 0x03
27481+
27482+#define CE_LOW 0x00
27483+#define CE_HIGH 0x04
27484+
27485+/* AST2300 only */
27486+#define IOMODEx1 0x00000000
27487+#define IOMODEx2 0x20000000
27488+#define IOMODEx2_dummy 0x30000000
27489+#define IOMODEx4 0x40000000
27490+#define IOMODEx4_dummy 0x50000000
27491+
27492+#define DUMMY_COMMAND_OUT 0x00008000
27493+/* ~AST2300 only */
27494+
27495+/* specificspi */
27496+#define SpecificSPI_N25Q512 0x00000001
27497+
27498+static ulong AST2300_SPICLK_DIV[16] = {0x0F, 0x07, 0x0E, 0x06, 0x0D, 0x05, 0x0C, 0x04, \
27499+ 0x0B, 0x03, 0x0A, 0x02, 0x09, 0x01, 0x08, 0x00 };
27500+
27501+/*-----------------------------------------------------------------------
27502+ * Functions
27503+ */
27504+static void reset_flash (flash_info_t * info);
27505+static void enable_write (flash_info_t * info);
27506+static void write_status_register (flash_info_t * info, uchar data);
27507+static void enable4b (flash_info_t * info);
27508+static void enable4b_spansion (flash_info_t * info);
27509+static void enable4b_numonyx (flash_info_t * info);
27510+static ulong flash_get_size (ulong base, int banknum);
27511+static int flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len);
27512+#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
27513+static flash_info_t *flash_get_info(ulong base);
27514+#endif
27515+
27516+
27517+/*-----------------------------------------------------------------------
27518+ * create an address based on the offset and the port width
27519+ */
27520+inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
27521+{
27522+#ifdef CONFIG_2SPIFLASH
27523+ if (info->start[0] >= PHYS_FLASH_2)
27524+ return ((uchar *) (info->start[sect] + (offset * 1) - (PHYS_FLASH_2 - PHYS_FLASH_2_BASE) ));
27525+ else
27526+ return ((uchar *) (info->start[sect] + (offset * 1)));
27527+#else
27528+ return ((uchar *) (info->start[sect] + (offset * 1)));
27529+#endif
27530+}
27531+
27532+/*-----------------------------------------------------------------------
27533+ * read a character at a port width address
27534+ */
27535+inline uchar flash_read_uchar (flash_info_t * info, uint offset)
27536+{
27537+ uchar *cp;
27538+
27539+ cp = flash_make_addr (info, 0, offset);
27540+#if defined(__LITTLE_ENDIAN)
27541+ return (cp[0]);
27542+#else
27543+ return (cp[1 - 1]);
27544+#endif
27545+}
27546+
27547+/*-----------------------------------------------------------------------
27548+ * read a short word by swapping for ppc format.
27549+ */
27550+ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
27551+{
27552+ uchar *addr;
27553+ ushort retval;
27554+
27555+#ifdef DEBUG
27556+ int x;
27557+#endif
27558+ addr = flash_make_addr (info, sect, offset);
27559+
27560+#ifdef DEBUG
27561+ debug ("ushort addr is at %p 1 = %d\n", addr,
27562+ 1);
27563+ for (x = 0; x < 2 * 1; x++) {
27564+ debug ("addr[%x] = 0x%x\n", x, addr[x]);
27565+ }
27566+#endif
27567+#if defined(__LITTLE_ENDIAN)
27568+ retval = ((addr[(1)] << 8) | addr[0]);
27569+#else
27570+ retval = ((addr[(2 * 1) - 1] << 8) |
27571+ addr[1 - 1]);
27572+#endif
27573+
27574+ debug ("retval = 0x%x\n", retval);
27575+ return retval;
27576+}
27577+
27578+/*-----------------------------------------------------------------------
27579+ * read a long word by picking the least significant byte of each maiximum
27580+ * port size word. Swap for ppc format.
27581+ */
27582+ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
27583+{
27584+ uchar *addr;
27585+ ulong retval;
27586+
27587+#ifdef DEBUG
27588+ int x;
27589+#endif
27590+ addr = flash_make_addr (info, sect, offset);
27591+
27592+#ifdef DEBUG
27593+ debug ("long addr is at %p 1 = %d\n", addr,
27594+ 1);
27595+ for (x = 0; x < 4 * 1; x++) {
27596+ debug ("addr[%x] = 0x%x\n", x, addr[x]);
27597+ }
27598+#endif
27599+#if defined(__LITTLE_ENDIAN)
27600+ retval = (addr[0] << 16) | (addr[(1)] << 24) |
27601+ (addr[(2 * 1)]) | (addr[(3 * 1)] << 8);
27602+#else
27603+ retval = (addr[(2 * 1) - 1] << 24) |
27604+ (addr[(1) - 1] << 16) |
27605+ (addr[(4 * 1) - 1] << 8) |
27606+ addr[(3 * 1) - 1];
27607+#endif
27608+ return retval;
27609+}
27610+
27611+/*-----------------------------------------------------------------------
27612+ */
27613+static void disable_cache(void)
27614+{
27615+#if defined(AST1300_CPU_CACHE_ENABLE)
27616+ ulong uldata;
27617+
27618+ uldata = *(volatile ulong *) (SCU_CACHE_CTRL_REGISTER);
27619+ uldata &= 0xfffffffd;
27620+ *(ulong *) (SCU_CACHE_CTRL_REGISTER) = uldata;
27621+#endif
27622+}
27623+
27624+static void enable_cache(void)
27625+{
27626+#if defined(AST1300_CPU_CACHE_ENABLE)
27627+ ulong uldata;
27628+
27629+ uldata = *(volatile ulong *) (SCU_CACHE_CTRL_REGISTER);
27630+ uldata |= 0x00000002;
27631+ *(ulong *) (SCU_CACHE_CTRL_REGISTER) = uldata;
27632+#endif
27633+}
27634+
27635+static void reset_flash (flash_info_t * info)
27636+{
27637+ ulong ulCtrlData, CtrlOffset, MiscCtrlOffset;
27638+
27639+ if (info->CE == 2)
27640+ {
27641+ CtrlOffset = SPICtrlRegOffset2;
27642+ }
27643+ else
27644+ {
27645+ CtrlOffset = SPICtrlRegOffset;
27646+ }
27647+
27648+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
27649+ ulCtrlData = info->iomode | (info->readcmd << 16) | (info->tCK_Read << 8) | (info->dummybyte << 6) | FASTREAD;
27650+#if 0
27651+ if (info->quadport)
27652+ {
27653+ MiscCtrlOffset = SPIMiscCtrlRegOffset;
27654+ *(ulong *) (STCBaseAddress + MiscCtrlOffset) = info->dummydata;
27655+ ulCtrlData |= DUMMY_COMMAND_OUT;
27656+ }
27657+#endif
27658+#else
27659+ ulCtrlData = (info->readcmd << 16) | (info->tCK_Read << 8) | (info->dummybyte << 6) | FASTREAD;
27660+ if (info->dualport)
27661+ ulCtrlData |= 0x08;
27662+#endif
27663+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27664+
27665+ enable_cache();
27666+}
27667+
27668+static void enable_write (flash_info_t * info)
27669+{
27670+ ulong base;
27671+ ulong ulCtrlData, CtrlOffset;
27672+ uchar jReg;
27673+
27674+ if (info->CE == 2)
27675+ {
27676+ CtrlOffset = SPICtrlRegOffset2;
27677+ }
27678+ else
27679+ {
27680+ CtrlOffset = SPICtrlRegOffset;
27681+ }
27682+
27683+ //base = info->start[0];
27684+ base = flash_make_addr (info, 0, 0);
27685+
27686+ ulCtrlData = (info->tCK_Write << 8);
27687+ ulCtrlData |= CE_LOW | USERMODE;
27688+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27689+ udelay(200);
27690+ *(uchar *) (base) = (uchar) (0x06);
27691+ udelay(10);
27692+ ulCtrlData &= CMD_MASK;
27693+ ulCtrlData |= CE_HIGH | USERMODE;
27694+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27695+ udelay(200);
27696+
27697+ ulCtrlData &= CMD_MASK;
27698+ ulCtrlData |= CE_LOW | USERMODE;
27699+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27700+ udelay(200);
27701+ *(uchar *) (base) = (uchar) (0x05);
27702+ udelay(10);
27703+ do {
27704+ jReg = *(volatile uchar *) (base);
27705+ } while (!(jReg & 0x02));
27706+ ulCtrlData &= CMD_MASK;
27707+ ulCtrlData |= CE_HIGH | USERMODE;
27708+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27709+ udelay(200);
27710+
27711+}
27712+
27713+static void write_status_register (flash_info_t * info, uchar data)
27714+{
27715+ ulong base;
27716+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
27717+ uchar jReg;
27718+
27719+ if (info->CE == 2)
27720+ {
27721+ CtrlOffset = SPICtrlRegOffset2;
27722+ }
27723+ else
27724+ {
27725+ CtrlOffset = SPICtrlRegOffset;
27726+ }
27727+
27728+ //base = info->start[0];
27729+ base = flash_make_addr (info, 0, 0);
27730+
27731+ enable_write (info);
27732+
27733+ ulCtrlData = (info->tCK_Write << 8);
27734+ ulCtrlData |= CE_LOW | USERMODE;
27735+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27736+ udelay(200);
27737+ *(uchar *) (base) = (uchar) (0x01);
27738+ udelay(10);
27739+ *(uchar *) (base) = (uchar) (data);
27740+ ulCtrlData &= CMD_MASK;
27741+ ulCtrlData |= CE_HIGH | USERMODE;
27742+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27743+ udelay(200);
27744+
27745+ ulCtrlData &= CMD_MASK;
27746+ ulCtrlData |= CE_LOW | USERMODE;
27747+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27748+ udelay(200);
27749+ *(uchar *) (base) = (uchar) (0x05);
27750+ udelay(10);
27751+ do {
27752+ jReg = *(volatile uchar *) (base);
27753+ } while (jReg & 0x01);
27754+ ulCtrlData &= CMD_MASK;
27755+ ulCtrlData |= CE_HIGH | USERMODE;
27756+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27757+ udelay(200);
27758+
27759+}
27760+
27761+static void enable4b (flash_info_t * info)
27762+{
27763+ ulong base;
27764+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
27765+ uchar jReg;
27766+
27767+ if (info->CE == 2)
27768+ {
27769+ CtrlOffset = SPICtrlRegOffset2;
27770+ }
27771+ else
27772+ {
27773+ CtrlOffset = SPICtrlRegOffset;
27774+ }
27775+
27776+ //base = info->start[0];
27777+ base = flash_make_addr (info, 0, 0);
27778+
27779+ ulCtrlData = (info->tCK_Write << 8);
27780+ ulCtrlData |= CE_LOW | USERMODE;
27781+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27782+ udelay(200);
27783+ *(uchar *) (base) = (uchar) (0xb7);
27784+ ulCtrlData &= CMD_MASK;
27785+ ulCtrlData |= CE_HIGH | USERMODE;
27786+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27787+ udelay(200);
27788+
27789+} /* enable4b */
27790+
27791+static void enable4b_spansion (flash_info_t * info)
27792+{
27793+ ulong base;
27794+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
27795+ uchar jReg;
27796+
27797+ if (info->CE == 2)
27798+ {
27799+ CtrlOffset = SPICtrlRegOffset2;
27800+ }
27801+ else
27802+ {
27803+ CtrlOffset = SPICtrlRegOffset;
27804+ }
27805+
27806+ //base = info->start[0];
27807+ base = flash_make_addr (info, 0, 0);
27808+
27809+ /* Enable 4B: BAR0 D[7] = 1 */
27810+ ulCtrlData = (info->tCK_Write << 8);
27811+ ulCtrlData |= CE_LOW | USERMODE;
27812+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27813+ udelay(200);
27814+ *(uchar *) (base) = (uchar) (0x17);
27815+ udelay(10);
27816+ *(uchar *) (base) = (uchar) (0x80);
27817+ ulCtrlData &= CMD_MASK;
27818+ ulCtrlData |= CE_HIGH | USERMODE;
27819+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27820+ udelay(200);
27821+
27822+ ulCtrlData &= CMD_MASK;
27823+ ulCtrlData |= CE_LOW | USERMODE;
27824+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27825+ udelay(200);
27826+ *(uchar *) (base) = (uchar) (0x16);
27827+ udelay(10);
27828+ do {
27829+ jReg = *(volatile uchar *) (base);
27830+ } while (!(jReg & 0x80));
27831+ ulCtrlData &= CMD_MASK;
27832+ ulCtrlData |= CE_HIGH | USERMODE;
27833+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27834+ udelay(200);
27835+
27836+} /* enable4b_spansion */
27837+
27838+static void enable4b_numonyx (flash_info_t * info)
27839+{
27840+ ulong base;
27841+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
27842+ uchar jReg;
27843+
27844+ if (info->CE == 2)
27845+ {
27846+ CtrlOffset = SPICtrlRegOffset2;
27847+ }
27848+ else
27849+ {
27850+ CtrlOffset = SPICtrlRegOffset;
27851+ }
27852+
27853+ //base = info->start[0];
27854+ base = flash_make_addr (info, 0, 0);
27855+
27856+ /* Enable Write */
27857+ enable_write (info);
27858+
27859+ /* Enable 4B: CMD:0xB7 */
27860+ ulCtrlData = (info->tCK_Write << 8);
27861+ ulCtrlData |= CE_LOW | USERMODE;
27862+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27863+ udelay(200);
27864+ *(uchar *) (base) = (uchar) (0xB7);
27865+ udelay(10);
27866+ ulCtrlData &= CMD_MASK;
27867+ ulCtrlData |= CE_HIGH | USERMODE;
27868+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27869+ udelay(200);
27870+
27871+} /* enable4b_numonyx */
27872+
27873+/*
27874+ *
27875+ */
27876+static ulong flash_get_size (ulong base, int banknum)
27877+{
27878+ flash_info_t *info = &flash_info[banknum];
27879+ int j;
27880+ unsigned long sector;
27881+ int erase_region_size;
27882+ ulong ulCtrlData, CtrlOffset;
27883+ ulong ulID;
27884+ uchar ch[3];
27885+ ulong cpuclk, div, reg;
27886+ ulong WriteClk, EraseClk, ReadClk;
27887+ ulong vbase;
27888+ ulong SCURevision;
27889+
27890+ ulong ulRefPLL;
27891+ ulong ulDeNumerator;
27892+ ulong ulNumerator;
27893+ ulong ulOD;
27894+
27895+ disable_cache();
27896+
27897+ info->start[0] = base;
27898+ vbase = flash_make_addr (info, 0, 0);
27899+
27900+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
27901+ CtrlOffset = SPICtrlRegOffset;
27902+ info->CE = 0;
27903+#else
27904+ if (vbase == PHYS_FLASH_1)
27905+ {
27906+ CtrlOffset = SPICtrlRegOffset2;
27907+ info->CE = 2;
27908+ }
27909+ else
27910+ {
27911+ CtrlOffset = SPICtrlRegOffset;
27912+ info->CE = 0;
27913+ }
27914+#endif
27915+
27916+ /* Get Flash ID */
27917+ ulCtrlData = *(ulong *) (STCBaseAddress + CtrlOffset) & CMD_MASK;
27918+ ulCtrlData |= CE_LOW | USERMODE;
27919+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27920+ udelay(200);
27921+ *(uchar *) (vbase) = (uchar) (0x9F);
27922+ udelay(10);
27923+ ch[0] = *(volatile uchar *)(vbase);
27924+ udelay(10);
27925+ ch[1] = *(volatile uchar *)(vbase);
27926+ udelay(10);
27927+ ch[2] = *(volatile uchar *)(vbase);
27928+ udelay(10);
27929+ ulCtrlData = *(ulong *) (STCBaseAddress + CtrlOffset) & CMD_MASK;
27930+ ulCtrlData |= CE_HIGH | USERMODE;
27931+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
27932+ udelay(200);
27933+ ulID = ((ulong)ch[0]) | ((ulong)ch[1] << 8) | ((ulong)ch[2] << 16) ;
27934+ info->flash_id = ulID;
27935+
27936+ //printf("SPI Flash ID: %x \n", ulID);
27937+
27938+ /* init default */
27939+ info->iomode = IOMODEx1;
27940+ info->address32 = 0;
27941+ info->quadport = 0;
27942+ info->specificspi = 0;
27943+
27944+ switch (info->flash_id)
27945+ {
27946+ case STM25P64:
27947+ info->sector_count = 128;
27948+ info->size = 0x800000;
27949+ erase_region_size = 0x10000;
27950+ info->readcmd = 0x0b;
27951+ info->dualport = 0;
27952+ info->dummybyte = 1;
27953+ info->buffersize = 256;
27954+ WriteClk = 40;
27955+ EraseClk = 20;
27956+ ReadClk = 40;
27957+ break;
27958+
27959+ case STM25P128:
27960+ info->sector_count = 64;
27961+ info->size = 0x1000000;
27962+ erase_region_size = 0x40000;
27963+ info->readcmd = 0x0b;
27964+ info->dualport = 0;
27965+ info->dummybyte = 1;
27966+ info->buffersize = 256;
27967+ WriteClk = 50;
27968+ EraseClk = 20;
27969+ ReadClk = 50;
27970+ break;
27971+
27972+ case N25Q256:
27973+ info->sector_count = 256;
27974+ info->size = 0x1000000;
27975+ erase_region_size = 0x10000;
27976+ info->readcmd = 0x0b;
27977+ info->dualport = 0;
27978+ info->dummybyte = 1;
27979+ info->buffersize = 256;
27980+ WriteClk = 50;
27981+ EraseClk = 20;
27982+ ReadClk = 50;
27983+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
27984+ info->sector_count = 512;
27985+ info->size = 0x2000000;
27986+ info->address32 = 1;
27987+#endif
27988+ break;
27989+
27990+ case N25Q512:
27991+ info->sector_count = 256;
27992+ info->size = 0x1000000;
27993+ erase_region_size = 0x10000;
27994+ info->readcmd = 0x0b;
27995+ info->dualport = 0;
27996+ info->dummybyte = 1;
27997+ info->buffersize = 256;
27998+ info->specificspi = SpecificSPI_N25Q512;
27999+ WriteClk = 50;
28000+ EraseClk = 20;
28001+ ReadClk = 50;
28002+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
28003+ info->sector_count = 1024;
28004+ info->size = 0x4000000;
28005+ info->address32 = 1;
28006+#endif
28007+ break;
28008+
28009+ case W25X16:
28010+ info->sector_count = 32;
28011+ info->size = 0x200000;
28012+ erase_region_size = 0x10000;
28013+ info->readcmd = 0x3b;
28014+ info->dualport = 1;
28015+ info->dummybyte = 1;
28016+ info->iomode = IOMODEx2;
28017+ info->buffersize = 256;
28018+ WriteClk = 50;
28019+ EraseClk = 25;
28020+ ReadClk = 50;
28021+ break;
28022+
28023+ case W25X64:
28024+ info->sector_count = 128;
28025+ info->size = 0x800000;
28026+ erase_region_size = 0x10000;
28027+ info->readcmd = 0x3b;
28028+ info->dualport = 1;
28029+ info->dummybyte = 1;
28030+ info->iomode = IOMODEx2;
28031+ info->buffersize = 256;
28032+ WriteClk = 50;
28033+ EraseClk = 25;
28034+ ReadClk = 50;
28035+ break;
28036+
28037+ case W25Q64BV:
28038+ info->sector_count = 128;
28039+ info->size = 0x800000;
28040+ erase_region_size = 0x10000;
28041+ info->readcmd = 0x3b;
28042+ info->dualport = 1;
28043+ info->dummybyte = 1;
28044+ info->iomode = IOMODEx2;
28045+ info->buffersize = 256;
28046+ WriteClk = 80;
28047+ EraseClk = 40;
28048+ ReadClk = 80;
28049+ break;
28050+
28051+ case W25Q128BV:
28052+ info->sector_count = 256;
28053+ info->size = 0x1000000;
28054+ erase_region_size = 0x10000;
28055+ info->readcmd = 0x3b;
28056+ info->dualport = 1;
28057+ info->dummybyte = 1;
28058+ info->iomode = IOMODEx2;
28059+ info->buffersize = 256;
28060+ WriteClk = 104;
28061+ EraseClk = 50;
28062+ ReadClk = 104;
28063+ break;
28064+
28065+ case W25Q256FV:
28066+ info->sector_count = 256;
28067+ info->size = 0x1000000;
28068+ erase_region_size = 0x10000;
28069+ info->readcmd = 0x0b;
28070+ info->dualport = 0;
28071+ info->dummybyte = 1;
28072+ info->buffersize = 256;
28073+ WriteClk = 50;
28074+ EraseClk = 20;
28075+ ReadClk = 50;
28076+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
28077+ info->sector_count = 512;
28078+ info->size = 0x2000000;
28079+ info->address32 = 1;
28080+#endif
28081+ break;
28082+
28083+ case S25FL064A:
28084+ info->sector_count = 128;
28085+ info->size = 0x800000;
28086+ erase_region_size = 0x10000;
28087+ info->readcmd = 0x0b;
28088+ info->dualport = 0;
28089+ info->dummybyte = 1;
28090+ info->buffersize = 256;
28091+ WriteClk = 50;
28092+ EraseClk = 25;
28093+ ReadClk = 50;
28094+ break;
28095+
28096+ case S25FL128P:
28097+ info->sector_count = 256;
28098+ info->size = 0x1000000;
28099+ erase_region_size = 0x10000;
28100+ info->readcmd = 0x0b;
28101+ info->dualport = 0;
28102+ info->dummybyte = 1;
28103+ info->buffersize = 256;
28104+ WriteClk = 100;
28105+ EraseClk = 40;
28106+ ReadClk = 100;
28107+ break;
28108+
28109+ case S25FL256S:
28110+ info->sector_count = 256;
28111+ info->size = 0x1000000;
28112+ erase_region_size = 0x10000;
28113+ info->readcmd = 0x0b;
28114+ info->dualport = 0;
28115+ info->dummybyte = 1;
28116+ info->buffersize = 256;
28117+ WriteClk = 50;
28118+ EraseClk = 20;
28119+ ReadClk = 50;
28120+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
28121+ info->sector_count = 512;
28122+ info->size = 0x2000000;
28123+ info->address32 = 1;
28124+#endif
28125+ break;
28126+
28127+ case MX25L25635E:
28128+ info->sector_count = 256;
28129+ info->size = 0x1000000;
28130+ erase_region_size = 0x10000;
28131+ info->readcmd = 0x0b;
28132+ info->dualport = 0;
28133+ info->dummybyte = 1;
28134+ info->buffersize = 256;
28135+ WriteClk = 50;
28136+ EraseClk = 20;
28137+ ReadClk = 50;
28138+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
28139+ info->sector_count = 512;
28140+ info->size = 0x2000000;
28141+ info->address32 = 1;
28142+#if defined(CONFIG_FLASH_SPIx2_Dummy)
28143+ info->readcmd = 0xbb;
28144+ info->dummybyte = 1;
28145+ info->dualport = 1;
28146+ info->iomode = IOMODEx2_dummy;
28147+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
28148+ info->readcmd = 0xeb;
28149+ info->dummybyte = 3;
28150+ info->dualport = 0;
28151+ info->iomode = IOMODEx4_dummy;
28152+ info->quadport = 1;
28153+ info->dummydata = 0xaa;
28154+#endif
28155+#endif
28156+ break;
28157+
28158+ case MX25L12805D:
28159+ info->sector_count = 256;
28160+ info->size = 0x1000000;
28161+ erase_region_size = 0x10000;
28162+ info->readcmd = 0x0b;
28163+ info->dualport = 0;
28164+ info->dummybyte = 1;
28165+ info->buffersize = 256;
28166+/*
28167+SCU7C: Silicon Revision ID Register
28168+D[31:24]: Chip ID
28169+0: AST2050/AST2100/AST2150/AST2200/AST3000
28170+1: AST2300
28171+
28172+D[23:16] Silicon revision ID for AST2300 generation and later
28173+0: A0
28174+1: A1
28175+2: A2
28176+.
28177+.
28178+.
28179+FPGA revision starts from 0x80
28180+
28181+AST2300 A0 SPI can't run faster than 50Mhz
28182+*/
28183+ WriteClk = 50;
28184+ EraseClk = 20;
28185+ ReadClk = 50;
28186+
28187+ SCURevision = *(ulong *) (SCU_REVISION_REGISTER);
28188+ if (((SCURevision >> 24) & 0xff) == 0x01) { //AST2300
28189+ if (((SCURevision >> 16) & 0xff) == 0x00) { //A0
28190+ WriteClk = 25;
28191+ EraseClk = 20;
28192+ ReadClk = 25;
28193+ }
28194+ }
28195+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
28196+#if defined(CONFIG_FLASH_SPIx2_Dummy)
28197+ info->readcmd = 0xbb;
28198+ info->dummybyte = 1;
28199+ info->dualport = 1;
28200+ info->iomode = IOMODEx2_dummy;
28201+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
28202+ info->readcmd = 0xeb;
28203+ info->dummybyte = 3;
28204+ info->dualport = 0;
28205+ info->iomode = IOMODEx4_dummy;
28206+ info->quadport = 1;
28207+ info->dummydata = 0xaa;
28208+#endif
28209+#endif
28210+ break;
28211+
28212+ case MX25L1605D:
28213+ info->sector_count = 32;
28214+ info->size = 0x200000;
28215+ erase_region_size = 0x10000;
28216+ info->readcmd = 0x0b;
28217+ info->dualport = 0;
28218+ info->dummybyte = 1;
28219+ info->buffersize = 256;
28220+ WriteClk = 50;
28221+ EraseClk = 20;
28222+ ReadClk = 50;
28223+ break;
28224+
28225+ case SST25VF016B:
28226+ info->sector_count = 32;
28227+ info->size = 0x200000;
28228+ erase_region_size = 0x10000;
28229+ info->readcmd = 0x0b;
28230+ info->dualport = 0;
28231+ info->dummybyte = 1;
28232+ info->buffersize = 1;
28233+ WriteClk = 50;
28234+ EraseClk = 25;
28235+ ReadClk = 50;
28236+ break;
28237+
28238+ case SST25VF064C:
28239+ info->sector_count = 128;
28240+ info->size = 0x800000;
28241+ erase_region_size = 0x10000;
28242+ info->readcmd = 0x0b;
28243+ info->dualport = 0;
28244+ info->dummybyte = 1;
28245+ info->buffersize = 1;
28246+ WriteClk = 50;
28247+ EraseClk = 25;
28248+ ReadClk = 50;
28249+ break;
28250+
28251+ case AT25DF161:
28252+ info->sector_count = 32;
28253+ info->size = 0x200000;
28254+ erase_region_size = 0x10000;
28255+ info->readcmd = 0x0b;
28256+ info->dualport = 0;
28257+ info->dummybyte = 1;
28258+ info->buffersize = 1;
28259+ WriteClk = 50;
28260+ EraseClk = 25;
28261+ ReadClk = 50;
28262+ break;
28263+
28264+ case AT25DF321:
28265+ info->sector_count = 32;
28266+ info->size = 0x400000;
28267+ erase_region_size = 0x10000;
28268+ info->readcmd = 0x0b;
28269+ info->dualport = 0;
28270+ info->dummybyte = 1;
28271+ info->buffersize = 1;
28272+ WriteClk = 50;
28273+ EraseClk = 25;
28274+ ReadClk = 50;
28275+ break;
28276+
28277+ default: /* use JEDEC ID */
28278+ erase_region_size = 0x10000;
28279+ info->readcmd = 0x0b;
28280+ info->dualport = 0;
28281+ info->dummybyte = 1;
28282+ info->buffersize = 1;
28283+ WriteClk = 50;
28284+ EraseClk = 25;
28285+ ReadClk = 50;
28286+ if ((info->flash_id & 0xFF) == 0x1F) /* Atmel */
28287+ {
28288+ switch (info->flash_id & 0x001F00)
28289+ {
28290+ case 0x000400:
28291+ info->sector_count = 8;
28292+ info->size = 0x80000;
28293+ break;
28294+ case 0x000500:
28295+ info->sector_count = 16;
28296+ info->size = 0x100000;
28297+ break;
28298+ case 0x000600:
28299+ info->sector_count = 32;
28300+ info->size = 0x200000;
28301+ break;
28302+ case 0x000700:
28303+ info->sector_count = 64;
28304+ info->size = 0x400000;
28305+ break;
28306+ case 0x000800:
28307+ info->sector_count = 128;
28308+ info->size = 0x800000;
28309+ break;
28310+ case 0x000900:
28311+ info->sector_count = 256;
28312+ info->size = 0x1000000;
28313+ break;
28314+ default:
28315+ printf("Can't support this SPI Flash!! \n");
28316+ return 0;
28317+ }
28318+ } /* Atmel JDEC */
28319+ else /* JDEC */
28320+ {
28321+ switch (info->flash_id & 0xFF0000)
28322+ {
28323+ case 0x120000:
28324+ info->sector_count = 4;
28325+ info->size = 0x40000;
28326+ break;
28327+ case 0x130000:
28328+ info->sector_count = 8;
28329+ info->size = 0x80000;
28330+ break;
28331+ case 0x140000:
28332+ info->sector_count =16;
28333+ info->size = 0x100000;
28334+ break;
28335+ case 0x150000:
28336+ info->sector_count =32;
28337+ info->size = 0x200000;
28338+ break;
28339+ case 0x160000:
28340+ info->sector_count =64;
28341+ info->size = 0x400000;
28342+ break;
28343+ case 0x170000:
28344+ info->sector_count =128;
28345+ info->size = 0x800000;
28346+ break;
28347+ case 0x180000:
28348+ info->sector_count =256;
28349+ info->size = 0x1000000;
28350+ break;
28351+ case 0x190000:
28352+ info->sector_count =256;
28353+ info->size = 0x1000000;
28354+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
28355+ info->sector_count = 512;
28356+ info->size = 0x2000000;
28357+ info->address32 = 1;
28358+#if defined(CONFIG_FLASH_SPIx2_Dummy)
28359+ info->readcmd = 0xbb;
28360+ info->dummybyte = 1;
28361+ info->dualport = 1;
28362+ info->iomode = IOMODEx2_dummy;
28363+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
28364+ info->readcmd = 0xeb;
28365+ info->dummybyte = 3;
28366+ info->dualport = 0;
28367+ info->iomode = IOMODEx4_dummy;
28368+ info->quadport = 1;
28369+ info->dummydata = 0xaa;
28370+#endif
28371+#endif
28372+ break;
28373+
28374+ case 0x200000:
28375+ info->sector_count =256;
28376+ info->size = 0x1000000;
28377+ if ((info->flash_id & 0xFF) == 0x20) /* numonyx */
28378+ info->specificspi = SpecificSPI_N25Q512;
28379+#if defined(CONFIG_FLASH_AST2300) || defined(CONFIG_AST1300)
28380+ info->sector_count = 1024;
28381+ info->size = 0x4000000;
28382+ info->address32 = 1;
28383+#if defined(CONFIG_FLASH_SPIx2_Dummy)
28384+ info->readcmd = 0xbb;
28385+ info->dummybyte = 1;
28386+ info->dualport = 1;
28387+ info->iomode = IOMODEx2_dummy;
28388+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
28389+ info->readcmd = 0xeb;
28390+ info->dummybyte = 3;
28391+ info->dualport = 0;
28392+ info->iomode = IOMODEx4_dummy;
28393+ info->quadport = 1;
28394+ info->dummydata = 0xaa;
28395+#endif
28396+#endif
28397+ break;
28398+
28399+ default:
28400+ printf("Can't support this SPI Flash!! \n");
28401+ return 0;
28402+ }
28403+ } /* JDEC */
28404+ }
28405+
28406+ debug ("erase_region_count = %d erase_region_size = %d\n",
28407+ erase_region_count, erase_region_size);
28408+
28409+ sector = base;
28410+ for (j = 0; j < info->sector_count; j++) {
28411+
28412+ info->start[j] = sector;
28413+ sector += erase_region_size;
28414+ info->protect[j] = 0; /* default: not protected */
28415+ }
28416+
28417+ /* set SPI flash extended info */
28418+#if defined(CONFIG_AST1300)
28419+ if (info->size > 0x200000) /* limit MAX Flash to 2MB for AST1300 */
28420+ info->size = 0x200000;
28421+#endif
28422+#if defined(CONFIG_AST2400) || defined(CONFIG_AST2300) || defined(CONFIG_AST2300_FPGA_1) || defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST1300)
28423+ reg = *((volatile ulong*) 0x1e6e2024);
28424+ if (reg & 0x40000)
28425+ {
28426+ reg = *((volatile ulong*) 0x1e6e2070);
28427+
28428+ ulRefPLL = 24;
28429+ ulDeNumerator = reg & 0x0F;
28430+ ulNumerator = (reg & 0x07E0) >> 5;
28431+ ulOD = (reg & 0x10) ? 1:2;
28432+
28433+ cpuclk = ulRefPLL * ulOD * (ulNumerator + 2) / (ulDeNumerator + 1);
28434+ }
28435+ else
28436+ {
28437+ reg = *((volatile ulong*) 0x1e6e2070);
28438+#if defined(CONFIG_AST2400)
28439+ if (reg & 0x00800000) //ref. clk:25MHz
28440+ {
28441+ switch (reg & 0x300)
28442+ {
28443+ case 0x000:
28444+ cpuclk = 400;
28445+ break;
28446+ case 0x100:
28447+ cpuclk = 375;
28448+ break;
28449+ case 0x200:
28450+ cpuclk = 350;
28451+ break;
28452+ case 0x300:
28453+ cpuclk = 325;
28454+ break;
28455+ }
28456+ }
28457+ else
28458+ {
28459+ switch (reg & 0x300) //ref. clk:24MHz
28460+ {
28461+ case 0x000:
28462+ cpuclk = 384;
28463+ break;
28464+ case 0x100:
28465+ cpuclk = 360;
28466+ break;
28467+ case 0x200:
28468+ cpuclk = 336;
28469+ break;
28470+ case 0x300:
28471+ cpuclk = 312;
28472+ break;
28473+ }
28474+ }
28475+#else
28476+ switch (reg & 0x300)
28477+ {
28478+ case 0x000:
28479+ cpuclk = 384;
28480+ break;
28481+ case 0x100:
28482+ cpuclk = 360;
28483+ break;
28484+ case 0x200:
28485+ cpuclk = 336;
28486+ break;
28487+ case 0x300:
28488+ cpuclk = 408;
28489+ break;
28490+ }
28491+#endif
28492+ }
28493+
28494+ reg = *((volatile ulong*) 0x1e6e2070);
28495+ switch (reg & 0xc00)
28496+ {
28497+ case 0x000:
28498+ cpuclk /= 1;
28499+ break;
28500+ case 0x400:
28501+ cpuclk /= 2;
28502+ break;
28503+ case 0x800:
28504+ cpuclk /= 4;
28505+ break;
28506+ case 0xC00:
28507+ cpuclk /= 3;
28508+ break;
28509+ }
28510+#else /* AST2100 */
28511+ reg = *((volatile ulong*) 0x1e6e2070);
28512+ switch (reg & 0xe00)
28513+ {
28514+ case 0x000:
28515+ cpuclk = 266;
28516+ break;
28517+ case 0x200:
28518+ cpuclk = 233;
28519+ break;
28520+ case 0x400:
28521+ cpuclk = 200;
28522+ break;
28523+ case 0x600:
28524+ cpuclk = 166;
28525+ break;
28526+ case 0x800:
28527+ cpuclk = 133;
28528+ break;
28529+ case 0xA00:
28530+ cpuclk = 100;
28531+ break;
28532+ case 0xC00:
28533+ cpuclk = 300;
28534+ break;
28535+ case 0xE00:
28536+ cpuclk = 24;
28537+ break;
28538+ }
28539+ switch (reg & 0x3000)
28540+ {
28541+ case 0x1000:
28542+ cpuclk /= 2;
28543+ break;
28544+ case 0x2000:
28545+ cpuclk /= 4;
28546+ break;
28547+ case 0x3000:
28548+ cpuclk /= 3;
28549+ break;
28550+ }
28551+#endif
28552+
28553+#if defined(CONFIG_AST2400) || defined(CONFIG_AST2300) || defined(CONFIG_AST2300_FPGA_1) || defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST1300)
28554+
28555+#if defined(CONFIG_AST2300) || defined(CONFIG_AST1300)
28556+ /* limit Max SPI CLK to 50MHz (Datasheet v1.2) */
28557+ if (WriteClk > 50) WriteClk = 50;
28558+ if (EraseClk > 50) EraseClk = 50;
28559+ if (ReadClk > 50) ReadClk = 50;
28560+#endif
28561+
28562+ div = 1;
28563+ while ( ((cpuclk/div) > WriteClk) && (div < 16) )
28564+ {
28565+ div++;
28566+ }
28567+ info->tCK_Write = AST2300_SPICLK_DIV[div-1];
28568+
28569+ div = 1;
28570+ while ( ((cpuclk/div) > EraseClk) && (div < 16) )
28571+ {
28572+ div++;
28573+ }
28574+ info->tCK_Erase = AST2300_SPICLK_DIV[div-1];
28575+
28576+ div = 1;
28577+ while ( ((cpuclk/div) > ReadClk) && (div < 16) )
28578+ {
28579+ div++;
28580+ }
28581+ info->tCK_Read = AST2300_SPICLK_DIV[div-1];
28582+#else
28583+ div = 2;
28584+ info->tCK_Write = 7;
28585+ while ( (cpuclk/div) > WriteClk )
28586+ {
28587+ info->tCK_Write--;
28588+ div +=2;
28589+ }
28590+ div = 2;
28591+ info->tCK_Erase = 7;
28592+ while ( (cpuclk/div) > EraseClk )
28593+ {
28594+ info->tCK_Erase--;
28595+ div +=2;
28596+ }
28597+ div = 2;
28598+ info->tCK_Read = 7;
28599+ while ( (cpuclk/div) > ReadClk )
28600+ {
28601+ info->tCK_Read--;
28602+ div +=2;
28603+ }
28604+#endif
28605+
28606+ /* unprotect flash */
28607+ write_status_register(info, 0);
28608+
28609+ if (info->quadport)
28610+ write_status_register(info, 0x40); /* enable QE */
28611+
28612+ if (info->address32)
28613+ {
28614+ reg = *((volatile ulong*) 0x1e6e2070); /* set H/W Trappings */
28615+ reg |= 0x10;
28616+ *((volatile ulong*) 0x1e6e2070) = reg;
28617+
28618+ reg = *((volatile ulong*) 0x1e620004); /* enable 32b control bit*/
28619+ reg |= (0x01 << info->CE);
28620+ *((volatile ulong*) 0x1e620004) = reg;
28621+
28622+ /* set flash chips to 32bits addressing mode */
28623+ if ((info->flash_id & 0xFF) == 0x01) /* Spansion */
28624+ enable4b_spansion(info);
28625+ else if ((info->flash_id & 0xFF) == 0x20) /* Numonyx */
28626+ enable4b_numonyx(info);
28627+ else /* MXIC, Winbond */
28628+ enable4b(info);
28629+
28630+ }
28631+
28632+ reset_flash(info);
28633+
28634+ return (info->size);
28635+}
28636+
28637+
28638+/*-----------------------------------------------------------------------
28639+ */
28640+static int flash_write_buffer (flash_info_t *info, uchar *src, ulong addr, int len)
28641+{
28642+ ulong j, base, offset;
28643+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
28644+ uchar jReg;
28645+
28646+ if (info->CE == 2)
28647+ {
28648+ CtrlOffset = SPICtrlRegOffset2;
28649+ }
28650+ else
28651+ {
28652+ CtrlOffset = SPICtrlRegOffset;
28653+ }
28654+
28655+ base = info->start[0];
28656+ offset = addr - base;
28657+ base = flash_make_addr (info, 0, 0);
28658+
28659+ enable_write (info);
28660+
28661+ ulCtrlData = (info->tCK_Write << 8);
28662+
28663+ ulCtrlData &= CMD_MASK;
28664+ ulCtrlData |= CE_LOW | USERMODE;
28665+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28666+ udelay(200);
28667+ *(uchar *) (base) = (uchar) (0x02);
28668+ udelay(10);
28669+ if (info->address32)
28670+ {
28671+ *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24);
28672+ udelay(10);
28673+ }
28674+ *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
28675+ udelay(10);
28676+ *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
28677+ udelay(10);
28678+ *(uchar *) (base) = (uchar) ((offset & 0x0000ff));
28679+ udelay(10);
28680+
28681+ for (j=0; j<len; j++)
28682+ {
28683+ *(uchar *) (base) = *(uchar *) (src++);
28684+ udelay(10);
28685+ }
28686+
28687+ ulCtrlData &= CMD_MASK;
28688+ ulCtrlData |= CE_HIGH | USERMODE;
28689+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28690+ udelay(200);
28691+
28692+ ulCtrlData &= CMD_MASK;
28693+ ulCtrlData |= CE_LOW | USERMODE;
28694+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28695+ udelay(200);
28696+ *(uchar *) (base) = (uchar) (0x05);
28697+ udelay(10);
28698+ do {
28699+ jReg = *(volatile uchar *) (base);
28700+ } while ((jReg & 0x01));
28701+ ulCtrlData &= CMD_MASK;
28702+ ulCtrlData |= CE_HIGH | USERMODE;
28703+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28704+ udelay(200);
28705+
28706+ /* RFSR */
28707+ if (info->specificspi == SpecificSPI_N25Q512)
28708+ {
28709+ ulCtrlData &= CMD_MASK;
28710+ ulCtrlData |= CE_LOW | USERMODE;
28711+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28712+ udelay(200);
28713+ *(uchar *) (base) = (uchar) (0x70);
28714+ udelay(10);
28715+ do {
28716+ jReg = *(volatile uchar *) (base);
28717+ } while (!(jReg & 0x80));
28718+ ulCtrlData &= CMD_MASK;
28719+ ulCtrlData |= CE_HIGH | USERMODE;
28720+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28721+ udelay(200);
28722+ }
28723+}
28724+
28725+/*-----------------------------------------------------------------------
28726+ *
28727+ * export functions
28728+ *
28729+ */
28730+
28731+/*-----------------------------------------------------------------------
28732+ *
28733+ */
28734+unsigned long flash_init (void)
28735+{
28736+ unsigned long size = 0;
28737+ int i;
28738+
28739+ /* Init: no FLASHes known */
28740+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
28741+ flash_info[i].flash_id = FLASH_UNKNOWN;
28742+ size += flash_info[i].size = flash_get_size (bank_base[i], i);
28743+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
28744+#ifndef CFG_FLASH_QUIET_TEST
28745+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
28746+ i, flash_info[i].size, flash_info[i].size << 20);
28747+#endif /* CFG_FLASH_QUIET_TEST */
28748+ }
28749+ }
28750+
28751+ /* Monitor protection ON by default */
28752+#if (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
28753+ flash_protect (FLAG_PROTECT_SET,
28754+ CONFIG_MONITOR_BASE,
28755+ CONFIG_MONITOR_BASE + monitor_flash_len - 1,
28756+ flash_get_info(CONFIG_MONITOR_BASE));
28757+#endif
28758+
28759+ /* Environment protection ON by default */
28760+#ifdef CONFIG_ENV_IS_IN_FLASH
28761+ flash_protect (FLAG_PROTECT_SET,
28762+ CONFIG_ENV_ADDR,
28763+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
28764+ flash_get_info(CONFIG_ENV_ADDR));
28765+#endif
28766+
28767+ /* Redundant environment protection ON by default */
28768+#ifdef CONFIG_ENV_ADDR_REDUND
28769+ flash_protect (FLAG_PROTECT_SET,
28770+ CONFIG_ENV_ADDR_REDUND,
28771+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
28772+ flash_get_info(CONFIG_ENV_ADDR_REDUND));
28773+#endif
28774+ return (size);
28775+}
28776+
28777+/*-----------------------------------------------------------------------
28778+ */
28779+#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
28780+static flash_info_t *flash_get_info(ulong base)
28781+{
28782+ int i;
28783+ flash_info_t * info = 0;
28784+
28785+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
28786+ info = & flash_info[i];
28787+ if (info->size && info->start[0] <= base &&
28788+ base <= info->start[0] + info->size - 1)
28789+ break;
28790+ }
28791+
28792+ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
28793+}
28794+#endif
28795+
28796+/*-----------------------------------------------------------------------
28797+ */
28798+int flash_erase (flash_info_t * info, int s_first, int s_last)
28799+{
28800+ int rcode = 0;
28801+ int prot;
28802+ flash_sect_t sect;
28803+
28804+ ulong base, offset;
28805+ ulong ulSMMBase, ulCtrlData, CtrlOffset;
28806+ uchar jReg;
28807+
28808+ disable_cache();
28809+
28810+ if (info->CE == 2)
28811+ {
28812+ CtrlOffset = SPICtrlRegOffset2;
28813+ }
28814+ else
28815+ {
28816+ CtrlOffset = SPICtrlRegOffset;
28817+ }
28818+
28819+ if ((s_first < 0) || (s_first > s_last)) {
28820+ puts ("- no sectors to erase\n");
28821+ return 1;
28822+ }
28823+
28824+ prot = 0;
28825+ for (sect = s_first; sect <= s_last; ++sect) {
28826+ if (info->protect[sect]) {
28827+ prot++;
28828+ }
28829+ }
28830+ if (prot) {
28831+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
28832+ } else {
28833+ putc ('\n');
28834+ }
28835+
28836+ ulCtrlData = (info->tCK_Erase << 8);
28837+ for (sect = s_first; sect <= s_last; sect++) {
28838+ if (info->protect[sect] == 0) { /* not protected */
28839+ /* start erasing */
28840+ enable_write(info);
28841+
28842+ base = info->start[0];
28843+ offset = info->start[sect] - base;
28844+ base = flash_make_addr (info, 0, 0);
28845+
28846+ ulCtrlData &= CMD_MASK;
28847+ ulCtrlData |= CE_LOW | USERMODE;
28848+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28849+ udelay(200);
28850+ *(uchar *) (base) = (uchar) (0xd8);
28851+ udelay(10);
28852+ if (info->address32)
28853+ {
28854+ *(uchar *) (base) = (uchar) ((offset & 0xff000000) >> 24);
28855+ udelay(10);
28856+ }
28857+ *(uchar *) (base) = (uchar) ((offset & 0xff0000) >> 16);
28858+ udelay(10);
28859+ *(uchar *) (base) = (uchar) ((offset & 0x00ff00) >> 8);
28860+ udelay(10);
28861+ *(uchar *) (base) = (uchar) ((offset & 0x0000ff));
28862+ udelay(10);
28863+
28864+ ulCtrlData &= CMD_MASK;
28865+ ulCtrlData |= CE_HIGH | USERMODE;
28866+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28867+ udelay(200);
28868+
28869+ ulCtrlData &= CMD_MASK;
28870+ ulCtrlData |= CE_LOW | USERMODE;
28871+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28872+ udelay(200);
28873+ *(uchar *) (base) = (uchar) (0x05);
28874+ udelay(10);
28875+ do {
28876+ jReg = *(volatile uchar *) (base);
28877+ } while ((jReg & 0x01));
28878+ ulCtrlData &= CMD_MASK;
28879+ ulCtrlData |= CE_HIGH | USERMODE;
28880+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28881+ udelay(200);
28882+
28883+ /* RFSR */
28884+ if (info->specificspi == SpecificSPI_N25Q512)
28885+ {
28886+ ulCtrlData &= CMD_MASK;
28887+ ulCtrlData |= CE_LOW | USERMODE;
28888+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28889+ udelay(200);
28890+ *(uchar *) (base) = (uchar) (0x70);
28891+ udelay(10);
28892+ do {
28893+ jReg = *(volatile uchar *) (base);
28894+ } while (!(jReg & 0x80));
28895+ ulCtrlData &= CMD_MASK;
28896+ ulCtrlData |= CE_HIGH | USERMODE;
28897+ *(ulong *) (STCBaseAddress + CtrlOffset) = ulCtrlData;
28898+ udelay(200);
28899+ }
28900+
28901+ putc ('.');
28902+ }
28903+ }
28904+ puts (" done\n");
28905+
28906+ reset_flash(info);
28907+
28908+ return rcode;
28909+}
28910+
28911+/*-----------------------------------------------------------------------
28912+ */
28913+void flash_print_info (flash_info_t * info)
28914+{
28915+ putc ('\n');
28916+ return;
28917+}
28918+
28919+/*-----------------------------------------------------------------------
28920+ * Copy memory to flash, returns:
28921+ * 0 - OK
28922+ * 1 - write timeout
28923+ * 2 - Flash not erased
28924+ */
28925+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
28926+{
28927+ int count;
28928+ unsigned char pat[] = {'|', '-', '/', '\\'};
28929+ int patcnt;
28930+
28931+ disable_cache();
28932+
28933+ /* get lower aligned address */
28934+ if (addr & (info->buffersize - 1))
28935+ {
28936+ count = cnt >= info->buffersize ? (info->buffersize - (addr & 0xff)):cnt;
28937+ flash_write_buffer (info, src, addr, count);
28938+ addr+= count;
28939+ src += count;
28940+ cnt -= count;
28941+ }
28942+
28943+ /* prog */
28944+ while (cnt > 0) {
28945+ count = cnt >= info->buffersize ? info->buffersize:cnt;
28946+ flash_write_buffer (info, src, addr, count);
28947+ addr+= count;
28948+ src += count;
28949+ cnt -= count;
28950+ printf("%c\b", pat[(patcnt++) & 0x03]);
28951+ }
28952+
28953+ reset_flash(info);
28954+
28955+ return (0);
28956+}
28957+
28958+#ifdef CONFIG_FLASH_AST2300_DMA
28959+void * memmove_dma(void * dest,const void *src,size_t count)
28960+{
28961+ ulong count_align, poll_time, data;
28962+
28963+ count_align = (count + 3) & 0xFFFFFFFC; /* 4-bytes align */
28964+ poll_time = 100; /* set 100 us as default */
28965+
28966+ /* force end of burst read */
28967+ *(volatile ulong *) (STCBaseAddress + SPICtrlRegOffset) |= CE_HIGH;
28968+ *(volatile ulong *) (STCBaseAddress + SPICtrlRegOffset) &= ~CE_HIGH;
28969+
28970+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (~FLASH_DMA_ENABLE);
28971+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_FLASH_BASE) = (ulong *) (src);
28972+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_DRAM_BASE) = (ulong *) (dest);
28973+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_LENGTH) = (ulong) (count_align);
28974+ *(ulong *) (STCBaseAddress + REG_FLASH_DMA_CONTROL) = (ulong) (FLASH_DMA_ENABLE);
28975+
28976+ /* wait poll */
28977+ do {
28978+ udelay(poll_time);
28979+ data = *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS);
28980+ } while (!(data & FLASH_STATUS_DMA_READY));
28981+
28982+ /* clear status */
28983+ *(ulong *) (STCBaseAddress + REG_FLASH_INTERRUPT_STATUS) |= FLASH_STATUS_DMA_CLEAR;
28984+}
28985+#endif
28986+#endif /* CONFIG_FLASH_SPI */
28987diff --git a/board/aspeed/ast2400/hactest.c b/board/aspeed/ast2400/hactest.c
28988new file mode 100755
28989index 0000000..bfa87d5
28990--- /dev/null
28991+++ b/board/aspeed/ast2400/hactest.c
28992@@ -0,0 +1,762 @@
28993+/*
28994+ * This program is distributed in the hope that it will be useful,
28995+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
28996+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28997+ * GNU General Public License for more details.
28998+ *
28999+ * You should have received a copy of the GNU General Public License
29000+ * along with this program; if not, write to the Free Software
29001+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29002+ * MA 02111-1307 USA
29003+ */
29004+
29005+/*
29006+ * Diagnostics support
29007+ */
29008+#include <common.h>
29009+#include <command.h>
29010+#include <post.h>
29011+#include "slt.h"
29012+
29013+#if ((CFG_CMD_SLT & CFG_CMD_HACTEST) && defined(CONFIG_SLT))
29014+#include "hactest.h"
29015+
29016+#include "aes.c"
29017+#include "rc4.c"
29018+
29019+static unsigned char crypto_src[CRYPTO_MAX_SRC], crypto_dst[CRYPTO_MAX_DST], crypto_context[CRYPTO_MAX_CONTEXT];
29020+static unsigned char hash_src[HASH_MAX_SRC], hash_dst[HASH_MAX_DST], hmac_key[HMAC_MAX_KEY];
29021+
29022+/*
29023+ * table
29024+ */
29025+static aes_test aestest[] = {
29026+ { CRYPTOMODE_ECB, 128,
29027+ {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c, '\0'},
29028+ {0x32, 0x43, 0xf6, 0xa8, 0x88, 0x5a, 0x30, 0x8d, 0x31, 0x31, 0x98, 0xa2, 0xe0, 0x37, 0x07, 0x34, '\0'},
29029+ {0x39, 0x25, 0x84, 0x1d, 0x02, 0xdc, 0x09, 0xfb, 0xdc, 0x11, 0x85, 0x97, 0x19, 0x6a, 0x0b, 0x32, '\0'} },
29030+ {0xFF, 0xFF, "", "", ""}, /* End Mark */
29031+};
29032+
29033+static rc4_test rc4test[] = {
29034+ {{0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, '\0'},
29035+ {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, '\0'}},
29036+ {{0xff}, {0xff}}, /* End Mark */
29037+};
29038+
29039+static hash_test hashtest[] = {
29040+ {HASHMODE_SHA1, 20,
29041+ "abc",
29042+ {0x53, 0x20, 0xb0, 0x8c, 0xa1, 0xf5, 0x74, 0x62, 0x50, 0x71, 0x89, 0x41, 0xc5, 0x0a, 0xdf, 0x4e, 0xbb, 0x55, 0x76, 0x06, '\0'}},
29043+ {0xFF, 0xFF, "", ""}, /* End Mark */
29044+};
29045+
29046+static hmac_test hmactest[] = {
29047+ {HASHMODE_SHA1, 64, 20,
29048+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16,0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, '\0' },
29049+ "Sample #1",
29050+ {0xbf, 0x39, 0xda, 0xb1, 0x7d, 0xc2, 0xe1, 0x23, 0x0d, 0x28, 0x35, 0x3b, 0x8c, 0xcb, 0x14, 0xb6, 0x22, 0x02, 0x65, 0xb3, '\0'}},
29051+ {0xFF, 0xFF, 0xFF, "", "", ""}, /* End Mark */
29052+};
29053+
29054+void EnableHMAC(void)
29055+{
29056+ unsigned long ulData;
29057+
29058+ /* init SCU */
29059+ *(unsigned long *) (0x1e6e2000) = 0x1688a8a8;
29060+
29061+ ulData = *(volatile unsigned long *) (0x1e6e200c);
29062+ ulData &= 0xfdfff;
29063+ *(unsigned long *) (0x1e6e200c) = ulData;
29064+ udelay(100);
29065+ ulData = *(volatile unsigned long *) (0x1e6e2004);
29066+ ulData &= 0xfffef;
29067+ *(unsigned long *) (0x1e6e2004) = ulData;
29068+
29069+}
29070+
29071+/* AES */
29072+void aes_enc_ast3000(aes_context *ctx, uint8 *input, uint8 *iv, uint8 *output, uint32 ulMsgLength , uint32 ulAESMode)
29073+{
29074+
29075+ unsigned long i, ulTemp, ulCommand;
29076+ unsigned char ch;
29077+ unsigned char *pjsrc, *pjdst, *pjcontext;
29078+
29079+ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
29080+ CRYPTO_AES | CRYPTO_ENCRYPTO | CRYPTO_SYNC_MODE_ASYNC;
29081+
29082+ switch (ctx->nr)
29083+ {
29084+ case 10:
29085+ ulCommand |= CRYPTO_AES128;
29086+ break;
29087+ case 12:
29088+ ulCommand |= CRYPTO_AES192;
29089+ break;
29090+ case 14:
29091+ ulCommand |= CRYPTO_AES256;
29092+ break;
29093+ }
29094+
29095+ switch (ulAESMode)
29096+ {
29097+ case CRYPTOMODE_ECB:
29098+ ulCommand |= CRYPTO_AES_ECB;
29099+ break;
29100+ case CRYPTOMODE_CBC:
29101+ ulCommand |= CRYPTO_AES_CBC;
29102+ break;
29103+ case CRYPTOMODE_CFB:
29104+ ulCommand |= CRYPTO_AES_CFB;
29105+ break;
29106+ case CRYPTOMODE_OFB:
29107+ ulCommand |= CRYPTO_AES_OFB;
29108+ break;
29109+ case CRYPTOMODE_CTR:
29110+ ulCommand |= CRYPTO_AES_CTR;
29111+ break;
29112+ }
29113+
29114+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
29115+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
29116+ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
29117+
29118+ /* Init HW */
29119+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
29120+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
29121+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
29122+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
29123+
29124+ /* Set source */
29125+ for (i=0; i< ulMsgLength; i++)
29126+ {
29127+ ch = *(uint8 *)(input + i);
29128+ *(uint8 *) (pjsrc + i) = ch;
29129+ }
29130+
29131+ /* Set Context */
29132+ /* Set IV */
29133+ for (i=0; i<16; i++)
29134+ {
29135+ ch = *(uint8 *) (iv + i);
29136+ *(uint8 *) (pjcontext + i) = ch;
29137+ }
29138+
29139+ /* Set Expansion Key */
29140+ for (i=0; i<(4*(ctx->nr+1)); i++)
29141+ {
29142+ ulTemp = ((ctx->erk[i] & 0xFF) << 24) + ((ctx->erk[i] & 0xFF00) << 8) + ((ctx->erk[i] & 0xFF0000) >> 8) + ((ctx->erk[i] & 0xFF000000) >> 24);
29143+ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
29144+ }
29145+
29146+ /* fire cmd */
29147+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
29148+ do {
29149+ ulTemp = *(volatile unsigned long *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
29150+ } while (ulTemp & CRYPTO_BUSY);
29151+
29152+ /* Output */
29153+ for (i=0; i<ulMsgLength; i++)
29154+ {
29155+ ch = *(uint8 *) (pjdst + i);
29156+ *(uint8 *) (output + i) = ch;
29157+ }
29158+
29159+} /* aes_enc_ast3000 */
29160+
29161+
29162+void aes_dec_ast3000(aes_context *ctx, uint8 *input, uint8 *iv, uint8 *output, uint32 ulMsgLength , uint32 ulAESMode)
29163+{
29164+ unsigned long i, ulTemp, ulCommand;
29165+ unsigned char ch;
29166+ unsigned char *pjsrc, *pjdst, *pjcontext;
29167+
29168+ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
29169+ CRYPTO_AES | CRYPTO_DECRYPTO | CRYPTO_SYNC_MODE_ASYNC;
29170+
29171+ switch (ctx->nr)
29172+ {
29173+ case 10:
29174+ ulCommand |= CRYPTO_AES128;
29175+ break;
29176+ case 12:
29177+ ulCommand |= CRYPTO_AES192;
29178+ break;
29179+ case 14:
29180+ ulCommand |= CRYPTO_AES256;
29181+ break;
29182+ }
29183+
29184+ switch (ulAESMode)
29185+ {
29186+ case CRYPTOMODE_ECB:
29187+ ulCommand |= CRYPTO_AES_ECB;
29188+ break;
29189+ case CRYPTOMODE_CBC:
29190+ ulCommand |= CRYPTO_AES_CBC;
29191+ break;
29192+ case CRYPTOMODE_CFB:
29193+ ulCommand |= CRYPTO_AES_CFB;
29194+ break;
29195+ case CRYPTOMODE_OFB:
29196+ ulCommand |= CRYPTO_AES_OFB;
29197+ break;
29198+ case CRYPTOMODE_CTR:
29199+ ulCommand |= CRYPTO_AES_CTR;
29200+ break;
29201+ }
29202+
29203+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
29204+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
29205+ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
29206+
29207+ /* Init HW */
29208+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
29209+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
29210+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
29211+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
29212+
29213+ /* Set source */
29214+ for (i=0; i< ulMsgLength; i++)
29215+ {
29216+ ch = *(uint8 *)(input + i);
29217+ *(uint8 *) (pjsrc + i) = ch;
29218+ }
29219+
29220+ /* Set Context */
29221+ /* Set IV */
29222+ for (i=0; i<16; i++)
29223+ {
29224+ ch = *(uint8 *) (iv + i);
29225+ *(uint8 *) (pjcontext + i) = ch;
29226+ }
29227+
29228+ /* Set Expansion Key */
29229+ for (i=0; i<(4*(ctx->nr+1)); i++)
29230+ {
29231+ ulTemp = ((ctx->erk[i] & 0xFF) << 24) + ((ctx->erk[i] & 0xFF00) << 8) + ((ctx->erk[i] & 0xFF0000) >> 8) + ((ctx->erk[i] & 0xFF000000) >> 24);
29232+ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
29233+ }
29234+
29235+ /* fire cmd */
29236+ *(unsigned long *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
29237+ do {
29238+ ulTemp = *(volatile unsigned long *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
29239+ } while (ulTemp & CRYPTO_BUSY);
29240+
29241+ /* Output */
29242+ for (i=0; i<ulMsgLength; i++)
29243+ {
29244+ ch = *(uint8 *) (pjdst + i);
29245+ *(uint8 *) (output + i) = ch;
29246+ }
29247+
29248+} /* aes_dec_ast3000 */
29249+
29250+void rc4_crypt_ast3000(uint8 *data, int ulMsgLength, uint8 *rc4_key, uint32 ulKeyLength)
29251+{
29252+ struct rc4_state s;
29253+ unsigned long i, ulTemp, ulCommand;
29254+ unsigned char ch;
29255+ unsigned char *pjsrc, *pjdst, *pjcontext;
29256+
29257+ ulCommand = CRYPTO_ENABLE_RW | CRYPTO_ENABLE_CONTEXT_LOAD | CRYPTO_ENABLE_CONTEXT_SAVE | \
29258+ CRYPTO_RC4 | CRYPTO_SYNC_MODE_ASYNC;
29259+
29260+ rc4_setup( &s, rc4_key, ulKeyLength );
29261+
29262+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) crypto_src);
29263+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) crypto_dst);
29264+ pjcontext = (unsigned char *) m16byteAlignment((unsigned long) crypto_context);
29265+
29266+ /* Init HW */
29267+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
29268+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_DST_BASE_OFFSET) = (unsigned long) pjdst;
29269+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_CONTEXT_BASE_OFFSET) = (unsigned long) pjcontext;
29270+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_LEN_OFFSET) = ulMsgLength;
29271+
29272+
29273+ /* Set source */
29274+ for (i=0; i< ulMsgLength; i++)
29275+ {
29276+ ch = *(uint8 *)(data + i);
29277+ *(uint8 *) (pjsrc + i) = ch;
29278+ }
29279+
29280+ /* Set Context */
29281+ /* Set i, j */
29282+ *(uint32 *) (pjcontext + 8) = 0x0001;
29283+
29284+ /* Set Expansion Key */
29285+ for (i=0; i<(256/4); i++)
29286+ {
29287+ ulTemp = (s.m[i * 4] & 0xFF) + ((s.m[i * 4 + 1] & 0xFF) << 8) + ((s.m[i * 4 + 2] & 0xFF) << 16) + ((s.m[i * 4+ 3] & 0xFF) << 24);
29288+ *(uint32 *) (pjcontext + i*4 + 16) = ulTemp;
29289+ }
29290+
29291+ /* fire cmd */
29292+ *(uint32 *) (HAC_REG_BASE + REG_CRYPTO_CMD_BASE_OFFSET) = ulCommand;
29293+ do {
29294+ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_CRYPTO_STATUS_OFFSET);
29295+ } while (ulTemp & CRYPTO_BUSY);
29296+
29297+ /* Output */
29298+ for (i=0; i<ulMsgLength; i++)
29299+ {
29300+ ch = *(volatile uint8 *) (pjdst + i);
29301+ *(uint8 *) (data + i) = ch;
29302+ }
29303+
29304+} /* rc4_crypt_ast3000 */
29305+
29306+/* Hash */
29307+void hash_ast3000(uint8 *msg, uint32 ulLength, unsigned char *output, uint32 ulHashMode)
29308+{
29309+ uint32 i, ulTemp, ulCommand, ulDigestLength, ulMyMsgLength;
29310+ uint8 ch;
29311+ unsigned char *pjsrc, *pjdst;
29312+
29313+ /* Get Info */
29314+ switch (ulHashMode)
29315+ {
29316+ case HASHMODE_MD5:
29317+ ulCommand = HASH_ALG_SELECT_MD5;
29318+ ulDigestLength = 16;
29319+ break;
29320+ case HASHMODE_SHA1:
29321+ ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
29322+ ulDigestLength = 20;
29323+ break;
29324+ case HASHMODE_SHA256:
29325+ ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
29326+ ulDigestLength = 32;
29327+ break;
29328+ case HASHMODE_SHA224:
29329+ ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
29330+ ulDigestLength = 28;
29331+ break;
29332+ }
29333+
29334+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
29335+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
29336+
29337+ /* 16byte alignment */
29338+ ulMyMsgLength = m16byteAlignment(ulLength);
29339+
29340+ /* Init. HW */
29341+ *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
29342+ *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
29343+ *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulMyMsgLength;
29344+
29345+ /* write src */
29346+ for (i=0; i<ulLength; i++)
29347+ {
29348+ ch = *(uint8 *)(msg+i);
29349+ *(uint8 *) (pjsrc + i) = ch;
29350+ }
29351+ for (i=ulLength; i<ulMyMsgLength; i++)
29352+ *(uint8 *) (pjsrc + i) = 0;
29353+
29354+ /* fire cmd */
29355+ *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand;
29356+
29357+ /* get digest */
29358+ do {
29359+ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);
29360+ } while (ulTemp & HASH_BUSY);
29361+
29362+ for (i=0; i<ulDigestLength; i++)
29363+ {
29364+ ch = *(volatile uint8 *) (pjdst + i);
29365+ *(uint8 *) (output + i) = ch;
29366+ }
29367+
29368+} /* hash_ast3000 */
29369+
29370+/* HMAC */
29371+void hmackey_ast3000(uint8 *key, uint32 ulKeyLength, uint32 ulHashMode)
29372+{
29373+ uint32 i, ulBlkLength, ulDigestLength, ulTemp, ulCommand;
29374+ uint8 k0[64], sum[32];
29375+ uint8 ch;
29376+ unsigned char *pjsrc, *pjdst, *pjkey;
29377+
29378+ /* Get Info */
29379+ switch (ulHashMode)
29380+ {
29381+ case HASHMODE_MD5:
29382+ ulCommand = HASH_ALG_SELECT_MD5;
29383+ ulDigestLength = 16;
29384+ break;
29385+ case HASHMODE_SHA1:
29386+ ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
29387+ ulDigestLength = 20;
29388+ break;
29389+ case HASHMODE_SHA256:
29390+ ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
29391+ ulDigestLength = 32;
29392+ break;
29393+ case HASHMODE_SHA224:
29394+ ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
29395+ ulDigestLength = 28;
29396+ break;
29397+ }
29398+ ulBlkLength = 64; /* MD5, SHA1/256/224: 64bytes */
29399+
29400+ /* Init */
29401+ memset( (void *) k0, 0, 64); /* reset to zero */
29402+ memset( (void *) sum, 0, 32); /* reset to zero */
29403+
29404+ /* Get k0 */
29405+ if (ulKeyLength <= ulBlkLength)
29406+ memcpy( (void *) k0, (void *) key, ulKeyLength );
29407+ else /* (ulKeyLength > ulBlkLength) */
29408+ {
29409+ hash_ast3000(key, ulKeyLength, sum, ulHashMode);
29410+ memcpy( (void *) k0, (void *) sum, ulDigestLength );
29411+ }
29412+
29413+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
29414+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
29415+ pjkey = (unsigned char *) m64byteAlignment((unsigned long) hmac_key);
29416+
29417+ /* Calculate digest */
29418+ *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
29419+ *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
29420+ *(uint32 *) (HAC_REG_BASE + REG_HASH_KEY_BASE_OFFSET) = (unsigned long) pjkey;
29421+ *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulBlkLength;
29422+
29423+ /* write key to src */
29424+ for (i=0; i<ulBlkLength; i++)
29425+ {
29426+ ch = *(uint8 *)(k0+i);
29427+ *(uint8 *) (pjsrc + i) = ch;
29428+ }
29429+
29430+ /* fire cmd for calculate */
29431+ *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand | HAC_DIGEST_CAL_ENABLE;
29432+ do {
29433+ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);
29434+ } while (ulTemp & HASH_BUSY);
29435+
29436+} /* hmackey_ast3000 */
29437+
29438+void hmac_ast3000(uint8 *key, uint32 ulKeyLength, uint8 *msg, uint32 ulMsgLength, uint32 ulHashMode, unsigned char *output)
29439+{
29440+ uint32 i, ulTemp, ulCommand, ulDigestLength, ulMyMsgLength;;
29441+ uint8 ch;
29442+ unsigned char *pjsrc, *pjdst, *pjkey;
29443+
29444+ /* Calculate digest */
29445+ switch (ulHashMode)
29446+ {
29447+ case HASHMODE_MD5:
29448+ ulCommand = HASH_ALG_SELECT_MD5;
29449+ ulDigestLength = 16;
29450+ break;
29451+ case HASHMODE_SHA1:
29452+ ulCommand = HASH_ALG_SELECT_SHA1 | 0x08;
29453+ ulDigestLength = 20;
29454+ break;
29455+ case HASHMODE_SHA256:
29456+ ulCommand = HASH_ALG_SELECT_SHA256 | 0x08;
29457+ ulDigestLength = 32;
29458+ break;
29459+ case HASHMODE_SHA224:
29460+ ulCommand = HASH_ALG_SELECT_SHA224 | 0x08;
29461+ ulDigestLength = 28;
29462+ break;
29463+ }
29464+
29465+ pjsrc = (unsigned char *) m16byteAlignment((unsigned long) hash_src);
29466+ pjdst = (unsigned char *) m16byteAlignment((unsigned long) hash_dst);
29467+ pjkey = (unsigned char *) m64byteAlignment((unsigned long) hmac_key);
29468+
29469+ /* 16byte alignment */
29470+ ulMyMsgLength = m16byteAlignment(ulMsgLength);
29471+
29472+ /* Init. HW */
29473+ *(uint32 *) (HAC_REG_BASE + REG_HASH_SRC_BASE_OFFSET) = (unsigned long) pjsrc;
29474+ *(uint32 *) (HAC_REG_BASE + REG_HASH_DST_BASE_OFFSET) = (unsigned long) pjdst;
29475+ *(uint32 *) (HAC_REG_BASE + REG_HASH_KEY_BASE_OFFSET) = (unsigned long) pjkey;
29476+ *(uint32 *) (HAC_REG_BASE + REG_HASH_LEN_OFFSET) = ulMyMsgLength;
29477+
29478+ /* write Text to src */
29479+ for (i=0; i<ulMsgLength; i++)
29480+ {
29481+ ch = *(uint8 *)(msg+i);
29482+ *(uint8 *) (pjsrc + i) = ch;
29483+ }
29484+ for (i=ulMsgLength; i<ulMyMsgLength; i++)
29485+ *(uint8 *) (pjsrc + i) = 0;
29486+
29487+ /* fire cmd */
29488+ *(uint32 *) (HAC_REG_BASE + REG_HASH_CMD_OFFSET) = ulCommand | HAC_ENABLE;
29489+ do {
29490+ ulTemp = *(volatile uint32 *) (HAC_REG_BASE + REG_HASH_STATUS_OFFSET);
29491+ } while (ulTemp & HASH_BUSY);
29492+
29493+ /* Output Digest */
29494+ for (i=0; i<ulDigestLength; i++)
29495+ {
29496+ ch = *(uint8 *) (pjdst + i);
29497+ *(uint8 *) (output + i) = ch;
29498+ }
29499+
29500+} /* hmac_ast3000 */
29501+
29502+/* main hactest procedure */
29503+int do_hactest (void)
29504+{
29505+ unsigned long i, j, Flags = 0;
29506+ aes_test *pjaes_test;
29507+ aes_context aes_ctx;
29508+ unsigned char AES_Mode[8], aes_output[64];
29509+ unsigned long ulAESMsgLength;
29510+
29511+ rc4_test *pjrc4_test;
29512+ unsigned char rc4_buf_sw[64], rc4_buf_hw[64];
29513+ unsigned long ulRC4KeyLength, ulRC4MsgLength;
29514+
29515+ hash_test *pjhash_test;
29516+ unsigned char HASH_Mode[8], hash_out[64];
29517+
29518+ hmac_test *pjhmac_test;
29519+ unsigned char HMAC_Mode[8], hmac_out[64];
29520+
29521+ EnableHMAC();
29522+
29523+ /* AES Test */
29524+ pjaes_test = aestest;
29525+ while (pjaes_test->aes_mode != 0xFF)
29526+ {
29527+
29528+ if (pjaes_test->aes_mode == CRYPTOMODE_CBC)
29529+ strcpy (AES_Mode, "CBC");
29530+ else if (pjaes_test->aes_mode == CRYPTOMODE_CFB)
29531+ strcpy (AES_Mode, "CFB");
29532+ else if (pjaes_test->aes_mode == CRYPTOMODE_OFB)
29533+ strcpy (AES_Mode, "OFB");
29534+ else if (pjaes_test->aes_mode == CRYPTOMODE_CTR)
29535+ strcpy (AES_Mode, "CTR");
29536+ else
29537+ strcpy (AES_Mode, "ECB");
29538+
29539+ /* Get Msg. Length */
29540+ ulAESMsgLength = strlen(pjaes_test->plaintext);
29541+ j = ( (ulAESMsgLength + 15) >> 4) << 4;
29542+ for (i=ulAESMsgLength; i<j; i++)
29543+ pjaes_test->plaintext[i] = 0;
29544+ ulAESMsgLength = j;
29545+
29546+ aes_set_key(&aes_ctx, pjaes_test->key, pjaes_test->key_length);
29547+
29548+ /* Encryption Test */
29549+ aes_enc_ast3000(&aes_ctx, pjaes_test->plaintext, pjaes_test->key, aes_output, ulAESMsgLength, pjaes_test->aes_mode);
29550+ if (strncmp(aes_output, pjaes_test->ciphertext, ulAESMsgLength))
29551+ {
29552+ Flags |= FLAG_AESTEST_FAIL;
29553+ printf("[INFO] AES%d %s Mode Encryption Failed \n", pjaes_test->key_length, AES_Mode);
29554+ printf("[DBG] Golden Data Dump .... \n");
29555+ for (i=0; i< ulAESMsgLength; i++)
29556+ {
29557+ printf("%02x ", pjaes_test->ciphertext[i]);
29558+ if (((i+1) % 8) == 0)
29559+ printf("\n");
29560+ }
29561+ printf("\n [DBG] Error Data Dump .... \n");
29562+ for (i=0; i< ulAESMsgLength; i++)
29563+ {
29564+ printf("%02x ", aes_output[i]);
29565+ if (((i+1) % 8) == 0)
29566+ printf("\n");
29567+ }
29568+ printf("\n");
29569+ }
29570+ else
29571+ {
29572+ /*
29573+ printf("[INFO] AES%d %s Mode Encryption Passed \n", pjaes_test->key_length, AES_Mode);
29574+ */
29575+ }
29576+
29577+ /* Decryption Test */
29578+ aes_dec_ast3000(&aes_ctx, pjaes_test->ciphertext, pjaes_test->key, aes_output, ulAESMsgLength, pjaes_test->aes_mode);
29579+ if (strncmp(aes_output, pjaes_test->plaintext, ulAESMsgLength))
29580+ {
29581+ Flags |= FLAG_AESTEST_FAIL;
29582+ printf("[INFO] AES%d %s Mode Decryption Failed \n", pjaes_test->key_length, AES_Mode);
29583+ printf("[DBG] Golden Data Dump .... \n");
29584+ for (i=0; i< ulAESMsgLength; i++)
29585+ {
29586+ printf("%02x ", pjaes_test->plaintext[i]);
29587+ if (((i+1) % 8) == 0)
29588+ printf("\n");
29589+ }
29590+ printf("\n [DBG] Error Data Dump .... \n");
29591+ for (i=0; i< ulAESMsgLength; i++)
29592+ {
29593+ printf("%02x ", aes_output[i]);
29594+ if (((i+1) % 8) == 0)
29595+ printf("\n");
29596+ }
29597+ printf("\n");
29598+ }
29599+ else
29600+ {
29601+ /*
29602+ printf("[INFO] AES%d %s Mode Decryption Passed \n", pjaes_test->key_length, AES_Mode);
29603+ */
29604+ }
29605+
29606+ pjaes_test++;
29607+ } /* AES */
29608+
29609+ /* RC4 Test */
29610+ pjrc4_test = rc4test;
29611+ while ((pjrc4_test->key[0] != 0xff) && (pjrc4_test->data[0] != 0xff))
29612+ {
29613+
29614+ /* Get Info */
29615+ ulRC4KeyLength = strlen(pjrc4_test->key);
29616+ ulRC4MsgLength = strlen(pjrc4_test->data);
29617+ memcpy( (void *) rc4_buf_sw, (void *) pjrc4_test->data, ulRC4MsgLength );
29618+ memcpy( (void *) rc4_buf_hw, (void *) pjrc4_test->data, ulRC4MsgLength );
29619+
29620+ /* Crypto */
29621+ rc4_crypt_sw(rc4_buf_sw, ulRC4MsgLength, pjrc4_test->key, ulRC4KeyLength);
29622+ rc4_crypt_ast3000(rc4_buf_hw, ulRC4MsgLength, pjrc4_test->key, ulRC4KeyLength);
29623+
29624+ if (strncmp(rc4_buf_hw, rc4_buf_sw, ulRC4MsgLength))
29625+ {
29626+ Flags |= FLAG_RC4TEST_FAIL;
29627+ printf("[INFO] RC4 Encryption Failed \n");
29628+ printf("[DBG] Golden Data Dump .... \n");
29629+ for (i=0; i< ulRC4MsgLength; i++)
29630+ {
29631+ printf("%02x ", rc4_buf_sw[i]);
29632+ if (((i+1) % 8) == 0)
29633+ printf("\n");
29634+ }
29635+ printf("\n [DBG] Error Data Dump .... \n");
29636+ for (i=0; i< ulRC4MsgLength; i++)
29637+ {
29638+ printf("%02x ", rc4_buf_hw[i]);
29639+ if (((i+1) % 8) == 0)
29640+ printf("\n");
29641+ }
29642+ printf("\n");
29643+ }
29644+ else
29645+ {
29646+ /*
29647+ printf("[INFO] RC4 Encryption Passed \n");
29648+ */
29649+ }
29650+
29651+ pjrc4_test++;
29652+
29653+ } /* RC4 */
29654+
29655+ /* Hash Test */
29656+ pjhash_test = hashtest;
29657+ while (pjhash_test->hash_mode != 0xFF)
29658+ {
29659+
29660+ if (pjhash_test->hash_mode == HASHMODE_MD5)
29661+ strcpy (HASH_Mode, "MD5");
29662+ else if (pjhash_test->hash_mode == HASHMODE_SHA1)
29663+ strcpy (HASH_Mode, "SHA1");
29664+ else if (pjhash_test->hash_mode == HASHMODE_SHA256)
29665+ strcpy (HASH_Mode, "SHA256");
29666+ else if (pjhash_test->hash_mode == HASHMODE_SHA224)
29667+ strcpy (HASH_Mode, "SHA224");
29668+
29669+ /* Hash */
29670+ hash_ast3000(pjhash_test->input, strlen(pjhash_test->input), hash_out, pjhash_test->hash_mode);
29671+ if (strncmp(hash_out, pjhash_test->digest, pjhash_test->digest_length))
29672+ {
29673+ Flags |= FLAG_HASHTEST_FAIL;
29674+ printf("[INFO] HASH %s Failed \n", HASH_Mode);
29675+ printf("[DBG] Golden Data Dump .... \n");
29676+ for (i=0; i< pjhash_test->digest_length; i++)
29677+ {
29678+ printf("%02x ",pjhash_test->digest[i]);
29679+ if (((i+1) % 8) == 0)
29680+ printf("\n");
29681+ }
29682+ printf("\n [DBG] Error Data Dump .... \n");
29683+ for (i=0; i< pjhash_test->digest_length; i++)
29684+ {
29685+ printf("%02x ",hash_out[i]);
29686+ if (((i+1) % 8) == 0)
29687+ printf("\n");
29688+ }
29689+ printf("\n");
29690+ }
29691+ else
29692+ {
29693+ /*
29694+ printf("[INFO] HASH %s Passed \n", HASH_Mode);
29695+ */
29696+ }
29697+
29698+ pjhash_test++;
29699+
29700+ } /* Hash Test */
29701+
29702+ /* HMAC Test */
29703+ pjhmac_test = hmactest;
29704+ while (pjhmac_test->hash_mode != 0xFF)
29705+ {
29706+
29707+ if (pjhmac_test->hash_mode == HASHMODE_MD5)
29708+ strcpy (HMAC_Mode, "MD5");
29709+ else if (pjhmac_test->hash_mode == HASHMODE_SHA1)
29710+ strcpy (HMAC_Mode, "SHA1");
29711+ else if (pjhmac_test->hash_mode == HASHMODE_SHA256)
29712+ strcpy (HMAC_Mode, "SHA256");
29713+ else if (pjhmac_test->hash_mode == HASHMODE_SHA224)
29714+ strcpy (HMAC_Mode, "SHA224");
29715+
29716+ /* HMAC */
29717+ hmackey_ast3000(pjhmac_test->key, pjhmac_test->key_length, pjhmac_test->hash_mode);
29718+ hmac_ast3000(pjhmac_test->key, pjhmac_test->key_length, pjhmac_test->input, strlen(pjhmac_test->input), pjhmac_test->hash_mode, hmac_out);
29719+ if (strncmp(hmac_out, pjhmac_test->digest, pjhmac_test->digest_length))
29720+ {
29721+ Flags |= FLAG_HASHTEST_FAIL;
29722+ printf("[INFO] HMAC %s Failed \n", HMAC_Mode);
29723+ printf("[DBG] Golden Data Dump .... \n");
29724+ for (i=0; i< pjhmac_test->digest_length; i++)
29725+ {
29726+ printf("%02x ",pjhmac_test->digest[i]);
29727+ if (((i+1) % 8) == 0)
29728+ printf("\n");
29729+ }
29730+ printf("\n [DBG] Error Data Dump .... \n");
29731+ for (i=0; i< pjhmac_test->digest_length; i++)
29732+ {
29733+ printf("%02x ",hmac_out[i]);
29734+ if (((i+1) % 8) == 0)
29735+ printf("\n");
29736+ }
29737+ printf("\n");
29738+ }
29739+ else
29740+ {
29741+ /*
29742+ printf("[INFO] HMAC %s Passed \n", HMAC_Mode);
29743+ */
29744+ }
29745+
29746+ pjhmac_test++;
29747+
29748+ } /* HMAC Test */
29749+
29750+ return Flags;
29751+
29752+}
29753+
29754+#endif /* CONFIG_SLT */
29755diff --git a/board/aspeed/ast2400/hactest.h b/board/aspeed/ast2400/hactest.h
29756new file mode 100755
29757index 0000000..fcf2186
29758--- /dev/null
29759+++ b/board/aspeed/ast2400/hactest.h
29760@@ -0,0 +1,194 @@
29761+/*
29762+ * This program is distributed in the hope that it will be useful,
29763+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
29764+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29765+ * GNU General Public License for more details.
29766+ *
29767+ * You should have received a copy of the GNU General Public License
29768+ * along with this program; if not, write to the Free Software
29769+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29770+ */
29771+/* Err Flags */
29772+#define FLAG_AESTEST_FAIL 0x00000001
29773+#define FLAG_RC4TEST_FAIL 0x00000002
29774+#define FLAG_HASHTEST_FAIL 0x00000004
29775+
29776+/* Specific */
29777+/*
29778+#define DRAM_BASE 0x40000000
29779+#define CRYPTO_SRC_BASE (DRAM_BASE + 0x100000)
29780+#define CRYPTO_DST_BASE (DRAM_BASE + 0x200000)
29781+#define CRYPTO_CONTEXT_BASE (DRAM_BASE + 0x300000)
29782+
29783+#define HASH_SRC_BASE (DRAM_BASE + 0x400000)
29784+#define HASH_DST_BASE (DRAM_BASE + 0x500000)
29785+#define HMAC_KEY_BASE (DRAM_BASE + 0x600000)
29786+*/
29787+#define m08byteAlignment(x) ((x + 0x00000007) & 0xFFFFFFF8)
29788+#define m16byteAlignment(x) ((x + 0x0000000F) & 0xFFFFFFF0)
29789+#define m64byteAlignment(x) ((x + 0x0000003F) & 0xFFFFFFC0)
29790+
29791+#define CRYPTO_ALIGNMENT 16
29792+#define CRYPTO_MAX_SRC (100+CRYPTO_ALIGNMENT)
29793+#define CRYPTO_MAX_DST (100+CRYPTO_ALIGNMENT)
29794+#define CRYPTO_MAX_CONTEXT (100+CRYPTO_ALIGNMENT)
29795+
29796+#define HASH_ALIGNMENT 16
29797+#define HMAC_KEY_ALIGNMENT 64
29798+#define HASH_MAX_SRC (100+HASH_ALIGNMENT)
29799+#define HASH_MAX_DST (32+HASH_ALIGNMENT)
29800+#define HMAC_MAX_KEY (64+HMAC_KEY_ALIGNMENT)
29801+
29802+/* General */
29803+#define HAC_REG_BASE 0x1e6e3000
29804+
29805+#define MAX_KEYLENGTH 100
29806+#define MAX_TEXTLENGTH 100
29807+#define MAX_AESTEXTLENGTH 256
29808+#define MAX_RC4TEXTLENGTH 256
29809+#define MAX_RC4KEYLENGTH 256
29810+
29811+#define CRYPTOMODE_ECB 0x00
29812+#define CRYPTOMODE_CBC 0x01
29813+#define CRYPTOMODE_CFB 0x02
29814+#define CRYPTOMODE_OFB 0x03
29815+#define CRYPTOMODE_CTR 0x04
29816+
29817+#define HASHMODE_MD5 0x00
29818+#define HASHMODE_SHA1 0x01
29819+#define HASHMODE_SHA256 0x02
29820+#define HASHMODE_SHA224 0x03
29821+
29822+#define MIXMODE_DISABLE 0x00
29823+#define MIXMODE_CRYPTO 0x02
29824+#define MIXMODE_HASH 0x03
29825+
29826+#define REG_CRYPTO_SRC_BASE_OFFSET 0x00
29827+#define REG_CRYPTO_DST_BASE_OFFSET 0x04
29828+#define REG_CRYPTO_CONTEXT_BASE_OFFSET 0x08
29829+#define REG_CRYPTO_LEN_OFFSET 0x0C
29830+#define REG_CRYPTO_CMD_BASE_OFFSET 0x10
29831+//#define REG_CRYPTO_ENABLE_OFFSET 0x14
29832+#define REG_CRYPTO_STATUS_OFFSET 0x1C
29833+
29834+#define REG_HASH_SRC_BASE_OFFSET 0x20
29835+#define REG_HASH_DST_BASE_OFFSET 0x24
29836+#define REG_HASH_KEY_BASE_OFFSET 0x28
29837+#define REG_HASH_LEN_OFFSET 0x2C
29838+#define REG_HASH_CMD_OFFSET 0x30
29839+//#define REG_HASH_ENABLE_OFFSET 0x14
29840+#define REG_HASH_STATUS_OFFSET 0x1C
29841+
29842+#define HASH_BUSY 0x01
29843+#define CRYPTO_BUSY 0x02
29844+
29845+//#define ENABLE_HASH 0x01
29846+//#define DISABLE_HASH 0x00
29847+//#define ENABLE_CRYPTO 0x02
29848+//#define DISABLE_CRYPTO 0x00
29849+
29850+#define CRYPTO_SYNC_MODE_MASK 0x03
29851+#define CRYPTO_SYNC_MODE_ASYNC 0x00
29852+#define CRYPTO_SYNC_MODE_PASSIVE 0x02
29853+#define CRYPTO_SYNC_MODE_ACTIVE 0x03
29854+
29855+#define CRYPTO_AES128 0x00
29856+#define CRYPTO_AES192 0x04
29857+#define CRYPTO_AES256 0x08
29858+
29859+#define CRYPTO_AES_ECB 0x00
29860+#define CRYPTO_AES_CBC 0x10
29861+#define CRYPTO_AES_CFB 0x20
29862+#define CRYPTO_AES_OFB 0x30
29863+#define CRYPTO_AES_CTR 0x40
29864+
29865+#define CRYPTO_ENCRYPTO 0x80
29866+#define CRYPTO_DECRYPTO 0x00
29867+
29868+#define CRYPTO_AES 0x000
29869+#define CRYPTO_RC4 0x100
29870+
29871+#define CRYPTO_ENABLE_RW 0x000
29872+#define CRYPTO_ENABLE_CONTEXT_LOAD 0x000
29873+#define CRYPTO_ENABLE_CONTEXT_SAVE 0x000
29874+
29875+#define HASH_SYNC_MODE_MASK 0x03
29876+#define HASH_SYNC_MODE_ASYNC 0x00
29877+#define HASH_SYNC_MODE_PASSIVE 0x02
29878+#define HASH_SYNC_MODE_ACTIVE 0x03
29879+
29880+#define HASH_READ_SWAP_ENABLE 0x04
29881+#define HMAC_SWAP_CONTROL_ENABLE 0x08
29882+
29883+#define HASH_ALG_SELECT_MASK 0x70
29884+#define HASH_ALG_SELECT_MD5 0x00
29885+#define HASH_ALG_SELECT_SHA1 0x20
29886+#define HASH_ALG_SELECT_SHA224 0x40
29887+#define HASH_ALG_SELECT_SHA256 0x50
29888+
29889+#define HAC_ENABLE 0x80
29890+#define HAC_DIGEST_CAL_ENABLE 0x180
29891+#define HASH_INT_ENABLE 0x200
29892+
29893+/* AES */
29894+#ifndef uint8
29895+#define uint8 unsigned char
29896+#endif
29897+
29898+#ifndef uint32
29899+#define uint32 unsigned long int
29900+#endif
29901+
29902+typedef struct
29903+{
29904+ uint32 erk[64]; /* encryption round keys */
29905+ uint32 drk[64]; /* decryption round keys */
29906+ int nr; /* number of rounds */
29907+}
29908+aes_context;
29909+
29910+typedef struct
29911+{
29912+ int aes_mode;
29913+ int key_length;
29914+
29915+ uint8 key[32]; /* as iv in CTR mode */
29916+ uint8 plaintext[64];
29917+ uint8 ciphertext[64];
29918+
29919+}
29920+aes_test;
29921+
29922+/* RC4 */
29923+typedef struct
29924+{
29925+ uint8 key[32];
29926+ uint8 data[64];
29927+}
29928+rc4_test;
29929+
29930+/* Hash */
29931+typedef struct
29932+{
29933+ int hash_mode;
29934+ int digest_length;
29935+
29936+ uint8 input[64];
29937+ uint8 digest[64];
29938+
29939+}
29940+hash_test;
29941+
29942+/* HMAC */
29943+typedef struct
29944+{
29945+ int hash_mode;
29946+ int key_length;
29947+ int digest_length;
29948+
29949+ uint8 key[100];
29950+ uint8 input[64];
29951+ uint8 digest[64];
29952+
29953+}
29954+hmac_test;
29955diff --git a/board/aspeed/ast2400/mactest.c b/board/aspeed/ast2400/mactest.c
29956new file mode 100755
29957index 0000000..22054b9
29958--- /dev/null
29959+++ b/board/aspeed/ast2400/mactest.c
29960@@ -0,0 +1,510 @@
29961+/*
29962+ * This program is distributed in the hope that it will be useful,
29963+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
29964+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29965+ * GNU General Public License for more details.
29966+ *
29967+ * You should have received a copy of the GNU General Public License
29968+ * along with this program; if not, write to the Free Software
29969+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29970+ */
29971+/*
29972+ * (C) Copyright 2007 ASPEED Software
29973+ * MAC Manufacture Test in ASPEED's SDK version 0.20.01
29974+ *
29975+ * Release History
29976+ * 1. First Release, river@20071130
29977+ * 2. Fix the endless loop when PHY is not ready, river@20071204
29978+ *
29979+ * Test items:
29980+ * 1. Support MARVELL PHY only in this version
29981+ * 2. MDC/MDIO
29982+ * 3. GMAC/Duplex TX/RX Full_Size, Packet_Length Test
29983+ * 4. 100M/Duplex TX/RX Full_Size, Packet_Length Test
29984+ *
29985+ *
29986+ *
29987+*/
29988+
29989+
29990+/*
29991+* Diagnostics support
29992+*/
29993+#include <common.h>
29994+#include <command.h>
29995+#include <post.h>
29996+#include <malloc.h>
29997+#include <net.h>
29998+#include "slt.h"
29999+
30000+#if ((CFG_CMD_SLT & CFG_CMD_MACTEST) && defined(CONFIG_SLT))
30001+#include "mactest.h"
30002+
30003+static int INL(u_long base, u_long addr)
30004+{
30005+ return le32_to_cpu(*(volatile u_long *)(addr + base));
30006+}
30007+
30008+static void OUTL(u_long base, int command, u_long addr)
30009+{
30010+ *(volatile u_long *)(addr + base) = cpu_to_le32(command);
30011+}
30012+
30013+
30014+static void SCU_MAC1_Enable (u8 enable)
30015+{
30016+ unsigned int SCU_Register;
30017+
30018+ if(enable) {
30019+//MAC1 RESET/PHY_LINK in SCU
30020+ SCU_Register = INL(SCU_BASE, SCU_RESET_CONTROL_REG);
30021+ OUTL(SCU_BASE, SCU_Register & ~(0x800), SCU_RESET_CONTROL_REG);
30022+ } else {
30023+ SCU_Register = INL(SCU_BASE, SCU_RESET_CONTROL_REG);
30024+ OUTL(SCU_BASE, SCU_Register |(0x800), SCU_RESET_CONTROL_REG);
30025+
30026+}
30027+}
30028+
30029+/*------------------------------------------------------------
30030+ . Reads a register from the MII Management serial interface
30031+ .-------------------------------------------------------------*/
30032+static u16 phy_read_register (u8 PHY_Register, u8 PHY_Address)
30033+{
30034+ u32 Data, Status = 0, Loop_Count = 0, PHY_Ready = 1;
30035+ u16 Return_Data;
30036+
30037+ OUTL(MAC1_IO_BASE, (PHY_Register << 21) + (PHY_Address << 16) + MIIRD + MDC_CYCTHR, PHYCR_REG);
30038+ do {
30039+ Status = (INL (MAC1_IO_BASE, PHYCR_REG) & MIIRD);
30040+ Loop_Count++;
30041+ if (Loop_Count >= PHY_LOOP) {
30042+ PHY_Ready = 0;
30043+ break;
30044+ }
30045+ } while (Status == MIIRD);
30046+
30047+ if (PHY_Ready == 0) {
30048+ printf ("PHY NOT REDAY\n");
30049+ return 0;
30050+ }
30051+
30052+ udelay(5*1000);
30053+ Data = INL (MAC1_IO_BASE, PHYDATA_REG);
30054+ Return_Data = (Data >> 16);
30055+
30056+ return Return_Data;
30057+}
30058+
30059+static void phy_write_register (u8 PHY_Register, u8 PHY_Address, u16 PHY_Data)
30060+{
30061+ u32 Status = 0, Loop_Count = 0, PHY_Ready = 1;
30062+
30063+ OUTL(MAC1_IO_BASE, PHY_Data, PHYDATA_REG);
30064+ OUTL(MAC1_IO_BASE, (PHY_Register << 21) + (PHY_Address << 16) + MIIWR + MDC_CYCTHR, PHYCR_REG);
30065+ do {
30066+ Status = (INL (MAC1_IO_BASE, PHYCR_REG) & MIIWR);
30067+ Loop_Count++;
30068+ if (Loop_Count >= PHY_LOOP) {
30069+ PHY_Ready = 0;
30070+ break;
30071+ }
30072+ } while (Status == MIIWR);
30073+ if (PHY_Ready == 0) {
30074+ printf ("PHY NOT REDAY\n");
30075+ }
30076+}
30077+
30078+static int wait_link_resolve (void)
30079+{
30080+ int resolved_status, Loop_Count = 0, PHY_Ready = 1;
30081+
30082+ do {
30083+ resolved_status = (phy_read_register (0x11, 0) & (PHY_RESOLVED_bit | PHY_LINK_bit));
30084+ Loop_Count++;
30085+ if (Loop_Count >= PHY_LOOP) {
30086+ PHY_Ready = 0;
30087+ printf ("PHY NOT READY\n");
30088+ break;
30089+ }
30090+ } while (resolved_status != (PHY_RESOLVED_bit | PHY_LINK_bit));
30091+
30092+ return PHY_Ready;
30093+}
30094+
30095+static void set_phy_speed (int chip, int speed, int duplex)
30096+{
30097+ unsigned short data, status;
30098+
30099+
30100+ if (chip == PHYID_VENDOR_MARVELL) {
30101+ if ((speed == PHY_SPEED_1G) && (duplex == DUPLEX_FULL)) {
30102+//Manual Control
30103+ phy_write_register (18, 0, 0);
30104+ data = phy_read_register (9, 0);
30105+ phy_write_register (9, 0, data | 0x1800);
30106+//PHY Reset
30107+ phy_write_register (0, 0, 0x0140 | 0x8000);
30108+ do {
30109+ status = (phy_read_register (0, 0) & 0x8000);
30110+ } while (status != 0);
30111+
30112+//Force 1G
30113+ phy_write_register (29, 0, 0x07);
30114+ data = phy_read_register (30, 0);
30115+ phy_write_register (30, 0, data | 0x08);
30116+ phy_write_register (29, 0, 0x10);
30117+ data = phy_read_register (30, 0);
30118+ phy_write_register (30, 0, data | 0x02);
30119+ phy_write_register (29, 0, 0x12);
30120+ data = phy_read_register (30, 0);
30121+ phy_write_register (30, 0, data | 0x01);
30122+
30123+ printf ("FORCE MARVELL PHY to 1G/DUPLEX DONE\n");
30124+ }
30125+ else if ((speed == PHY_SPEED_100M) && (duplex == DUPLEX_FULL)) {
30126+//PHY Reset
30127+ phy_write_register (0, 0, 0x2100 | 0x8000);
30128+ do {
30129+ status = (phy_read_register (0, 0) & 0x8000);
30130+ } while (status != 0);
30131+
30132+//Force 100M
30133+ data = phy_read_register (0, 0);
30134+ phy_write_register (0, 0, data | 0x4000 | 0x8000);
30135+ do {
30136+ status = (phy_read_register (0, 0) & 0x8000);
30137+ } while (status != 0);
30138+ data = phy_read_register (0, 0);
30139+
30140+ printf ("FORCE MARVELL PHY to 100M/DUPLEX DONE\n");
30141+ }
30142+ }
30143+ else if ( (chip == PHYID_VENDOR_RTL8201E) || (chip == PHYID_VENDOR_BROADCOM) ){
30144+ /* basic setting */
30145+ data = phy_read_register (0, 0);
30146+ data &= 0x7140;
30147+ data |= 0x4000;
30148+ if (speed == PHY_SPEED_100M)
30149+ data |= 0x2000;
30150+ if (duplex == DUPLEX_FULL)
30151+ data |= 0x0100;
30152+ phy_write_register (0, 0, data);
30153+
30154+ /* reset */
30155+ phy_write_register (0, 0, data | 0x8000);
30156+ do {
30157+ status = (phy_read_register (0, 0) & 0x8000);
30158+ } while (status != 0);
30159+ udelay(100*1000);
30160+
30161+ /* basic setting */
30162+ phy_write_register (0, 0, data);
30163+
30164+ if (chip == PHYID_VENDOR_RTL8201E)
30165+ printf ("FORCE RTL8201E PHY to 100M/DUPLEX DONE\n");
30166+ else if (chip == PHYID_VENDOR_BROADCOM)
30167+ printf ("FORCE Broadcom PHY to 100M/DUPLEX DONE\n");
30168+
30169+ }
30170+
30171+}
30172+
30173+static void MAC1_reset (void)
30174+{
30175+ OUTL(MAC1_IO_BASE, SW_RST_bit, MACCR_REG);
30176+ for (; (INL(MAC1_IO_BASE, MACCR_REG ) & SW_RST_bit) != 0; ) {udelay(1000);}
30177+ OUTL(MAC1_IO_BASE, 0, IER_REG );
30178+}
30179+
30180+static int set_mac1_control_register (int Chip_ID)
30181+{
30182+ unsigned long MAC_CR_Register = 0;
30183+ int PHY_Ready = 1;
30184+ u16 PHY_Status, PHY_Speed, PHY_Duplex, Advertise, Link_Partner;
30185+
30186+ MAC_CR_Register = SPEED_100M_MODE_bit | RX_ALLADR_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit;
30187+
30188+ if ( (Chip_ID == PHYID_VENDOR_BROADCOM) || (Chip_ID == PHYID_VENDOR_RTL8201E)) {
30189+ Advertise = phy_read_register (0x04, 0);
30190+ Link_Partner = phy_read_register (0x05, 0);
30191+ Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK);
30192+ Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK);
30193+ if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) {
30194+ MAC_CR_Register |= SPEED_100M_MODE_bit;
30195+ MAC_CR_Register |= FULLDUP_bit;
30196+ }
30197+ else if ((Advertise & Link_Partner) & PHY_100M_HALF) {
30198+ MAC_CR_Register |= SPEED_100M_MODE_bit;
30199+ MAC_CR_Register &= ~FULLDUP_bit;
30200+ }
30201+ else if ((Advertise & Link_Partner) & PHY_10M_DUPLEX) {
30202+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
30203+ MAC_CR_Register |= FULLDUP_bit;
30204+ }
30205+ else if ((Advertise & Link_Partner) & PHY_10M_HALF) {
30206+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
30207+ MAC_CR_Register &= ~FULLDUP_bit;
30208+ }
30209+ }
30210+ else if (Chip_ID == PHYID_VENDOR_MARVELL) {
30211+
30212+ PHY_Ready = wait_link_resolve ();
30213+
30214+ if (PHY_Ready == 1) {
30215+ PHY_Status = phy_read_register (0x11, 0);
30216+ PHY_Speed = (PHY_Status & PHY_SPEED_MASK) >> 14;
30217+ PHY_Duplex = (PHY_Status & PHY_DUPLEX_MASK) >> 13;
30218+
30219+ if (PHY_Speed == SPEED_1000M) {
30220+ MAC_CR_Register |= GMAC_MODE_bit;
30221+ }
30222+ else {
30223+ MAC_CR_Register &= ~GMAC_MODE_bit;
30224+ if (PHY_Speed == SPEED_10M) {
30225+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
30226+ }
30227+ }
30228+ if (PHY_Duplex == DUPLEX_HALF) {
30229+ MAC_CR_Register &= ~FULLDUP_bit;
30230+ }
30231+ }
30232+ }
30233+ OUTL(MAC1_IO_BASE, MAC_CR_Register, MACCR_REG);
30234+
30235+ return PHY_Ready;
30236+}
30237+
30238+static void ring_buffer_alloc (void)
30239+{
30240+ unsigned int i, j;
30241+
30242+//Write data into TX buffer
30243+ for (i = 0; i < NUM_TX; i++) {
30244+ for (j = 0; j < TX_BUFF_SZ; j++) {
30245+ tx_buffer[i][j] = i * 4 + j;
30246+ }
30247+ }
30248+//Initialize RX buffer to 0
30249+ for (i = 0; i < NUM_RX; i++) {
30250+ for (j = 0; j < RX_BUFF_SZ; j++) {
30251+ rx_buffer[i][j] = 0;
30252+ }
30253+ }
30254+//Prepare descriptor
30255+ for (i = 0; i < NUM_RX; i++) {
30256+ rx_ring[i].status = cpu_to_le32(RXPKT_RDY + RX_BUFF_SZ);
30257+ rx_ring[i].buf = ((u32) &rx_buffer[i]);
30258+ rx_ring[i].reserved = 0;
30259+ }
30260+ for (i = 0; i < NUM_TX; i++) {
30261+ tx_ring[i].status = 0;
30262+ tx_ring[i].des1 = 0;
30263+ tx_ring[i].buf = ((u32) &tx_buffer[i]);
30264+ tx_ring[i].reserved = 0;
30265+ }
30266+
30267+ rx_ring[NUM_RX - 1].status |= cpu_to_le32(EDORR);
30268+ tx_ring[NUM_TX - 1].status |= cpu_to_le32(EDOTR);
30269+
30270+ OUTL(MAC1_IO_BASE, ((u32) &tx_ring), TXR_BADR_REG);
30271+ OUTL(MAC1_IO_BASE, ((u32) &rx_ring), RXR_BADR_REG);
30272+
30273+ tx_new = 0;
30274+ rx_new = 0;
30275+}
30276+
30277+static int packet_test (void)
30278+{
30279+ unsigned int rx_status, length, i, Loop_Count = 0;
30280+
30281+ tx_ring[tx_new].status |= cpu_to_le32(LTS | FTS | TX_BUFF_SZ);
30282+ tx_ring[tx_new].status |= cpu_to_le32(TXDMA_OWN);
30283+ OUTL(MAC1_IO_BASE, POLL_DEMAND, TXPD_REG);
30284+
30285+//Compare result
30286+ do {
30287+ rx_status = rx_ring[rx_new].status;
30288+ Loop_Count++;
30289+ } while (!(rx_status & RXPKT_STATUS) && (Loop_Count < PHY_LOOP));
30290+ if (rx_status & (RX_ERR | CRC_ERR | FTL | RUNT | RX_ODD_NB)) {
30291+ /* There was an error.*/
30292+ printf("RX error status = 0x%08X\n", rx_status);
30293+ return PACKET_TEST_FAIL;
30294+ } else {
30295+ length = (rx_status & BYTE_COUNT_MASK);
30296+ for (i = 0; i < RX_BUFF_SZ / 4; i++) {
30297+ if (rx_buffer[rx_new][i] != tx_buffer[tx_new][i]) {
30298+ printf ("ERROR at packet %d, address %x\n", rx_new, i);
30299+ printf ("Gold = %8x, Real = %8x\n", tx_buffer[tx_new][i], rx_buffer[rx_new][i]);
30300+ return PACKET_TEST_FAIL;
30301+ }
30302+ }
30303+ }
30304+ tx_new = (tx_new + 1) % NUM_TX;
30305+ rx_new = (rx_new + 1) % NUM_RX;
30306+
30307+ return TEST_PASS;
30308+}
30309+
30310+static int packet_length_test (int packet_length)
30311+{
30312+ unsigned int rx_status, length, i, Loop_Count = 0;
30313+
30314+ tx_ring[tx_new].status &= (~(BYTE_COUNT_MASK));
30315+ tx_ring[tx_new].status |= cpu_to_le32(LTS | FTS | packet_length);
30316+ tx_ring[tx_new].status |= cpu_to_le32(TXDMA_OWN);
30317+ OUTL(MAC1_IO_BASE, POLL_DEMAND, TXPD_REG);
30318+
30319+//Compare result
30320+ do {
30321+ rx_status = rx_ring[rx_new].status;
30322+ Loop_Count++;
30323+ } while (!(rx_status & RXPKT_STATUS) && (Loop_Count < PHY_LOOP));
30324+ if (rx_status & (RX_ERR | CRC_ERR | FTL | RUNT | RX_ODD_NB)) {
30325+ /* There was an error.*/
30326+ printf("RX error status = 0x%08X\n", rx_status);
30327+ return PACKET_LENGTH_TEST_FAIL;
30328+ } else {
30329+ length = (rx_status & BYTE_COUNT_MASK) - 4;
30330+ if (length != packet_length) {
30331+ printf ("Received Length ERROR. Gold = %d, Fail = %d\n",packet_length, length);
30332+ printf ("rx_new = %d, tx_new = %d\n", rx_new, tx_new);
30333+ return PACKET_LENGTH_TEST_FAIL;
30334+ }
30335+ for (i = 0; i < length; i++) {
30336+ if (rx_buffer[rx_new][i] != tx_buffer[tx_new][i]) {
30337+ printf ("ERROR at packet %d, address %x\n", rx_new, i);
30338+ printf ("Gold = %8x, Real = %8x\n", tx_buffer[tx_new][i], rx_buffer[rx_new][i]);
30339+ return PACKET_LENGTH_TEST_FAIL;
30340+ }
30341+ }
30342+ }
30343+ rx_ring[rx_new].status &= (~(RXPKT_STATUS));
30344+ tx_new = (tx_new + 1) % NUM_TX;
30345+ rx_new = (rx_new + 1) % NUM_RX;
30346+
30347+ return TEST_PASS;
30348+}
30349+
30350+static int MAC1_init (int id)
30351+{
30352+ int phy_status = 0;
30353+
30354+ MAC1_reset ();
30355+ phy_status = set_mac1_control_register (id);
30356+ ring_buffer_alloc ();
30357+
30358+ return phy_status;
30359+}
30360+
30361+int do_mactest (void)
30362+{
30363+ unsigned int phy_id, i;
30364+ int test_result = 0, phy_status = 0;
30365+
30366+ SCU_MAC1_Enable(1);
30367+ phy_id = ((phy_read_register (0x02, 0) << 16) + phy_read_register (0x03, 0)) & PHYID_VENDOR_MASK;
30368+ if (phy_id == PHYID_VENDOR_MARVELL) {
30369+ printf ("PHY DETECTED ------> MARVELL\n");
30370+
30371+ set_phy_speed (phy_id, PHY_SPEED_1G, DUPLEX_FULL);
30372+ if ((phy_status = MAC1_init (phy_id)) != 0) {
30373+ for (i = 0; i < NUM_TX; i++) {
30374+ test_result |= packet_test ();
30375+ if (test_result != 0)
30376+ break;
30377+ }
30378+ }
30379+ else if (phy_status == 0) {
30380+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
30381+ test_result = 3;
30382+ return test_result;
30383+ }
30384+ if ((phy_status = MAC1_init (phy_id)) != 0) {
30385+ for (i = 60; i < TX_BUFF_SZ; i++) {
30386+ test_result |= packet_length_test (i);
30387+ if (test_result != 0)
30388+ break;
30389+ }
30390+ }
30391+ else if (phy_status == 0) {
30392+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
30393+ test_result = 3;
30394+ return test_result;
30395+ }
30396+ set_phy_speed (phy_id, PHY_SPEED_100M, DUPLEX_FULL);
30397+ if ((phy_status = MAC1_init (phy_id)) != 0) {
30398+ for (i = 0; i < NUM_TX; i++) {
30399+ test_result |= packet_test ();
30400+ if (test_result != 0)
30401+ break;
30402+ }
30403+ }
30404+ else if (phy_status == 0) {
30405+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
30406+ test_result = 3;
30407+ return test_result;
30408+ }
30409+
30410+ if ((phy_status = MAC1_init (phy_id)) != 0) {
30411+ for (i = 60; i < TX_BUFF_SZ; i++) {
30412+ test_result |= packet_length_test (i);
30413+ if (test_result != 0)
30414+ break;
30415+ }
30416+ }
30417+ else if (phy_status == 0) {
30418+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
30419+ test_result = 3;
30420+ return test_result;
30421+ }
30422+ }
30423+ else if ( (phy_id == PHYID_VENDOR_RTL8201E) || (phy_id == PHYID_VENDOR_BROADCOM) ){
30424+
30425+ if (phy_id == PHYID_VENDOR_RTL8201E)
30426+ printf ("PHY DETECTED ------> RTL 8201E \n");
30427+ else if (phy_id == PHYID_VENDOR_BROADCOM)
30428+ printf ("PHY DETECTED ------> Broadcom \n");
30429+
30430+ set_phy_speed (phy_id, PHY_SPEED_100M, DUPLEX_FULL);
30431+ if ((phy_status = MAC1_init (phy_id)) != 0) {
30432+ for (i = 0; i < NUM_TX; i++) {
30433+ test_result |= packet_test ();
30434+ if (test_result != 0)
30435+ break;
30436+ }
30437+ }
30438+ else if (phy_status == 0) {
30439+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
30440+ test_result = 3;
30441+ return test_result;
30442+ }
30443+
30444+ if ((phy_status = MAC1_init (phy_id)) != 0) {
30445+ for (i = 60; i < TX_BUFF_SZ; i++) {
30446+ test_result |= packet_length_test (i);
30447+ if (test_result != 0)
30448+ break;
30449+ }
30450+ }
30451+ else if (phy_status == 0) {
30452+ printf ("PHY FAIL: Please Check If you are using LOOP BACK Connector\n");
30453+ test_result = 3;
30454+ return test_result;
30455+ }
30456+ }
30457+
30458+ if ((phy_status == 0) && (test_result & PACKET_TEST_FAIL)) {
30459+ printf ("Packet Test FAIL !\n");
30460+ }
30461+ else if ((phy_status == 0) && (test_result & PACKET_LENGTH_TEST_FAIL)) {
30462+ printf ("Packet Length Test FAIL !\n");
30463+ }
30464+
30465+ SCU_MAC1_Enable(0);
30466+ return test_result;
30467+
30468+}
30469+
30470+#endif /* CONFIG_SLT */
30471diff --git a/board/aspeed/ast2400/mactest.h b/board/aspeed/ast2400/mactest.h
30472new file mode 100755
30473index 0000000..e75b7bb
30474--- /dev/null
30475+++ b/board/aspeed/ast2400/mactest.h
30476@@ -0,0 +1,215 @@
30477+/*
30478+ * This program is distributed in the hope that it will be useful,
30479+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
30480+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30481+ * GNU General Public License for more details.
30482+ *
30483+ * You should have received a copy of the GNU General Public License
30484+ * along with this program; if not, write to the Free Software
30485+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30486+ */
30487+/* MACTest.h */
30488+
30489+// --------------------------------------------------------------------
30490+// General Definition
30491+// --------------------------------------------------------------------
30492+#define MAC1_IO_BASE 0x1E660000
30493+#define PHY_LOOP 100000
30494+#define NUM_RX 48
30495+#define NUM_TX 48
30496+#define RX_BUFF_SZ 1514
30497+#define TX_BUFF_SZ 1514
30498+#define TOUT_LOOP 1000000
30499+#define ETH_ALEN 6
30500+#define POLL_DEMAND 1
30501+
30502+
30503+// --------------------------------------------------------------------
30504+// MAC Register Index
30505+// --------------------------------------------------------------------
30506+#define ISR_REG 0x00 // interrups status register
30507+#define IER_REG 0x04 // interrupt maks register
30508+#define MAC_MADR_REG 0x08 // MAC address (Most significant)
30509+#define MAC_LADR_REG 0x0c // MAC address (Least significant)
30510+#define MAHT0_REG 0x10 // Multicast Address Hash Table 0 register
30511+#define MAHT1_REG 0x14 // Multicast Address Hash Table 1 register
30512+#define TXPD_REG 0x18 // Transmit Poll Demand register
30513+#define RXPD_REG 0x1c // Receive Poll Demand register
30514+#define TXR_BADR_REG 0x20 // Transmit Ring Base Address register
30515+#define RXR_BADR_REG 0x24 // Receive Ring Base Address register
30516+#define HPTXPD_REG 0x28
30517+#define HPTXR_BADR_REG 0x2c
30518+#define ITC_REG 0x30 // interrupt timer control register
30519+#define APTC_REG 0x34 // Automatic Polling Timer control register
30520+#define DBLAC_REG 0x38 // DMA Burst Length and Arbitration control register
30521+#define DMAFIFOS_REG 0x3c
30522+#define FEAR_REG 0x44
30523+#define TPAFCR_REG 0x48
30524+#define RBSR_REG 0x4c
30525+#define MACCR_REG 0x50 // MAC control register
30526+#define MACSR_REG 0x54 // MAC status register
30527+#define PHYCR_REG 0x60 // PHY control register
30528+#define PHYDATA_REG 0x64 // PHY Write Data register
30529+
30530+// --------------------------------------------------------------------
30531+// PHYCR_REG
30532+// --------------------------------------------------------------------
30533+#define PHY_RE_AUTO_bit (1UL<<9)
30534+#define PHY_READ_bit (1UL<<26)
30535+#define PHY_WRITE_bit (1UL<<27)
30536+// --------------------------------------------------------------------
30537+// PHYCR_REG
30538+// --------------------------------------------------------------------
30539+#define PHY_AUTO_OK_bit (1UL<<5)
30540+// --------------------------------------------------------------------
30541+// PHY INT_STAT_REG
30542+// --------------------------------------------------------------------
30543+#define PHY_SPEED_CHG_bit (1UL<<14)
30544+#define PHY_DUPLEX_CHG_bit (1UL<<13)
30545+#define PHY_LINK_CHG_bit (1UL<<10)
30546+#define PHY_AUTO_COMP_bit (1UL<<11)
30547+// --------------------------------------------------------------------
30548+// PHY SPE_STAT_REG
30549+// --------------------------------------------------------------------
30550+#define PHY_RESOLVED_bit (1UL<<11)
30551+#define PHY_LINK_bit (1UL<<10)
30552+#define PHY_SPEED_mask 0xC000
30553+#define PHY_SPEED_10M 0x0
30554+#define PHY_SPEED_100M 0x1
30555+#define PHY_SPEED_1G 0x2
30556+#define PHY_DUPLEX_mask 0x2000
30557+#define PHY_SPEED_DUPLEX_MASK 0x01E0
30558+#define PHY_100M_DUPLEX 0x0100
30559+#define PHY_100M_HALF 0x0080
30560+#define PHY_10M_DUPLEX 0x0040
30561+#define PHY_10M_HALF 0x0020
30562+#define LINK_STATUS 0x04
30563+#define PHYID_VENDOR_MASK 0xfffffc00
30564+#define PHYID_VENDOR_MARVELL 0x01410c00
30565+#define PHYID_VENDOR_BROADCOM 0x00406000
30566+#define PHYID_VENDOR_RTL8201E 0x001cc800
30567+#define DUPLEX_FULL 0x01
30568+#define DUPLEX_HALF 0x00
30569+
30570+
30571+
30572+// --------------------------------------------------------------------
30573+// MACCR_REG
30574+// --------------------------------------------------------------------
30575+
30576+#define SW_RST_bit (1UL<<31) // software reset/
30577+#define DIRPATH_bit (1UL<<21)
30578+#define RX_IPCS_FAIL_bit (1UL<<20)
30579+#define SPEED_100M_MODE_bit (1UL<<19)
30580+#define RX_UDPCS_FAIL_bit (1UL<<18)
30581+#define RX_BROADPKT_bit (1UL<<17) // Receiving broadcast packet
30582+#define RX_MULTIPKT_bit (1UL<<16) // receiving multicast packet
30583+#define RX_HT_EN_bit (1UL<<15)
30584+#define RX_ALLADR_bit (1UL<<14) // not check incoming packet's destination address
30585+#define JUMBO_LF_bit (1UL<<13)
30586+#define RX_RUNT_bit (1UL<<12) // Store incoming packet even its length is les than 64 byte
30587+#define CRC_CHK_bit (1UL<<11)
30588+#define CRC_APD_bit (1UL<<10) // append crc to transmit packet
30589+#define GMAC_MODE_bit (1UL<<9)
30590+#define FULLDUP_bit (1UL<<8) // full duplex
30591+#define ENRX_IN_HALFTX_bit (1UL<<7)
30592+#define LOOP_EN_bit (1UL<<6) // Internal loop-back
30593+#define HPTXR_EN_bit (1UL<<5)
30594+#define REMOVE_VLAN_bit (1UL<<4)
30595+#define RXMAC_EN_bit (1UL<<3) // receiver enable
30596+#define TXMAC_EN_bit (1UL<<2) // transmitter enable
30597+#define RXDMA_EN_bit (1UL<<1) // enable DMA receiving channel
30598+#define TXDMA_EN_bit (1UL<<0) // enable DMA transmitting channel
30599+
30600+
30601+// --------------------------------------------------------------------
30602+// SCU_REG
30603+// --------------------------------------------------------------------
30604+#define SCU_BASE 0x1E6E2000
30605+#define SCU_PROTECT_KEY_REG 0x0
30606+#define SCU_PROT_KEY_MAGIC 0x1688a8a8
30607+#define SCU_RESET_CONTROL_REG 0x04
30608+#define SCU_RESET_MAC1 (1u << 11)
30609+#define SCU_RESET_MAC2 (1u << 12)
30610+#define SCU_HARDWARE_TRAPPING_REG 0x70
30611+#define SCU_HT_MAC_INTF_LSBIT 6
30612+#define SCU_HT_MAC_INTERFACE (0x7u << SCU_HT_MAC_INTF_LSBIT)
30613+#define MAC_INTF_SINGLE_PORT_MODES (1u<<0/*GMII*/ | 1u<<3/*MII_ONLY*/ | 1u<<4/*RMII_ONLY*/)
30614+#define SCU_HT_MAC_GMII 0x0u
30615+// MII and MII mode
30616+#define SCU_HT_MAC_MII_MII 0x1u
30617+#define SCU_HT_MAC_MII_ONLY 0x3u
30618+#define SCU_HT_MAC_RMII_ONLY 0x4u
30619+#define SCU_MULTIFUNCTION_PIN_REG 0x74
30620+#define SCU_MFP_MAC2_PHYLINK (1u << 26)
30621+#define SCU_MFP_MAC1_PHYLINK (1u << 25)
30622+#define SCU_MFP_MAC2_MII_INTF (1u << 21)
30623+#define SCU_MFP_MAC2_MDC_MDIO (1u << 20)
30624+#define SCU_SILICON_REVISION_REG 0x7C
30625+
30626+//---------------------------------------------------
30627+// PHY R/W Register Bit
30628+//---------------------------------------------------
30629+#define MIIWR (1UL<<27)
30630+#define MIIRD (1UL<<26)
30631+#define MDC_CYCTHR 0x34
30632+#define PHY_SPEED_MASK 0xC000
30633+#define PHY_DUPLEX_MASK 0x2000
30634+#define SPEED_1000M 0x02
30635+#define SPEED_100M 0x01
30636+#define SPEED_10M 0x00
30637+#define DUPLEX_FULL 0x01
30638+#define DUPLEX_HALF 0x00
30639+#define RESOLVED_BIT 0x800
30640+
30641+#define PHY_SPEED_DUPLEX_MASK 0x01E0
30642+#define PHY_100M_DUPLEX 0x0100
30643+#define PHY_100M_HALF 0x0080
30644+#define PHY_10M_DUPLEX 0x0040
30645+#define PHY_10M_HALF 0x0020
30646+
30647+//---------------------------------------------------
30648+// Descriptor bits.
30649+//---------------------------------------------------
30650+#define TXDMA_OWN 0x80000000 /* Own Bit */
30651+#define RXPKT_RDY 0x00000000
30652+#define RXPKT_STATUS 0x80000000
30653+#define EDORR 0x40000000 /* Receive End Of Ring */
30654+#define LRS 0x10000000 /* Last Descriptor */
30655+#define RD_ES 0x00008000 /* Error Summary */
30656+#define EDOTR 0x40000000 /* Transmit End Of Ring */
30657+#define T_OWN 0x80000000 /* Own Bit */
30658+#define LTS 0x10000000 /* Last Segment */
30659+#define FTS 0x20000000 /* First Segment */
30660+#define CRC_ERR 0x00080000
30661+#define TD_ES 0x00008000 /* Error Summary */
30662+#define TD_SET 0x08000000 /* Setup Packet */
30663+#define RX_ERR 0x00040000
30664+#define FTL 0x00100000
30665+#define RUNT 0x00200000
30666+#define RX_ODD_NB 0x00400000
30667+#define BYTE_COUNT_MASK 0x00003FFF
30668+
30669+//---------------------------------------------------
30670+// SPEED/DUPLEX Parameters
30671+//---------------------------------------------------
30672+
30673+//---------------------------------------------------
30674+// Return Status
30675+//---------------------------------------------------
30676+#define TEST_PASS 0
30677+#define PACKET_TEST_FAIL 1
30678+#define PACKET_LENGTH_TEST_FAIL 2
30679+
30680+struct mac_desc {
30681+ volatile s32 status;
30682+ u32 des1;
30683+ u32 reserved;
30684+ u32 buf;
30685+};
30686+static struct mac_desc rx_ring[NUM_RX] __attribute__ ((aligned(32))); /* RX descriptor ring */
30687+static struct mac_desc tx_ring[NUM_TX] __attribute__ ((aligned(32))); /* TX descriptor ring */
30688+static int rx_new; /* RX descriptor ring pointer */
30689+static int tx_new; /* TX descriptor ring pointer */
30690+static volatile unsigned char rx_buffer[NUM_RX][RX_BUFF_SZ] __attribute__ ((aligned(32))); /* RX buffer */
30691+static volatile unsigned char tx_buffer[NUM_TX][TX_BUFF_SZ] __attribute__ ((aligned(32))); /* TX buffer */
30692diff --git a/board/aspeed/ast2400/mictest.c b/board/aspeed/ast2400/mictest.c
30693new file mode 100755
30694index 0000000..1b2b342
30695--- /dev/null
30696+++ b/board/aspeed/ast2400/mictest.c
30697@@ -0,0 +1,146 @@
30698+/*
30699+ * This program is distributed in the hope that it will be useful,
30700+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
30701+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30702+ * GNU General Public License for more details.
30703+ *
30704+ * You should have received a copy of the GNU General Public License
30705+ * along with this program; if not, write to the Free Software
30706+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30707+ * MA 02111-1307 USA
30708+ */
30709+
30710+/*
30711+ * Diagnostics support
30712+ */
30713+#include <common.h>
30714+#include <command.h>
30715+#include <post.h>
30716+#include "slt.h"
30717+
30718+#if ((CFG_CMD_SLT & CFG_CMD_MICTEST) && defined(CONFIG_SLT))
30719+#include "mictest.h"
30720+
30721+static unsigned char ctrlbuf[MIC_MAX_CTRL];
30722+static unsigned char chksumbuf[MIC_MAX_CHKSUM];
30723+
30724+void vInitSCU(void)
30725+{
30726+ unsigned long ulData;
30727+
30728+ *(unsigned long *) (0x1e6e2000) = 0x1688A8A8;
30729+
30730+ udelay(100);
30731+
30732+ ulData = *(unsigned long *) (0x1e6e2004);
30733+ ulData &= 0xbffff;
30734+ *(unsigned long *) (0x1e6e2004) = ulData;
30735+
30736+}
30737+
30738+void vInitMIC(void)
30739+{
30740+ unsigned long i, j, ulPageNumber;
30741+ unsigned char *pjctrl, *pjsum;
30742+
30743+ ulPageNumber = DRAMSIZE >> 12;
30744+
30745+ pjctrl = (unsigned char *)(m16byteAlignment((unsigned long) ctrlbuf));
30746+ pjsum = (unsigned char *)(m16byteAlignment((unsigned long) chksumbuf));
30747+
30748+ /* init ctrl buffer (2bits for one page) */
30749+ for (i=0; i< (ulPageNumber/4); i++)
30750+ *(unsigned char *) (pjctrl + i) = DEFAULT_CTRL;
30751+
30752+ /* init chksum buf (4bytes for one page) */
30753+ for (i=0; i<ulPageNumber; i++)
30754+ *(unsigned long *) (pjsum + i*4) = DEFAULT_CHKSUM;
30755+
30756+ *(unsigned long *) (MIC_BASE + MIC_CTRLBUFF_REG) = (unsigned long) pjctrl;
30757+ *(unsigned long *) (MIC_BASE + MIC_CHKSUMBUF_REG) = (unsigned long) pjsum;
30758+ *(unsigned long *) (MIC_BASE + MIC_RATECTRL_REG) = (unsigned long) DEFAULT_RATE;
30759+ *(unsigned long *) (MIC_BASE + MIC_ENGINECTRL_REG) = MIC_ENABLE_MIC | (DRAMSIZE - 0x1000);
30760+
30761+}
30762+
30763+void vDisableMIC(void)
30764+{
30765+ *(unsigned long *) (MIC_BASE + MIC_ENGINECTRL_REG) = MIC_RESET_MIC;
30766+
30767+}
30768+
30769+int do_chksum(void)
30770+{
30771+ unsigned long i, j, k, ulPageNumber;
30772+ int Status = 0;
30773+ unsigned short tmp;
30774+ volatile unsigned long sum1, sum2;
30775+ unsigned long goldensum, chksum;
30776+ unsigned long len, tlen;
30777+ unsigned char *pjsum;
30778+
30779+ ulPageNumber = DRAMSIZE >> 12;
30780+ pjsum = (unsigned char *)(m16byteAlignment((unsigned long) chksumbuf));
30781+
30782+ /* start test */
30783+ for (i=0; i<ulPageNumber; i++)
30784+ {
30785+
30786+ sum1 = 0xffff, sum2 = 0xffff;
30787+ len = 0x0800;
30788+ j = 0;
30789+
30790+ while (len)
30791+ {
30792+ tlen = len > 360 ? 360 : len;
30793+ len -= tlen;
30794+ do {
30795+ tmp = *(unsigned short *) (DRAM_BASE + ((i << 12) + j));
30796+ sum1 += (unsigned long) tmp;
30797+ sum2 += sum1;
30798+ j+=2;
30799+ } while (--tlen);
30800+ sum1 = (sum1 & 0xffff) + (sum1 >> 16);
30801+ sum2 = (sum2 & 0xffff) + (sum2 >> 16);
30802+ }
30803+
30804+ sum1 = (sum1 & 0xffff) + (sum1 >> 16);
30805+ sum2 = (sum2 & 0xffff) + (sum2 >> 16);
30806+
30807+ goldensum = (sum2 << 16) | sum1;
30808+ k= 0;
30809+ do {
30810+ chksum = *(unsigned long *) (pjsum + i*4);
30811+ udelay(100);
30812+ k++;
30813+ } while ((chksum == 0) && (k<1000));
30814+
30815+ if (chksum != goldensum)
30816+ {
30817+ Status = 1;
30818+ printf("[FAIL] MIC Chksum Failed at Page %x \n", i);
30819+ }
30820+
30821+ } /* end of i loop */
30822+
30823+ return (Status);
30824+
30825+}
30826+
30827+int do_mictest (void)
30828+{
30829+ unsigned long Flags = 0;
30830+
30831+ vInitSCU();
30832+ vInitMIC();
30833+
30834+ if (do_chksum())
30835+ Flags = 1;
30836+
30837+ vDisableMIC();
30838+
30839+ return Flags;
30840+
30841+}
30842+
30843+#endif /* CONFIG_SLT */
30844diff --git a/board/aspeed/ast2400/mictest.h b/board/aspeed/ast2400/mictest.h
30845new file mode 100755
30846index 0000000..e14bb41
30847--- /dev/null
30848+++ b/board/aspeed/ast2400/mictest.h
30849@@ -0,0 +1,55 @@
30850+/*
30851+ * This program is distributed in the hope that it will be useful,
30852+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
30853+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30854+ * GNU General Public License for more details.
30855+ *
30856+ * You should have received a copy of the GNU General Public License
30857+ * along with this program; if not, write to the Free Software
30858+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30859+ */
30860+/* Macro */
30861+#define m08byteAlignment(x) ((x + 0x00000007) & 0xFFFFFFF8)
30862+#define m16byteAlignment(x) ((x + 0x0000000F) & 0xFFFFFFF0)
30863+#define m64byteAlignment(x) ((x + 0x0000003F) & 0xFFFFFFC0)
30864+
30865+/* Options */
30866+#define MIC_TEST_PAGE 32
30867+#define DRAMSIZE (MIC_TEST_PAGE * 0x1000)
30868+#define MIC_MAX_CTRL (MIC_TEST_PAGE / 4 + 16)
30869+#define MIC_MAX_CHKSUM (MIC_TEST_PAGE * 4 + 16)
30870+
30871+/* Default Setting */
30872+#define DEFAULT_RATE 0x00000000
30873+#define DEFAULT_CTRL 0xFF
30874+#define DEFAULT_CHKSUM 0x00000000
30875+#define DEFAULT_WRITEBACK 0x08880000
30876+
30877+/* Reg. Definition */
30878+#define DRAM_BASE 0x40000000
30879+#define MIC_BASE 0x1e640000
30880+#define MIC_CTRLBUFF_REG 0x00
30881+#define MIC_CHKSUMBUF_REG 0x04
30882+#define MIC_RATECTRL_REG 0x08
30883+#define MIC_ENGINECTRL_REG 0x0C
30884+#define MIC_STOPPAGE_REG 0x10
30885+#define MIC_STATUS_REG 0x14
30886+#define MIC_STATUS1_REG 0x18
30887+#define MIC_STATUS2_REG 0x1C
30888+
30889+#define MIC_RESET_MIC 0x00000000
30890+#define MIC_ENABLE_MIC 0x10000000
30891+#define MIC_MAXPAGE_MASK 0x0FFFF000
30892+#define MIC_WRITEBACK_MASK 0xFFFF0000
30893+#define MIC_STOPPAGE_MASK 0x0000FFFF
30894+#define MIC_PAGEERROR 0x40000000
30895+#define MIC_PAGE1ERROR 0x10000000
30896+#define MIC_PAGE2ERROR 0x20000000
30897+#define MIC_INTMASK 0x00060000
30898+#define MIC_ERRPAGENO_MASK 0x0000FFFF
30899+
30900+#define MIC_CTRL_MASK 0x03
30901+#define MIC_CTRL_SKIP 0x00
30902+#define MIC_CTRL_CHK1 0x01
30903+#define MIC_CTRL_CHK2 0x02
30904+#define MIC_CTRL_CHK3 0x03
30905diff --git a/board/aspeed/ast2400/pci.c b/board/aspeed/ast2400/pci.c
30906new file mode 100755
30907index 0000000..5b17466
30908--- /dev/null
30909+++ b/board/aspeed/ast2400/pci.c
30910@@ -0,0 +1,243 @@
30911+/*
30912+ * This program is free software; you can redistribute it and/or
30913+ * modify it under the terms of the GNU General Public License as
30914+ * published by the Free Software Foundation; either version 2, or (at
30915+ * your option) any later version.
30916+ */
30917+
30918+#include <common.h>
30919+#include <pci.h>
30920+
30921+#ifdef CONFIG_PCI
30922+
30923+#define PCI_CSR_BASE 0x60000000
30924+#define ASPEED_PCI_IO_BASE 0x00000000
30925+#define ASPEED_PCI_IO_SIZE 0x00010000
30926+#define ASPEED_PCI_MEM_BASE 0x68000000
30927+#define ASPEED_PCI_MEM_SIZE 0x18000000
30928+
30929+#define CSR_CRP_CMD_OFFSET 0x00
30930+#define CSR_CRP_WRITE_OFFSET 0x04
30931+#define CSR_CRP_READ_OFFSET 0x08
30932+#define CSR_PCI_ADDR_OFFSET 0x0C
30933+#define CSR_PCI_CMD_OFFSET 0x10
30934+#define CSR_PCI_WRITE_OFFSET 0x14
30935+#define CSR_PCI_READ_OFFSET 0x18
30936+#define CSR_PCI_STATUS_OFFSET 0x1C
30937+
30938+#define CRP_ADDR_REG (volatile ulong*) (PCI_CSR_BASE + CSR_CRP_CMD_OFFSET)
30939+#define CRP_WRITE_REG (volatile ulong*) (PCI_CSR_BASE + CSR_CRP_WRITE_OFFSET)
30940+#define CRP_READ_REG (volatile ulong*) (PCI_CSR_BASE + CSR_CRP_READ_OFFSET)
30941+#define PCI_ADDR_REG (volatile ulong*) (PCI_CSR_BASE + CSR_PCI_ADDR_OFFSET)
30942+#define PCI_CMD_REG (volatile ulong*) (PCI_CSR_BASE + CSR_PCI_CMD_OFFSET)
30943+#define PCI_WRITE_REG (volatile ulong*) (PCI_CSR_BASE + CSR_PCI_WRITE_OFFSET)
30944+#define PCI_READ_REG (volatile ulong*) (PCI_CSR_BASE + CSR_PCI_READ_OFFSET)
30945+
30946+#define PCI_CMD_READ 0x0A
30947+#define PCI_CMD_WRITE 0x0B
30948+
30949+#define RESET_PCI_STATUS *(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_STATUS_OFFSET) = 0x01
30950+#define CHK_PCI_STATUS (*(volatile ulong*) (PCI_CSR_BASE + CSR_PCI_STATUS_OFFSET) & 0x03)
30951+
30952+static int pci_config_access (u8 access_type, u32 dev, u32 reg, u32 * data)
30953+{
30954+ u32 bus;
30955+ u32 device;
30956+ u32 function;
30957+
30958+ bus = ((dev & 0xff0000) >> 16);
30959+ device = ((dev & 0xf800) >> 11);
30960+ function = (dev & 0x0700);
30961+
30962+ if (bus == 0) {
30963+ // Type 0 Configuration
30964+ *PCI_ADDR_REG = (u32) (1UL << device | function | (reg & 0xfc));
30965+ } else {
30966+ // Type 1 Configuration
30967+ *PCI_ADDR_REG = (u32) (dev | ((reg / 4) << 2) | 1);
30968+ }
30969+
30970+ RESET_PCI_STATUS;
30971+
30972+ if (access_type == PCI_CMD_WRITE) {
30973+ *PCI_CMD_REG = (ulong) PCI_CMD_WRITE;
30974+ *PCI_WRITE_REG = *data;
30975+ } else {
30976+ *PCI_CMD_REG = (ulong) PCI_CMD_READ;
30977+ *data = *PCI_READ_REG;
30978+ }
30979+
30980+ return (CHK_PCI_STATUS);
30981+}
30982+
30983+static int aspeed_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
30984+{
30985+ u32 data;
30986+
30987+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data)) {
30988+ *val = 0;
30989+ return -1;
30990+ }
30991+
30992+ *val = (data >> ((reg & 3) << 3)) & 0xff;
30993+
30994+ return 0;
30995+}
30996+
30997+
30998+static int aspeed_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
30999+{
31000+ u32 data;
31001+
31002+ if (reg & 1)
31003+ return -1;
31004+
31005+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data)) {
31006+ *val = 0;
31007+ return -1;
31008+ }
31009+
31010+ *val = (data >> ((reg & 3) << 3)) & 0xffff;
31011+
31012+ return 0;
31013+}
31014+
31015+
31016+static int aspeed_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
31017+ u32 * val)
31018+{
31019+ u32 data = 0;
31020+
31021+ if (reg & 3)
31022+ return -1;
31023+
31024+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data)) {
31025+ *val = 0;
31026+ return -1;
31027+ }
31028+
31029+ *val = data;
31030+
31031+ return (0);
31032+}
31033+
31034+static int aspeed_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
31035+{
31036+ u32 data = 0;
31037+
31038+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data))
31039+ return -1;
31040+
31041+ data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
31042+ ((reg & 3) << 3));
31043+
31044+ if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
31045+ return -1;
31046+
31047+ return 0;
31048+}
31049+
31050+
31051+static int aspeed_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
31052+{
31053+ u32 data = 0;
31054+
31055+ if (reg & 1)
31056+ return -1;
31057+
31058+ if (pci_config_access (PCI_CMD_READ, dev, reg, &data))
31059+ return -1;
31060+
31061+ data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
31062+ ((reg & 3) << 3));
31063+
31064+ if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
31065+ return -1;
31066+
31067+ return 0;
31068+}
31069+
31070+static int aspeed_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
31071+{
31072+ u32 data;
31073+
31074+ if (reg & 3) {
31075+ return -1;
31076+ }
31077+
31078+ data = val;
31079+
31080+ if (pci_config_access (PCI_CMD_WRITE, dev, reg, &data))
31081+ return -1;
31082+
31083+ return (0);
31084+}
31085+
31086+/*
31087+ * Initialize PCIU
31088+ */
31089+aspeed_pciu_init ()
31090+{
31091+
31092+ unsigned long reg;
31093+
31094+ /* Reset PCI Host */
31095+ reg = *((volatile ulong*) 0x1e6e2004);
31096+ *((volatile ulong*) 0x1e6e2004) = reg | 0x00280000;
31097+
31098+ reg = *((volatile ulong*) 0x1e6e2074); /* REQ2 */
31099+ *((volatile ulong*) 0x1e6e2074) = reg | 0x00000010;
31100+
31101+ *((volatile ulong*) 0x1e6e2008) |= 0x00080000;
31102+ reg = *((volatile ulong*) 0x1e6e200c);
31103+ *((volatile ulong*) 0x1e6e200c) = reg & 0xfff7ffff;
31104+ udelay(1);
31105+ *((volatile ulong*) 0x1e6e2004) &= 0xfff7ffff;
31106+
31107+ /* Initial PCI Host */
31108+ RESET_PCI_STATUS;
31109+
31110+ *CRP_ADDR_REG = ((ulong)(PCI_CMD_READ) << 16) | 0x04;
31111+ reg = *CRP_READ_REG;
31112+
31113+ *CRP_ADDR_REG = ((ulong)(PCI_CMD_WRITE) << 16) | 0x04;
31114+ *CRP_WRITE_REG = reg | 0x07;
31115+
31116+}
31117+
31118+/*
31119+ * Initialize Module
31120+ */
31121+
31122+void aspeed_init_pci (struct pci_controller *hose)
31123+{
31124+ hose->first_busno = 0;
31125+ hose->last_busno = 0xff;
31126+
31127+ aspeed_pciu_init (); /* Initialize PCIU */
31128+
31129+ /* PCI memory space #1 */
31130+ pci_set_region (hose->regions + 0,
31131+ ASPEED_PCI_MEM_BASE, ASPEED_PCI_MEM_BASE, ASPEED_PCI_MEM_SIZE, PCI_REGION_MEM);
31132+
31133+ /* PCI I/O space */
31134+ pci_set_region (hose->regions + 1,
31135+ ASPEED_PCI_IO_BASE, ASPEED_PCI_IO_BASE, ASPEED_PCI_IO_SIZE, PCI_REGION_IO);
31136+
31137+ hose->region_count = 2;
31138+
31139+ hose->read_byte = aspeed_pci_read_config_byte;
31140+ hose->read_word = aspeed_pci_read_config_word;
31141+ hose->read_dword = aspeed_pci_read_config_dword;
31142+ hose->write_byte = aspeed_pci_write_config_byte;
31143+ hose->write_word = aspeed_pci_write_config_word;
31144+ hose->write_dword = aspeed_pci_write_config_dword;
31145+
31146+ pci_register_hose (hose);
31147+
31148+ hose->last_busno = pci_hose_scan (hose);
31149+
31150+ return;
31151+}
31152+#endif /* CONFIG_PCI */
31153+
31154diff --git a/board/aspeed/ast2400/platform.S b/board/aspeed/ast2400/platform.S
31155new file mode 100644
31156index 0000000..27e8f26
31157--- /dev/null
31158+++ b/board/aspeed/ast2400/platform.S
31159@@ -0,0 +1,3089 @@
31160+/*
31161+ * This program is distributed in the hope that it will be useful,
31162+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
31163+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31164+ * GNU General Public License for more details.
31165+ *
31166+ * You should have received a copy of the GNU General Public License
31167+ * along with this program; if not, write to the Free Software
31168+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31169+ */
31170+/*
31171+ * Board specific setup info
31172+ *
31173+ ******************************************************************************
31174+ * ASPEED Technology Inc.
31175+ * AST2300/AST2400 DDR2/DDR3 SDRAM controller initialization and calibration sequence
31176+ *
31177+ * Gary Hsu, <gary_hsu@aspeedtech.com>
31178+ *
31179+ * Release date: 2014.12.29 formal release for SDK0.60
31180+ *
31181+ * Modified list from v0.23
31182+ * EC1. Modify DQIDLY and DQSI-MCLK2X calibration algorithm
31183+ * EC2. Remove pass 2 DQIDLY finetune process
31184+ * EC3. Modify ECC code
31185+ * EC4. Add AST2400 supporting
31186+ * EC5. Add SPI timing calibration for AST2400
31187+ * EC6. Remove AST2300-A0 PCI-e workaround
31188+ * EC7. Add CK duty calibration for AST2400
31189+ * EC8. Remove #define CONFIG_DRAM_UART_OUT, default has message output to UART5
31190+ * EC9. Add DRAM size auto-detection
31191+ * EC10. Add GPIO register clear when watchdog reboot (only for AST2400)
31192+ * EC11. Move the "Solve ASPM" code position of AST2300 to avoid watchdog reset
31193+ *
31194+ * Modified list from v0.53
31195+ * EC1. Add solution of LPC lock issue due to watchdog reset. (AP note A2300-11)
31196+ *
31197+ * Modified list from v0.56
31198+ * EC1. Fix read DQS input mask window too late issue if DRAM's t_DQSCK is earlier too much
31199+ * (ex. Nanya NT5CB64M16FP)
31200+ * 1. Change init value of MCR18[4] from '1' to '0'
31201+ * 2. Add CBR4 code to finetune MCR18[4]
31202+ *
31203+ * Modified list from v0.59
31204+ * EC1. Add DQS input gating window delay tuning (1/2 T) when CBR retry
31205+ * EC2. Modify DLL1 MAdj = 0x4C
31206+ *
31207+ * Optional define variable
31208+ * 1. DRAM Speed //
31209+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
31210+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
31211+ * 2. ECC Function enable
31212+ * CONFIG_DRAM_ECC // define to enable ECC function
31213+ * // when enabled, must define the ECC protected memory size at 0x1e6e0054
31214+ * 3. UART5 message output //
31215+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
31216+ ******************************************************************************
31217+ */
31218+
31219+#include <config.h>
31220+#include <version.h>
31221+/******************************************************************************
31222+ Calibration Macro Start
31223+ Usable registers:
31224+ r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11
31225+ ******************************************************************************/
31226+/* PATTERN_TABLE,
31227+ init_delay_timer,
31228+ check_delay_timer,
31229+ clear_delay_timer,
31230+ record_dll2_pass_range,
31231+ record_dll2_pass_range_h,
31232+ are for DRAM calibration */
31233+
31234+PATTERN_TABLE:
31235+ .word 0xff00ff00
31236+ .word 0xcc33cc33
31237+ .word 0xaa55aa55
31238+ .word 0x88778877
31239+ .word 0x92cc4d6e @ 5
31240+ .word 0x543d3cde
31241+ .word 0xf1e843c7
31242+ .word 0x7c61d253
31243+ .word 0x00000000 @ 8
31244+
31245+ .macro init_delay_timer
31246+ ldr r0, =0x1e782024 @ Set Timer3 Reload
31247+ str r2, [r0]
31248+
31249+ ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
31250+ ldr r1, =0x00040000
31251+ str r1, [r0]
31252+
31253+ ldr r0, =0x1e782030 @ Enable Timer3
31254+ ldr r1, [r0]
31255+ mov r2, #7
31256+ orr r1, r1, r2, lsl #8
31257+ str r1, [r0]
31258+
31259+ ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout
31260+ .endm
31261+
31262+ .macro check_delay_timer
31263+ ldr r1, [r0]
31264+ bic r1, r1, #0xFFFBFFFF
31265+ mov r2, r1, lsr #18
31266+ cmp r2, #0x01
31267+ .endm
31268+
31269+ .macro clear_delay_timer
31270+ ldr r0, =0x1e782030 @ Disable Timer3
31271+ ldr r1, [r0]
31272+ bic r1, r1, #0x00000F00
31273+ str r1, [r0]
31274+
31275+ ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
31276+ ldr r1, =0x00040000
31277+ str r1, [r0]
31278+ .endm
31279+
31280+ .macro record_dll2_pass_range
31281+ ldr r1, [r0]
31282+ bic r2, r1, #0xFFFFFF00
31283+ cmp r2, r3 @ record min
31284+ bicgt r1, r1, #0x000000FF
31285+ orrgt r1, r1, r3
31286+ bic r2, r1, #0xFFFF00FF
31287+ cmp r3, r2, lsr #8 @ record max
31288+ bicgt r1, r1, #0x0000FF00
31289+ orrgt r1, r1, r3, lsl #8
31290+ str r1, [r0]
31291+ .endm
31292+
31293+ .macro record_dll2_pass_range_h
31294+ ldr r1, [r0]
31295+ bic r2, r1, #0xFF00FFFF
31296+ mov r2, r2, lsr #16
31297+ cmp r2, r3 @ record min
31298+ bicgt r1, r1, #0x00FF0000
31299+ orrgt r1, r1, r3, lsl #16
31300+ bic r2, r1, #0x00FFFFFF
31301+ cmp r3, r2, lsr #24 @ record max
31302+ bicgt r1, r1, #0xFF000000
31303+ orrgt r1, r1, r3, lsl #24
31304+ str r1, [r0]
31305+ .endm
31306+
31307+ .macro init_spi_checksum
31308+ ldr r0, =0x1e620084
31309+ ldr r1, =0x20010000
31310+ str r1, [r0]
31311+ ldr r0, =0x1e62008C
31312+ ldr r1, =0x20000200
31313+ str r1, [r0]
31314+ ldr r0, =0x1e620080
31315+ ldr r1, =0x0000000D
31316+ orr r2, r2, r7
31317+ orr r1, r1, r2, lsl #8
31318+ and r2, r6, #0xF
31319+ orr r1, r1, r2, lsl #4
31320+ str r1, [r0]
31321+ ldr r0, =0x1e620008
31322+ ldr r2, =0x00000800
31323+ .endm
31324+
31325+/******************************************************************************
31326+ Calibration Macro End
31327+ ******************************************************************************/
31328+LPC_Patch: @ load to SRAM base 0x1e720400
31329+ str r1, [r0]
31330+ str r3, [r2]
31331+ bic r1, r1, #0xFF
31332+LPC_Patch_S1:
31333+ subs r5, r5, #0x01
31334+ moveq pc, r8
31335+ ldr r3, [r2]
31336+ tst r3, #0x01
31337+ movne pc, r8
31338+ mov pc, r7
31339+LPC_Patch_S2: @ load to SRAM base 0x1e720480
31340+ str r1, [r0]
31341+ mov pc, r9
31342+LPC_Patch_E:
31343+
31344+.globl lowlevel_init
31345+lowlevel_init:
31346+
31347+init_dram:
31348+ /* save lr */
31349+ mov r4, lr
31350+/* Test - DRAM initial time */
31351+ ldr r0, =0x1e782044
31352+ ldr r1, =0xFFFFFFFF
31353+ str r1, [r0]
31354+
31355+ ldr r0, =0x1e782030
31356+ ldr r1, [r0]
31357+ bic r1, r1, #0x0000F000
31358+ str r1, [r0]
31359+ mov r2, #3
31360+ orr r1, r1, r2, lsl #12
31361+ str r1, [r0]
31362+/* Test - DRAM initial time */
31363+
31364+ /*Set Scratch register Bit 7 before initialize*/
31365+ ldr r0, =0x1e6e2000
31366+ ldr r1, =0x1688a8a8
31367+ str r1, [r0]
31368+
31369+ ldr r0, =0x1e6e2040
31370+ ldr r1, [r0]
31371+ orr r1, r1, #0x80
31372+ str r1, [r0]
31373+
31374+ /* Fix LPC lock issue for AST2300 */
31375+ ldr r0, =0x1e6e207c @ Check AST2300
31376+ ldr r1, [r0]
31377+ mov r1, r1, lsr #24
31378+ cmp r1, #0x01
31379+ bne lpc_recover_end @ not match AST2300
31380+
31381+ mov r3, #0x0
31382+lpc_recover_check:
31383+ ldr r0, =0x1e78900c @ check HICR3[4]=0x1
31384+ ldr r1, [r0]
31385+ tst r1, #0x10
31386+ beq lpc_recover_end
31387+ ldr r0, =0x1e789004 @ check HICR1[7]=0x1
31388+ ldr r1, [r0]
31389+ tst r1, #0x80
31390+ beq lpc_recover_end
31391+ ldr r0, =0x1e7890a0 @ check LHCR0[27:24]=0x6
31392+ ldr r1, [r0]
31393+ mov r1, r1, lsr #24
31394+ and r1, r1, #0xF
31395+ cmp r1, #0x06
31396+ bne lpc_recover_end
31397+ add r3, r3, #0x01
31398+ cmp r3, #0x5 @ repeat 5 times
31399+ ble lpc_recover_check
31400+
31401+ mov r3, #0x0
31402+lpc_recover_init:
31403+ ldr r0, =0x1e7890a4 @ set LHCR1[1:0]=0x0
31404+ ldr r1, =0x00000000
31405+ str r1, [r0]
31406+ add r3, r3, #0x01
31407+ cmp r3, #0x20
31408+ bge lpc_recover_end
31409+ ldr r1, [r0]
31410+ tst r1, #0x01
31411+ bne lpc_recover_init
31412+
31413+ ldr r0, =0x1e7890b0 @ set LHCR4[7:0]=0xFF
31414+ ldr r1, =0x000000FF
31415+ str r1, [r0]
31416+ ldr r0, =0x1e7890b4 @ set LHCR5[31:0]=0xFFFFFFFF
31417+ ldr r1, =0xFFFFFFFF
31418+ str r1, [r0]
31419+ ldr r0, =0x1e7890b8 @ set LHCR6[31:0]=0xFFFFFFFF
31420+ str r1, [r0]
31421+
31422+ adr r6, LPC_Patch
31423+ adr r7, LPC_Patch_S2
31424+ ldr r0, =0x1e720400
31425+copy_lpc_patch_1:
31426+ ldr r1, [r6]
31427+ str r1, [r0]
31428+ add r6, r6, #0x4
31429+ add r0, r0, #0x4
31430+ cmp r6, r7
31431+ bne copy_lpc_patch_1
31432+
31433+ adr r6, LPC_Patch_S2
31434+ adr r7, LPC_Patch_E
31435+ ldr r0, =0x1e720480
31436+copy_lpc_patch_2:
31437+ ldr r1, [r6]
31438+ str r1, [r0]
31439+ add r6, r6, #0x4
31440+ add r0, r0, #0x4
31441+ cmp r6, r7
31442+ bne copy_lpc_patch_2
31443+
31444+ ldr r0, =0x1e7890a0 @ set LHCR0[31:0]=0xFFFFFF01
31445+ ldr r1, =0xFFFFFF01
31446+ add r2, r0, #0x4
31447+ mov r3, #0x01
31448+ mov r5, #0x10
31449+ adr r9, lpc_recover_end
31450+ adr r6, LPC_Patch
31451+ adr r7, LPC_Patch_S1
31452+ sub r6, r7, r6
31453+ ldr r7, =0x1e720400
31454+ add r7, r7, r6
31455+ ldr r8, =0x1e720480
31456+ ldr pc, =0x1e720400
31457+
31458+lpc_recover_end:
31459+ ldr r0, =0x1e7890a0 @ set LHCR0[31:0]=0xFFFFFF00
31460+ ldr r1, =0xFFFFFF00
31461+ str r1, [r0]
31462+ /* <END> Fix LPC lock issue for AST2300 */
31463+
31464+ /* Check Scratch Register Bit 6 */
31465+ ldr r0, =0x1e6e2040
31466+ ldr r1, [r0]
31467+ bic r1, r1, #0xFFFFFFBF
31468+ mov r2, r1, lsr #6
31469+ cmp r2, #0x01
31470+ beq platform_exit
31471+
31472+ ldr r2, =0x033103F1 @ load PLL parameter for 24Mhz CLKIN (396:324)
31473+/* ldr r2, =0x019001F0 @ load PLL parameter for 24Mhz CLKIN (408:336) */
31474+ ldr r0, =0x1e6e207c @ Check Revision ID
31475+ ldr r1, [r0]
31476+ mov r1, r1, lsr #24
31477+ cmp r1, #0x02
31478+ bne set_MPLL @ not match AST2400
31479+
31480+ ldr r0, =0x1e6e2070 @ Check CLKIN freq
31481+ ldr r1, [r0]
31482+ mov r1, r1, lsr #23
31483+ tst r1, #0x01
31484+ ldrne r2, =0x017001D0 @ load PLL parameter for 25Mhz CLKIN (400:325)
31485+
31486+set_MPLL:
31487+ ldr r0, =0x1e6e2020 @ M-PLL (DDR SDRAM) Frequency
31488+ ldr r1, =0xFFFF
31489+#if defined(CONFIG_DRAM_336)
31490+ mov r2, r2, lsr #16
31491+#endif
31492+ and r1, r2, r1
31493+ str r1, [r0]
31494+
31495+/* Debug - UART console message */
31496+ ldr r0, =0x1e78400c
31497+ mov r1, #0x83
31498+ str r1, [r0]
31499+
31500+ ldr r0, =0x1e6e202c
31501+ ldr r2, [r0]
31502+ mov r2, r2, lsr #12
31503+ tst r2, #0x01
31504+ ldr r0, =0x1e784000
31505+ moveq r1, #0x0D @ Baudrate 115200
31506+ movne r1, #0x01 @ Baudrate 115200, div13
31507+#if defined(CONFIG_DRAM_UART_38400)
31508+ moveq r1, #0x27 @ Baudrate 38400
31509+ movne r1, #0x03 @ Baudrate 38400 , div13
31510+#endif
31511+ str r1, [r0]
31512+
31513+ ldr r0, =0x1e784004
31514+ mov r1, #0x00
31515+ str r1, [r0]
31516+
31517+ ldr r0, =0x1e78400c
31518+ mov r1, #0x03
31519+ str r1, [r0]
31520+
31521+ ldr r0, =0x1e784008
31522+ mov r1, #0x07
31523+ str r1, [r0]
31524+
31525+ ldr r0, =0x1e784000
31526+ mov r1, #0x0D @ '\r'
31527+ str r1, [r0]
31528+ mov r1, #0x0A @ '\n'
31529+ str r1, [r0]
31530+ mov r1, #0x44 @ 'D'
31531+ str r1, [r0]
31532+ mov r1, #0x52 @ 'R'
31533+ str r1, [r0]
31534+ mov r1, #0x41 @ 'A'
31535+ str r1, [r0]
31536+ mov r1, #0x4D @ 'M'
31537+ str r1, [r0]
31538+ mov r1, #0x20 @ ' '
31539+ str r1, [r0]
31540+ mov r1, #0x49 @ 'I'
31541+ str r1, [r0]
31542+ mov r1, #0x6E @ 'n'
31543+ str r1, [r0]
31544+ mov r1, #0x69 @ 'i'
31545+ str r1, [r0]
31546+ mov r1, #0x74 @ 't'
31547+ str r1, [r0]
31548+ mov r1, #0x2D @ '-'
31549+ str r1, [r0]
31550+ mov r1, #0x44 @ 'D'
31551+ str r1, [r0]
31552+ mov r1, #0x44 @ 'D'
31553+ str r1, [r0]
31554+ mov r1, #0x52 @ 'R'
31555+ str r1, [r0]
31556+/* Debug - UART console message */
31557+
31558+ /* Delay about 100us */
31559+ ldr r0, =0x1e782030 @ Init Timer3 Control
31560+ ldr r1, [r0]
31561+ bic r1, r1, #0x00000F00
31562+ str r1, [r0]
31563+
31564+ ldr r2, =0x00000064 @ Set Timer3 Reload = 100 us
31565+ init_delay_timer
31566+delay_0:
31567+ check_delay_timer
31568+ bne delay_0
31569+ clear_delay_timer
31570+ /* end delay 100us */
31571+
31572+/******************************************************************************
31573+ Init DRAM common registers
31574+ ******************************************************************************/
31575+ ldr r0, =0x1e6e0000
31576+ ldr r1, =0xfc600309
31577+ str r1, [r0]
31578+
31579+ /* Reset MMC */
31580+ ldr r1, =0x00000000
31581+ ldr r0, =0x1e6e0034
31582+ str r1, [r0]
31583+ ldr r0, =0x1e6e0018
31584+ str r1, [r0]
31585+ ldr r0, =0x1e6e0024
31586+ str r1, [r0]
31587+ ldr r0, =0x1e6e0064 @ REG_MADJ, power down DLL
31588+ str r1, [r0]
31589+
31590+ ldr r1, =0x00034C4C @ REG_MADJ, reset DLL
31591+ str r1, [r0]
31592+
31593+ ldr r0, =0x1e6e0068 @ REG_SADJ
31594+ ldr r1, =0x00001800
31595+ str r1, [r0]
31596+
31597+ /* Delay about 10us */
31598+ ldr r2, =0x0000000B @ Set Timer3 Reload = 10 us
31599+ init_delay_timer
31600+delay_1:
31601+ check_delay_timer
31602+ bne delay_1
31603+ clear_delay_timer
31604+ /* end delay 10us */
31605+
31606+ ldr r0, =0x1e6e0064 @ REG_MADJ | 0xC0000, enable DLL
31607+ ldr r1, [r0]
31608+ ldr r2, =0xC0000
31609+ orr r1, r1, r2
31610+ str r1, [r0]
31611+
31612+ ldr r0, =0x1e6e0008
31613+ ldr r1, =0x0090040f /* VGA */
31614+ str r1, [r0]
31615+
31616+ ldr r0, =0x1e6e0018
31617+ ldr r1, =0x4000A120
31618+ str r1, [r0]
31619+
31620+ ldr r0, =0x1e6e0018
31621+ ldr r1, =0x00000120
31622+ str r1, [r0]
31623+
31624+ ldr r0, =0x1e6e0038
31625+ ldr r1, =0x00000000
31626+ str r1, [r0]
31627+
31628+ ldr r0, =0x1e6e0040
31629+ ldr r1, =0xFF444444
31630+ str r1, [r0]
31631+
31632+ ldr r0, =0x1e6e0044
31633+ ldr r1, =0x22222222
31634+ str r1, [r0]
31635+
31636+ ldr r0, =0x1e6e0048
31637+ ldr r1, =0x22222222
31638+ str r1, [r0]
31639+
31640+ ldr r0, =0x1e6e004c
31641+ ldr r1, =0x22222222
31642+ str r1, [r0]
31643+
31644+ ldr r0, =0x1e6e0050
31645+ ldr r1, =0x80000000
31646+ str r1, [r0]
31647+
31648+ ldr r0, =0x1e6e0050
31649+ ldr r1, =0x00000000
31650+ str r1, [r0]
31651+
31652+ ldr r0, =0x1e6e0054
31653+ ldr r1, =0x00000000
31654+ str r1, [r0]
31655+
31656+ ldr r0, =0x1e6e0060 @ REG_DRV
31657+ ldr r1, =0x000000FA @ 408 MHz
31658+#if defined(CONFIG_DRAM_336)
31659+ ldr r1, =0x000000FA
31660+#endif
31661+ str r1, [r0]
31662+
31663+ ldr r0, =0x1e6e0070
31664+ ldr r1, =0x00000000
31665+ str r1, [r0]
31666+
31667+ ldr r0, =0x1e6e0074
31668+ ldr r1, =0x00000000
31669+ str r1, [r0]
31670+
31671+ ldr r0, =0x1e6e0078
31672+ ldr r1, =0x00000000
31673+ str r1, [r0]
31674+
31675+ ldr r0, =0x1e6e007c
31676+ ldr r1, =0x00000000
31677+ str r1, [r0]
31678+
31679+ ldr r0, =0x1e6e0080
31680+ ldr r1, =0x00000000
31681+ str r1, [r0]
31682+
31683+ ldr r0, =0x1e6e0084
31684+ ldr r1, =0x00FFFFFF
31685+ str r1, [r0]
31686+
31687+ ldr r0, =0x1e6e0088 @ REG_DQIDLY
31688+ ldr r1, =0x00000089 @ 408 MHz
31689+#if defined(CONFIG_DRAM_336)
31690+ ldr r1, =0x00000074
31691+#endif
31692+ str r1, [r0]
31693+
31694+ ldr r0, =0x1e6e0020 @ REG_DQSIC
31695+ ldr r1, =0x000000E2 @ 408 MHz
31696+#if defined(CONFIG_DRAM_336)
31697+ ldr r1, =0x000000BA
31698+#endif
31699+ str r1, [r0]
31700+
31701+ /* Delay about 10us */
31702+ ldr r2, =0x0000000B @ Set Timer3 Reload = 10 us
31703+ init_delay_timer
31704+delay_2:
31705+ check_delay_timer
31706+ bne delay_2
31707+ clear_delay_timer
31708+ /* end delay 10us */
31709+
31710+ /* Check DRAM Type by H/W Trapping */
31711+ ldr r0, =0x1e6e2070
31712+ ldr r1, [r0]
31713+ bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2
31714+ mov r2, r1, lsr #24
31715+ cmp r2, #0x01
31716+ beq ddr2_init
31717+ b ddr3_init
31718+.LTORG
31719+
31720+/******************************************************************************
31721+ DDR3 Init
31722+
31723+ tRCD = 15 ns
31724+ tRAS = 37.5 ns
31725+ tRRD = max(4 CK,10 ns)
31726+ tRP = 15 ns
31727+ tRFC = 110ns/1Gbit, 160ns/2Gbit, 300ns/4Gbit
31728+ tRTP = max(4 CK,7.5 ns)
31729+ tWR = 15 ns
31730+ tXSNR = max(10 CK,200 ns)
31731+ tWTR = max(4 CK,7.5 ns)
31732+ tFAW = 50 ns
31733+ tMRD = max(15 CK,20 ns)
31734+ ******************************************************************************/
31735+ddr3_init:
31736+/* Debug - UART console message */
31737+ ldr r0, =0x1e784000
31738+ mov r1, #0x33 @ '3'
31739+ str r1, [r0]
31740+ mov r1, #0x0D @ '\r'
31741+ str r1, [r0]
31742+ mov r1, #0x0A @ '\n'
31743+ str r1, [r0]
31744+/* Debug - UART console message */
31745+
31746+ ldr r0, =0x1e6e0004
31747+ ldr r1, =0x00000531 @ Default set to 1Gbit
31748+ str r1, [r0]
31749+
31750+ ldr r0, =0x1e6e0010 @ REG_AC1
31751+ ldr r1, =0x33302825 @ 408 MHz
31752+#if defined(CONFIG_DRAM_336)
31753+ ldr r1, =0x22202725
31754+#endif
31755+ str r1, [r0]
31756+
31757+ /* Check DRAM CL Timing by H/W Trapping */
31758+ ldr r0, =0x1e6e2070
31759+ ldr r1, [r0]
31760+ bic r1, r1, #0xF9FFFFFF
31761+ mov r2, r1, lsr #9 @ Set CL
31762+ ldr r1, =0x00020000
31763+ add r2, r2, r1
31764+ ldr r1, [r0]
31765+ bic r1, r1, #0xFBFFFFFF
31766+ mov r1, r1, lsr #6 @ Set CWL
31767+ orr r2, r2, r1
31768+ ldr r1, =0x00300000
31769+ add r2, r2, r1
31770+
31771+ ldr r0, =0x1e6e0014 @ REG_AC2
31772+ ldr r1, =0xCC00963F @ 408 MHz
31773+#if defined(CONFIG_DRAM_336)
31774+ ldr r1, =0xAA007636
31775+#endif
31776+ orr r1, r1, r2
31777+ str r1, [r0]
31778+
31779+ ldr r0, =0x1e6e0004 @ check 2400 mode
31780+ ldr r2, [r0]
31781+ mov r2, r2, lsr #10
31782+
31783+ ldr r0, =0x1e6e006c @ REG_IOZ
31784+ ldr r1, =0x00002312 @ 408 MHz
31785+#if defined(CONFIG_DRAM_336)
31786+ ldr r1, =0x00002312
31787+#endif
31788+ tst r2, #0x01
31789+ moveq r1, r1, lsr #8
31790+ str r1, [r0]
31791+
31792+ ldr r0, =0x1e6e0120
31793+ mov r1, #0
31794+ str r1, [r0]
31795+ tst r2, #0x01 @ check AST2300
31796+ beq CBRDLL1_2300_Start
31797+ ldr r0, =0x1e6e207c @ check AST2400 revision A0
31798+ ldr r1, [r0]
31799+ mov r1, r1, lsr #16
31800+ and r1, r1, #0xFF
31801+ cmp r1, #0x0
31802+ beq CBRDLL1_2300_Start
31803+ b CBRDLL1_2400_Start
31804+MCLK2X_Phase_CBR_Done_DDR3:
31805+ ldr r0, =0x1e6e0018
31806+ ldr r1, [r0]
31807+ orr r1, r1, #0x40
31808+ str r1, [r0]
31809+
31810+ ldr r0, =0x1e6e0034
31811+ ldr r1, =0x00000001
31812+ str r1, [r0]
31813+
31814+ ldr r0, =0x1e6e000c
31815+ ldr r1, =0x00000040
31816+ str r1, [r0]
31817+
31818+ /* Delay about 400us */
31819+ ldr r2, =0x00000190 @ Set Timer3 Reload = 400 us
31820+ init_delay_timer
31821+delay3_4:
31822+ check_delay_timer
31823+ bne delay3_4
31824+ clear_delay_timer
31825+ /* end delay 400us */
31826+
31827+ /* Check DRAM CL Timing by H/W Trapping */
31828+ ldr r0, =0x1e6e2070
31829+ ldr r1, [r0]
31830+ bic r1, r1, #0xF9FFFFFF
31831+ mov r2, r1, lsr #21 @ Set CL
31832+ ldr r1, =0x00000010
31833+ add r2, r2, r1
31834+ ldr r1, [r0]
31835+ bic r1, r1, #0xFBFFFFFF
31836+ mov r1, r1, lsr #7 @ Set CWL
31837+ orr r2, r2, r1
31838+
31839+ ldr r0, =0x1e6e002c @ REG_MRS
31840+ ldr r1, =0x04001700 @ 408 MHz
31841+#if defined(CONFIG_DRAM_336)
31842+ ldr r1, =0x04001500
31843+#endif
31844+ orr r1, r1, r2
31845+ str r1, [r0]
31846+
31847+ ldr r0, =0x1e6e0030 @ REG_EMRS
31848+ ldr r1, =0x00000000 @ 408 MHz
31849+#if defined(CONFIG_DRAM_336)
31850+ ldr r1, =0x00000000
31851+#endif
31852+ str r1, [r0]
31853+
31854+ ldr r0, =0x1e6e0028 @ Set EMRS2
31855+ ldr r1, =0x00000005
31856+ str r1, [r0]
31857+
31858+ ldr r0, =0x1e6e0028 @ Set EMRS3
31859+ ldr r1, =0x00000007
31860+ str r1, [r0]
31861+
31862+ ldr r0, =0x1e6e0028 @ Set EMRS
31863+ ldr r1, =0x00000003
31864+ str r1, [r0]
31865+
31866+ ldr r0, =0x1e6e0028 @ Set MRS
31867+ ldr r1, =0x00000001
31868+ str r1, [r0]
31869+
31870+ ldr r0, =0x1e6e002c @ REG_MRS
31871+ ldr r1, =0x04001600 @ 408 MHz
31872+#if defined(CONFIG_DRAM_336)
31873+ ldr r1, =0x04001400
31874+#endif
31875+ orr r1, r1, r2
31876+ str r1, [r0]
31877+
31878+ ldr r0, =0x1e6e000c @ Refresh 8 times
31879+ ldr r1, =0x00005C48
31880+ str r1, [r0]
31881+
31882+ ldr r0, =0x1e6e0028 @ Set MRS
31883+ ldr r1, =0x00000001
31884+ str r1, [r0]
31885+
31886+ ldr r0, =0x1e6e000c @ Set refresh cycle
31887+ ldr r1, =0x00002001
31888+ str r1, [r0]
31889+
31890+ ldr r0, =0x1e6e0014
31891+ ldr r1, [r0]
31892+ bic r1, r1, #0xFFF9FFFF
31893+ mov r2, r1, lsr #3 @ get CL
31894+
31895+ ldr r0, =0x1e6e0034 @ REG_PWC
31896+ ldr r1, =0x00000303 @ 408 MHz
31897+#if defined(CONFIG_DRAM_336)
31898+ ldr r1, =0x00000303
31899+#endif
31900+ orr r1, r1, r2
31901+ str r1, [r0]
31902+
31903+ b Calibration_Start
31904+.LTORG
31905+/******************************************************************************
31906+ End DDR3 Init
31907+ ******************************************************************************/
31908+
31909+/******************************************************************************
31910+ DDR2 Init
31911+
31912+ tRCD = 15 ns
31913+ tRAS = 45 ns
31914+ tRRD = 10 ns
31915+ tRP = 15 ns
31916+ tRFC = 105ns/512Mbit, 127.5ns/1Gbit, 197.5ns/2Gbit, 327.5ns/4Gbit
31917+ tRTP = 7.5 ns
31918+ tWR = 15 ns
31919+ tXSNR = 200 ns
31920+ tWTR = 7.5 ns
31921+ tFAW = 50 ns
31922+ tMRD = 4 CK
31923+ ******************************************************************************/
31924+ddr2_init:
31925+/* Debug - UART console message */
31926+ ldr r0, =0x1e784000
31927+ mov r1, #0x32 @ '2'
31928+ str r1, [r0]
31929+ mov r1, #0x0D @ '\r'
31930+ str r1, [r0]
31931+ mov r1, #0x0A @ '\n'
31932+ str r1, [r0]
31933+/* Debug - UART console message */
31934+
31935+ ldr r0, =0x1e6e0004
31936+ ldr r1, =0x00000510 @ Default set to 512Mbit
31937+ str r1, [r0]
31938+
31939+ ldr r0, =0x1e6e0010 @ REG_AC1
31940+ ldr r1, =0x33302714 @ 408 MHz
31941+#if defined(CONFIG_DRAM_336)
31942+ ldr r1, =0x22201613
31943+#endif
31944+ str r1, [r0]
31945+
31946+ /* Check DRAM CL Timing by H/W Trapping */
31947+ ldr r0, =0x1e6e2070
31948+ ldr r1, [r0]
31949+ bic r1, r1, #0xF9FFFFFF
31950+ mov r2, r1, lsr #5 @ Set CL
31951+ mov r1, r2, lsr #4 @ Set CWL
31952+ orr r2, r2, r1
31953+ ldr r1, =0x00110000
31954+ add r2, r2, r1
31955+
31956+ ldr r0, =0x1e6e0014 @ REG_AC2
31957+ ldr r1, =0xCC00B03F @ 408 MHz
31958+#if defined(CONFIG_DRAM_336)
31959+ ldr r1, =0xAA00903B
31960+#endif
31961+ orr r1, r1, r2
31962+ str r1, [r0]
31963+
31964+ ldr r0, =0x1e6e0004 @ check 2400 mode
31965+ ldr r2, [r0]
31966+ mov r2, r2, lsr #10
31967+
31968+ ldr r0, =0x1e6e006c @ REG_IOZ
31969+ ldr r1, =0x00002312 @ 408 MHz
31970+#if defined(CONFIG_DRAM_336)
31971+ ldr r1, =0x00002312
31972+#endif
31973+ tst r2, #0x01
31974+ moveq r1, r1, lsr #8
31975+ str r1, [r0]
31976+
31977+ ldr r0, =0x1e6e0120
31978+ mov r1, #1
31979+ str r1, [r0]
31980+ tst r2, #0x01 @ check AST2300
31981+ beq CBRDLL1_2300_Start
31982+ ldr r0, =0x1e6e207c @ check AST2400 revision A0
31983+ ldr r1, [r0]
31984+ mov r1, r1, lsr #16
31985+ and r1, r1, #0xFF
31986+ cmp r1, #0x0
31987+ beq CBRDLL1_2300_Start
31988+ b CBRDLL1_2400_Start
31989+MCLK2X_Phase_CBR_Done_DDR2:
31990+
31991+ ldr r0, =0x1e6e0034
31992+ ldr r1, =0x00000001
31993+ str r1, [r0]
31994+
31995+ ldr r0, =0x1e6e000c
31996+ ldr r1, =0x00000000
31997+ str r1, [r0]
31998+
31999+ /* Delay about 400us */
32000+ ldr r2, =0x00000190 @ Set Timer3 Reload = 400 us
32001+ init_delay_timer
32002+delay2_4:
32003+ check_delay_timer
32004+ bne delay2_4
32005+ clear_delay_timer
32006+ /* end delay 400us */
32007+
32008+ /* Check DRAM CL Timing by H/W Trapping */
32009+ ldr r0, =0x1e6e2070
32010+ ldr r1, [r0]
32011+ bic r1, r1, #0xF9FFFFFF
32012+ mov r2, r1, lsr #21 @ Set CL
32013+ ldr r1, =0x00000040
32014+ orr r2, r2, r1
32015+
32016+ ldr r0, =0x1e6e002c @ REG_MRS
32017+ ldr r1, =0x00000D03 @ 408 MHz
32018+#if defined(CONFIG_DRAM_336)
32019+ ldr r1, =0x00000B03
32020+#endif
32021+ orr r1, r1, r2
32022+ str r1, [r0]
32023+
32024+ ldr r0, =0x1e6e0030 @ REG_EMRS
32025+ ldr r1, =0x00000040 @ 408 MHz
32026+#if defined(CONFIG_DRAM_336)
32027+ ldr r1, =0x00000040
32028+#endif
32029+ str r1, [r0]
32030+
32031+ ldr r0, =0x1e6e0028 @ Set EMRS2
32032+ ldr r1, =0x00000005
32033+ str r1, [r0]
32034+
32035+ ldr r0, =0x1e6e0028 @ Set EMRS3
32036+ ldr r1, =0x00000007
32037+ str r1, [r0]
32038+
32039+ ldr r0, =0x1e6e0028 @ Set EMRS
32040+ ldr r1, =0x00000003
32041+ str r1, [r0]
32042+
32043+ ldr r0, =0x1e6e0028 @ Set MRS
32044+ ldr r1, =0x00000001
32045+ str r1, [r0]
32046+
32047+ ldr r0, =0x1e6e000c @ Refresh 8 times
32048+ ldr r1, =0x00005C08
32049+ str r1, [r0]
32050+
32051+ ldr r0, =0x1e6e002c @ REG_MRS
32052+ ldr r1, =0x00000C03 @ 408 MHz
32053+#if defined(CONFIG_DRAM_336)
32054+ ldr r1, =0x00000A03
32055+#endif
32056+ orr r1, r1, r2
32057+ str r1, [r0]
32058+
32059+ ldr r0, =0x1e6e0028 @ Set MRS
32060+ ldr r1, =0x00000001
32061+ str r1, [r0]
32062+
32063+ ldr r0, =0x1e6e0030 @ REG_EMRS
32064+ ldr r1, =0x000003C0 @ 408 MHz
32065+#if defined(CONFIG_DRAM_336)
32066+ ldr r1, =0x000003C0
32067+#endif
32068+ str r1, [r0]
32069+
32070+ ldr r0, =0x1e6e0028 @ Set EMRS
32071+ ldr r1, =0x00000003
32072+ str r1, [r0]
32073+
32074+ ldr r0, =0x1e6e0030 @ REG_EMRS
32075+ ldr r1, =0x00000040 @ 408 MHz
32076+#if defined(CONFIG_DRAM_336)
32077+ ldr r1, =0x00000040
32078+#endif
32079+ str r1, [r0]
32080+
32081+ ldr r0, =0x1e6e0028 @ Set EMRS
32082+ ldr r1, =0x00000003
32083+ str r1, [r0]
32084+
32085+ ldr r0, =0x1e6e000c @ Set refresh cycle
32086+ ldr r1, =0x00002001
32087+ str r1, [r0]
32088+
32089+ ldr r0, =0x1e6e0014
32090+ ldr r1, [r0]
32091+ bic r1, r1, #0xFFF9FFFF
32092+ mov r2, r1, lsr #3 @ get CL
32093+
32094+ ldr r0, =0x1e6e0034 @ REG_PWC
32095+ ldr r1, =0x00000503 @ 408 MHz
32096+#if defined(CONFIG_DRAM_336)
32097+ ldr r1, =0x00000503
32098+#endif
32099+ orr r1, r1, r2
32100+ str r1, [r0]
32101+
32102+ b Calibration_Start
32103+.LTORG
32104+/******************************************************************************
32105+ End DDR2 Init
32106+ ******************************************************************************/
32107+/******************************************************************************
32108+ DDR CK duty finetune program
32109+ SRAM buffer definition
32110+ 0x1E720204 : gdll golden DLL1 record
32111+ 0x1E720208 : gduty golden duty setting record
32112+ 0x1E72020C : gdutysum golden duty data record
32113+ 0x1E720210 : duty record of delay 0 invert
32114+ 0x1E720214 : duty record of delay 1 invert
32115+ ....
32116+ 0x1E72024C : duty record of delay 15 invert
32117+ 0x1E720250 : duty record of delay 0
32118+ 0x1E720254 : duty record of delay 1
32119+ ....
32120+ 0x1E72028C : duty record of delay 15
32121+
32122+ Register usage
32123+ r0 - r3 = free
32124+ r4 = record the return pc value, do not use
32125+ r5 = free
32126+ r6 = free
32127+ r7 = duty count
32128+ r8 = gdll
32129+ r9 = gduty
32130+ r10 = gdutysum
32131+ ******************************************************************************/
32132+CBRDLL1_2400_Start:
32133+ ldr r0, =0x1e6e0120
32134+ ldr r1, [r0]
32135+ orr r1, r1, #0x02
32136+ str r1, [r0]
32137+
32138+ ldr r1, =0x00000000
32139+ ldr r0, =0x1e720204
32140+ ldr r2, =0x1e7202a0
32141+init_sram_start0:
32142+ str r1, [r0]
32143+ add r0, r0, #4
32144+ cmp r0, r2
32145+ blt init_sram_start0
32146+
32147+ ldr r0, =0x1e6e0034
32148+ mov r1, #0x20
32149+ str r1, [r0]
32150+
32151+ ldr r0, =0x1e6e0060
32152+ ldr r1, [r0]
32153+ mov r2, #0x01
32154+ orr r1, r1, r2, lsl #13
32155+ str r1, [r0]
32156+
32157+ mov r7, #0x0 @ init duty count
32158+ mov r8, #0x0 @ init gdll
32159+ mov r9, #0x0 @ init gduty
32160+ mov r10, #0x0 @ init gdutysum
32161+cbrdll1_duty_start:
32162+ cmp r7, #32
32163+ bge cbrdll1_duty_end
32164+
32165+ ldr r0, =0x1e6e0018
32166+ ldr r1, =0x00008120
32167+ str r1, [r0]
32168+
32169+ ldr r0, =0x1e6e0060
32170+ ldr r1, [r0]
32171+ bic r1, r1, #0x00001F00
32172+ orr r1, r1, r7, lsl #8
32173+ mov r2, #0x10
32174+ eor r1, r1, r2, lsl #8
32175+ str r1, [r0]
32176+
32177+ ldr r0, =0x1e6e0000 @ dummy read
32178+ ldr r1, [r0]
32179+
32180+ b CBRDLL1_2300_Start
32181+CBRDLL1_2400_Call:
32182+
32183+ mov r5, #0x01 @ init dqidly count
32184+ mov r6, #0x00 @ init duty sum
32185+cbrdll1_duty_cal_start:
32186+ cmp r5, #0x05
32187+ bge cbrdll1_duty_cal_end
32188+
32189+ ldr r0, =0x1e6e0018
32190+ ldr r1, =0x00200120
32191+ orr r1, r1, r5, lsl #16
32192+ str r1, [r0]
32193+
32194+ ldr r0, =0x1e6e0000
32195+ ldr r1, [r0]
32196+
32197+ ldr r0, =0x1e6e0018
32198+ ldr r1, [r0]
32199+ mov r2, #0x10
32200+ orr r1, r1, r2, lsl #24
32201+ str r1, [r0]
32202+
32203+ ldr r0, =0x1e6e0080
32204+ ldr r1, =0x80000000 @ init duty cal waiting
32205+cbrdll1_duty_cal_wait:
32206+ ldr r2, [r0]
32207+ tst r2, r1
32208+ beq cbrdll1_duty_cal_wait
32209+
32210+ ldr r0, =0x1e6e008c
32211+ ldr r2, [r0]
32212+
32213+ ldr r0, =0x1e720210
32214+ add r0, r0, r7, lsl #2
32215+ str r2, [r0]
32216+
32217+ ldr r1, =0xFFFF
32218+ and r3, r1, r2
32219+ cmp r3, r1
32220+ moveq r2, r2, lsr #16
32221+ and r3, r1, r2
32222+ add r6, r6, r3
32223+ ldr r1, =0xF000
32224+ cmp r3, r1
32225+ blt cbrdll1_duty_cal_end
32226+ add r5, r5, #0x01
32227+ b cbrdll1_duty_cal_start
32228+
32229+cbrdll1_duty_cal_end:
32230+ mov r6, r6, lsr #2 @ get dutysum
32231+ cmp r6, r10 @ check dutysum > gdutysum
32232+ ble cbrdll1_duty_next
32233+ ldr r0, =0x1e6e0068
32234+ ldr r8, [r0]
32235+ eor r9, r7, #0x10
32236+ mov r10, r6
32237+
32238+cbrdll1_duty_next:
32239+ add r7, r7, #0x01
32240+ cmp r7, #16 @ check duty >= 15
32241+ blt cbrdll1_duty_start
32242+ ldr r0, =0xFA00 @ check gdutysum > 0xFA00
32243+ cmp r10, r0
32244+ blt cbrdll1_duty_start
32245+
32246+cbrdll1_duty_end:
32247+ ldr r0, =0x1e6e0060
32248+ ldr r1, [r0]
32249+ bic r1, r1, #0x00001F00
32250+ orr r1, r1, r9, lsl #8
32251+ str r1, [r0]
32252+
32253+ ldr r0, =0x1e6e0068
32254+ bic r8, r8, #0xFF000000
32255+ bic r8, r8, #0x00FF0000
32256+ str r8, [r0]
32257+
32258+ ldr r0, =0x1e720204 @ record result
32259+ str r8, [r0]
32260+ add r0, r0, #0x04
32261+ str r9, [r0]
32262+ add r0, r0, #0x04
32263+ str r10, [r0]
32264+
32265+ ldr r0, =0x1e6e0018
32266+ ldr r1, =0x00008120
32267+ str r1, [r0]
32268+ ldr r0, =0x1e6e0000 @ dummy read
32269+ ldr r1, [r0]
32270+ ldr r0, =0x1e6e0018
32271+ ldr r1, =0x00000120
32272+ str r1, [r0]
32273+
32274+ ldr r0, =0x1e6e0120
32275+ ldr r1, [r0]
32276+ cmp r1, #0x3
32277+ beq MCLK2X_Phase_CBR_Done_DDR2
32278+ b MCLK2X_Phase_CBR_Done_DDR3
32279+
32280+/******************************************************************************
32281+ MCLK2X lock to MCLK program
32282+ r0 - r3 = free
32283+ r5 = madjmax
32284+ r6 = dllend
32285+ 0x1E720200 = 0x96cnt:failcnt:dllmax:dllmin
32286+ ******************************************************************************/
32287+CBRDLL1_2300_Start:
32288+ ldr r0, =0x1e6e0064
32289+ ldr r5, [r0]
32290+ and r5, r5, #0xFF @ init madjmax
32291+ mov r6, r5 @ init dllend
32292+
32293+ ldr r1, =0x000000ff
32294+ ldr r0, =0x1e720200
32295+ str r1, [r0] @ init dllcnt2:dllmax:dllmin
32296+
32297+ mov r3, #0x0 @ init loop count
32298+cbrdll1_scan_start:
32299+ cmp r3, r6
32300+ bge cbrdll1_scan_end
32301+
32302+ ldr r0, =0x1e6e0018
32303+ ldr r1, =0x00008120
32304+ str r1, [r0]
32305+
32306+ ldr r0, =0x1e6e0068
32307+ mov r1, r3
32308+ cmp r1, r5
32309+ subge r1, r1, r5
32310+ str r1, [r0]
32311+
32312+ ldr r0, =0x1e6e0000 @ dummy read
32313+ ldr r1, [r0]
32314+
32315+ ldr r0, =0x1e6e0018
32316+ ldr r1, =0x00000120
32317+ str r1, [r0]
32318+
32319+ ldr r0, =0x1e6e0000 @ dummy read
32320+ ldr r1, [r0]
32321+ ldr r0, =0x1e6e0000 @ dummy read
32322+ ldr r1, [r0]
32323+
32324+ ldr r0, =0x1e6e001c
32325+ ldr r1, [r0]
32326+ mov r1, r1, lsr #16
32327+ and r1, r1, #0xFF
32328+
32329+ and r2, r1, #0x96
32330+ cmp r2, #0x96
32331+ beq cbrdll1_scan_pass @ if (mclk2x_phase & 0x96) == 0x96
32332+ ldr r0, =0x1e720200
32333+ ldr r1, [r0]
32334+ mov r2, r1, lsr #8
32335+ ands r2, r2, #0xFF @ get dllmax
32336+ beq cbrdll1_scan_next @ if dllmax == 0
32337+ mov r2, r1, lsr #16
32338+ and r2, r2, #0xFF
32339+ add r2, r2, #0x01
32340+ cmp r2, #0x02
32341+ movge r6, r3
32342+ bic r1, r1, #0x00FF0000
32343+ orr r1, r1, r2, lsl #16
32344+ str r1, [r0]
32345+ b cbrdll1_scan_next
32346+
32347+cbrdll1_scan_pass:
32348+ cmp r3, #0x0 @ if dll = 0
32349+ moveq r3, #0x0F
32350+ addeq r6, r6, #0x10
32351+ beq cbrdll1_scan_next
32352+ ldr r0, =0x1e720200
32353+ ldr r2, [r0]
32354+ cmp r1, #0x96
32355+ bne cbrdll1_scan_pass2
32356+ mov r1, r2, lsr #24
32357+ add r1, r1, #0x01
32358+ bic r2, r2, #0xFF000000
32359+ orr r2, r2, r1, lsl #24
32360+ cmp r1, #0x03 @ check (phase == 0x96) count == 3
32361+ bicge r2, r2, #0x0000FF00
32362+ bicge r2, r2, #0x000000FF
32363+ orrge r2, r2, r3, lsl #8
32364+ orrge r2, r2, r3
32365+ str r2, [r0]
32366+ bge cbrdll1_scan_end
32367+
32368+cbrdll1_scan_pass2:
32369+ and r1, r2, #0xFF @ if(dllmin > dll)
32370+ cmp r1, r3
32371+ bicgt r2, r2, #0x000000FF
32372+ orrgt r2, r2, r3
32373+
32374+ mov r1, r2, lsr #8 @ if(dllmax < dll)
32375+ and r1, r1, #0xFF
32376+ cmp r1, r3
32377+ biclt r2, r2, #0x0000FF00
32378+ orrlt r2, r2, r3, lsl #8
32379+
32380+ bic r2, r2, #0x00FF0000
32381+ str r2, [r0]
32382+
32383+cbrdll1_scan_next:
32384+ add r3, r3, #0x01
32385+ b cbrdll1_scan_start
32386+
32387+cbrdll1_scan_end:
32388+ ldr r0, =0x1e720200
32389+ ldr r1, [r0]
32390+ mov r2, r1, lsr #8 @ get dllmax
32391+ ands r2, r2, #0xFF
32392+ bne cbrdll1_scan_done @ if(dllmax != 0)
32393+ ldr r0, =0x1e6e0064
32394+ ldr r3, [r0]
32395+ bic r1, r3, #0x000C0000
32396+ str r1, [r0]
32397+ add r0, r0, #0x04
32398+ mov r1, #0x0
32399+ str r1, [r0]
32400+
32401+ /* Delay about 10us */
32402+ ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us
32403+ init_delay_timer
32404+delay0_1:
32405+ check_delay_timer
32406+ bne delay0_1
32407+ clear_delay_timer
32408+ /* end delay 10us */
32409+
32410+ ldr r0, =0x1e6e0064
32411+ str r3, [r0]
32412+
32413+ /* Delay about 10us */
32414+ ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us
32415+ init_delay_timer
32416+delay0_2:
32417+ check_delay_timer
32418+ bne delay0_2
32419+ clear_delay_timer
32420+ /* end delay 10us */
32421+
32422+ b CBRDLL1_2300_Start
32423+
32424+cbrdll1_scan_done:
32425+ and r1, r1, #0xFF
32426+ add r1, r1, r2
32427+ mov r6, r1, lsr #1 @ dll1.0 = (dllmin + dllmax) >> 1
32428+ cmp r6, r5
32429+ subge r6, r6, r5
32430+ add r3, r6, r5, lsr #2 @ dll1.1 = dll1.0 + (MADJ >> 2)
32431+
32432+ ldr r0, =0x1e6e0004
32433+ ldr r1, [r0]
32434+ mov r1, r1, lsr #10
32435+ tst r1, #0x1
32436+ bne cbrdll1_scan_set_2400
32437+ cmp r3, r5
32438+ subge r3, r3, r5
32439+ mov r2, #0x0
32440+ tst r3, #0x08
32441+ beq cbrdll1_scan_set_2300_2 @ if !(dll & 8)
32442+cbrdll1_scan_set_2300_1: @ if (dll & 8)
32443+ mov r1, #0x0
32444+ tst r3, #0x08
32445+ addeq r1, r1, #0x01
32446+ cmp r2, #0x05
32447+ addge r1, r1, #0x01
32448+ cmp r1, #0x02
32449+ beq cbrdll1_scan_set
32450+ add r2, r2, #0x01
32451+ add r3, r3, #0x01
32452+ cmp r3, r5
32453+ subge r3, r3, r5
32454+ b cbrdll1_scan_set_2300_1
32455+
32456+cbrdll1_scan_set_2300_2:
32457+ and r1, r3, #0x07
32458+ cmp r1, #0x07
32459+ beq cbrdll1_scan_set
32460+ cmp r2, #0x05
32461+ bge cbrdll1_scan_set
32462+ add r2, r2, #0x01
32463+ add r3, r3, #0x01
32464+ cmp r3, r5
32465+ subge r3, r3, r5
32466+ b cbrdll1_scan_set_2300_2
32467+
32468+cbrdll1_scan_set_2400:
32469+ add r3, r3, #0x05 @ dll1.1 = dll1.0 + (MADJ >> 2) + 5
32470+ cmp r3, r5
32471+ subge r3, r3, r5
32472+
32473+cbrdll1_scan_set:
32474+ orr r1, r6, r3, lsl #8
32475+ ldr r0, =0x1e6e0068
32476+ str r1, [r0]
32477+
32478+ ldr r0, =0x1e6e0120
32479+ ldr r1, [r0]
32480+ cmp r1, #0x0
32481+ beq MCLK2X_Phase_CBR_Done_DDR3
32482+ cmp r1, #0x1
32483+ beq MCLK2X_Phase_CBR_Done_DDR2
32484+ b CBRDLL1_2400_Call
32485+
32486+.LTORG
32487+
32488+/******************************************************************************
32489+ Calibration Code Start
32490+ SRAM buffer definition
32491+ 0x1E720000 : Pass 1, DLLI MIN value range
32492+ 0x1E720008 : DQS0 DLL valid range, 2nd time CBR
32493+ 0x1E72000C : DQS1 DLL valid range, 2nd time CBR
32494+ 0x1E720010 : DQ0 DLL valid range, Pass 1
32495+ 0x1E720014 : DQ1 DLL valid range, Pass 1
32496+ ....
32497+ 0x1E720048 : DQ14 DLL valid range, Pass 1
32498+ 0x1E72004C : DQ15 DLL valid range, Pass 1
32499+ 0x1E720090 : DLL1 SAdj record
32500+ 0x1E720094 : DQL Pass1 finetune result
32501+ 0x1E720098 : DQH Pass1 finetune result
32502+ 0x1E72009C : DRAM initial time, (us)
32503+ 0x1E7200A0 : CBR3 retry counter
32504+ 0x1E7200A4 : DRAM initial time, (us)
32505+ 0x1E7200A8 : Released date
32506+ 0x1E7200AC : Released SDK version
32507+ 0x1E7200B0 : DQS input mask window for MCR18[4] = 0
32508+ 0x1E7200B4 : DQS input mask window for MCR18[4] = 1
32509+ 0x1E720100 : DQIDLY=00, DLL valid range
32510+ 0x1E720104 : DQIDLY=01, DLL valid range
32511+ ....
32512+ 0x1E720178 : DQIDLY=30, DLL valid range
32513+ 0x1E72017C : DQIDLY=31, DLL valid range
32514+ 0x1E720180 : DQSI-MCLK2X P-phase pass record DLL2= 0-31
32515+ 0x1E720184 : DQSI-MCLK2X P-phase pass record DLL2=32-63
32516+ 0x1E720188 : DQSI-MCLK2X N-phase pass record DLL2= 0-31
32517+ 0x1E72018C : DQSI-MCLK2X N-phase pass record DLL2=32-63
32518+ ******************************************************************************/
32519+Calibration_Start_pre: @ Toggle DQSI mask delay
32520+ ldr r0, =0x1e6e0018
32521+ ldr r1, [r0]
32522+ eor r1, r1, #0x10
32523+ str r1, [r0]
32524+
32525+Calibration_Start:
32526+/* Init SRAM buffer */
32527+ ldr r1, =0x000000ff
32528+ ldr r0, =0x1e720000
32529+ ldr r2, =0x1e720100
32530+init_sram_start:
32531+ str r1, [r0]
32532+ add r0, r0, #4
32533+ cmp r0, r2
32534+ blt init_sram_start
32535+
32536+ ldr r1, =0x00ff00ff
32537+ ldr r0, =0x1e720100
32538+ ldr r2, =0x1e720180
32539+init_sram_start2:
32540+ str r1, [r0]
32541+ add r0, r0, #4
32542+ cmp r0, r2
32543+ blt init_sram_start2
32544+
32545+ ldr r1, =0x00000000
32546+ ldr r0, =0x1e720180
32547+ ldr r2, =0x1e720200
32548+init_sram_start3:
32549+ str r1, [r0]
32550+ add r0, r0, #4
32551+ cmp r0, r2
32552+ blt init_sram_start3
32553+
32554+ ldr r0, =0x1e6e0068 @ save the DLL1 SAdj initial value
32555+ ldr r1, [r0]
32556+ ldr r0, =0x1e720090
32557+ str r1, [r0]
32558+
32559+/* Start
32560+ r0 = free
32561+ r1 = free
32562+ r2 = free
32563+ r3 = free
32564+ r4 = record the return pc value, do not use
32565+ r5 = pattern table index
32566+ r6 = pass count
32567+ r7 = dram DLL2 parameter index (0x1e6e0068), max is 0x4C
32568+*/
32569+/******************************************************************************
32570+ Fine DQI delay and DQSI-MCLK phase
32571+ r8 = DQIDLY count
32572+ r9 = DQSI-MCLK2X phase count
32573+ r10 = pattern fail retry counter, initialize to 2 (fail 2 times)
32574+ r11 = passcnt accumulator for each DQIDLY
32575+ *****************************************************************************/
32576+CBR0_START:
32577+/* Debug - UART console message */
32578+ ldr r0, =0x1e784000
32579+ mov r1, #0x43 @ 'C'
32580+ str r1, [r0]
32581+ mov r1, #0x42 @ 'B'
32582+ str r1, [r0]
32583+ mov r1, #0x52 @ 'R'
32584+ str r1, [r0]
32585+ mov r1, #0x30 @ '0'
32586+ str r1, [r0]
32587+ mov r1, #0x2D @ '-'
32588+ str r1, [r0]
32589+/* Debug - UART console message */
32590+
32591+ ldr r0, =0x1e6e0018
32592+ ldr r1, [r0]
32593+ bic r1, r1, #0xFF000000
32594+ bic r1, r1, #0x00FF0000
32595+ str r1, [r0]
32596+
32597+ ldr r0, =0x1e6e0074 @ set the testing DRAM size = 1KB
32598+ ldr r1, =0x000003FF
32599+ str r1, [r0]
32600+
32601+ mov r8, #0x00 @ init DQIDLY
32602+ mov r9, #0x00 @ init DQSI-MCLK2X phase
32603+ mov r11, #0x01 @ init passcnt accumulator
32604+
32605+cbr0_next_dqidly:
32606+ cmp r9, #0x00
32607+ bne cbr0_next_dqsiphase
32608+ cmp r11, #0x00
32609+ addeq r8, r8, #0x01 @ jump 1 stage if no pass at previous stage
32610+ mov r11, #0x00
32611+ add r8, r8, #0x01
32612+ cmp r8, #0x1F @ max DQIDLY = 31
32613+ bgt CBR0_END
32614+
32615+/* Debug - UART console message */
32616+ ldr r0, =0x1e784000
32617+ and r1, r8, #0x07
32618+ add r1, r1, #0x30 @ '0-7'
32619+ str r1, [r0]
32620+/* Debug - UART console message */
32621+
32622+ ldr r0, =0x1e6e0018
32623+ ldr r1, [r0]
32624+ bic r1, r1, #0x00FF0000
32625+ orr r1, r1, r8, lsl #16
32626+ str r1, [r0]
32627+ mov r9, #0x01 @ '1':p_phase, '0':n_phase
32628+
32629+ /* Delay about 3us */ @ wait DQIDLY load
32630+ ldr r2, =0x00000003 @ Set Timer4 Reload = 3 us
32631+ init_delay_timer
32632+delay_4:
32633+ check_delay_timer
32634+ bne delay_4
32635+ clear_delay_timer
32636+ /* end delay 3us */
32637+
32638+ b cbr0_dll2_scan_start
32639+
32640+cbr0_next_dqsiphase:
32641+ ldr r0, =0x1e6e0018
32642+ ldr r1, [r0]
32643+ orr r1, r1, r9, lsl #23 @ set DQSI-MCLK2X phase
32644+ str r1, [r0]
32645+ mov r9, #0x00
32646+
32647+cbr0_dll2_scan_start:
32648+ mov r6, #0x00 @ init pass count
32649+ mov r7, #0x00 @ init DLL2 parameter index
32650+
32651+/****************************
32652+ DLL2 delay margin test loop
32653+ ***************************/
32654+cbr0_next_dll2_parameter:
32655+ ldr r0, =0x1e6e0068 @ load DLL2 parameter
32656+ ldr r1, [r0]
32657+ bic r1, r1, #0x00FF0000
32658+ bic r1, r1, #0xFF000000
32659+ orr r1, r1, r7, lsl #16
32660+ str r1, [r0]
32661+ ldr r2, =0x40404040 @ DLL2 max is 0x40404040
32662+ cmp r7, r2
32663+ bge cbr0_next_dqidly
32664+ ldr r2, =0x01010101
32665+ add r7, r7, r2
32666+
32667+/* CBRScan3() start */
32668+ adrl r5, PATTERN_TABLE @ init pattern table index
32669+/****************************
32670+ Test pattern iteration loop
32671+ ***************************/
32672+cbr0_next_test_pattern:
32673+ mov r10, #2 @ set the retry loop = 2 of each pattern
32674+ ldr r1, [r5] @ load test pattern
32675+ ldr r0, =0x1e6e007c
32676+ str r1, [r0]
32677+ cmp r1, #0x00 @ the last data in pattern is 0x00
32678+ bne cbr0_test_burst
32679+
32680+ and r3, r7, #0xFF
32681+ sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1
32682+ cmp r3, #0x00
32683+ beq cbr0_next_dqidly @ pass at dlli = 0, invalid
32684+ add r6, r6, #0x01 @ increment pass count
32685+ add r11, r11, #0x01 @ increment pass count
32686+
32687+ ldr r0, =0x1e720180 @ record DLL2 pass window
32688+ cmp r9, #0x00 @ DQSI-MCLK2X phase check
32689+ addeq r0, r0, #0x08
32690+ cmp r3, #32
32691+ addge r0, r0, #0x4
32692+ and r1, r3, #0x1F
32693+ mov r2, #0x1
32694+ mov r2, r2, lsl r1
32695+ ldr r1, [r0]
32696+ orr r1, r1, r2
32697+ str r1, [r0]
32698+
32699+ ldr r0, =0x1e720100 @ record DLL2 min:max value for each DQIDLY
32700+ add r0, r0, r8, lsl #2
32701+ cmp r9, #0x00 @ DQSI-MCLK2X phase check
32702+ beq cbr0_test_pass_dqsin
32703+ record_dll2_pass_range
32704+ b cbr0_next_dll2_parameter
32705+
32706+cbr0_test_pass_dqsin:
32707+ record_dll2_pass_range_h
32708+ b cbr0_next_dll2_parameter
32709+
32710+cbr0_test_pattern_fail:
32711+ cmp r6, #5 @ passcnt >= 5
32712+ bge cbr0_next_dqidly
32713+ ldr r0, =0x1e720100 @ reset DLL2 min:max value
32714+ add r0, r0, r8, lsl #2
32715+ ldr r1, [r0]
32716+ ldr r2, =0xFFFF0000
32717+ ldr r3, =0x000000FF
32718+ cmp r9, #0x00
32719+ moveq r2, r2, lsr #16
32720+ moveq r3, r3, lsl #16
32721+ and r1, r1, r2
32722+ orr r1, r1, r3
32723+ str r1, [r0]
32724+ b cbr0_next_dll2_parameter @ CBRScan3() end and test result fail, go to next step
32725+
32726+/****************************
32727+ Test fail retry loop
32728+ ***************************/
32729+cbr0_pattern_fail_retry:
32730+
32731+/* CBRTest3() start */
32732+cbr0_test_burst:
32733+ ldr r0, =0x1e6e0070
32734+ ldr r1, =0x00000000
32735+ str r1, [r0]
32736+ ldr r1, =0x000000C1
32737+ str r1, [r0]
32738+ ldr r3, =0x3000
32739+cbr0_wait_engine_idle_0:
32740+ ldr r2, [r0]
32741+ tst r2, r3 @ D[12] = idle bit
32742+ beq cbr0_wait_engine_idle_0
32743+
32744+ ldr r2, [r0] @ read fail bit status
32745+ mov r1, #0x0
32746+ str r1, [r0]
32747+ mov r2, r2, lsr #13 @ D[13] = fail bit
32748+ cmp r2, #0x00
32749+ bne cbr0_test_fail
32750+
32751+cbr0_test_single:
32752+ ldr r0, =0x1e6e0070
32753+ ldr r1, =0x00000000
32754+ str r1, [r0]
32755+ ldr r1, =0x00000085
32756+ str r1, [r0]
32757+ ldr r3, =0x3000
32758+cbr0_wait_engine_idle_1:
32759+ ldr r2, [r0]
32760+ tst r2, r3 @ D[12] = idle bit
32761+ beq cbr0_wait_engine_idle_1
32762+
32763+ ldr r2, [r0] @ read fail bit status
32764+ mov r1, #0x0
32765+ str r1, [r0]
32766+ mov r2, r2, lsr #13 @ D[13] = fail bit
32767+ cmp r2, #0x00
32768+ beq cbr0_test_pass
32769+
32770+/* CBRTest3() end */
32771+
32772+cbr0_test_fail:
32773+ subs r10, r10, #1
32774+ bne cbr0_pattern_fail_retry
32775+ b cbr0_test_pattern_fail @ CBRScan3() return(0)
32776+
32777+cbr0_test_pass:
32778+ add r5, r5, #0x04 @ increase the test pattern index
32779+ b cbr0_next_test_pattern
32780+
32781+CBR0_END:
32782+ mov r5, #0x0 @ init DQIDLY search count
32783+ mov r6, #0x0 @ init max_margin:g_margin
32784+ mov r8, #0x0 @ init g_side
32785+ mov r7, #0x0 @ init maximum margin DQIDLY,DQSI-MCLK2X phase
32786+cbr0_search_dll_margin_s:
32787+ ldr r0, =0x1e720100
32788+ add r0, r0, r5, lsl #2
32789+ ldr r1, [r0]
32790+ and r2, r1, #0xFF @ get dllmin_p
32791+ mov r1, r1, lsr #8
32792+ and r3, r1, #0xFF @ get dllmax_p
32793+ subs r2, r3, r2 @ get margin-P
32794+ movmi r2, #0x0
32795+ mov r1, r1, lsr #8
32796+ and r3, r1, #0xFF @ get dllmin_n
32797+ mov r1, r1, lsr #8
32798+ and r1, r1, #0xFF @ get dllmax_n
32799+ subs r3, r1, r3 @ get margin-N
32800+ movmi r3, #0x0
32801+ add r1, r2, r3
32802+ cmp r1, #0x0
32803+ beq cbr0_search_dll_margin_e @ if margin-P = 0 && margin-N = 0
32804+
32805+ ldr r9, [r0]
32806+ ldr r0, =0x1e720180
32807+ cmp r2, r3
32808+ orrlt r5, r5, #0x80 @ margin-N > margin-P
32809+ addlt r0, r0, #0x08
32810+ movlt r9, r9, lsr #16
32811+ movge r3, r2 @ max(margin-P/N)
32812+ add r2, r3, #0x2 @ define +/- 2 steps of variation
32813+ mov r1, r6, lsr #16
32814+ cmp r2, r1
32815+ blt cbr0_search_dll_margin_e @ if max(margin-P/N) + 2 < max_margin
32816+
32817+ and r1, r9, #0xFF @ r1 = dlli counter
32818+ cmp r1, #32
32819+ ldrge r2, [r0, #0x4] @ load pass window
32820+ ldrlt r2, [r0]
32821+ and r1, r1, #0x1F
32822+ mov r10, #0x1 @ init test bit mask
32823+ mov r10, r10, lsl r1
32824+ and r1, r9, #0xFF
32825+cbr0_search_dllmin_margin_s:
32826+ tst r2, r10
32827+ beq cbr0_search_dllmin_margin_e
32828+ mov r10, r10, lsr #1
32829+ cmp r1, #32
32830+ ldreq r2, [r0]
32831+ ldreq r10, =0x80000000
32832+ subs r1, r1, #0x1
32833+ bne cbr0_search_dllmin_margin_s
32834+
32835+cbr0_search_dllmin_margin_e:
32836+ and r2, r9, #0xFF
32837+ sub r11, r2, r1 @ get dllmin side margin
32838+
32839+ mov r9, r9, lsr #8
32840+ and r1, r9, #0xFF @ r1 = dlli counter
32841+ cmp r1, #32
32842+ ldrge r2, [r0, #0x4] @ load pass window
32843+ ldrlt r2, [r0]
32844+ and r1, r1, #0x1F
32845+ mov r10, #0x1 @ init test bit mask
32846+ mov r10, r10, lsl r1
32847+ and r1, r9, #0xFF
32848+cbr0_search_dllmax_margin_s:
32849+ tst r2, r10
32850+ beq cbr0_search_dllmax_margin_e
32851+ mov r10, r10, lsl #1
32852+ cmp r1, #31
32853+ ldreq r2, [r0, #0x4]
32854+ ldreq r10, =0x00000001
32855+ add r1, r1, #0x1
32856+ cmp r1, #64
32857+ bne cbr0_search_dllmax_margin_s
32858+
32859+cbr0_search_dllmax_margin_e:
32860+ and r2, r9, #0xFF
32861+ sub r1, r1, r2 @ get dllmax side margin
32862+ cmp r1, r11
32863+ movlt r11, r1 @ get side_margin
32864+
32865+cbr0_check_dll_margin: @ if max(margin-P/N) > g_margin && side_margin >= g_side && dqidly <= 20
32866+ cmp r5, #20
32867+ bgt cbr0_check_dll_margin2
32868+ and r1, r6, #0xFF
32869+ cmp r3, r1
32870+ ble cbr0_check_dll_margin3
32871+ cmp r11, r8
32872+ bge cbr0_set_dll_margin
32873+
32874+cbr0_check_dll_margin2: @ if max(margin-P/N) > g_margin+1 && side_margin >= g_side)
32875+ and r1, r6, #0xFF
32876+ add r2, r1, #0x1
32877+ cmp r3, r2
32878+ ble cbr0_check_dll_margin3
32879+ cmp r11, r8
32880+ bge cbr0_set_dll_margin
32881+
32882+cbr0_check_dll_margin3: @ if side_margin > g_side && g_side < 8
32883+ cmp r8, #8
32884+ bge cbr0_search_dll_margin_e
32885+ cmp r11, r8
32886+ ble cbr0_search_dll_margin_e
32887+
32888+cbr0_set_dll_margin:
32889+ mov r1, r6, lsr #16
32890+ cmp r3, r1
32891+ bicgt r6, r6, #0x00FF0000
32892+ orrgt r6, r6, r3, lsl #16
32893+ bic r6, r6, #0x000000FF
32894+ orr r6, r6, r3
32895+ mov r7, r5
32896+ mov r8, r11
32897+
32898+cbr0_search_dll_margin_e:
32899+ and r5, r5, #0x7F
32900+ add r5, r5, #0x01
32901+ cmp r5, #0x20 @ last DQIDLY
32902+ blt cbr0_search_dll_margin_s
32903+
32904+ ldr r0, =0x1e6e0018
32905+ ldr r1, [r0]
32906+ bic r1, r1, #0x00FF0000
32907+ orr r1, r1, r7, lsl #16
32908+ str r1, [r0]
32909+
32910+ ldr r0, =0x1e6e0068
32911+ ldr r1, [r0]
32912+ bic r1, r1, #0x00FF0000
32913+ bic r1, r1, #0xFF000000
32914+ str r1, [r0]
32915+
32916+ /* Delay about 5us */
32917+ ldr r2, =0x00000005 @ Set Timer5 Reload = 5 us
32918+ init_delay_timer
32919+delay_5:
32920+ check_delay_timer
32921+ bne delay_5
32922+ clear_delay_timer
32923+ /* end delay 5us */
32924+
32925+ ldr r0, =0x1e6e000c @ Set refresh cycle
32926+ ldr r1, =0x00005C01
32927+ str r1, [r0]
32928+
32929+/******************************************************************************
32930+ Fine tune per bit DQ input delay -- Pass 1, left edge align
32931+ r8 = free
32932+ r9 = DQ fail bit accumulator
32933+ r10 = pattern fail counter, initialize to 5 (fail 5 times)
32934+ r11 = free
32935+ *****************************************************************************/
32936+CBR1_START:
32937+/* Debug - UART console message */
32938+ ldr r0, =0x1e784000
32939+ mov r1, #0x0D @ '\r'
32940+ str r1, [r0]
32941+ mov r1, #0x0A @ '\n'
32942+ str r1, [r0]
32943+ mov r1, #0x43 @ 'C'
32944+ str r1, [r0]
32945+ mov r1, #0x42 @ 'B'
32946+ str r1, [r0]
32947+ mov r1, #0x52 @ 'R'
32948+ str r1, [r0]
32949+ mov r1, #0x31 @ '1'
32950+ str r1, [r0]
32951+/* Debug - UART console message */
32952+
32953+ mov r6, #0x00 @ init pass count
32954+ mov r7, #0x00 @ init DLL2 parameter index
32955+
32956+/****************************
32957+ DLL2 delay margin test loop
32958+ ***************************/
32959+cbr1_next_dll2_parameter:
32960+ ldr r0, =0x1e6e0068 @ load DLL2 parameter
32961+ ldr r1, [r0]
32962+ bic r1, r1, #0x00FF0000
32963+ bic r1, r1, #0xFF000000
32964+ orr r1, r1, r7, lsl #16
32965+ str r1, [r0]
32966+ ldr r2, =0x40404040 @ parameter's max is to 0x40404040
32967+ cmp r7, r2
32968+ bge CBR1_END
32969+ ldr r2, =0x01010101
32970+ add r7, r7, r2
32971+
32972+ ldr r0, =0x1e6e0074 @ set the testing DRAM size = 4KB
32973+ ldr r1, =0x00000FFF
32974+ str r1, [r0]
32975+
32976+/* CBRScan2() start */
32977+ ldr r9, =0xFFFF @ init test status
32978+ adrl r5, PATTERN_TABLE @ init pattern table index
32979+/****************************
32980+ Test pattern iteration loop
32981+ ***************************/
32982+cbr1_next_test_pattern:
32983+ mov r10, #5 @ set the retry loop of each pattern
32984+ ldr r1, [r5] @ load test pattern
32985+ ldr r0, =0x1e6e007c
32986+ str r1, [r0]
32987+ cmp r1, #0x00 @ the last data in pattern is 0x00
32988+ bne cbr1_test_single
32989+
32990+cbr1_test_pattern_end:
32991+ cmp r9, #0x00
32992+ bne cbr1_test_pass_dqi
32993+ cmp r6, #10
32994+ bge CBR1_END
32995+ b cbr1_next_dll2_parameter @ CBRScan2() end and test result fail, go to next step
32996+
32997+cbr1_test_pass_dqi:
32998+ and r3, r7, #0xFF
32999+ sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1
33000+ add r6, r6, #0x01 @ increment pass count
33001+ ldr r0, =0x1e720010
33002+ mov r8, #0x01
33003+cbr1_test_pass_dqi_loop_s:
33004+ tst r9, r8
33005+ beq cbr1_test_pass_dqi_loop_e
33006+ record_dll2_pass_range
33007+
33008+cbr1_test_pass_dqi_loop_e:
33009+ add r0, r0, #0x04
33010+ mov r8, r8, lsl #1
33011+ ldr r1, =0xFFFF
33012+ tst r8, r1
33013+ bne cbr1_test_pass_dqi_loop_s
33014+ b cbr1_next_dll2_parameter
33015+
33016+/****************************
33017+ Test fail retry loop
33018+ ***************************/
33019+cbr1_pattern_fail_retry:
33020+
33021+/* CBRTest2() start */
33022+cbr1_test_single:
33023+ ldr r0, =0x1e6e0070
33024+ ldr r1, =0x00000000
33025+ str r1, [r0]
33026+ ldr r1, =0x00000005
33027+ str r1, [r0]
33028+ ldr r3, =0x1000
33029+ ldr r1, =0x1000
33030+cbr1_wait_engine_idle_0:
33031+ subs r1, r1, #1
33032+ beq cbr1_test_single_end
33033+ ldr r2, [r0]
33034+ tst r2, r3 @ D[12] = idle bit
33035+ beq cbr1_wait_engine_idle_0
33036+
33037+cbr1_test_single_end:
33038+ ldr r0, =0x1e6e0078 @ read fail bit status
33039+ ldr r11, [r0]
33040+ orr r11, r11, r11, lsr #16
33041+ bic r11, r11, #0xFF000000
33042+ bic r11, r11, #0x00FF0000
33043+
33044+ ldr r1, =0xFFFF
33045+ cmp r11, r1
33046+ beq cbr1_test_fail
33047+
33048+cbr1_test_burst:
33049+ ldr r0, =0x1e6e0070
33050+ ldr r2, =0x00000000
33051+ str r2, [r0]
33052+ ldr r2, =0x00000041
33053+ str r2, [r0]
33054+ ldr r3, =0x1000
33055+ ldr r1, =0x1000
33056+cbr1_wait_engine_idle_1:
33057+ subs r1, r1, #1
33058+ beq cbr1_test_burst_end
33059+ ldr r2, [r0]
33060+ tst r2, r3 @ D[12] = idle bit
33061+ beq cbr1_wait_engine_idle_1
33062+
33063+cbr1_test_burst_end:
33064+ ldr r0, =0x1e6e0078 @ read fail bit status
33065+ ldr r2, [r0]
33066+ orr r2, r2, r2, lsr #16
33067+ bic r2, r2, #0xFF000000
33068+ bic r2, r2, #0x00FF0000
33069+ orr r11, r11, r2
33070+
33071+ ldr r2, =0xFFFF
33072+ cmp r11, r2
33073+ bne cbr1_test_pass
33074+/* CBRTest2() end */
33075+
33076+cbr1_test_fail:
33077+ subs r10, r10, #1
33078+ bne cbr1_pattern_fail_retry
33079+ mov r9, #0x00
33080+ b cbr1_test_pattern_end @ CBRScan2() return(0)
33081+
33082+cbr1_test_pass:
33083+ ldr r1, =0xFFFF @ record the pass bit
33084+ eor r11, r11, r1
33085+ and r9, r9, r11 @ DQ pass bit
33086+ cmp r9, #0x00
33087+ beq cbr1_test_pattern_end @ CBRScan2() return(0)
33088+
33089+ add r5, r5, #0x04 @ increase the test pattern index
33090+ b cbr1_next_test_pattern
33091+
33092+CBR1_END:
33093+ mov r5, #0x0 @ init DQ DLL_min sum
33094+ mov r6, #0x0 @ init DQ DLL_min valid count
33095+ ldr r0, =0x1e72000c
33096+ ldr r3, =0x1e720050
33097+cbr1_search_dllmin_s:
33098+ add r0, r0, #0x04
33099+ cmp r0, r3
33100+ beq cbr1_search_dllmin_e
33101+ ldr r1, [r0]
33102+ mov r2, r1, lsr #8
33103+ and r2, r2, #0xFF @ get dllmax
33104+ and r1, r1, #0xFF @ get dllmin
33105+ subs r2, r2, r1 @ dllmax - dllmin
33106+ bmi cbr1_search_dllmin_s @ no valid margin found, bypass fine tune
33107+ cmp r2, #10 @ (dllmax - dllmin) < 10
33108+ blt cbr1_search_dllmin_s @ no enough margin found, bypass fine tune
33109+ add r5, r5, r1
33110+ add r6, r6, #1
33111+ b cbr1_search_dllmin_s
33112+
33113+cbr1_search_dllmin_e:
33114+ cmp r6, #16
33115+ bne Calibration_Start_pre @ not all bits valid, retry again
33116+
33117+ mov r5, r5, lsr #4
33118+ ldr r0, =0x1e720000
33119+ str r5, [r0]
33120+
33121+ mov r6, #0x00 @ init DQL CBR value
33122+ ldr r0, =0x1e720030
33123+ ldr r7, =0x1e72000c
33124+cbr1_set_result_dql:
33125+ sub r0, r0, #4
33126+ cmp r0, r7
33127+ beq cbr1_set_result_next
33128+ mov r6, r6, lsl #3
33129+ ldr r1, [r0]
33130+ mov r2, r1, lsr #8
33131+ and r2, r2, #0xFF @ get dllmax
33132+ and r1, r1, #0xFF @ get dllmin
33133+ mov r3, r1 @ dll = dllmin
33134+ cmp r5, r3
33135+ blt cbr1_set_result_dql_neg
33136+ sub r1, r5, r3
33137+ mov r2, #19
33138+ mul r1, r2, r1
33139+ mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5
33140+ cmp r1, #2 @ dqi_tune max = 2
33141+ movgt r1, #2
33142+ orr r6, r6, r1
33143+ b cbr1_set_result_dql
33144+
33145+cbr1_set_result_dql_neg:
33146+ sub r1, r3, r5
33147+ mov r2, #19
33148+ mul r1, r2, r1
33149+ mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5
33150+ cmp r1, #2 @ dqi_tune max = -2
33151+ movgt r1, #2
33152+ mov r2, #8
33153+ sub r1, r2, r1
33154+ and r1, r1, #7
33155+ orr r6, r6, r1
33156+ b cbr1_set_result_dql
33157+
33158+cbr1_set_result_next:
33159+ ldr r0, =0x1e6e0080 @ save DQL fine tune result
33160+ str r6, [r0]
33161+ ldr r0, =0x1e720094
33162+ str r6, [r0]
33163+
33164+ mov r6, #0x00 @ init DQH CBR value
33165+ ldr r0, =0x1e720050
33166+ ldr r7, =0x1e72002c
33167+cbr1_set_result_dqh:
33168+ sub r0, r0, #4
33169+ cmp r0, r7
33170+ beq cbr1_set_result_end
33171+ mov r6, r6, lsl #3
33172+ ldr r1, [r0]
33173+ mov r2, r1, lsr #8
33174+ and r2, r2, #0xFF @ get dllmax
33175+ and r1, r1, #0xFF @ get dllmin
33176+ mov r3, r1 @ dll = dllmin
33177+ cmp r5, r3
33178+ blt cbr1_set_result_dqh_neg
33179+ sub r1, r5, r3
33180+ mov r2, #19
33181+ mul r1, r2, r1
33182+ mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5
33183+ cmp r1, #3 @ dqi_tune max = 2
33184+ movgt r1, #3
33185+ subs r1, r1, #1
33186+ movmi r1, #7
33187+ orr r6, r6, r1
33188+ b cbr1_set_result_dqh
33189+
33190+cbr1_set_result_dqh_neg:
33191+ sub r1, r3, r5
33192+ mov r2, #19
33193+ mul r1, r2, r1
33194+ mov r1, r1, lsr #5 @ dqi_tune = ((gold_dll - dll) * 19) >> 5
33195+ add r1, r1, #1
33196+ cmp r1, #2 @ dqi_tune max = -2
33197+ movgt r1, #2
33198+ mov r2, #8
33199+ sub r1, r2, r1
33200+ and r1, r1, #7
33201+ orr r6, r6, r1
33202+ b cbr1_set_result_dqh
33203+
33204+cbr1_set_result_end:
33205+ ldr r0, =0x1e6e0084 @ save DQH fine tune result
33206+ str r6, [r0]
33207+ ldr r0, =0x1e720098
33208+ str r6, [r0]
33209+
33210+/******************************************************************************
33211+ Search the DLL2 detail margin
33212+ *****************************************************************************/
33213+ ldr r0, =0x1e7200a0
33214+ mov r1, #0
33215+ str r1, [r0]
33216+
33217+CBR3_START:
33218+/* Debug - UART console message */
33219+ ldr r0, =0x1e784000
33220+ mov r1, #0x33 @ '3'
33221+ str r1, [r0]
33222+/* Debug - UART console message */
33223+
33224+ mov r6, #0x00 @ init pass count
33225+ mov r7, #0x00 @ init DLL2 parameter index
33226+ ldr r1, =0x000000ff
33227+ ldr r0, =0x1e720008 @ init DQL dllmax,dllmin
33228+ str r1, [r0]
33229+ ldr r0, =0x1e72000c @ init DQH dllmax,dllmin
33230+ str r1, [r0]
33231+
33232+ ldr r0, =0x1e7200a0 @ CBR3 iteration counter
33233+ ldr r1, [r0]
33234+ add r1, r1, #1
33235+ str r1, [r0]
33236+
33237+/****************************
33238+ DLL2 delay margin test loop
33239+ ***************************/
33240+cbr3_next_dll2_parameter:
33241+ ldr r0, =0x1e6e0068 @ load DLL2 parameter
33242+ ldr r1, [r0]
33243+ bic r1, r1, #0x00FF0000
33244+ bic r1, r1, #0xFF000000
33245+ orr r1, r1, r7, lsl #16
33246+ str r1, [r0]
33247+ ldr r2, =0x40404040 @ parameter's max is to 0x40404040
33248+ cmp r7, r2
33249+ bge CBR3_END
33250+ ldr r2, =0x01010101
33251+ add r7, r7, r2
33252+
33253+ ldr r0, =0x1e6e0074 @ set the testing DRAM size = 64KB
33254+ ldr r1, =0x0000FFFF
33255+ str r1, [r0]
33256+
33257+/* CBRScan() start */
33258+ mov r9, #0x03 @ init test status
33259+ adrl r5, PATTERN_TABLE @ init pattern table index
33260+/****************************
33261+ Test pattern iteration loop
33262+ ***************************/
33263+cbr3_next_test_pattern:
33264+ mov r10, #5 @ set the retry loop of each pattern
33265+ ldr r1, [r5] @ load test pattern
33266+ ldr r0, =0x1e6e007c
33267+ str r1, [r0]
33268+ cmp r1, #0x00 @ the last data in pattern is 0x00
33269+ bne cbr3_test_single
33270+
33271+cbr3_test_pattern_end:
33272+ cmp r9, #0x00
33273+ bne cbr3_test_pass_dql
33274+ cmp r6, #10
33275+ bge CBR3_END
33276+ b cbr3_next_dll2_parameter @ CBRScan() end and test result fail, go to next step
33277+
33278+cbr3_test_pass_dql:
33279+ and r3, r7, #0xFF
33280+ sub r3, r3, #0x01 @ we add one after loop check so we need to decrease 1
33281+ add r6, r6, #0x01 @ increment pass count
33282+ tst r9, #0x01
33283+ beq cbr3_test_pass_dqh
33284+
33285+ ldr r0, =0x1E720008
33286+ record_dll2_pass_range
33287+
33288+cbr3_test_pass_dqh:
33289+ tst r9, #0x02
33290+ beq cbr3_next_dll2_parameter
33291+ ldr r0, =0x1E72000c
33292+ record_dll2_pass_range
33293+ b cbr3_next_dll2_parameter
33294+
33295+/****************************
33296+ Test fail retry loop
33297+ ***************************/
33298+cbr3_pattern_fail_retry:
33299+
33300+/* CBRTest() start */
33301+cbr3_test_single:
33302+ ldr r0, =0x1e6e0070
33303+ ldr r1, =0x00000000
33304+ str r1, [r0]
33305+ ldr r1, =0x00000005
33306+ str r1, [r0]
33307+ ldr r3, =0x1000
33308+ ldr r8, =0x10000
33309+cbr3_wait_engine_idle_0:
33310+ subs r8, r8, #1
33311+ beq cbr3_test_single_end
33312+ ldr r2, [r0]
33313+ tst r2, r3 @ D[12] = idle bit
33314+ beq cbr3_wait_engine_idle_0
33315+
33316+cbr3_test_single_end:
33317+ ldr r0, =0x1e6e0078 @ read fail bit status
33318+ ldr r11, [r0]
33319+ orr r11, r11, r11, lsr #16
33320+ bic r11, r11, #0xFF000000
33321+ bic r11, r11, #0x00FF0000
33322+
33323+ ldr r1, =0xFF
33324+ tst r11, r1
33325+ beq cbr3_test_burst
33326+ tst r11, r1, lsl #8
33327+ bne cbr3_test_fail
33328+
33329+cbr3_test_burst:
33330+ mov r1, #0x00 @ initialize loop index, r1 is loop's index
33331+cbr3_test_burst_loop:
33332+ ldr r0, =0x1e6e0070
33333+ ldr r2, =0x00000000
33334+ str r2, [r0]
33335+ mov r2, r1, lsl #3
33336+ orr r2, r2, #0x41 @ test command = 0x41 | (datagen << 3)
33337+ str r2, [r0]
33338+ ldr r3, =0x1000
33339+ ldr r8, =0x10000
33340+cbr3_wait_engine_idle_1:
33341+ subs r8, r8, #1
33342+ beq cbr3_test_burst_end
33343+ ldr r2, [r0]
33344+ tst r2, r3 @ D[12] = idle bit
33345+ beq cbr3_wait_engine_idle_1
33346+
33347+cbr3_test_burst_end:
33348+ ldr r0, =0x1e6e0078 @ read fail bit status
33349+ ldr r2, [r0]
33350+ orr r2, r2, r2, lsr #16
33351+ bic r2, r2, #0xFF000000
33352+ bic r2, r2, #0x00FF0000
33353+ orr r11, r11, r2
33354+
33355+ ldr r2, =0xFF
33356+ tst r11, r2
33357+ beq cbr3_next_test_burst_mode
33358+ tst r11, r2, lsl #8
33359+ beq cbr3_next_test_burst_mode
33360+/* CBRTest() end */
33361+
33362+cbr3_test_fail:
33363+ subs r10, r10, #1
33364+ bne cbr3_pattern_fail_retry
33365+ mov r9, #0x00
33366+ b cbr3_test_pattern_end @ CBRScan() return(0)
33367+
33368+cbr3_next_test_burst_mode:
33369+ add r1, r1, #1 @ increase the test mode index
33370+ cmp r1, #0x08 @ there are 8 modes
33371+ bne cbr3_test_burst_loop
33372+
33373+ ldr r1, =0xFF @ record the pass byte
33374+ tst r11, r1
33375+ andne r9, r9, #0x02 @ DQL fail
33376+ tst r11, r1, lsl #8
33377+ andne r9, r9, #0x01 @ DQH fail
33378+ cmp r9, #0x00
33379+ beq cbr3_test_pattern_end @ CBRScan() return(0)
33380+
33381+ add r5, r5, #0x04 @ increase the test pattern index
33382+ b cbr3_next_test_pattern
33383+
33384+CBR3_END:
33385+ ldr r0, =0x1e72000c @ check DQH margin
33386+ ldr r1, [r0]
33387+ mov r2, r1, lsr #8
33388+ and r2, r2, #0xFF @ get dllmax
33389+ and r1, r1, #0xFF @ get dllmin
33390+ subs r5, r2, r1 @ dllmax - dllmin
33391+ bmi CBR3_START @ no valid margin found, retry again
33392+ cmp r5, #10 @ (dllmax - dllmin) < 10
33393+ blt CBR3_START @ no enough margin found, retry again
33394+ add r2, r1, r2 @ (dllmin[1] + dllmax[1] + 1) >> 1
33395+ add r2, r2, #0x01
33396+ mov r1, r2, lsr #1
33397+ mov r3, r1, lsl #8
33398+ ldr r1, [r0] @ store the dll search result
33399+ bic r1, r1, #0xFF000000
33400+ bic r1, r1, #0x00FF0000
33401+ orr r1, r1, r3, lsl #8
33402+ str r1, [r0]
33403+
33404+ ldr r0, =0x1e720008 @ check DQL margin
33405+ ldr r1, [r0]
33406+ mov r2, r1, lsr #8
33407+ and r2, r2, #0xFF @ get dllmax
33408+ and r1, r1, #0xFF @ get dllmin
33409+ subs r5, r2, r1 @ dllmax - dllmin
33410+ bmi CBR3_START @ no valid margin found, retry again
33411+ cmp r5, #10 @ (dllmax - dllmin) < 10
33412+ blt CBR3_START @ no enough margin found, retry again
33413+ add r2, r1, r2 @ (dllmin[0] + dllmax[0] + 1) >> 1
33414+ add r2, r2, #0x01
33415+ mov r1, r2, lsr #1
33416+ ldr r2, [r0] @ store the dll search result
33417+ bic r2, r2, #0xFF000000
33418+ bic r2, r2, #0x00FF0000
33419+ orr r2, r2, r1, lsl #16
33420+ str r2, [r0]
33421+ orr r3, r3, r1
33422+
33423+ ldr r0, =0x1e6e0068 @ save the result dll value
33424+ ldr r1, [r0]
33425+ bic r1, r1, #0xFF000000
33426+ bic r1, r1, #0x00FF0000
33427+ orr r1, r1, r3, lsl #16
33428+ str r1, [r0]
33429+ b CBR4_START
33430+
33431+.LTORG
33432+
33433+/******************************************************************************
33434+ Search the DQS input mask margin
33435+ *****************************************************************************/
33436+CBR4_START:
33437+/* Debug - UART console message */
33438+ ldr r0, =0x1e784000
33439+ mov r1, #0x34 @ '4'
33440+ str r1, [r0]
33441+/* Debug - UART console message */
33442+
33443+ ldr r0, =0x1e6e0074 @ set the testing DRAM size = 4KB
33444+ ldr r1, =0x00000FFF
33445+ str r1, [r0]
33446+
33447+ mov r8, #0x00 @ init MCR18[4]
33448+ ldr r1, =0x000000ff
33449+ ldr r0, =0x1e7200b0 @ init MCR18[4]=0 max,min
33450+ str r1, [r0]
33451+ ldr r0, =0x1e7200b4 @ init MCR18[4]=1 max,min
33452+ str r1, [r0]
33453+
33454+ ldr r0, =0x1e6e0018
33455+ ldr r1, [r0]
33456+ bic r1, r1, #0x0000001F
33457+ str r1, [r0]
33458+
33459+ b cbr4_scan_start
33460+
33461+cbr4_next_maskdly:
33462+ add r8, r8, #0x01
33463+ and r2, r8, #0x01
33464+ ldr r0, =0x1e6e0018
33465+ ldr r1, [r0]
33466+ bic r1, r1, #0x0000001F
33467+ orr r1, r1, r2, lsl #4
33468+ str r1, [r0]
33469+ cmp r8, #0x02
33470+ bge CBR4_END
33471+
33472+cbr4_scan_start:
33473+ mov r6, #0x00 @ init pass count
33474+ mov r7, #0x00 @ init mask delay
33475+
33476+/****************************
33477+ DQS Mask delay margin test loop
33478+ ***************************/
33479+cbr4_next_parameter:
33480+ cmp r7, #0x10 @ max delay = 0xF
33481+ bge cbr4_next_maskdly
33482+ ldr r0, =0x1e6e0018 @ load MCR18 parameter
33483+ ldr r1, [r0]
33484+ bic r1, r1, #0x0000000F
33485+ orr r1, r1, r7
33486+ str r1, [r0]
33487+ add r7, r7, #0x01
33488+
33489+/* CBRScan3() start */
33490+ adrl r5, PATTERN_TABLE @ init pattern table index
33491+/****************************
33492+ Test pattern iteration loop
33493+ ***************************/
33494+cbr4_next_test_pattern:
33495+ mov r10, #2 @ set the retry loop = 2 of each pattern
33496+ ldr r1, [r5] @ load test pattern
33497+ ldr r0, =0x1e6e007c
33498+ str r1, [r0]
33499+ cmp r1, #0x00 @ the last data in pattern is 0x00
33500+ bne cbr4_test_burst
33501+
33502+ and r3, r7, #0xFF
33503+ sub r3, r3, #0x01 @ we add 1 after loop check so we need to decrease 1
33504+ add r6, r6, #0x01 @ increment pass count
33505+
33506+ ldr r0, =0x1e7200b0 @ record pass window
33507+ add r0, r0, r8, lsl #2
33508+ record_dll2_pass_range
33509+ mov r2, #0x01
33510+ add r1, r1, r2, lsl #16
33511+ str r1, [r0]
33512+ b cbr4_next_parameter
33513+
33514+cbr4_test_pattern_fail:
33515+ cmp r6, #5 @ passcnt >= 5
33516+ bge cbr4_next_maskdly
33517+ b cbr4_next_parameter
33518+
33519+/****************************
33520+ Test fail retry loop
33521+ ***************************/
33522+cbr4_pattern_fail_retry:
33523+
33524+/* CBRTest3() start */
33525+cbr4_test_burst:
33526+ ldr r0, =0x1e6e0070
33527+ ldr r1, =0x00000000
33528+ str r1, [r0]
33529+ ldr r1, =0x000000C1
33530+ str r1, [r0]
33531+ ldr r3, =0x3000
33532+cbr4_wait_engine_idle_0:
33533+ ldr r2, [r0]
33534+ tst r2, r3 @ D[12] = idle bit
33535+ beq cbr4_wait_engine_idle_0
33536+
33537+ ldr r2, [r0] @ read fail bit status
33538+ mov r1, #0x0
33539+ str r1, [r0]
33540+ mov r2, r2, lsr #13 @ D[13] = fail bit
33541+ cmp r2, #0x00
33542+ bne cbr4_test_fail
33543+
33544+cbr4_test_single:
33545+ ldr r0, =0x1e6e0070
33546+ ldr r1, =0x00000000
33547+ str r1, [r0]
33548+ ldr r1, =0x00000085
33549+ str r1, [r0]
33550+ ldr r3, =0x3000
33551+cbr4_wait_engine_idle_1:
33552+ ldr r2, [r0]
33553+ tst r2, r3 @ D[12] = idle bit
33554+ beq cbr4_wait_engine_idle_1
33555+
33556+ ldr r2, [r0] @ read fail bit status
33557+ mov r1, #0x0
33558+ str r1, [r0]
33559+ mov r2, r2, lsr #13 @ D[13] = fail bit
33560+ cmp r2, #0x00
33561+ beq cbr4_test_pass
33562+
33563+/* CBRTest3() end */
33564+
33565+cbr4_test_fail:
33566+ subs r10, r10, #1
33567+ bne cbr4_pattern_fail_retry
33568+ b cbr4_test_pattern_fail @ CBRScan3() return(0)
33569+
33570+cbr4_test_pass:
33571+ add r5, r5, #0x04 @ increase the test pattern index
33572+ b cbr4_next_test_pattern
33573+
33574+CBR4_END:
33575+ ldr r0, =0x1e7200b0 @ check mask margin
33576+ ldr r1, [r0]
33577+ add r0, r0, #0x04
33578+ ldr r2, [r0]
33579+ ands r6, r2, #0xFF @ get min of MCR18[4] = 1
33580+ bne cbr4_noset_delay
33581+ ands r5, r1, #0xFF @ get min of MCR18[4] = 0
33582+ bne cbr4_set_delay
33583+ mov r1, r1, lsr #8 @ get max of MCR18[4] = 0
33584+ and r1, r1, #0xFF
33585+ mov r2, r2, lsr #8 @ get max of MCR18[4] = 1
33586+ and r2, r2, #0xFF
33587+ sub r1, r1, r5
33588+ sub r2, r2, r6
33589+ cmp r1, r2
33590+ bge cbr4_noset_delay
33591+
33592+cbr4_set_delay:
33593+ ldr r0, =0x1e6e0018
33594+ ldr r1, [r0]
33595+ orr r1, r1, #0x10
33596+ str r1, [r0]
33597+
33598+cbr4_noset_delay:
33599+ ldr r0, =0x1e6e0070
33600+ ldr r1, =0x00000000
33601+ str r1, [r0]
33602+
33603+/******************************************************************************
33604+ CBR Finish
33605+ *****************************************************************************/
33606+/******************************************************************************
33607+ Check DRAM Size
33608+ *****************************************************************************/
33609+ ldr r0, =0x1e6e2070
33610+ ldr r1, [r0]
33611+ bic r1, r1, #0xFEFFFFFF @ bit[24]=1 => DDR2
33612+ mov r2, r1, lsr #24
33613+ cmp r2, #0x01
33614+ beq check_ddr2_size
33615+
33616+ ldr r0, =0x1e6e0004
33617+ ldr r5, [r0]
33618+ bic r5, r5, #0x00000003 @ record MCR04
33619+ orr r1, r5, #0x3
33620+ str r1, [r0] @ set to 4Gbit
33621+ ldr r6, =0x003F2217
33622+#if defined(CONFIG_DRAM_336)
33623+ ldr r6, =0x00361C13
33624+#endif
33625+ b check_dram_size
33626+
33627+check_ddr2_size:
33628+ ldr r0, =0x1e6e0004
33629+ ldr r5, [r0]
33630+ bic r5, r5, #0x00000023 @ record MCR04
33631+ orr r1, r5, #0x23
33632+ str r1, [r0] @ set to 4Gbit
33633+ ldr r6, =0x3F2B1B16
33634+#if defined(CONFIG_DRAM_336)
33635+ ldr r6, =0x3B231612
33636+#endif
33637+
33638+ ldr r0, =0x40000000
33639+ ldr r1, =0x1817191A
33640+ str r1, [r0]
33641+ ldr r0, =0x40002000
33642+ ldr r1, =0x73616532
33643+ str r1, [r0]
33644+ ldr r0, =0x40000000
33645+ ldr r1, =0x1817191A
33646+ ldr r2, [r0]
33647+ cmp r1, r2
33648+ bne check_dram_size_end @ == 512Mbit
33649+ orr r5, r5, #0x20 @ >= 1Gbit
33650+ mov r6, r6, lsr #8
33651+
33652+check_dram_size:
33653+ ldr r0, =0x50100000
33654+ ldr r1, =0x41424344
33655+ str r1, [r0]
33656+ ldr r0, =0x48100000
33657+ ldr r1, =0x25262728
33658+ str r1, [r0]
33659+ ldr r0, =0x40100000
33660+ ldr r1, =0x191A1B1C
33661+ str r1, [r0]
33662+ ldr r0, =0x50100000
33663+ ldr r1, =0x41424344
33664+ ldr r2, [r0]
33665+ cmp r2, r1 @ == 4Gbit
33666+ orreq r5, r5, #0x03
33667+ moveq r6, r6, lsr #16
33668+ beq check_dram_size_end
33669+ ldr r0, =0x48100000
33670+ ldr r1, =0x25262728
33671+ ldr r2, [r0]
33672+ cmp r2, r1 @ == 2Gbit
33673+ orreq r5, r5, #0x02
33674+ moveq r6, r6, lsr #8
33675+ beq check_dram_size_end
33676+ orr r5, r5, #0x01 @ == 1Gbit
33677+
33678+check_dram_size_end:
33679+ ldr r0, =0x1e6e0004
33680+ str r5, [r0]
33681+ ldr r0, =0x1e6e0014
33682+ ldr r1, [r0]
33683+ bic r1, r1, #0x000000FF
33684+ and r6, r6, #0xFF
33685+ orr r1, r1, r6
33686+ str r1, [r0]
33687+
33688+ ldr r0, =0x1e6e0120 @ VGA Compatible Mode
33689+ ldr r1, =0x000050C0 @ 408 MHz
33690+#if defined(CONFIG_DRAM_336)
33691+ ldr r1, =0x00004DC0
33692+#endif
33693+ str r1, [r0]
33694+
33695+/******************************************************************************
33696+ Version Number
33697+ *****************************************************************************/
33698+ ldr r0, =0x1e7200a8
33699+ ldr r1, =0x20141229 @ released date
33700+ str r1, [r0]
33701+
33702+ add r0, r0, #4
33703+ ldr r1, =0x00000060 @ released SDK version
33704+ str r1, [r0]
33705+
33706+/******************************************************************************
33707+ Calibration Code End
33708+ ******************************************************************************/
33709+
33710+set_scratch:
33711+ /*Set Scratch register Bit 6 after ddr initial finished */
33712+ ldr r0, =0x1e6e2040
33713+ ldr r1, [r0]
33714+ orr r1, r1, #0x40
33715+ str r1, [r0]
33716+
33717+/* Debug - UART console message */
33718+ ldr r0, =0x1e784000
33719+ mov r1, #0x44 @ 'D'
33720+ str r1, [r0]
33721+ mov r1, #0x6F @ 'o'
33722+ str r1, [r0]
33723+ mov r1, #0x6E @ 'n'
33724+ str r1, [r0]
33725+ mov r1, #0x65 @ 'e'
33726+ str r1, [r0]
33727+ mov r1, #0x0D @ '\r'
33728+ str r1, [r0]
33729+ mov r1, #0x0A @ '\n'
33730+ str r1, [r0]
33731+/* Debug - UART console message */
33732+
33733+/******************************************************************************
33734+ Solve PCIe ASPM issue, only applied to AST2300 series
33735+ ******************************************************************************/
33736+ ldr r0, =0x1e6e207c @ Check bounding for AST1150 existence
33737+ ldr r1, [r0]
33738+ mov r2, r1, lsr #24
33739+ cmp r2, #0x01
33740+ bne platform_exit @ not match AST2300
33741+ bic r1, r1, #0xFFFFFCFF
33742+ mov r1, r1, lsr #8
33743+ cmp r1, #0x02
33744+ beq platform_exit @ match AST1050
33745+
33746+ ldr r0, =0x1e6e2004 @ Disable I2C controller reset
33747+ ldr r1, [r0]
33748+ orr r1, r1, #0x04
33749+ str r1, [r0]
33750+ bic r1, r1, #0x04
33751+ str r1, [r0]
33752+
33753+ ldr r0, =0x1e78a054 @ Check I2C bus state, if busy then quit
33754+ ldr r1, [r0]
33755+ mov r1, r1, lsr #17
33756+ and r1, r1, #0x03
33757+ cmp r1, #0x03
33758+ bne platform_exit
33759+
33760+ ldr r0, =0x1e78a040 @ Init I2C1 controller
33761+ mov r1, #0x01
33762+ orr r1, r1, r1, lsl #16
33763+ str r1, [r0]
33764+
33765+ ldr r0, =0x1e78a044
33766+ ldr r1, =0x77776704
33767+ str r1, [r0]
33768+
33769+ mov r1, #0x0
33770+ ldr r0, =0x1e78a048
33771+ str r1, [r0]
33772+ ldr r0, =0x1e78a04c
33773+ str r1, [r0]
33774+
33775+ ldr r0, =0x1e78a050
33776+ ldr r1, =0xFFFFFFFF
33777+ str r1, [r0]
33778+
33779+ ldr r0, =0x1e78a200 @ Set AST1150 I2C password
33780+ ldr r1, =0x00A88FA8
33781+ str r1, [r0]
33782+
33783+ ldr r0, =0x1e78a05c
33784+ ldr r1, =0x00000200 @ Enable buffer mode transfering 3 bytes
33785+ str r1, [r0]
33786+
33787+ ldr r0, =0x1e78a054
33788+ ldr r1, =0x00000063 @ Fire commmand
33789+ str r1, [r0]
33790+
33791+ ldr r0, =0x1e78a050
33792+i2c_wait_cmddone_1:
33793+ ldr r1, [r0]
33794+ tst r1, #0x38
33795+ beq i2c_wait_cmddone_1
33796+ tst r1, #0x2A @ transmit error
33797+ bne platform_exit2
33798+ ldr r1, =0xFFFFFFFF
33799+ str r1, [r0]
33800+
33801+ ldr r0, =0x1e78a200 @ Disable ASPM capability
33802+ ldr r1, =0x04005DA8
33803+ str r1, [r0]
33804+
33805+ ldr r0, =0x1e78a204
33806+ ldr r1, =0x00000024
33807+ str r1, [r0]
33808+
33809+ ldr r0, =0x1e78a05c
33810+ ldr r1, =0x00000200 @ Enable buffer mode transfering 3 bytes
33811+ str r1, [r0]
33812+
33813+ ldr r0, =0x1e78a054
33814+ ldr r1, =0x00000063 @ Fire commmand
33815+ str r1, [r0]
33816+
33817+ ldr r0, =0x1e78a050
33818+i2c_wait_cmddone_2:
33819+ ldr r1, [r0]
33820+ tst r1, #0x38
33821+ beq i2c_wait_cmddone_2
33822+ tst r1, #0x2A @ transmit error
33823+ bne platform_exit2
33824+ ldr r1, =0xFFFFFFFF
33825+ str r1, [r0]
33826+
33827+platform_exit2:
33828+ ldr r0, =0x1e78a040 @ Disable I2C1 controller
33829+ mov r1, #0x00
33830+ str r1, [r0]
33831+
33832+ b platform_exit
33833+.LTORG
33834+
33835+platform_exit:
33836+#ifdef CONFIG_DRAM_ECC
33837+ ldr r0, =0x1e6e0004
33838+ ldr r1, [r0]
33839+ orr r1, r1, #0x80
33840+ str r1, [r0]
33841+
33842+ ldr r0, =0x1e6e0054
33843+ ldr r1, =0x05000000 /* ECC protected memory size, default set at 80M */
33844+ str r1, [r0]
33845+
33846+ ldr r0, =0x1e6e007C
33847+ ldr r1, =0x00000000
33848+ str r1, [r0]
33849+ ldr r0, =0x1e6e0074
33850+ str r1, [r0]
33851+
33852+ ldr r0, =0x1e6e0070
33853+ ldr r1, =0x00000221
33854+ str r1, [r0]
33855+
33856+ ldr r0, =0x1e6e0070
33857+ ldr r2, =0x00001000
33858+ECC_Init_Flag:
33859+ ldr r1, [r0]
33860+ tst r1, r2 @ D[12] = 1, Done
33861+ beq ECC_Init_Flag
33862+
33863+ ldr r0, =0x1e6e0070
33864+ ldr r1, =0x00000000
33865+ str r1, [r0]
33866+
33867+ ldr r0, =0x1e6e0050
33868+ ldr r1, =0x80000000
33869+ str r1, [r0]
33870+
33871+ ldr r0, =0x1e6e0050
33872+ ldr r1, =0x00000000
33873+ str r1, [r0]
33874+
33875+ ldr r0, =0x1e6e0070
33876+ ldr r1, =0x00000400
33877+ str r1, [r0]
33878+#endif
33879+ ldr r0, =0x1e6e2008 @ Set Video ECLK phase
33880+ ldr r1, [r0]
33881+ ldr r2, =0xfffffff3
33882+ and r1, r1, r2
33883+ orr r1, r1, #0x08
33884+ str r1, [r0]
33885+
33886+ ldr r0, =0x1e6e2004
33887+ ldr r1, [r0]
33888+ ldr r2, =0xFFBFFFFF @ Enable JTAG Master, solve ARM stucked by JTAG issue
33889+ and r1, r1, r2
33890+ str r1, [r0]
33891+
33892+ ldr r0, =0x1e6e2048 @ Set MAC interface delay timing
33893+ ldr r1, =0x2255
33894+ str r1, [r0]
33895+
33896+ ldr r0, =0x1e6e2070 @ Set MAC AHB bus clock
33897+ ldr r1, [r0]
33898+ mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10
33899+ tst r1, #0xC0
33900+ movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6
33901+ ldr r0, =0x1e6e2008
33902+ ldr r1, [r0]
33903+ bic r1, r1, #0x00070000
33904+ orr r1, r1, r2, lsl #16
33905+ str r1, [r0]
33906+
33907+/* Test - DRAM initial time */
33908+ ldr r0, =0x1e782040
33909+ ldr r1, [r0]
33910+ ldr r0, =0xFFFFFFFF
33911+ sub r1, r0, r1
33912+ ldr r0, =0x1e72009c
33913+ str r1, [r0]
33914+ ldr r0, =0x1e7200a4
33915+ str r1, [r0]
33916+ ldr r0, =0x1e782030
33917+ ldr r1, [r0]
33918+ bic r1, r1, #0x0000F000
33919+ str r1, [r0]
33920+/* Test - DRAM initial time */
33921+
33922+/******************************************************************************
33923+ Reset GPIO registers when watchdog reset
33924+ ******************************************************************************/
33925+ ldr r0, =0x1e6e207c @ Check Revision ID
33926+ ldr r1, [r0]
33927+ mov r1, r1, lsr #24
33928+ cmp r1, #0x02
33929+ bne platform_exit3 @ not match AST2400
33930+
33931+ ldr r0, =0x1e6e203c @ Check watchdog reset event
33932+ ldr r1, [r0]
33933+ and r1, r1, #0x06
33934+ cmp r1, #0x0
33935+ beq platform_exit3 @ no watchdog reset event
33936+
33937+ ldr r0, =0x1e6e209c @ Check watchdog GPIO selection
33938+ ldr r1, [r0]
33939+ mov r1, r1, lsr #21
33940+ tst r1, #0x01
33941+ beq platform_exit3 @ no watchdog reset selection
33942+
33943+ ldr r1, =0x00000000 @ clear GPIO register reset by PRST_N
33944+ ldr r2, =0xFFFFFFFF
33945+ ldr r0, =0x1e780008
33946+ str r1, [r0]
33947+ ldr r0, =0x1e78000c
33948+ str r1, [r0]
33949+ ldr r0, =0x1e780010
33950+ str r1, [r0]
33951+ ldr r0, =0x1e780014
33952+ str r1, [r0]
33953+ ldr r0, =0x1e780018
33954+ str r2, [r0]
33955+ ldr r0, =0x1e780028
33956+ str r1, [r0]
33957+ ldr r0, =0x1e78002c
33958+ str r1, [r0]
33959+ ldr r0, =0x1e780030
33960+ str r1, [r0]
33961+ ldr r0, =0x1e780034
33962+ str r1, [r0]
33963+ ldr r0, =0x1e780038
33964+ str r2, [r0]
33965+ ldr r0, =0x1e780040
33966+ str r1, [r0]
33967+ ldr r0, =0x1e780044
33968+ str r1, [r0]
33969+ ldr r0, =0x1e780048
33970+ str r1, [r0]
33971+ ldr r0, =0x1e78004c
33972+ str r1, [r0]
33973+ ldr r0, =0x1e780050
33974+ str r1, [r0]
33975+ ldr r0, =0x1e780054
33976+ str r1, [r0]
33977+ ldr r0, =0x1e780058
33978+ str r1, [r0]
33979+ ldr r0, =0x1e780060
33980+ str r1, [r0]
33981+ ldr r0, =0x1e780064
33982+ str r1, [r0]
33983+ ldr r0, =0x1e780068
33984+ str r1, [r0]
33985+ ldr r0, =0x1e78006c
33986+ str r1, [r0]
33987+ ldr r0, =0x1e780090
33988+ str r1, [r0]
33989+ ldr r0, =0x1e780094
33990+ str r1, [r0]
33991+ ldr r0, =0x1e780098
33992+ str r1, [r0]
33993+ ldr r0, =0x1e78009c
33994+ str r1, [r0]
33995+ ldr r0, =0x1e7800a0
33996+ str r1, [r0]
33997+ ldr r0, =0x1e7800a4
33998+ str r1, [r0]
33999+ ldr r0, =0x1e7800a8
34000+ str r2, [r0]
34001+ ldr r0, =0x1e7800b0
34002+ str r1, [r0]
34003+ ldr r0, =0x1e7800b4
34004+ str r1, [r0]
34005+ ldr r0, =0x1e7800b8
34006+ str r1, [r0]
34007+ ldr r0, =0x1e7800e0
34008+ str r1, [r0]
34009+ ldr r0, =0x1e7800e4
34010+ str r1, [r0]
34011+ ldr r0, =0x1e7800e8
34012+ str r1, [r0]
34013+ ldr r0, =0x1e7800ec
34014+ str r1, [r0]
34015+ ldr r0, =0x1e7800f0
34016+ str r1, [r0]
34017+ ldr r0, =0x1e7800f4
34018+ str r1, [r0]
34019+ ldr r0, =0x1e7800f8
34020+ str r2, [r0]
34021+ ldr r0, =0x1e780100
34022+ str r1, [r0]
34023+ ldr r0, =0x1e780104
34024+ str r1, [r0]
34025+ ldr r0, =0x1e780108
34026+ str r1, [r0]
34027+ ldr r0, =0x1e780110
34028+ str r1, [r0]
34029+ ldr r0, =0x1e780114
34030+ str r1, [r0]
34031+ ldr r0, =0x1e780118
34032+ str r1, [r0]
34033+ ldr r0, =0x1e78011c
34034+ str r1, [r0]
34035+ ldr r0, =0x1e780120
34036+ str r1, [r0]
34037+ ldr r0, =0x1e780124
34038+ str r1, [r0]
34039+ ldr r0, =0x1e780128
34040+ str r2, [r0]
34041+ ldr r0, =0x1e780130
34042+ str r1, [r0]
34043+ ldr r0, =0x1e780134
34044+ str r1, [r0]
34045+ ldr r0, =0x1e780138
34046+ str r1, [r0]
34047+ ldr r0, =0x1e780140
34048+ str r1, [r0]
34049+ ldr r0, =0x1e780144
34050+ str r1, [r0]
34051+ ldr r0, =0x1e780148
34052+ str r1, [r0]
34053+ ldr r0, =0x1e78014c
34054+ str r1, [r0]
34055+ ldr r0, =0x1e780150
34056+ str r1, [r0]
34057+ ldr r0, =0x1e780154
34058+ str r1, [r0]
34059+ ldr r0, =0x1e780158
34060+ str r2, [r0]
34061+ ldr r0, =0x1e780160
34062+ str r1, [r0]
34063+ ldr r0, =0x1e780164
34064+ str r1, [r0]
34065+ ldr r0, =0x1e780168
34066+ str r1, [r0]
34067+ ldr r0, =0x1e780170
34068+ str r1, [r0]
34069+ ldr r0, =0x1e780174
34070+ str r1, [r0]
34071+ ldr r0, =0x1e780178
34072+ str r1, [r0]
34073+ ldr r0, =0x1e78017c
34074+ str r1, [r0]
34075+ ldr r0, =0x1e780180
34076+ str r1, [r0]
34077+ ldr r0, =0x1e780184
34078+ str r1, [r0]
34079+ ldr r0, =0x1e780188
34080+ str r2, [r0]
34081+ ldr r0, =0x1e780190
34082+ str r1, [r0]
34083+ ldr r0, =0x1e780194
34084+ str r1, [r0]
34085+ ldr r0, =0x1e780198
34086+ str r1, [r0]
34087+ ldr r0, =0x1e7801d0
34088+ str r1, [r0]
34089+ ldr r0, =0x1e7801d4
34090+ str r1, [r0]
34091+
34092+ ldr r0, =0x1e780204 @ clear SGPIOM register reset by PRST_N
34093+ str r1, [r0]
34094+ ldr r0, =0x1e780208
34095+ str r1, [r0]
34096+ ldr r0, =0x1e78020c
34097+ str r1, [r0]
34098+ ldr r0, =0x1e780210
34099+ str r1, [r0]
34100+ ldr r0, =0x1e780214
34101+ str r2, [r0]
34102+ ldr r0, =0x1e780220
34103+ str r1, [r0]
34104+ ldr r0, =0x1e780224
34105+ str r1, [r0]
34106+ ldr r0, =0x1e780228
34107+ str r1, [r0]
34108+ ldr r0, =0x1e78022c
34109+ str r1, [r0]
34110+ ldr r0, =0x1e780230
34111+ str r2, [r0]
34112+ ldr r0, =0x1e78023c
34113+ str r1, [r0]
34114+ ldr r0, =0x1e780240
34115+ str r1, [r0]
34116+ ldr r0, =0x1e780244
34117+ str r1, [r0]
34118+ ldr r0, =0x1e780248
34119+ str r1, [r0]
34120+ ldr r0, =0x1e78024c
34121+ str r2, [r0]
34122+ ldr r0, =0x1e780254
34123+ ldr r3, =0x01000040
34124+ str r3, [r0]
34125+ ldr r0, =0x1e780258
34126+ str r1, [r0]
34127+ ldr r0, =0x1e78025c
34128+ str r1, [r0]
34129+ ldr r0, =0x1e780260
34130+ str r1, [r0]
34131+
34132+ ldr r0, =0x1e780300 @ clear SGPIOS register reset by PRST_N
34133+ str r1, [r0]
34134+ ldr r0, =0x1e780304
34135+ str r1, [r0]
34136+ ldr r0, =0x1e780308
34137+ str r1, [r0]
34138+ ldr r0, =0x1e78030c
34139+ str r1, [r0]
34140+ ldr r0, =0x1e780310
34141+ str r1, [r0]
34142+ ldr r0, =0x1e780314
34143+ str r1, [r0]
34144+ ldr r0, =0x1e780318
34145+ str r2, [r0]
34146+ ldr r0, =0x1e78031c
34147+ str r2, [r0]
34148+ ldr r0, =0x1e780320
34149+ str r2, [r0]
34150+
34151+platform_exit3:
34152+
34153+/******************************************************************************
34154+ SPI Timing Calibration, not applicable to AST2300 series
34155+ ******************************************************************************/
34156+ ldr r0, =0x1e6e207c @ Check Revision ID
34157+ ldr r1, [r0]
34158+ mov r1, r1, lsr #24
34159+ cmp r1, #0x02
34160+ blt platform_exit4 @ not match AST2400 or later
34161+
34162+ ldr r0, =0x1e6e2070 @ Check SPI flash
34163+ ldr r1, [r0]
34164+ and r1, r1, #0x03
34165+ cmp r1, #0x02
34166+ bne platform_exit4
34167+
34168+ mov r2, #0x0
34169+ mov r6, #0x0
34170+ mov r7, #0x0
34171+ init_spi_checksum
34172+spi_checksum_wait_0:
34173+ ldr r1, [r0]
34174+ tst r1, r2
34175+ beq spi_checksum_wait_0
34176+ ldr r0, =0x1e620090
34177+ ldr r5, [r0] @ record golden checksum
34178+ ldr r0, =0x1e620080
34179+ mov r1, #0x0
34180+ str r1, [r0]
34181+
34182+ ldr r0, =0x1e620010 @ set to fast read mode
34183+ ldr r1, =0x000B0041
34184+ str r1, [r0]
34185+
34186+ ldr r6, =0x00F7E6D0 @ Init spiclk loop
34187+ mov r8, #0x0 @ Init delay record
34188+
34189+spi_cbr_next_clkrate:
34190+ mov r6, r6, lsr #0x4
34191+ cmp r6, #0x0
34192+ beq spi_cbr_end
34193+
34194+ mov r7, #0x0 @ Init delay loop
34195+ mov r8, r8, lsl #4
34196+
34197+spi_cbr_next_delay_s:
34198+ mov r2, #0x8
34199+ init_spi_checksum
34200+spi_checksum_wait_1:
34201+ ldr r1, [r0]
34202+ tst r1, r2
34203+ beq spi_checksum_wait_1
34204+ ldr r0, =0x1e620090
34205+ ldr r2, [r0] @ read checksum
34206+ ldr r0, =0x1e620080
34207+ mov r1, #0x0
34208+ str r1, [r0]
34209+ cmp r2, r5
34210+ bne spi_cbr_next_delay_e
34211+
34212+ mov r2, #0x0
34213+ init_spi_checksum
34214+spi_checksum_wait_2:
34215+ ldr r1, [r0]
34216+ tst r1, r2
34217+ beq spi_checksum_wait_2
34218+ ldr r0, =0x1e620090
34219+ ldr r2, [r0] @ read checksum
34220+ ldr r0, =0x1e620080
34221+ mov r1, #0x0
34222+ str r1, [r0]
34223+ cmp r2, r5
34224+ bne spi_cbr_next_delay_e
34225+
34226+ orr r8, r8, r7 @ record passed delay
34227+ b spi_cbr_next_clkrate
34228+
34229+spi_cbr_next_delay_e:
34230+ add r7, r7, #0x1
34231+ cmp r7, #0x6
34232+ blt spi_cbr_next_delay_s
34233+ b spi_cbr_next_clkrate
34234+
34235+spi_cbr_end:
34236+ ldr r0, =0x1e620094
34237+ str r8, [r0]
34238+ ldr r0, =0x1e620010
34239+ mov r1, #0x0
34240+ str r1, [r0]
34241+
34242+platform_exit4:
34243+
34244+ /* restore lr */
34245+ mov lr, r4
34246+
34247+ /* back to arch calling code */
34248+ mov pc, lr
34249diff --git a/board/aspeed/ast2400/rc4.c b/board/aspeed/ast2400/rc4.c
34250new file mode 100755
34251index 0000000..32e0ffa
34252--- /dev/null
34253+++ b/board/aspeed/ast2400/rc4.c
34254@@ -0,0 +1,68 @@
34255+/*
34256+ * This program is distributed in the hope that it will be useful,
34257+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34258+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34259+ * GNU General Public License for more details.
34260+ *
34261+ * You should have received a copy of the GNU General Public License
34262+ * along with this program; if not, write to the Free Software
34263+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34264+ */
34265+struct rc4_state
34266+{
34267+ int x, y, m[256];
34268+};
34269+
34270+void rc4_setup( struct rc4_state *s, unsigned char *key, int length )
34271+{
34272+ int i, j, k, *m, a;
34273+
34274+ s->x = 0;
34275+ s->y = 0;
34276+ m = s->m;
34277+
34278+ for( i = 0; i < 256; i++ )
34279+ {
34280+ m[i] = i;
34281+ }
34282+
34283+ j = k = 0;
34284+
34285+ for( i = 0; i < 256; i++ )
34286+ {
34287+ a = m[i];
34288+ j = (unsigned char) ( j + a + key[k] );
34289+ m[i] = m[j]; m[j] = a;
34290+ if( ++k >= length ) k = 0;
34291+ }
34292+}
34293+
34294+void rc4_crypt( struct rc4_state *s, unsigned char *data, int length )
34295+{
34296+ int i, x, y, *m, a, b;
34297+
34298+ x = s->x;
34299+ y = s->y;
34300+ m = s->m;
34301+
34302+ for( i = 0; i < length; i++ )
34303+ {
34304+ x = (unsigned char) ( x + 1 ); a = m[x];
34305+ y = (unsigned char) ( y + a );
34306+ m[x] = b = m[y];
34307+ m[y] = a;
34308+ data[i] ^= m[(unsigned char) ( a + b )];
34309+ }
34310+
34311+ s->x = x;
34312+ s->y = y;
34313+}
34314+
34315+void rc4_crypt_sw(unsigned char *data, int ulMsgLength, unsigned char *rc4_key, unsigned long ulKeyLength )
34316+{
34317+ struct rc4_state s;
34318+
34319+ rc4_setup( &s, rc4_key, ulKeyLength );
34320+
34321+ rc4_crypt( &s, data, ulMsgLength );
34322+}
34323diff --git a/board/aspeed/ast2400/regtest.c b/board/aspeed/ast2400/regtest.c
34324new file mode 100755
34325index 0000000..1cd75ae
34326--- /dev/null
34327+++ b/board/aspeed/ast2400/regtest.c
34328@@ -0,0 +1,91 @@
34329+/*
34330+ * This program is distributed in the hope that it will be useful,
34331+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34332+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34333+ * GNU General Public License for more details.
34334+ *
34335+ * You should have received a copy of the GNU General Public License
34336+ * along with this program; if not, write to the Free Software
34337+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34338+ * MA 02111-1307 USA
34339+ */
34340+
34341+/*
34342+ * Diagnostics support
34343+ */
34344+#include <common.h>
34345+#include <command.h>
34346+#include <post.h>
34347+#include "slt.h"
34348+
34349+#if ((CFG_CMD_SLT & CFG_CMD_REGTEST) && defined(CONFIG_SLT))
34350+#include "regtest.h"
34351+
34352+int do_regtest (void)
34353+{
34354+ _SOCRegTestInfo *pjSOCRegInfo;
34355+ _SOCRegTestTbl *pjRegTable;
34356+ unsigned long ulRegBase;
34357+ unsigned long ulIndex, ulBack, ulAND, ulMask, ulData, ulTemp;
34358+ unsigned long Flags = 0;
34359+
34360+ /* unlock reg */
34361+ *(unsigned long *) (0x1e600000) = 0xaeed1a03; /* AHBC */
34362+ *(unsigned long *) (0x1e6e0000) = 0xfc600309; /* MMC */
34363+ *(unsigned long *) (0x1e6e2000) = 0x1688a8a8; /* SCU */
34364+
34365+ /* SCU */
34366+
34367+ /* do test */
34368+ pjSOCRegInfo = SOCRegTestInfo;
34369+ while (strcmp(pjSOCRegInfo->jName, "END"))
34370+ {
34371+ /* Reg. Test Start */
34372+ ulRegBase = pjSOCRegInfo->ulRegOffset;
34373+ pjRegTable = pjSOCRegInfo->pjTblIndex;
34374+
34375+ while (pjRegTable->ulIndex != 0xFFFFFFFF)
34376+ {
34377+ ulIndex = ulRegBase + pjRegTable->ulIndex;
34378+
34379+ ulBack = *(unsigned long *) (ulIndex);
34380+
34381+ ulMask = pjRegTable->ulMask;
34382+ ulAND = ~pjRegTable->ulMask;
34383+
34384+ ulData = 0xFFFFFFFF & pjRegTable->ulMask;
34385+ *(unsigned long *) (ulIndex) = ulData;
34386+ ulTemp = *(volatile unsigned long *) (ulIndex) & pjRegTable->ulMask;
34387+ if (ulData != ulTemp)
34388+ {
34389+ Flags |= pjSOCRegInfo->ulFlags;
34390+ printf("[DBG] RegTest: Failed Index:%x, Data:%x, Temp:%x \n", ulIndex, ulData, ulTemp);
34391+ }
34392+
34393+ ulData = 0x00000000 & pjRegTable->ulMask;
34394+ *(unsigned long *) (ulIndex) = ulData;
34395+ ulTemp = *(volatile unsigned long *) (ulIndex) & pjRegTable->ulMask;
34396+ if (ulData != ulTemp)
34397+ {
34398+ Flags |= pjSOCRegInfo->ulFlags;
34399+ printf("[DBG] RegTest: Failed Index:%x, Data:%x, Temp:%x \n", ulIndex, ulData, ulTemp);
34400+ }
34401+
34402+ *(unsigned long *) (ulIndex) = ulBack;
34403+
34404+ pjRegTable++;
34405+
34406+ } /* Individual Reg. Test */
34407+
34408+ if (Flags & pjSOCRegInfo->ulFlags)
34409+ printf("[INFO] RegTest: %s Failed \n", pjSOCRegInfo->jName);
34410+
34411+ pjSOCRegInfo++;
34412+
34413+ } /* Reg. Test */
34414+
34415+ return Flags;
34416+
34417+}
34418+
34419+#endif /* CONFIG_SLT */
34420diff --git a/board/aspeed/ast2400/regtest.h b/board/aspeed/ast2400/regtest.h
34421new file mode 100755
34422index 0000000..49a360e
34423--- /dev/null
34424+++ b/board/aspeed/ast2400/regtest.h
34425@@ -0,0 +1,255 @@
34426+/*
34427+ * This program is distributed in the hope that it will be useful,
34428+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34429+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34430+ * GNU General Public License for more details.
34431+ *
34432+ * You should have received a copy of the GNU General Public License
34433+ * along with this program; if not, write to the Free Software
34434+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34435+ */
34436+typedef struct {
34437+ unsigned long ulIndex;
34438+ unsigned long ulMask;
34439+} _SOCRegTestTbl;
34440+
34441+typedef struct {
34442+ unsigned char jName[10];
34443+ unsigned long ulRegOffset;
34444+ _SOCRegTestTbl *pjTblIndex;
34445+ unsigned long ulFlags;
34446+} _SOCRegTestInfo;
34447+
34448+_SOCRegTestTbl SMCRegTestTbl[] = {
34449+ {0x00000000, 0x00001FF3},
34450+ {0x00000004, 0xFFFFFFFF},
34451+ {0x00000008, 0x0FFF17FF},
34452+ {0x0000000C, 0xFFFFFFFF},
34453+ {0x00000010, 0xFF5FFFF3},
34454+ {0x00000018, 0x0FFFFFFF},
34455+ {0xFFFFFFFF, 0xFFFFFFFF},
34456+};
34457+
34458+_SOCRegTestTbl AHBCRegTestTbl[] = {
34459+ {0x00000080, 0x0000FFFE},
34460+ {0x00000088, 0x01000000},
34461+ {0x0000008c, 0x00000031},
34462+ {0xFFFFFFFF, 0xFFFFFFFF},
34463+};
34464+
34465+_SOCRegTestTbl MICRegTestTbl[] = {
34466+/*
34467+ {0x00000000, 0x0FFFFFF8},
34468+ {0x00000004, 0x0FFFFFF8},
34469+ {0x00000008, 0x0000FFFF},
34470+ {0x0000000C, 0x0FFFF000},
34471+ {0x00000010, 0xFFFFFFFF},
34472+*/
34473+ {0xFFFFFFFF, 0xFFFFFFFF},
34474+};
34475+
34476+_SOCRegTestTbl MAC1RegTestTbl[] = {
34477+ {0xFFFFFFFF, 0xFFFFFFFF},
34478+};
34479+
34480+_SOCRegTestTbl MAC2RegTestTbl[] = {
34481+ {0xFFFFFFFF, 0xFFFFFFFF},
34482+};
34483+
34484+_SOCRegTestTbl USB2RegTestTbl[] = {
34485+ {0xFFFFFFFF, 0xFFFFFFFF},
34486+};
34487+
34488+_SOCRegTestTbl VICRegTestTbl[] = {
34489+ {0x0000000C, 0xFFFFFFFF},
34490+ {0x00000024, 0xFFFFFFFF},
34491+ {0x00000028, 0xFFFFFFFF},
34492+ {0x0000002C, 0xFFFFFFFF},
34493+ {0xFFFFFFFF, 0xFFFFFFFF},
34494+};
34495+
34496+_SOCRegTestTbl MMCRegTestTbl[] = {
34497+ {0xFFFFFFFF, 0xFFFFFFFF},
34498+};
34499+
34500+_SOCRegTestTbl USB11RegTestTbl[] = {
34501+ {0xFFFFFFFF, 0xFFFFFFFF},
34502+};
34503+
34504+_SOCRegTestTbl SCURegTestTbl[] = {
34505+ {0xFFFFFFFF, 0xFFFFFFFF},
34506+};
34507+
34508+_SOCRegTestTbl HASERegTestTbl[] = {
34509+ {0x00000000, 0x0FFFFFF8},
34510+ {0x00000004, 0x0FFFFFF8},
34511+ {0x00000008, 0x0FFFFFF8},
34512+ {0x0000000C, 0x0FFFFFF8},
34513+ //{0x00000010, 0x00001FFF},
34514+ {0x00000020, 0x0FFFFFF8},
34515+ {0x00000024, 0x0FFFFFF8},
34516+ {0x00000028, 0x0FFFFFc0},
34517+ {0x0000002C, 0x0FFFFFFF},
34518+ //{0x00000030, 0x000003FF},
34519+ {0xFFFFFFFF, 0xFFFFFFFF},
34520+};
34521+
34522+_SOCRegTestTbl I2SRegTestTbl[] = {
34523+ {0xFFFFFFFF, 0xFFFFFFFF},
34524+};
34525+
34526+_SOCRegTestTbl CRTRegTestTbl[] = {
34527+/*
34528+ {0x00000000, 0x001F3703},
34529+ {0x00000004, 0x0000FFC1},
34530+*/
34531+ {0x00000010, 0x0FFF0FFF},
34532+ {0x00000014, 0x0FFF0FFF},
34533+ {0x00000018, 0x07FF07FF},
34534+ {0x0000001C, 0x07FF07FF},
34535+ {0x00000020, 0x0FFFFFF8},
34536+ {0x00000024, 0x07FF3FF8},
34537+/*
34538+ {0x00000028, 0x003F003F},
34539+ {0x00000030, 0x003F003F},
34540+ {0x00000034, 0x0FFF0FFF},
34541+ {0x00000038, 0x0FFFFFF8},
34542+*/
34543+ {0x00000040, 0x0FFF0FFF},
34544+ {0x00000044, 0x07FF07FF},
34545+ {0x00000048, 0x0FFFFFF8},
34546+ {0x0000004C, 0x00FF07F8},
34547+ {0x00000050, 0x000F0F0F},
34548+/*
34549+ {0x00000060, 0x001F3703},
34550+ {0x00000064, 0x0000FFC1},
34551+*/
34552+ {0x00000070, 0x0FFF0FFF},
34553+ {0x00000074, 0x0FFF0FFF},
34554+ {0x00000078, 0x07FF07FF},
34555+ {0x0000007C, 0x07FF07FF},
34556+ {0x00000080, 0x0FFFFFF8},
34557+ {0x00000084, 0x07FF3FF8},
34558+/*
34559+ {0x00000088, 0x003F003F},
34560+ {0x00000090, 0x003F003F},
34561+ {0x00000094, 0x0FFF0FFF},
34562+ {0x00000098, 0x0FFFFFF8},
34563+*/
34564+ {0x000000A0, 0x0FFF0FFF},
34565+ {0x000000A4, 0x07FF07FF},
34566+ {0x000000A8, 0x0FFFFFF8},
34567+ {0x000000AC, 0x00FF07F8},
34568+ {0x000000B0, 0x000F0F0F},
34569+ {0xFFFFFFFF, 0xFFFFFFFF},
34570+};
34571+
34572+_SOCRegTestTbl VIDEORegTestTbl[] = {
34573+ {0xFFFFFFFF, 0xFFFFFFFF},
34574+};
34575+
34576+_SOCRegTestTbl A2PRegTestTbl[] = {
34577+ {0xFFFFFFFF, 0xFFFFFFFF},
34578+};
34579+
34580+_SOCRegTestTbl MDMARegTestTbl[] = {
34581+ {0xFFFFFFFF, 0xFFFFFFFF},
34582+};
34583+
34584+_SOCRegTestTbl M2DRegTestTbl[] = {
34585+ {0xFFFFFFFF, 0xFFFFFFFF},
34586+};
34587+
34588+_SOCRegTestTbl GPIORegTestTbl[] = {
34589+ {0xFFFFFFFF, 0xFFFFFFFF},
34590+};
34591+
34592+_SOCRegTestTbl RTCRegTestTbl[] = {
34593+ {0xFFFFFFFF, 0xFFFFFFFF},
34594+};
34595+
34596+_SOCRegTestTbl TIMERRegTestTbl[] = {
34597+ {0xFFFFFFFF, 0xFFFFFFFF},
34598+};
34599+
34600+_SOCRegTestTbl UART1RegTestTbl[] = {
34601+ {0xFFFFFFFF, 0xFFFFFFFF},
34602+};
34603+
34604+_SOCRegTestTbl UART2RegTestTbl[] = {
34605+ {0xFFFFFFFF, 0xFFFFFFFF},
34606+};
34607+
34608+_SOCRegTestTbl WDTRegTestTbl[] = {
34609+ {0xFFFFFFFF, 0xFFFFFFFF},
34610+};
34611+
34612+_SOCRegTestTbl PWMRegTestTbl[] = {
34613+ {0xFFFFFFFF, 0xFFFFFFFF},
34614+};
34615+
34616+_SOCRegTestTbl VUART1RegTestTbl[] = {
34617+ {0xFFFFFFFF, 0xFFFFFFFF},
34618+};
34619+
34620+_SOCRegTestTbl VUART2RegTestTbl[] = {
34621+ {0xFFFFFFFF, 0xFFFFFFFF},
34622+};
34623+
34624+_SOCRegTestTbl LPCRegTestTbl[] = {
34625+ {0xFFFFFFFF, 0xFFFFFFFF},
34626+};
34627+
34628+_SOCRegTestTbl I2CRegTestTbl[] = {
34629+ {0xFFFFFFFF, 0xFFFFFFFF},
34630+};
34631+
34632+_SOCRegTestTbl PECIRegTestTbl[] = {
34633+ {0xFFFFFFFF, 0xFFFFFFFF},
34634+};
34635+
34636+_SOCRegTestTbl PCIARegTestTbl[] = {
34637+ {0xFFFFFFFF, 0xFFFFFFFF},
34638+};
34639+
34640+_SOCRegTestTbl PCIRegTestTbl[] = {
34641+ {0xFFFFFFFF, 0xFFFFFFFF},
34642+};
34643+
34644+
34645+/* Test List */
34646+_SOCRegTestInfo SOCRegTestInfo[] = {
34647+ /* Test Name, Reg. Offset, Test Table, Error Code */
34648+ { "SMCREG", 0x16000000, SMCRegTestTbl, 0x00000001},
34649+ { "AHBCREG", 0x1e600000, AHBCRegTestTbl, 0x00000002},
34650+ { "MICREG", 0x1e640000, MICRegTestTbl, 0x00000004},
34651+ { "MAC1REG", 0x1e660000, MAC1RegTestTbl, 0x00000008},
34652+ { "MAC2REG", 0x1e680000, MAC2RegTestTbl, 0x00000010},
34653+ { "USB2REG", 0x1e6a0000, USB2RegTestTbl, 0x00000020},
34654+ { "VICREG", 0x1e6c0000, VICRegTestTbl, 0x00000040},
34655+ { "MMCREG", 0x1e6e0000, MMCRegTestTbl, 0x00000080},
34656+ { "USB11REG", 0x1e6e1000, USB11RegTestTbl, 0x00000100},
34657+ { "SCUREG", 0x1e6e2000, SCURegTestTbl, 0x00000200},
34658+ { "HASEREG", 0x1e6e3000, HASERegTestTbl, 0x00000400},
34659+ { "I2SREG", 0x1e6e5000, I2SRegTestTbl, 0x00000800},
34660+ { "CRTREG", 0x1e6e6000, CRTRegTestTbl, 0x00001000},
34661+ { "VIDEOREG", 0x1e700000, VIDEORegTestTbl, 0x00002000},
34662+ { "A2PREG", 0x1e720000, A2PRegTestTbl, 0x00004000},
34663+ { "MDMAREG", 0x1e740000, MDMARegTestTbl, 0x00008000},
34664+ { "2DREG", 0x1e760000, M2DRegTestTbl, 0x00010000},
34665+ { "GPIOREG", 0x1e780000, GPIORegTestTbl, 0x00020000},
34666+ { "RTCREG", 0x1e781000, RTCRegTestTbl, 0x00040000},
34667+ { "TIMERREG", 0x1e782000, TIMERRegTestTbl, 0x00080000},
34668+ { "UART1REG", 0x1e783000, UART1RegTestTbl, 0x00100000},
34669+ { "UART2REG", 0x1e784000, UART2RegTestTbl, 0x00200000},
34670+ { "WDTREG", 0x1e785000, WDTRegTestTbl, 0x00400000},
34671+ { "PWMREG", 0x1e786000, PWMRegTestTbl, 0x00800000},
34672+ {"VUART1REG", 0x1e787000, VUART1RegTestTbl, 0x01000000},
34673+ {"VUART2REG", 0x1e788000, VUART2RegTestTbl, 0x02000000},
34674+ { "LPCREG", 0x1e789000, LPCRegTestTbl, 0x04000000},
34675+ { "I2CREG", 0x1e78A000, I2CRegTestTbl, 0x08000000},
34676+ { "PECIREG", 0x1e78B000, PECIRegTestTbl, 0x10000000},
34677+ { "PCIAREG", 0x1e78C000, PCIARegTestTbl, 0x20000000},
34678+ { "PCIREG", 0x60000000, PCIRegTestTbl, 0x40000000},
34679+ { "END", 0xffffffff, NULL, 0xffffffff}
34680+};
34681diff --git a/board/aspeed/ast2400/slt.c b/board/aspeed/ast2400/slt.c
34682new file mode 100755
34683index 0000000..3283d34
34684--- /dev/null
34685+++ b/board/aspeed/ast2400/slt.c
34686@@ -0,0 +1,105 @@
34687+/*
34688+ * This program is distributed in the hope that it will be useful,
34689+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34690+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34691+ * GNU General Public License for more details.
34692+ *
34693+ * You should have received a copy of the GNU General Public License
34694+ * along with this program; if not, write to the Free Software
34695+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34696+ * MA 02111-1307 USA
34697+ */
34698+
34699+/*
34700+ * Diagnostics support
34701+ */
34702+#include <common.h>
34703+#include <command.h>
34704+#include <post.h>
34705+#include "slt.h"
34706+
34707+#if defined (CONFIG_SLT)
34708+
34709+int do_slt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
34710+{
34711+ int flags = 0;
34712+ int loop = 1;
34713+
34714+ if (argc > 1) {
34715+ loop = simple_strtoul(argv[1], NULL, 10);
34716+ }
34717+
34718+ do {
34719+
34720+do_slt_start:
34721+ /* Reg. Test */
34722+#if (CFG_CMD_SLT & CFG_CMD_REGTEST)
34723+ if (do_regtest())
34724+ {
34725+ flags |= FLAG_REGTEST_FAIL;
34726+ printf("[INFO] RegTest Failed \n");
34727+ }
34728+ else
34729+ printf("[INFO] RegTest Passed \n");
34730+#endif
34731+#if (CFG_CMD_SLT & CFG_CMD_MACTEST)
34732+ if (do_mactest())
34733+ {
34734+ flags |= FLAG_MACTEST_FAIL;
34735+ printf("[INFO] MACTest Failed \n");
34736+ }
34737+ else
34738+ printf("[INFO] MACTest Passed \n");
34739+#endif
34740+#if (CFG_CMD_SLT & CFG_CMD_VIDEOTEST)
34741+ if (do_videotest())
34742+ {
34743+ flags |= FLAG_VIDEOTEST_FAIL;
34744+ printf("[INFO] VideoTest Failed \n");
34745+ }
34746+ else
34747+ printf("[INFO] VideoTest Passed \n");
34748+#endif
34749+#if (CFG_CMD_SLT & CFG_CMD_HACTEST)
34750+ if (do_hactest())
34751+ {
34752+ flags |= FLAG_HACTEST_FAIL;
34753+ printf("[INFO] HACTest Failed \n");
34754+ }
34755+ else
34756+ printf("[INFO] HACTest Passed \n");
34757+#endif
34758+#if (CFG_CMD_SLT & CFG_CMD_MICTEST)
34759+ if (do_mictest())
34760+ {
34761+ flags |= FLAG_MICTEST_FAIL;
34762+ printf("[INFO] MICTest Failed \n");
34763+ }
34764+ else
34765+ printf("[INFO] MICTest Passed \n");
34766+#endif
34767+
34768+ /* Summary */
34769+ if (flags)
34770+ printf ("[INFO] SLT Test Failed!! \n");
34771+ else
34772+ printf ("[INFO] SLT Test Passed!! \n");
34773+
34774+ if (loop == 0) /* infinite */
34775+ goto do_slt_start;
34776+ else
34777+ loop--;
34778+
34779+ } while (loop);
34780+
34781+ return 0;
34782+}
34783+/***************************************************/
34784+
34785+U_BOOT_CMD(
34786+ slt, CONFIG_SYS_MAXARGS, 0, do_slt,
34787+ "slt - slt test program \n",
34788+ NULL
34789+);
34790+
34791+#endif /* CONFIG_SLT */
34792diff --git a/board/aspeed/ast2400/slt.h b/board/aspeed/ast2400/slt.h
34793new file mode 100755
34794index 0000000..4e650bc
34795--- /dev/null
34796+++ b/board/aspeed/ast2400/slt.h
34797@@ -0,0 +1,29 @@
34798+/*
34799+ * This program is distributed in the hope that it will be useful,
34800+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34801+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34802+ * GNU General Public License for more details.
34803+ *
34804+ * You should have received a copy of the GNU General Public License
34805+ * along with this program; if not, write to the Free Software
34806+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34807+ */
34808+#define CFG_CMD_REGTEST 0x00000001
34809+#define CFG_CMD_MACTEST 0x00000002
34810+#define CFG_CMD_VIDEOTEST 0x00000004
34811+#define CFG_CMD_HACTEST 0x00000008
34812+#define CFG_CMD_MICTEST 0x00000010
34813+#define CFG_CMD_OSDTEST 0x00000020
34814+#define CFG_CMD_2DTEST 0x00000040
34815+#define CFG_CMD_HWCTEST 0x00000080
34816+
34817+#define FLAG_REGTEST_FAIL 0x00000001
34818+#define FLAG_MACTEST_FAIL 0x00000002
34819+#define FLAG_VIDEOTEST_FAIL 0x00000004
34820+#define FLAG_HACTEST_FAIL 0x00000008
34821+#define FLAG_MICTEST_FAIL 0x00000010
34822+#define FLAG_OSDTEST_FAIL 0x00000020
34823+#define FLAG_2DTEST_FAIL 0x00000040
34824+#define FLAG_HWCTEST_FAIL 0x00000080
34825+
34826+
34827diff --git a/board/aspeed/ast2400/type.h b/board/aspeed/ast2400/type.h
34828new file mode 100755
34829index 0000000..f57ee5a
34830--- /dev/null
34831+++ b/board/aspeed/ast2400/type.h
34832@@ -0,0 +1,116 @@
34833+/*
34834+ * This program is distributed in the hope that it will be useful,
34835+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34836+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34837+ * GNU General Public License for more details.
34838+ *
34839+ * You should have received a copy of the GNU General Public License
34840+ * along with this program; if not, write to the Free Software
34841+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34842+ */
34843+#ifndef _TYPE_H_
34844+#define _TYPE_H_
34845+
34846+ typedef unsigned char BOOL;
34847+ typedef unsigned char UINT8;
34848+ typedef unsigned short UINT16;
34849+ typedef unsigned int UINT32;
34850+
34851+ #define FLONG unsigned long
34852+ #define BYTE unsigned char
34853+ #define INT int
34854+ #define VOID void
34855+ #define BOOLEAN unsigned short
34856+ #define ULONG unsigned long
34857+ #define USHORT unsigned short
34858+ #define UCHAR unsigned char
34859+ #define CHAR char
34860+ #define LONG long
34861+ #define PUCHAR UCHAR *
34862+ #define PULONG ULONG *
34863+
34864+ #define FAIL 1
34865+
34866+ #define intfunc int386
34867+
34868+ #define outdwport outpd
34869+ #define indwport inpd
34870+ #define outport outp
34871+ #define inport inp
34872+
34873+ //#define NULL ((void *)0)
34874+ #define FALSE 0
34875+ #define TRUE 1
34876+
34877+ #define ReadMemoryBYTE(baseaddress,offset) *(BYTE *)((ULONG)(baseaddress)+(ULONG)(offset))
34878+ #define ReadMemoryLong(baseaddress,offset) *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
34879+ #define ReadMemoryShort(baseaddress,offset) *(USHORT *)((ULONG)(baseaddress)+(ULONG)(offset))
34880+ #define WriteMemoryBYTE(baseaddress,offset,data) *(BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)
34881+ #define WriteMemoryLong(baseaddress,offset,data) *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
34882+ #define WriteMemoryShort(baseaddress,offset,data) *(USHORT *)((ULONG)(baseaddress)+(ULONG)(offset))=(USHORT)(data)
34883+ #define WriteMemoryLongWithANDData(baseaddress, offset, anddata, data) *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = *(ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) & (ULONG)(anddata) | (ULONG)(data)
34884+
34885+ #define WriteMemoryLongWithMASK(baseaddress, offset, data, mask) \
34886+ *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = *(volatile ULONG *)(((ULONG)(baseaddress)+(ULONG)(offset)) & (ULONG)(~(mask))) | ((ULONG)(data) & (ULONG)(mask))
34887+
34888+ #define ReadMemoryLongHost(baseaddress,offset) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
34889+ #define WriteMemoryLongHost(baseaddress,offset,data) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
34890+ #define WriteMemoryBYTEHost(baseaddress,offset,data) *(volatile BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)
34891+#define WriteMemoryLongWithMASKHost(baseaddress, offset, data, mask) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = (((*(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)))&(~mask)) | (ULONG)((data)&(mask)))
34892+
34893+ #define ReadMemoryLongClient(baseaddress,offset) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))
34894+ #define WriteMemoryLongClient(baseaddress,offset,data) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset))=(ULONG)(data)
34895+ #define WriteMemoryBYTEClient(baseaddress,offset,data) *(volatile BYTE *)((ULONG)(baseaddress)+(ULONG)(offset)) = (BYTE)(data)
34896+#define WriteMemoryLongWithMASKClient(baseaddress, offset, data, mask) *(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)) = (((*(volatile ULONG *)((ULONG)(baseaddress)+(ULONG)(offset)))&(~mask)) | (ULONG)((data)&(mask)))
34897+
34898+#ifdef BUF_GLOBALS
34899+#define BUF_EXT
34900+#else
34901+#define BUF_EXT extern
34902+#endif
34903+
34904+BUF_EXT ULONG g_CAPTURE_VIDEO1_BUF1_ADDR; /* VIDEO1_BUF_1_ADDR*/
34905+BUF_EXT ULONG g_CAPTURE_VIDEO1_BUF2_ADDR; /* VIDEO1_BUF_2_ADDR*/
34906+BUF_EXT ULONG g_VIDEO1_COMPRESS_BUF_ADDR; /* Encode destination address */
34907+BUF_EXT ULONG g_VIDEO1_CRC_BUF_ADDR;
34908+BUF_EXT ULONG g_VIDEO1_FLAG_BUF_ADDR;
34909+BUF_EXT ULONG g_VIDEO1_RC4_BUF_ADDR;
34910+
34911+
34912+BUF_EXT ULONG g_CAPTURE_VIDEO2_BUF1_ADDR;
34913+BUF_EXT ULONG g_CAPTURE_VIDEO2_BUF2_ADDR;
34914+BUF_EXT ULONG g_VIDEO2_COMPRESS_BUF_ADDR;
34915+BUF_EXT ULONG g_VIDEO2_CRC_BUF_ADDR;
34916+BUF_EXT ULONG g_VIDEO2_FLAG_BUF_ADDR;
34917+BUF_EXT ULONG g_VIDEO2_RC4_BUF_ADDR;
34918+
34919+BUF_EXT ULONG g_VIDEO1_DECODE_BUF_1_ADDR;
34920+BUF_EXT ULONG g_VIDEO1_DECODE_BUF_2_ADDR;
34921+BUF_EXT ULONG g_VIDEO1_DECOMPRESS_BUF_ADDR;
34922+BUF_EXT ULONG g_VIDEO1_DECODE_RC4_BUF_ADDR;
34923+
34924+BUF_EXT ULONG g_VIDEO2_DECODE_BUF_1_ADDR;
34925+BUF_EXT ULONG g_VIDEO2_DECODE_BUF_2_ADDR;
34926+BUF_EXT ULONG g_VIDEO2_DECOMPRESS_BUF_ADDR;
34927+BUF_EXT ULONG g_VIDEO2_DECODE_RC4_BUF_ADDR;
34928+
34929+BUF_EXT ULONG g_CAPTURE_VIDEOM_BUF1_ADDR;
34930+BUF_EXT ULONG g_CAPTURE_VIDEOM_BUF2_ADDR;
34931+BUF_EXT ULONG g_VIDEOM_COMPRESS_BUF_ADDR;
34932+BUF_EXT ULONG g_VIDEOM_FLAG_BUF_ADDR;
34933+BUF_EXT ULONG g_VIDEOM_RC4_BUF_ADDR;
34934+
34935+BUF_EXT ULONG g_VIDEOM_DECODE_BUF_1_ADDR;
34936+BUF_EXT ULONG g_VIDEOM_DECODE_BUF_2_ADDR;
34937+BUF_EXT ULONG g_VIDEOM_DECOMPRESS_BUF_ADDR;
34938+BUF_EXT ULONG g_VIDEOM_DECODE_RC4_BUF_ADDR;
34939+
34940+#ifdef WIN_GLOBALS
34941+#define WIN_EXT
34942+#else
34943+#define WIN_EXT extern
34944+#endif
34945+
34946+WIN_EXT USHORT g_DefWidth, g_DefHeight;
34947+
34948+#endif
34949diff --git a/board/aspeed/ast2400/u-boot.lds b/board/aspeed/ast2400/u-boot.lds
34950new file mode 100755
34951index 0000000..ff0fe22
34952--- /dev/null
34953+++ b/board/aspeed/ast2400/u-boot.lds
34954@@ -0,0 +1,56 @@
34955+/*
34956+ * (C) Copyright 2004
34957+ * Wolfgang Denk, DENX Software Engineering, <wg@denx.de>
34958+ *
34959+ * See file CREDITS for list of people who contributed to this
34960+ * project.
34961+ *
34962+ * This program is free software; you can redistribute it and/or
34963+ * modify it under the terms of the GNU General Public License as
34964+ * published by the Free Software Foundation; either version 2 of
34965+ * the License, or (at your option) any later version.
34966+ *
34967+ * This program is distributed in the hope that it will be useful,
34968+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34969+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34970+ * GNU General Public License for more details.
34971+ *
34972+ * You should have received a copy of the GNU General Public License
34973+ * along with this program; if not, write to the Free Software
34974+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34975+ * MA 02111-1307 USA
34976+ */
34977+
34978+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
34979+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
34980+OUTPUT_ARCH(arm)
34981+ENTRY(_start)
34982+SECTIONS
34983+{
34984+ . = 0x00000000;
34985+
34986+ . = ALIGN(4);
34987+ .text :
34988+ {
34989+ cpu/arm926ejs/start.o (.text)
34990+ *(.text)
34991+ }
34992+
34993+ . = ALIGN(4);
34994+ .rodata : { *(.rodata) }
34995+
34996+ . = ALIGN(4);
34997+ .data : { *(.data) }
34998+
34999+ . = ALIGN(4);
35000+ .got : { *(.got) }
35001+
35002+ __u_boot_cmd_start = .;
35003+ .u_boot_cmd : { *(.u_boot_cmd) }
35004+ __u_boot_cmd_end = .;
35005+
35006+ . = ALIGN(4);
35007+ __bss_start = .;
35008+ .bss : { *(.bss) }
35009+ _end = .;
35010+}
35011diff --git a/board/aspeed/ast2400/vdef.h b/board/aspeed/ast2400/vdef.h
35012new file mode 100755
35013index 0000000..3c99b7e
35014--- /dev/null
35015+++ b/board/aspeed/ast2400/vdef.h
35016@@ -0,0 +1,500 @@
35017+/*
35018+ * This program is distributed in the hope that it will be useful,
35019+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
35020+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35021+ * GNU General Public License for more details.
35022+ *
35023+ * You should have received a copy of the GNU General Public License
35024+ * along with this program; if not, write to the Free Software
35025+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35026+ */
35027+#ifndef _VDEF_H_
35028+#define _VDEF_H_
35029+
35030+#define VIDEO1 0
35031+#define VIDEO1_ON 0x01
35032+#define VIDEO2 1
35033+#define VIDEO2_ON 0x02
35034+
35035+#define VIDEOM_ON 0x04
35036+#define VIDEOM 2
35037+
35038+#define CRT_1 0
35039+#define CRT_1_ON 0x01
35040+#define CRT_2 1
35041+#define CRT_2_ON 0x02
35042+
35043+#define SINGLE_CODEC_SINGLE_CAPTURE 0
35044+#define AUTO_CODEC_SINGLE_CAPTURE 2
35045+#define AUTO_CODEC_AUTO_CAPTURE 3
35046+
35047+#define MAC1_BASE 0x1E660000
35048+#define APB_BRIDGE_1_BASE 0x1E6E0000
35049+#define VIDEO_REG_BASE 0x1E700000
35050+#define APB_BRIDGE_2_BASE 0x1E780000
35051+
35052+#define DRAM_INIT_BASE 0x1E6E0000
35053+
35054+#define SDRAM_PROTECT_REG 0x00
35055+ #define SDRAM_WRITE_DISABLE 0
35056+ #define SDRAM_WRITE_ENABLE 1
35057+
35058+#define SCU_BASE 0x1E6E0000
35059+#define SCU_OFFSET 0x2000
35060+
35061+#define VIC_BASE 0x1E6C0000
35062+ #define VIDEO_INT_BIT 7
35063+
35064+#define IRQ_STATUS_REG 0x00
35065+#define RAW_INT_STATUS_REG 0x08
35066+#define INT_SEL_REG 0x0C
35067+ #define FIQ_INT 1
35068+ #define IRQ_INT 0
35069+#define INT_EN_REG 0x10
35070+#define INT_EN_CLEAR_REG 0x14
35071+#define INT_SOFT_REG 0x18
35072+#define INT_SOFT_CLEAR_REG 0x1C
35073+#define INT_SENSE_REG 0x24
35074+ #define LEVEL_SENSE 1
35075+ #define EDGE_SENSE 0
35076+#define INT_EVENT_REG 0x2C
35077+ #define HIGH_LEVEL_SENSE 1
35078+ #define LOW_LEVEL_SENSE 0
35079+
35080+#define SCU_HW_TRAPPING_REG 0x70 + SCU_OFFSET
35081+ #define CLIENT_MODE_EN_BIT 18
35082+ #define CLIENT_MODE_EN_MASK 0x00040000
35083+ #define BE_HOST_CHIP 0
35084+ #define BE_CLIENT_CHIP 1
35085+
35086+#define SCU_ULOCK_KEY 0x1688A8A8
35087+
35088+#define SCU_PROTECT_REG 0x00 + SCU_OFFSET
35089+ #define SCU_WRITE_DISABLE 0
35090+ #define SCU_WRITE_ENABLE 1
35091+
35092+#define SCU_CONTROL_REG 0x04 + SCU_OFFSET
35093+ #define VIDEO_ENGINE_RESET 0x00000040
35094+ #define VIDEO_ENGINE_RESET_BIT 6
35095+ #define VIDEO_ENGINE_RESET_MASK 0x00000040
35096+ #define VIDEO_RESET_EN 1
35097+ #define VIDEO_RESET_OFF 0
35098+
35099+#define SCU_CLOCK_SELECTION_REG 0x08 + SCU_OFFSET
35100+ #define PORTA_CLOCK_DELAY_MASK 7 << 8 //Video port A output clcok selection
35101+ #define PORTA_CLOCK_INV_DELAY_1NS 5 << 8 //Clock inversed and delay ~ 2ns
35102+ #define PORTA_CLOCK_INV_DELAY_2NS 6 << 8 //Clock inversed and delay ~ 3ns
35103+ #define PORTB_CLOCK_DELAY_MASK 7 << 12 //Video port B output clock delay
35104+ #define PORTB_CLOCK_INV_DELAY_1NS 5 << 12 //Clock inversed and delay ~ 3ns
35105+ #define PORTB_CLOCK_INV_DELAY_2NS 6 << 12 //Clock inversed and delay ~ 3ns
35106+ #define PORTB_CLOCK_SEL 1 << 15 //Video port B clock selection
35107+ #define PORTB_FROM_D1CLK 0 << 15
35108+ #define PORTB_FROM_D2CLK 1 << 15
35109+ #define ECLK_CLK_SEL_MASK (3 << 2)
35110+ #define ECLK_FROM_HPLL (1 << 2)
35111+
35112+ #define D2CLK_CLOCK_SELECTION 0x00020000
35113+ #define D2CLK_CLOCK_SELECTION_BIT 17
35114+ #define D2CLK_CLOCK_SELECTION_MASK 0x00060000
35115+ #define NORMAL_CRT1 0
35116+ #define V1CLK_VIDEO1 2
35117+ #define V1CLK_VIDEO2 3
35118+
35119+#define SCU_CLOCK_STOP_REG 0x0C + SCU_OFFSET
35120+ #define EN_ECLK 0 << 0 //Enable ECLK (For Video Engine)
35121+ #define STOP_ECLK_BIT 0
35122+ #define STOP_ECLK_MASK 1 << 0
35123+ #define EN_V1CLK 0 << 3 //Enable V1CLK (For Video Capture #1)
35124+ #define STOP_V1CLK_BIT 3
35125+ #define STOP_V1CLK_MASK 1 << 3
35126+ #define EN_D1CLK 0 << 10 //Enable D1CLK (For CRT1)
35127+ #define STOP_D1CLK_BIT 10
35128+ #define STOP_D1CLK_MASK 1 << 10
35129+ #define EN_D2CLK 0 << 11 //Stop D2CLK (For CRT2)
35130+ #define STOP_D2CLK (1 << 11)
35131+ #define STOP_D2CLK_BIT 11
35132+ #define STOP_D2CLK_MASK 1 << 11
35133+ #define EN_V2CLK 0 << 12 //Stop V2CLK (For Video Capture #2)
35134+ #define STOP_V2CLK_BIT 12
35135+ #define STOP_V2CLK_MASK 1 << 12
35136+ #define STOP_HACE_BIT 13
35137+ #define EN_HACE (0 << 13)
35138+ #define STOP_HACE_MASK (1 << 13)
35139+ #define EN_I2SCLK 0 << 18
35140+ #define STOP_I2SCLK_MASK 1 << 18
35141+
35142+#define SCU_PIN_CTRL1_REG 0x74 + SCU_OFFSET
35143+ #define I2C_5_PIN_EN 1 << 12 //Enable I2C #5 PIN
35144+ #define I2C_5_PIN_OFF 0 << 12 //Disable I2C #5 PIN
35145+ #define I2C_5_PIN_MASK 1 << 12
35146+ #define VGA_PIN_OFF 0 << 15 //Enable VGA pins
35147+ #define VGA_PIN_MASK 1 << 15
35148+ #define VIDEO_PORTA_EN 1 << 16 //Enable Video port A control pins
35149+ #define VIDEO_PORTA_MASK 1 << 16
35150+ #define VIDEO_PORTB_EN 1 << 17 //Enable Video port B control pins
35151+ #define VIDEO_PORTB_MASK 1 << 17
35152+ #define VIDEO_VP1_EN 1 << 22 //Enable VP[11:0]
35153+ #define VIDEO_VP1_MASK 1 << 22
35154+ #define VIDEO_VP2_EN 1 << 23 //Enable VP[23:12]
35155+ #define VIDEO_VP2_MASK 1 << 23
35156+ #define I2S_PIN_EN 1 << 29 //Enable I2S function pins
35157+ #define I2S_PIN_MASK 1 << 29
35158+
35159+#define SCU_PIN_CTRL2_REG 0x78 + SCU_OFFSET
35160+ #define VIDEO_PORTA_SINGLE_EDGE_MASK 1 << 0
35161+ #define VIDEO_PORTA_SINGLE_EDGE 1 << 0 //Enable Video port A single mode
35162+ #define VIDEO_PORTA_DUAL_EDGE 0 << 0
35163+ #define VIDEO_PORTB_SINGLE_EDGE_MASK 1 << 1
35164+ #define VIDEO_PORTB_DUAL_EDGE 0 << 1
35165+ #define VIDEO_PORTB_SINGLE_EDGE 1 << 1 //Enable Video port B single mode
35166+
35167+#define SCU_M_PLL_PARAM_REG 0x20 + SCU_OFFSET
35168+
35169+#define DRAM_BASE 0x40000000
35170+
35171+#define INPUT_BITCOUNT_YUV444 4
35172+#define INPUT_BITCOUNT_YUV420 2
35173+
35174+/* HW comment value */
35175+//PASSWORD
35176+#define VIDEO_UNLOCK_KEY 0x1A038AA8
35177+#define SCU_UNLOCK_KEY 0x1688A8A8
35178+#define SDRAM_UNLOCK_KEY 0xFC600309
35179+
35180+
35181+//#define SAMPLE_RATE 12000000.0
35182+#ifdef OSC_NEW
35183+ #define SAMPLE_RATE 24576000.0
35184+#else
35185+ #define SAMPLE_RATE 24000000.0
35186+#endif
35187+
35188+#define MODEDETECTION_VERTICAL_STABLE_MAXIMUM 0x4
35189+#define MODEDETECTION_HORIZONTAL_STABLE_MAXIMUM 0x4
35190+#define MODEDETECTION_VERTICAL_STABLE_THRESHOLD 0x4
35191+#define MODEDETECTION_HORIZONTAL_STABLE_THRESHOLD 0x8
35192+
35193+#define MODEDETECTION_EDGE_PIXEL_THRES_DIGITAL 2
35194+#define MODEDETECTION_EDGE_PIXEL_THRES_ANALOGE 0x0A
35195+
35196+#define MODEDETECTION_OK 0
35197+#define MODEDETECTION_ERROR 1
35198+#define JUDGE_MODE_ERROR 2
35199+
35200+//I2C Loop Count
35201+#define LOOP_COUNT 1000
35202+#define CAN_NOT_FIND_DEVICE 1
35203+#define SET_I2C_DONE 0
35204+#define I2C_BASE 0xA000
35205+#define AC_TIMING 0x77743355
35206+
35207+//I2C channel and Devices
35208+#define I2C_VIDEO1_EEPROM 0x2
35209+#define I2C_VIDEO2_EEPROM 0x5
35210+#define I2C_VIDEO2_9883 0x4
35211+/*
35212+ULONG CAPTURE1_ADDRESS = 0x1000000;
35213+ULONG CAPTURE2_ADDRESS = 0x3000000;
35214+ULONG PASS1_ENCODE_SOURCE_ADDRESS = 0x1000000;
35215+ULONG PASS1_ENCODE_DESTINATION_ADDRESS = 0x2000000;
35216+ULONG Buffer1_DECODE_SOURCE_ADDRESS = 0x1000000;
35217+ULONG Buffer2_DECODE_SOURCE_ADDRESS = 0x1400000;
35218+ULONG PASS1_DECODE_DESTINATION_ADDRESS = 0x600000;
35219+ULONG CAPTURE_2ND_ADDRESS = 0x1800000;
35220+ULONG PASS1_2ND_ENCODE_SOURCE_ADDRESS = 0x1800000;
35221+ULONG PASS1_2ND_ENCODE_DESTINATION_ADDRESS = 0x2800000;
35222+ULONG PASS1_2ND_DECODE_SOURCE_ADDRESS = 0x1000000;
35223+ULONG PASS1_2ND_DECODE_DESTINATION_ADDRESS = 0x600000;
35224+ULONG PASS2_ENCODE_SOURCE_ADDRESS = 0x000000;
35225+ULONG PASS2_ENCODE_DESTINATION_ADDRESS = 0xC00000;
35226+ULONG PASS2_DECODE_SOURCE_ADDRESS = 0xC00000;
35227+ULONG PASS2_DECODE_DESTINATION_ADDRESS = 0x600000;
35228+ULNG PASS2_DECODE_REFERENCE_ADDRESS = 0x600000;
35229+*/
35230+
35231+typedef struct _CTL_REG_G {
35232+ ULONG CompressMode:1;
35233+ ULONG SkipEmptyFrame:1;
35234+ ULONG MemBurstLen:2;
35235+ ULONG LineBufEn:2;
35236+ ULONG Unused:26;
35237+} CTL_REG_G;
35238+
35239+
35240+typedef union _U_CTL_G {
35241+ ULONG Value;
35242+ CTL_REG_G CtlReg;
35243+} U_CTL_G;
35244+
35245+typedef struct _MODE_DETECTION_PARAM_REG {
35246+ ULONG Unused1:8;
35247+ ULONG EdgePixelThres:8;
35248+ ULONG VerStableMax:4;
35249+ ULONG HorStableMax:4;
35250+ ULONG VerDiffMax:4;
35251+ ULONG HorDiffMax:4;
35252+} MODE_DETECTION_PARAM_REG;
35253+
35254+typedef struct _CRC_PRI_PARAM_REG {
35255+ ULONG Enable:1;
35256+ ULONG HighBitOnly:1;
35257+ ULONG SkipCountMax:6;
35258+ ULONG PolyLow:8;
35259+ ULONG PolyHigh:16;
35260+} CRC_PRI_PARAM_REG;
35261+
35262+typedef union _U_CRC_PRI_PARAM {
35263+ ULONG Value;
35264+ CRC_PRI_PARAM_REG CRCPriParam;
35265+} U_CRC_PRI_PARAM;
35266+
35267+typedef struct _CRC_SEC_PARAM_REG {
35268+ ULONG Unused1:8;
35269+ ULONG PolyLow:8;
35270+ ULONG PolyHigh:16;
35271+} CRC_SEC_PARAM_REG;
35272+
35273+typedef union _U_CRC_SEC_PARAM {
35274+ ULONG Value;
35275+ CRC_SEC_PARAM_REG CRCSecParam;
35276+} U_CRC_SEC_PARAM;
35277+
35278+typedef struct _GENERAL_INFO {
35279+ BYTE EnableVideoM;
35280+ BYTE CenterMode;
35281+ BYTE RC4NoResetFrame;
35282+ BYTE RC4TestMode;
35283+ U_CTL_G uCtlReg;
35284+ U_CRC_PRI_PARAM uCRCPriParam;
35285+ U_CRC_SEC_PARAM uCRCSecParam;
35286+} GENERAL_INFO, *PGENERAL_INFO;
35287+
35288+typedef struct _SEQ_CTL_REG {
35289+ ULONG Unused1:1;
35290+ ULONG Unused2:1;
35291+ ULONG Unused3:1;
35292+ ULONG CaptureAutoMode:1;
35293+ ULONG Unused4:1;
35294+ ULONG CodecAutoMode:1;
35295+ ULONG Unused5:1;
35296+ ULONG WatchDog:1;
35297+ ULONG CRTSel:1;
35298+ ULONG AntiTearing:1;
35299+ ULONG DataType:2;
35300+ ULONG Unused6:20;
35301+} SEQ_CTL_REG;
35302+
35303+typedef union _U_SEQ_CTL {
35304+ ULONG Value;
35305+ SEQ_CTL_REG SeqCtlReg;
35306+} U_SEQ_CTL;
35307+
35308+typedef struct _CTL_REG {
35309+ ULONG SrcHsync:1;
35310+ ULONG SrcVsync:1;
35311+ ULONG ExtSrc:1;
35312+ ULONG AnalongExtSrc:1;
35313+ ULONG IntTimingGen:1;
35314+ ULONG IntDataFrom:1;
35315+ ULONG WriteFmt:2;
35316+ ULONG VGACursor:1;
35317+ ULONG LinearMode:1;
35318+ ULONG ClockDelay:2;
35319+ ULONG CCIR656Src:1;
35320+ ULONG PortClock:1;
35321+ ULONG ExtPort:1;
35322+ ULONG Unused1:1;
35323+ ULONG FrameRate:8;
35324+ ULONG Unused2:8;
35325+} CTL_REG;
35326+
35327+typedef union _U_CTL {
35328+ ULONG Value;
35329+ CTL_REG CtlReg;
35330+} U_CTL_REG;
35331+
35332+typedef struct _TIMING_GEN_SETTING_H {
35333+ ULONG HDEEnd:13;
35334+ ULONG Unused1:3;
35335+ ULONG HDEStart:13;
35336+ ULONG Unused2:3;
35337+} TIMING_GEN_SETTING_H;
35338+
35339+typedef struct _TIMING_GEN_SETTING_V {
35340+ ULONG VDEEnd:13;
35341+ ULONG Unused1:3;
35342+ ULONG VDEStart:13;
35343+ ULONG Unused2:3;
35344+} TIMING_GEN_SETTING_V;
35345+
35346+typedef struct _BCD_CTL_REG {
35347+ ULONG Enable:1;
35348+ ULONG Unused1:15;
35349+ ULONG Tolerance:8;
35350+ ULONG Unused2:8;
35351+} BCD_CTL_REG;
35352+
35353+typedef union _U_BCD_CTL {
35354+ ULONG Value;
35355+ BCD_CTL_REG BCDCtlReg;
35356+} U_BCD_CTL;
35357+
35358+typedef struct _COMPRESS_WINDOW_REG {
35359+ ULONG VerLine:13;
35360+ ULONG Unused1:3;
35361+ ULONG HorPixel:13;
35362+ ULONG Unused2:3;
35363+} COMPRESS_WINDOW_REG;
35364+
35365+typedef struct _STREAM_BUF_SIZE {
35366+ ULONG PacketSize:3;
35367+ ULONG RingBufNum:2;
35368+ ULONG Unused1:11;
35369+ ULONG SkipHighMBThres:7;
35370+ ULONG SkipTestMode:2;
35371+ ULONG Unused2:7;
35372+} STREAM_BUF_SIZE;
35373+
35374+typedef union _U_STREAM_BUF {
35375+ ULONG Value;
35376+ STREAM_BUF_SIZE StreamBufSize;
35377+} U_STREAM_BUF;
35378+
35379+
35380+typedef struct _COMPRESS_CTL_REG {
35381+ ULONG JPEGOnly:1; /* True: Jpeg Only mode(Disable VQ), False:Jpeg and VQ mix mode */
35382+ ULONG En4VQ:1; /* True: 1, 2, 4 color mode, False: 1,2 color mode */
35383+ ULONG CodecMode:1; /* High and best Quantization encoding/decoding setting*/
35384+ ULONG DualQuality:1;
35385+ ULONG EnBest:1;
35386+ ULONG EnRC4:1;
35387+ ULONG NorChromaDCTTable:5;
35388+ ULONG NorLumaDCTTable:5;
35389+ ULONG EnHigh:1;
35390+ ULONG TestCtl:2;
35391+ ULONG UVFmt:1;
35392+ ULONG HufTable:2;
35393+ ULONG AlterValue1:5;
35394+ ULONG AlterValue2:5;
35395+} COMPRESS_CTL_REG;
35396+
35397+typedef union _U_COMPRESS_CTL {
35398+ ULONG Value;
35399+ COMPRESS_CTL_REG CompressCtlReg;
35400+} U_COMPRESS_CTL;
35401+
35402+typedef struct _QUANTI_TABLE_LOW_REG {
35403+ ULONG ChromaTable:5;
35404+ ULONG LumaTable:5;
35405+ ULONG Unused1:22;
35406+} QUANTI_TABLE_LOW_REG;
35407+
35408+typedef union _U_CQUANTI_TABLE_LOW {
35409+ ULONG Value;
35410+ QUANTI_TABLE_LOW_REG QTableLowReg;
35411+} U_QUANTI_TABLE_LOW;
35412+
35413+typedef struct _QUANTI_VALUE_REG {
35414+ ULONG High:15;
35415+ ULONG Unused1:1;
35416+ ULONG Best:15;
35417+ ULONG Unused2:1;
35418+} QUANTI_VALUE_REG;
35419+
35420+typedef union _U_QUANTI_VALUE {
35421+ ULONG Value;
35422+ QUANTI_VALUE_REG QValueReg;
35423+} U_QUANTI_VALUE;
35424+
35425+typedef struct _BSD_PARAM_REG {
35426+ ULONG HighThres:8;
35427+ ULONG LowThres:8;
35428+ ULONG HighCount:6;
35429+ ULONG Unused1:2;
35430+ ULONG LowCount:6;
35431+ ULONG Unused2:2;
35432+} BSD_PARAM_REG;
35433+
35434+typedef union _U_BSD_PARAM {
35435+ ULONG Value;
35436+ BSD_PARAM_REG BSDParamReg;
35437+} U_BSD_PARAM;
35438+
35439+typedef struct _VIDEO_INFO {
35440+ BYTE ExtADCAct; /* read from modection register */
35441+ BYTE EnableRC4;
35442+ BYTE DownScalingMethod;
35443+ USHORT AnalogDifferentialThreshold; /* BCD tolerance */
35444+ USHORT DigitalDifferentialThreshold; /* BCD tolerance */
35445+ USHORT DstWidth;
35446+ USHORT DstHeight;
35447+ USHORT SrcWidth;
35448+ USHORT SrcHeight;
35449+ BYTE HighLumaTable; /* if High and best Jpeg codec enable, use HighLumaTable and HighChromaTable, otherwise HighDeQuantiValue and BestDequantiValue*/
35450+ BYTE HighChromaTable;
35451+ BYTE HighDeQuantiValue;
35452+ BYTE BestDequantiValue;
35453+ U_SEQ_CTL uSeqCtlReg;
35454+ U_CTL_REG uCtlReg;
35455+ U_BCD_CTL uBCDCtlReg;
35456+ U_STREAM_BUF uStreamBufSize;
35457+ U_COMPRESS_CTL uCompressCtlReg;
35458+ U_QUANTI_TABLE_LOW uQTableLowReg;
35459+ U_QUANTI_VALUE uQValueReg;
35460+ U_BSD_PARAM uBSDParamReg;
35461+} VIDEO_INFO, *PVIDEO_INFO ;
35462+
35463+typedef struct _VIDEOM_SEQ_CTL_REG {
35464+ ULONG Unused1:1; //Bit 0
35465+ ULONG Unused2:1; //Bit 1
35466+ ULONG Unused3:1; //Bit 2
35467+ ULONG StreamMode:1; //Bit 3
35468+ ULONG Unused4:1; //Bit 4
35469+ ULONG CodecAutoMode:1; //Bit 5
35470+ ULONG Unused6:1; //Bit 6
35471+ ULONG Unused7:1; //Bit 7
35472+ ULONG SrcSel:1; //Bit 8
35473+ ULONG Unused9:1; //Bit 9
35474+ ULONG DataType:2; //Bit[11:10]
35475+ ULONG Unused12:20;
35476+} VIDEOM_SEQ_CTL_REG;
35477+
35478+typedef union _U_VIDEOM_SEQ_CTL {
35479+ ULONG Value;
35480+ VIDEOM_SEQ_CTL_REG SeqCtlReg;
35481+} U_VIDEOM_SEQ_CTL;
35482+
35483+typedef struct _VIDEOM_INFO {
35484+ BYTE DownScalingMethod;
35485+ USHORT AnalogDifferentialThreshold; /* BCD tolerance */
35486+ USHORT DigitalDifferentialThreshold; /* BCD tolerance */
35487+ USHORT DstWidth;
35488+ USHORT DstHeight;
35489+ USHORT SrcWidth;
35490+ USHORT SrcHeight;
35491+ BYTE HighLumaTable; /* if High and best Jpeg codec enable, use HighLumaTable and HighChromaTable, otherwise HighDeQuantiValue and BestDequantiValue*/
35492+ BYTE HighChromaTable;
35493+ BYTE HighDeQuantiValue;
35494+ BYTE BestDequantiValue;
35495+ BYTE PacketSize; //the same as video1 & video2
35496+ BYTE RingBufNum;
35497+ BYTE EnableRC4;
35498+ U_VIDEOM_SEQ_CTL uSeqCtlReg;
35499+ U_BCD_CTL uBCDCtlReg;
35500+ U_COMPRESS_CTL uCompressCtlReg;
35501+ U_QUANTI_TABLE_LOW uQTableLowReg;
35502+ U_QUANTI_VALUE uQValueReg;
35503+ U_BSD_PARAM uBSDParamReg;
35504+} VIDEOM_INFO, *PVIDEOM_INFO ;
35505+
35506+typedef struct _VIDEO_MODE_INFO
35507+{
35508+ USHORT X;
35509+ USHORT Y;
35510+ USHORT ColorDepth;
35511+ USHORT RefreshRate;
35512+ BYTE ModeIndex;
35513+} VIDEO_MODE_INFO, *PVIDEO_MODE_INFO;
35514+
35515+#endif
35516+
35517diff --git a/board/aspeed/ast2400/vesa.h b/board/aspeed/ast2400/vesa.h
35518new file mode 100755
35519index 0000000..69aba90
35520--- /dev/null
35521+++ b/board/aspeed/ast2400/vesa.h
35522@@ -0,0 +1,163 @@
35523+/*
35524+ * This program is distributed in the hope that it will be useful,
35525+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
35526+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35527+ * GNU General Public License for more details.
35528+ *
35529+ * You should have received a copy of the GNU General Public License
35530+ * along with this program; if not, write to the Free Software
35531+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35532+ */
35533+#ifndef _VESA_H_
35534+#define _VESA_H_
35535+
35536+typedef enum
35537+{
35538+ VCLK25_175 = 0x00,
35539+ VCLK28_322 = 0x01,
35540+ VCLK31_5 = 0x02,
35541+ VCLK31_574 = 0x03,
35542+ VCLK32_76 = 0x04,
35543+ VCLK33_154 = 0x05,
35544+ VCLK36 = 0x06,
35545+ VCLK40 = 0x07,
35546+ VCLK45_978 = 0x08,
35547+ VCLK49_5 = 0x09,
35548+ VCLK50 = 0x0A,
35549+ VCLK52_95 = 0x0B,
35550+ VCLK56_25 = 0x0C,
35551+ VCLK65 = 0x0D,
35552+ VCLK74_48 = 0x0E,
35553+ VCLK75 = 0x0F,
35554+ VCLK78_75 = 0x10,
35555+ VCLK79_373 = 0x11,
35556+ VCLK81_624 = 0x12,
35557+ VCLK83_462 = 0x13,
35558+ VCLK84_715 = 0x14,
35559+ VCLK94_5 = 0x15,
35560+ VCLK106_5 = 0x16,
35561+ VCLK108 = 0x17,
35562+ VCLK119 = 0x18,
35563+ VCLK135 = 0x19,
35564+ VCLK136_358 = 0x1A,
35565+ VCLK146_25 = 0x1B,
35566+ VCLK154 = 0x1C,
35567+ VCLK157_5 = 0x1D,
35568+ VCLK162 = 0x1E
35569+} ePIXEL_CLOCK;
35570+
35571+typedef struct {
35572+ USHORT HorizontalTotal;
35573+ USHORT VerticalTotal;
35574+ USHORT HorizontalActive;
35575+ USHORT VerticalActive;
35576+ BYTE RefreshRate;
35577+ double HorizontalFrequency;
35578+ USHORT HSyncTime;
35579+ USHORT HBackPorch;
35580+ USHORT VSyncTime;
35581+ USHORT VBackPorch;
35582+ USHORT HLeftBorder;
35583+ USHORT HRightBorder;
35584+ USHORT VBottomBorder;
35585+ USHORT VTopBorder;
35586+ USHORT PixelClock;
35587+ BOOL HorPolarity;
35588+ BOOL VerPolarity;
35589+ BYTE ADCIndex1;
35590+ BYTE ADCIndex2;
35591+ BYTE ADCIndex3;
35592+ BYTE ADCIndex5;
35593+ BYTE ADCIndex6;
35594+ BYTE ADCIndex7;
35595+ BYTE ADCIndex8;
35596+ BYTE ADCIndex9;
35597+ BYTE ADCIndexA;
35598+ BYTE ADCIndexF;
35599+ BYTE ADCIndex15;
35600+ int HorizontalShift;
35601+ int VerticalShift;
35602+} VESA_MODE;
35603+
35604+#define HOR_POSITIVE 0
35605+#define HOR_NEGATIVE 1
35606+#define VER_POSITIVE 0
35607+#define VER_NEGATIVE 1
35608+
35609+#ifdef VESA_GLOBALS
35610+
35611+// Note: Modified for modes which have border issue
35612+VESA_MODE vModeTable[] = {
35613+////////////////////////// 60Hz mode
35614+// 720x480 done
35615+ {1056, 497, 720, 480, 60, 29.900, 88, 104, 3, 13, 0, 0, 0, 0, VCLK31_574, HOR_NEGATIVE, VER_NEGATIVE, 0x41, 0xF0, 0x48, 0x05, 0x20, 0x58, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 2},
35616+// 848x480 done
35617+ {1064, 517, 848, 480, 60, 31.160, 88, 91, 3, 26, 0, 0, 0, 0, VCLK33_154, HOR_NEGATIVE, VER_NEGATIVE, 0x42, 0x70, 0x48, 0x05, 0x20, 0x58, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 2},
35618+ {800, 525, 640, 480, 60, 31.469, 96, 40, 2, 25, 1, 1, 8, 8, VCLK25_175, HOR_NEGATIVE, VER_NEGATIVE, 0x31, 0xF0, 0x48, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 2},
35619+// 720x576
35620+ {912, 597, 720, 576, 60, 35.920, 72, 88, 3, 17, 0, 0, 0, 0, VCLK32_76, HOR_NEGATIVE, VER_NEGATIVE, 0x38, 0xF0, 0x48, 0x05, 0x20, 0x48, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 2},
35621+// 960x600 GTF done
35622+ {1232, 622, 960, 600, 60, 37.320, 96, 136, 3, 18, 0, 0, 0, 0, VCLK45_978, HOR_NEGATIVE, VER_NEGATIVE, 0x4C, 0xF0, 0x60, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35623+ {1056, 628, 800, 600, 60, 37.879, 128, 88, 4, 23, 0, 0, 0, 0, VCLK40, HOR_POSITIVE, VER_POSITIVE, 0x41, 0xF0, 0x60, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35624+// 1088x612 GTF done
35625+ {1392, 634, 1088, 612, 60, 38.04, 112, 152, 3, 18, 0, 0, 0, 0, VCLK52_95, HOR_NEGATIVE, VER_NEGATIVE, 0x56, 0xF0, 0x60, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35626+// 1280x720 GTF done
35627+ {1664, 746, 1280, 720, 60, 44.760, 136, 192, 3, 22, 0, 0, 0, 0, VCLK74_48, HOR_NEGATIVE, VER_NEGATIVE, 0x67, 0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35628+// 1360x768 GTF done
35629+ {1776, 795, 1360, 768, 60, 47.700, 144, 208, 3, 23, 0, 0, 0, 0, VCLK84_715, HOR_NEGATIVE, VER_NEGATIVE, 0x6E, 0xF0, 0xA8, 0x05, 0x20, 0x90, 0x60, 0x60, 0x60, 0x5E, 0xFE, 7, 1},
35630+// 1280x768 done
35631+ {1664, 798, 1280, 768, 60, 47.700, 128, 184, 7, 20, 0, 0, 0, 0, VCLK79_373, HOR_NEGATIVE, VER_NEGATIVE, 0x67, 0xF0, 0xA8, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60, 0x5E, 0xFE, 7, 1},
35632+ {1344, 806, 1024, 768, 60, 48.363, 136, 160, 6, 29, 0, 0, 0, 0, VCLK65, HOR_NEGATIVE, VER_NEGATIVE, 0x53, 0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 7},
35633+// 1280x800 GTF done
35634+ {1680, 828, 1280, 800, 60, 49.680, 136, 200, 3, 24, 0, 0, 0, 0, VCLK83_462, HOR_NEGATIVE, VER_NEGATIVE, 0x68, 0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35635+// 1152x864 GTF done
35636+ {1520, 895, 1152, 864, 60, 53.700, 120, 184, 3, 27, 0, 0, 0, 0, VCLK81_624, HOR_NEGATIVE, VER_NEGATIVE, 0x5E, 0xF0, 0xA8, 0x05, 0x20, 0x78, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35637+// 1600x900 GTF done
35638+ {2128, 932, 1600, 900, 60, 55.920, 168, 264, 3, 28, 0, 0, 0, 0, VCLK119, HOR_NEGATIVE, VER_NEGATIVE, 0x84, 0xF0, 0xA8, 0x05, 0x20, 0xA8, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35639+// 1440X900 CVT done
35640+ {1904, 933, 1440, 900, 60, 55.935, 152, 232, 6, 25, 0, 0, 0, 0, VCLK106_5, HOR_NEGATIVE, VER_POSITIVE, 0x76, 0xF0, 0xA8, 0x05, 0x20, 0x96, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35641+ {1800, 1000, 1280, 960, 60, 60.000, 112, 312, 3, 36, 0, 0, 0, 0, VCLK108, HOR_POSITIVE, VER_POSITIVE, 0x70, 0x70, 0xA8, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35642+// 1600x1024 GTF done
35643+ {2144, 1060, 1600, 1024, 60, 63.600, 168, 272, 3, 32, 0, 0, 0, 0, VCLK136_358, HOR_NEGATIVE, VER_NEGATIVE, 0x85, 0xF0, 0xE8, 0x05, 0x20, 0xA8, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35644+ {1688, 1066, 1280, 1024, 60, 63.981, 112, 248, 3, 38, 0, 0, 0, 0, VCLK108, HOR_POSITIVE, VER_POSITIVE, 0x69, 0x70, 0xA8, 0x05, 0x20, 0x70, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35645+// 1680X1050 CVT done Reduced Blanking
35646+ {1840, 1080, 1680, 1050, 60, 64.674, 32, 80, 6, 21, 0, 0, 0, 0, VCLK119, HOR_POSITIVE, VER_NEGATIVE, 0x72, 0xF0, 0xA8, 0x05, 0x20, 0x20, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35647+// 1920X1200 CVT done Reduced Blanking
35648+ {2080, 1235, 1920, 1200, 60, 74.038, 32, 80, 6, 26, 0, 0, 0, 0, VCLK154, HOR_POSITIVE, VER_NEGATIVE, 0x81, 0xF0, 0xA8, 0x05, 0x20, 0x20, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35649+ //{2160, 1250, 1600, 1200, 60,75.000, 192, 304, 3, 46, 0, 0, 0, 0, VCLK162, HOR_POSITIVE, VER_POSITIVE},
35650+ {2160, 1248, 1600, 1200, 60, 75.000, 192, 304, 3, 46, 0, 0, 0, 0, VCLK162, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xE8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35651+
35652+////////////////////// Not 60Hz mode
35653+ {900, 449, 720, 400, 70, 31.469, 108, 45, 2, 25, 1, 1, 8, 8, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x38, 0x30, 0x48, 0x05, 0x20, 0x6C, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 1},
35654+ {832, 520, 640, 480, 72, 37.861, 40, 120, 3, 20, 1, 1, 8, 8, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x33, 0xF0, 0x48, 0x05, 0x20, 0x28, 0x60, 0x60, 0x60, 0x5E, 0xFE, 6, 3},
35655+ {840, 500, 640, 480, 75, 37.500, 64, 120, 3, 16, 0, 0, 0, 0, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x34, 0x70, 0x48, 0x05, 0x20, 0x40, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 3},
35656+ {832, 509, 640, 480, 85, 43.269, 56, 80, 3, 25, 0, 0, 0, 0, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x33, 0xF0, 0x48, 0x05, 0x20, 0x38, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 3},
35657+ {1024, 625, 800, 600, 56, 35.156, 72, 128, 2, 22, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x3F, 0xF0, 0x60, 0x05, 0x20, 0x48, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35658+ {1040, 666, 800, 600, 72, 48.077, 120, 64, 6, 23, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x40, 0xF0, 0x60, 0x05, 0x20, 0x78, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35659+ {1056, 625, 800, 600, 75, 46.875, 80, 160, 3, 21, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x41, 0xF0, 0x60, 0x05, 0x20, 0x50, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35660+ {1048, 631, 800, 600, 85, 53.674, 64, 152, 3, 27, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x41, 0x70, 0x60, 0x05, 0x20, 0x40, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35661+ {1328, 806, 1024, 768, 70, 56.476, 136, 144, 6, 29, 0, 0, 0, 0, 0, HOR_NEGATIVE, VER_NEGATIVE, 0x52, 0xF0, 0xA8, 0x05, 0x20, 0x88, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 7},
35662+ {1312, 800, 1024, 768, 75, 60.023, 96, 176, 3, 28, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x51, 0xF0, 0xA8, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 1},
35663+ {1376, 808, 1024, 768, 85, 68.677, 96, 208, 3, 36, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x55, 0xF0, 0xA8, 0x05, 0x20, 0x60, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 1},
35664+ {1600, 900, 1152, 864, 75, 67.500, 128, 256, 3, 32, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x63, 0xF0, 0xA8, 0x05, 0x20, 0x80, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35665+ {1728, 1011, 1280, 960, 85, 85.938, 160, 224, 3, 47, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x6B, 0xF0, 0xA8, 0x05, 0x20, 0xA0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35666+ {1688, 1066, 1280, 1024, 75, 79.976, 144, 248, 3, 38, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x69, 0x70, 0xE8, 0x05, 0x20, 0x90, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35667+ {1728, 1072, 1280, 1024, 85, 91.146, 160, 224, 3, 44, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x6B, 0xF0, 0xA8, 0x05, 0x20, 0xA0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35668+ {2160, 1250, 1600, 1200, 65, 81.250, 192, 304, 3, 46, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35669+ {2160, 1250, 1600, 1200, 70, 87.500, 192, 304, 3, 46, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35670+ {2160, 1250, 1600, 1200, 75, 93.750, 192, 304, 3, 46, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0},
35671+ {2160, 1250, 1600, 1200, 85, 106.250,192, 304, 3, 46, 0, 0, 0, 0, 0, HOR_POSITIVE, VER_POSITIVE, 0x86, 0xF0, 0xA8, 0x05, 0x20, 0xC0, 0x60, 0x60, 0x60, 0x5E, 0xFE, -1, 0}
35672+};
35673+
35674+USHORT ModeNumberCount = sizeof (vModeTable) / sizeof (VESA_MODE);
35675+USHORT Mode60HZCount = 21;
35676+
35677+#else /* NOT VESA_GLOBALS */
35678+extern VESA_MODE vModeTable[];
35679+extern USHORT ModeNumberCount;
35680+extern USHORT Mode60HZCount;
35681+#endif
35682+
35683+#endif /* _VESA_H_ */
35684+
35685+
35686diff --git a/board/aspeed/ast2400/vfun.c b/board/aspeed/ast2400/vfun.c
35687new file mode 100755
35688index 0000000..f707e80
35689--- /dev/null
35690+++ b/board/aspeed/ast2400/vfun.c
35691@@ -0,0 +1,545 @@
35692+/*
35693+ * This program is distributed in the hope that it will be useful,
35694+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
35695+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35696+ * GNU General Public License for more details.
35697+ *
35698+ * You should have received a copy of the GNU General Public License
35699+ * along with this program; if not, write to the Free Software
35700+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35701+ */
35702+#define BUF_GLOBALS
35703+#include "type.h"
35704+#include "vdef.h"
35705+#include "vreg.h"
35706+#include "crt.h"
35707+#include "vfun.h"
35708+
35709+ULONG UnlockSCURegHost(ULONG MMIOBase, ULONG Key)
35710+{
35711+ WriteMemoryLongHost(SCU_BASE, SCU_PROTECT_REG, Key);
35712+ return ReadMemoryLongHost(SCU_BASE,SCU_PROTECT_REG);
35713+}
35714+
35715+void ResetVideoHost(void)
35716+{
35717+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, VIDEO_RESET_EN << VIDEO_ENGINE_RESET_BIT, VIDEO_ENGINE_RESET_MASK);
35718+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, VIDEO_RESET_OFF << VIDEO_ENGINE_RESET_BIT, VIDEO_ENGINE_RESET_MASK);
35719+}
35720+
35721+void StartModeDetectionTriggerHost(ULONG MMIOBase, ULONG offset)
35722+{
35723+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, MODE_DETECTION_TRIGGER);
35724+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, MODE_DETECTION_TRIGGER, MODE_DETECTION_TRIGGER);
35725+}
35726+
35727+BOOL ReadVideoInterruptHost(ULONG MMIOBase, ULONG value)
35728+{
35729+ return ((ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_READ_REG) & value) ? TRUE : FALSE);
35730+}
35731+
35732+ULONG UnlockVideoRegHost(ULONG MMIOBase, ULONG Key)
35733+{
35734+ WriteMemoryLongHost(VIDEO_REG_BASE, KEY_CONTROL_REG, Key);
35735+ return ReadMemoryLongHost(VIDEO_REG_BASE,KEY_CONTROL_REG);
35736+}
35737+
35738+void StartVideoCaptureTriggerHost(ULONG MMIOBase, ULONG offset)
35739+{
35740+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, VIDEO_CAPTURE_TRIGGER);
35741+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, VIDEO_CAPTURE_TRIGGER, VIDEO_CAPTURE_TRIGGER);
35742+}
35743+
35744+void StartVideoCodecTriggerHost(ULONG MMIOBase, ULONG offset)
35745+{
35746+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, VIDEO_CODEC_TRIGGER);
35747+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, VIDEO_CODEC_TRIGGER, VIDEO_CODEC_TRIGGER);
35748+}
35749+
35750+void StopModeDetectionTriggerHost(ULONG MMIOBase, ULONG offset)
35751+{
35752+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, offset, 0, MODE_DETECTION_TRIGGER);
35753+}
35754+
35755+void ClearVideoInterruptHost(ULONG MMIOBase, ULONG value)
35756+{
35757+ //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_CLEAR_REG, value, value);
35758+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_CLEAR_REG, value);
35759+}
35760+
35761+/* UnLock SCU Host and Reset Engine */
35762+BOOL CheckOnStartHost(void)
35763+{
35764+ int i=0, dwValue=0;
35765+
35766+ do
35767+ {
35768+ dwValue = UnlockSCURegHost(0, SCU_UNLOCK_KEY);
35769+ i++;
35770+ }
35771+ while ((SCU_WRITE_ENABLE != dwValue) && (i<10));
35772+
35773+ //Clear SCU Reset Register
35774+ WriteMemoryLongHost(SCU_BASE, SCU_CONTROL_REG, 0);
35775+
35776+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_ECLK | EN_V1CLK | EN_V2CLK), (STOP_ECLK_MASK | STOP_V1CLK_MASK | STOP_V2CLK_MASK));
35777+
35778+#if defined(CONFIG_AST2300)
35779+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x90 + SCU_OFFSET), 0x00000020, 0x00000030); //enable 24bits
35780+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x88 + SCU_OFFSET), 0x000fff00, 0x000fff00); //enable video multi-pins
35781+#else //AST2100
35782+ //WriteMemoryLongWithMASKHost(SCU_BASE, SCU_PIN_CTRL1_REG, (VIDEO_PORTA_EN | VIDEO_PORTB_EN | VIDEO_VP1_EN | VIDEO_VP2_EN) ,
35783+ // (VIDEO_PORTA_MASK | VIDEO_PORTB_MASK | VIDEO_VP1_MASK | VIDEO_VP2_MASK));
35784+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_PIN_CTRL2_REG, (VIDEO_PORTA_SINGLE_EDGE | VIDEO_PORTB_SINGLE_EDGE) ,
35785+ (VIDEO_PORTA_SINGLE_EDGE_MASK | VIDEO_PORTB_SINGLE_EDGE_MASK));
35786+#endif
35787+
35788+ ResetVideoHost();
35789+
35790+ return TRUE;
35791+}
35792+
35793+BOOL CheckOnStartClient(void)
35794+{
35795+ int i=0, dwValue=0;
35796+
35797+ do
35798+ {
35799+ dwValue = UnlockSCURegHost(0, SCU_UNLOCK_KEY);
35800+ i++;
35801+ }
35802+ while ((SCU_WRITE_ENABLE != dwValue) && (i<10));
35803+
35804+ //Clear SCU Reset Register
35805+ WriteMemoryLongClient(SCU_BASE, SCU_CONTROL_REG, 0);
35806+
35807+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_ECLK | EN_V1CLK | EN_D1CLK | EN_D2CLK | EN_V2CLK),
35808+ (STOP_ECLK_MASK | STOP_D1CLK_MASK | STOP_D2CLK_MASK | STOP_V1CLK_MASK | STOP_V2CLK_MASK));
35809+
35810+ //WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_SELECTION_REG, PORTB_FROM_D2CLK | PORTB_CLOCK_INV_DELAY_3NS | PORTA_CLOCK_INV_DELAY_3NS, PORTB_CLOCK_SEL | PORTB_CLOCK_DELAY_MASK | PORTA_CLOCK_DELAY_MASK);
35811+ //A1EVA
35812+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_SELECTION_REG, (PORTB_FROM_D2CLK | PORTB_CLOCK_INV_DELAY_1NS | PORTA_CLOCK_INV_DELAY_1NS), (PORTB_CLOCK_SEL | PORTB_CLOCK_DELAY_MASK | PORTA_CLOCK_DELAY_MASK));
35813+ WriteMemoryLongWithMASKClient(SCU_BASE, 0x202C, (0x03<<9), (0x03<<9));
35814+
35815+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL1_REG, (VIDEO_PORTA_EN | VIDEO_PORTB_EN | VIDEO_VP1_EN | VIDEO_VP2_EN),
35816+ (VIDEO_PORTA_MASK | VIDEO_PORTB_MASK | VIDEO_VP1_MASK | VIDEO_VP2_MASK));
35817+
35818+#if CONFIG_AST3000
35819+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL2_REG, (VIDEO_PORTA_DUAL_EDGE | VIDEO_PORTB_DUAL_EDGE),
35820+ (VIDEO_PORTA_SINGLE_EDGE_MASK | VIDEO_PORTB_SINGLE_EDGE_MASK));
35821+#else
35822+ //2100 is single edge
35823+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL2_REG, (VIDEO_PORTA_SINGLE_EDGE | VIDEO_PORTB_SINGLE_EDGE),
35824+ (VIDEO_PORTA_SINGLE_EDGE_MASK | VIDEO_PORTB_SINGLE_EDGE_MASK));
35825+#endif
35826+
35827+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_CLOCK_STOP_REG, (EN_D1CLK | EN_D2CLK), (STOP_D1CLK_MASK | STOP_D2CLK_MASK));
35828+ WriteMemoryLongWithMASKClient(SCU_BASE, SCU_PIN_CTRL1_REG, VGA_PIN_OFF, VGA_PIN_MASK);
35829+
35830+ //ResetVideoHost();
35831+
35832+ return TRUE;
35833+}
35834+
35835+ULONG InitializeVideoEngineHost (ULONG MMIOBase,
35836+ int nVideo,
35837+ BOOL HorPolarity,
35838+ BOOL VerPolarity)
35839+{
35840+ //ULONG temp, temp1, temp2;
35841+ ULONG dwRegOffset = nVideo * 0x100;
35842+ ULONG dwValue;
35843+ int i;
35844+
35845+
35846+ /* General Video Control */
35847+ //LineBufEn 0
35848+ //dwValue = (COMPRESS_MODE << CODEC_DECOMPRESS_MODE_BIT) | DELAY_VSYNC_EN;
35849+ dwValue = 0;
35850+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CONTROL_REG, dwValue);
35851+ //Video Data Truncation Register
35852+ WriteMemoryLongHost(VIDEO_REG_BASE, 0x328, 0);
35853+
35854+ //D2CLK clock must config according to video's line buffer
35855+ if (VIDEO1 == nVideo)
35856+ dwValue = LINE_BUFFER_VIDEO1;
35857+ else
35858+ dwValue = LINE_BUFFER_VIDEO2;
35859+
35860+ //D2CLK clock must config according to video's line buffer
35861+ switch (dwValue)
35862+ {
35863+ case LINE_BUFFER_OFF:
35864+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, NORMAL_CRT1, D2CLK_CLOCK_SELECTION_MASK);
35865+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, STOP_D2CLK, STOP_D2CLK_MASK);
35866+ break;
35867+ case LINE_BUFFER_VIDEO1:
35868+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, V1CLK_VIDEO1 << D2CLK_CLOCK_SELECTION_BIT, D2CLK_CLOCK_SELECTION_MASK);
35869+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_D2CLK, STOP_D2CLK_MASK);
35870+ break;
35871+ case LINE_BUFFER_VIDEO2:
35872+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_SELECTION_REG, V1CLK_VIDEO2 << D2CLK_CLOCK_SELECTION_BIT, D2CLK_CLOCK_SELECTION_MASK);
35873+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_D2CLK, STOP_D2CLK_MASK);
35874+ break;
35875+ case LINE_BUFFER_VIDEOM:
35876+ //If select this option, it will config at videoM INIT
35877+ break;
35878+ default:
35879+ break;
35880+ }
35881+
35882+ dwValue = 0;
35883+ //VR30 now is capture window in the compression
35884+ dwValue = g_DefHeight << CAPTURE_VER_LINE_BIT |
35885+ g_DefWidth << CAPTURE_HOR_PIXEL_BIT;
35886+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CAPTURE_WINDOWS_REG + dwRegOffset, dwValue);
35887+
35888+ dwValue = 0;
35889+ //VR34 now is destionation window in the compression
35890+ dwValue = g_DefHeight << COMPRESS_VER_LINE_BIT |
35891+ g_DefWidth << COMPRESS_HOR_PIXEL_BIT;
35892+
35893+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_WINDOWS_REG + dwRegOffset, dwValue);
35894+
35895+ //BitCOUNT according compress data format
35896+ dwValue = YUV444_MODE;
35897+ if (YUV444_MODE == dwValue)
35898+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV444, BUF_LINE_OFFSET_MASK);
35899+ else
35900+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV420, BUF_LINE_OFFSET_MASK);
35901+
35902+ // CRC
35903+ //Disable
35904+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_PRIMARY_REG, 0x0);
35905+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_SECOND_REG, 0x0);
35906+
35907+ /* Sequence Control register */
35908+ //Oonly Encoder need to set
35909+ /* Engine Sequence Contol Register */
35910+ dwValue = (WATCH_DOG_EN << WATCH_DOG_ENABLE_BIT) |
35911+ VIDEO_CAPTURE_AUTO_MODE |
35912+ VIDEO_CODEC_AUTO_MODE;
35913+
35914+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG + dwRegOffset, dwValue);
35915+
35916+ /* Control register */
35917+ dwValue = (HOR_NEGATIVE == HorPolarity) ? NO_INVERSE_POL : INVERSE_POL;
35918+ dwValue = (((VER_NEGATIVE == VerPolarity) ? NO_INVERSE_POL : INVERSE_POL) << VIDEO_VSYNC_POLARITY_BIT) | dwValue;
35919+
35920+ /* HW Recommand*/
35921+ //dwValue = (TILE_MODE << 9) | dwValue;
35922+ dwValue = (EXTERNAL_VGA_SOURCE << EXTERNAL_SOURCE_BIT) | dwValue;
35923+
35924+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG + dwRegOffset, dwValue);
35925+
35926+ /* BCD register */
35927+ //NO BCD
35928+ dwValue = 0;
35929+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BCD_CONTROL_REG + dwRegOffset, dwValue);
35930+
35931+ /* Stream Buffer Size register */
35932+ dwValue = (YUV_TEST << SKIP_TEST_MODE_BIT) |
35933+ (PACKET_SIZE_32KB << STREAM_PACKET_SIZE_BIT) |
35934+ (PACKETS_8 << RING_BUF_PACKET_NUM_BIT);
35935+ /* the same with Video1, Video2, and VideoM*/
35936+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_STREAM_BUF_SIZE, dwValue);
35937+
35938+ /* Comression control register */
35939+ dwValue = (USE_UV_CIR656 << UV_CIR656_FORMAT_BIT)|
35940+ (JPEG_MIX_MODE << JPEG_ONLY_BIT)|
35941+ (VQ_4_COLOR_MODE << VQ_4_COLOR_BIT)|
35942+ (QUANTI_CODEC_MODE << QUALITY_CODEC_SETTING_BIT)|
35943+ (7 << NORMAL_QUANTI_CHROMI_TABLE_BIT) |
35944+ (23 << NORMAL_QUANTI_LUMI_TABLE_BIT);
35945+
35946+ //Video2 have same value as video1
35947+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_CONTROL_REG, dwValue);
35948+
35949+ /* JPEG Quantization Table register */
35950+ dwValue = 0;
35951+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_TABLE_LOW_REG, dwValue);
35952+
35953+ /* Quantization value register */
35954+ //Video2 have same value as video1
35955+ dwValue = 0;
35956+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_VALUE_REG, dwValue);
35957+
35958+ //Video BSD Parameter Register
35959+ //Video2 have same value as video1
35960+ dwValue = 0;
35961+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BSD_PARA_REG, dwValue);
35962+
35963+ //no scale
35964+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_REG, 0x10001000);
35965+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER0_REG, 0x00200000);
35966+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER1_REG, 0x00200000);
35967+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER2_REG, 0x00200000);
35968+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_SCALE_FACTOR_PARAMETER3_REG, 0x00200000);
35969+ return TRUE;
35970+}
35971+
35972+ULONG InitializeVideoEngineClient (ULONG MMIOBase,
35973+ int nVideo)
35974+{
35975+ //ULONG temp, temp1, temp2;
35976+ ULONG dwRegOffset = nVideo * 0x100;
35977+ ULONG dwValue;
35978+ int i;
35979+
35980+
35981+ /* General Video Control */
35982+ //LineBufEn 0
35983+ dwValue = (DECOMPRESS_MODE << CODEC_DECOMPRESS_MODE_BIT);
35984+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CONTROL_REG, dwValue);
35985+ //Video Data Truncation Register
35986+ WriteMemoryLongHost(VIDEO_REG_BASE, 0x328, 0);
35987+
35988+ //VR30 now is capture window in the compression
35989+ dwValue = g_DefHeight << CAPTURE_VER_LINE_BIT |
35990+ g_DefWidth << CAPTURE_HOR_PIXEL_BIT;
35991+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CAPTURE_WINDOWS_REG + dwRegOffset, dwValue, CAPTURE_VER_LINE_MASK | CAPTURE_HOR_PIXEL_MASK);
35992+
35993+ //VR34 now is destionation window in the compression
35994+ dwValue = g_DefHeight << COMPRESS_VER_LINE_BIT |
35995+ g_DefWidth << COMPRESS_HOR_PIXEL_BIT;
35996+
35997+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_WINDOWS_REG + dwRegOffset, dwValue, COMPRESS_VER_LINE_MASK | COMPRESS_HOR_PIXEL_MASK);
35998+
35999+ //BitCOUNT according compress data format
36000+ dwValue = YUV444_MODE;
36001+ if (YUV444_MODE == dwValue)
36002+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV444, BUF_LINE_OFFSET_MASK);
36003+ else
36004+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_LINE_OFFSET_REG + dwRegOffset, g_DefWidth * INPUT_BITCOUNT_YUV420, BUF_LINE_OFFSET_MASK);
36005+
36006+ // CRC
36007+ //Disable
36008+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_PRIMARY_REG, 0x0);
36009+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO_CRC_SECOND_REG, 0x0);
36010+
36011+ /* Sequence Control register */
36012+ //Oonly Encoder need to set
36013+ /* Engine Sequence Contol Register */
36014+ dwValue = VIDEO_CAPTURE_AUTO_MODE |
36015+ VIDEO_CODEC_AUTO_MODE;
36016+
36017+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG + dwRegOffset, dwValue);
36018+
36019+ /* Control register */
36020+ /* HW Recommand*/
36021+ dwValue = (TILE_MODE << 9);
36022+
36023+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG + dwRegOffset, dwValue);
36024+
36025+ /* BCD register */
36026+ //NO BCD
36027+ dwValue = 0;
36028+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BCD_CONTROL_REG + dwRegOffset, dwValue);
36029+
36030+ /* Stream Buffer Size register */
36031+ dwValue = (YUV_TEST << SKIP_TEST_MODE_BIT) |
36032+ (PACKET_SIZE_32KB << STREAM_PACKET_SIZE_BIT) |
36033+ (PACKETS_8 << RING_BUF_PACKET_NUM_BIT);
36034+ /* the same with Video1, Video2, and VideoM*/
36035+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_STREAM_BUF_SIZE, dwValue);
36036+
36037+
36038+ /* Comression control register */
36039+ dwValue = (USE_UV_CIR656 << UV_CIR656_FORMAT_BIT)|
36040+ (JPEG_MIX_MODE << JPEG_ONLY_BIT)|
36041+ (VQ_4_COLOR_MODE << VQ_4_COLOR_BIT)|
36042+ (QUANTI_CODEC_MODE << QUALITY_CODEC_SETTING_BIT)|
36043+ (7 << NORMAL_QUANTI_CHROMI_TABLE_BIT) |
36044+ (23 << NORMAL_QUANTI_LUMI_TABLE_BIT);
36045+
36046+ //Video2 have same value as video1
36047+ if (VIDEO1 == nVideo)
36048+ {
36049+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_CONTROL_REG, dwValue);
36050+ }
36051+ else
36052+ {
36053+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEOM_COMPRESS_CONTROL_REG, dwValue);
36054+ }
36055+
36056+ /* JPEG Quantization Table register */
36057+ dwValue = 0;
36058+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_TABLE_LOW_REG, dwValue);
36059+
36060+ /* Quantization value register */
36061+ //Video2 have same value as video1
36062+ dwValue = 0;
36063+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_QUANTI_VALUE_REG, dwValue);
36064+
36065+ //Video BSD Parameter Register
36066+ //Video2 have same value as video1
36067+ dwValue = 0;
36068+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BSD_PARA_REG, dwValue);
36069+
36070+ return TRUE;
36071+}
36072+
36073+BYTE GetI2CRegClient(ULONG MMIOBase,
36074+ BYTE DeviceSelect,
36075+ BYTE DeviceAddress,
36076+ BYTE RegisterIndex)
36077+{
36078+ BYTE Data;
36079+ ULONG Status;
36080+
36081+// Reset
36082+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 0);
36083+// Set AC Timing and Speed
36084+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x04, AC_TIMING);
36085+// Lower Speed
36086+// WriteMemoryLongWithANDData (VideoEngineInfo->VGAPCIInfo.ulMMIOBaseAddress, I2C_BASE + DeviceSelect * 0x40 + 0x04, 0, 0x33317805);
36087+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x08, 0);
36088+// Clear Interrupt
36089+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36090+// Enable Master Mode
36091+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 1);
36092+// Enable Interrupt
36093+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0xAF);
36094+// BYTE I2C Mode
36095+// Start and Send Device Address
36096+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
36097+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
36098+// Wait TX ACK
36099+ do {
36100+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
36101+ } while (Status != 1);
36102+// Clear Interrupt
36103+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36104+// Send Device Register Index
36105+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterIndex);
36106+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
36107+// Wait Tx ACK
36108+ do {
36109+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
36110+ } while (Status != 1);
36111+// Clear Interrupt
36112+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36113+// Start, Send Device Address + 1(Read Mode), Receive Data
36114+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress + 1);
36115+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x1B);
36116+// Wait Rx Done
36117+ do {
36118+ Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x04) >> 2;
36119+ } while (Status != 1);
36120+// Clear Interrupt
36121+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36122+
36123+// Enable STOP Interrupt
36124+ WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10, 0x10);
36125+// Issue STOP Command
36126+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x20);
36127+// Wait STOP
36128+ do {
36129+ Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x10) >> 4;
36130+ } while (Status != 1);
36131+// Disable STOP Interrupt
36132+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10);
36133+// Clear Interrupt
36134+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36135+// Read Received Data
36136+ Data = (BYTE)((ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20) & 0xFF00) >> 8);
36137+
36138+ return Data;
36139+}
36140+
36141+ULONG SetI2CRegClient(ULONG MMIOBase,
36142+ BYTE DeviceSelect,
36143+ BYTE DeviceAddress,
36144+ BYTE RegisterIndex,
36145+ BYTE RegisterValue)
36146+{
36147+ ULONG Status;
36148+ ULONG Count = 0;
36149+
36150+// Reset
36151+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 0);
36152+// Set Speed
36153+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x04, AC_TIMING);
36154+// Lower Speed
36155+// WriteMemoryLongWithANDData (VideoEngineInfo->VGAPCIInfo.ulMMIOBaseAddress, I2C_BASE + DeviceSelect * 0x40 + 0x04, 0, 0x33317805);
36156+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x08, 0);
36157+// Clear Interrupt
36158+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36159+// Enable Master Mode
36160+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x00, 1);
36161+// Enable Interrupt
36162+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0xAF);
36163+// BYTE I2C Mode
36164+// Start and Send Device Address
36165+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
36166+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
36167+// Wait Tx ACK
36168+ do {
36169+ Count++;
36170+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
36171+
36172+ if (2 == Status)
36173+ {
36174+ //Clear Interrupt
36175+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36176+ //Re-Send Start and Send Device Address while NACK return
36177+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, DeviceAddress);
36178+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x3);
36179+ }
36180+ //else
36181+ {
36182+ if (Count > LOOP_COUNT) {
36183+ return CAN_NOT_FIND_DEVICE;
36184+ }
36185+ }
36186+ } while (Status != 1);
36187+ Count = 0;
36188+// Clear Interrupt
36189+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36190+// Send Device Register Index
36191+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterIndex);
36192+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
36193+// Wait Tx ACK
36194+ do {
36195+ Count++;
36196+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
36197+ if (Count > LOOP_COUNT) {
36198+ return CAN_NOT_FIND_DEVICE;
36199+ }
36200+ } while (Status != 1);
36201+ Count = 0;
36202+// Clear Interrupt
36203+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36204+// Send Device Register Value and Stop
36205+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x20, RegisterValue);
36206+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x2);
36207+// Wait Tx ACK
36208+ do {
36209+ Count++;
36210+ Status = ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x03;
36211+ if (Count > LOOP_COUNT) {
36212+ return CAN_NOT_FIND_DEVICE;
36213+ }
36214+ } while (Status != 1);
36215+ Count = 0;
36216+// Clear Interrupt
36217+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36218+// Enable STOP Interrupt
36219+ WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0x10, 0x10);
36220+// Issue STOP Command
36221+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x14, 0x20);
36222+// Wait STOP
36223+ do {
36224+ Count++;
36225+ Status = (ReadMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10) & 0x10) >> 4;
36226+ if (Count > LOOP_COUNT) {
36227+ return CAN_NOT_FIND_DEVICE;
36228+ }
36229+ } while (Status != 1);
36230+// Disable STOP Interrupt
36231+ WriteMemoryLongWithMASKClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x0C, 0, 0x10);
36232+// Clear Interrupt
36233+ WriteMemoryLongClient(APB_BRIDGE_2_BASE, I2C_BASE + DeviceSelect * 0x40 + 0x10, 0xFFFFFFFF);
36234+
36235+ return SET_I2C_DONE;
36236+}
36237diff --git a/board/aspeed/ast2400/vfun.h b/board/aspeed/ast2400/vfun.h
36238new file mode 100755
36239index 0000000..90f9ec4
36240--- /dev/null
36241+++ b/board/aspeed/ast2400/vfun.h
36242@@ -0,0 +1,79 @@
36243+/*
36244+ * This program is distributed in the hope that it will be useful,
36245+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
36246+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36247+ * GNU General Public License for more details.
36248+ *
36249+ * You should have received a copy of the GNU General Public License
36250+ * along with this program; if not, write to the Free Software
36251+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36252+ */
36253+#ifndef _VFUN_H_
36254+#define _VFUN_H_
36255+
36256+//#define vBufAlign(x) ((x + 0x0000007F) & 0xFFFFFF80) //128 byte alignment
36257+#define vBufAlign(x) ((x + 0x000003FF) & 0xFFFFFC00) //128 byte alignment
36258+#define vBufAlign2(x) ((x + 0x0000FFFF) & 0xFFFF0000) //128 byte alignment
36259+#define v16byteAlign(x) ((x + 0x0000000F) & 0xFFFFFFF0)
36260+#define vBuf_ALIGNMENT 128
36261+
36262+#define HOST_TOTAL_SIZE 0x8000000 /* 128M */
36263+#define STATION_TOTAL_SIZE 0xF800000 /* 120M */
36264+
36265+#define VIDEO_SOURCE_SIZE 0x200000 /* 800X600X4 = 0x1D4C00 */
36266+#define VIDEO_MAX_STREAM_SIZE 0x400000 /* 32X128K = 0x400000 */
36267+#define VIDEO_FLAG_SIZE 0x5000 /* 1920X1200/128 = 0x4650*/
36268+#define VIDEO_CRC_SIZE 0x50000 /* 1920/64X1200X8 = 0x46500*/
36269+
36270+#define VIDEO1_EN_TOTAL_SIZE (VIDEO_SOURCE_SIZE*2+VIDEO_MAX_STREAM_SIZE+VIDEO_FLAG_SIZE+VIDEO_CRC_SIZE) /* 0x1655000 = about 23M*/
36271+#define VIDEO2_EN_TOTAL_SIZE VIDEO1_EN_TOTAL_SIZE
36272+//#define VIDEOM_EN_TOTAL_SIZE (VIDEO_SOURCE_SIZE*2+VIDEO_MAX_STREAM_SIZE+VIDEO_FLAG_SIZE) /* 0x1605000 = about 22.7M */
36273+//#define VIDEO_HOST_SIZE (VIDEO1_EN_TOTAL_SIZE + VIDEO2_EN_TOTAL_SIZE + VIDEOM_EN_TOTAL_SIZE) /* 0x69922816 = about 70M */
36274+#define VIDEO_HOST_SIZE (VIDEO1_EN_TOTAL_SIZE + VIDEO2_EN_TOTAL_SIZE) /* NOT NEED VIDEOM */
36275+
36276+#define VIDEO1_EN_BASE 0x100000
36277+#define VIDEO2_EN_BASE (VIDEO1_EN_BASE + VIDEO1_EN_TOTAL_SIZE)
36278+#define VIDEOM_EN_BASE (VIDEO2_EN_BASE + VIDEO2_EN_TOTAL_SIZE)
36279+
36280+#define VIDEO1_DE_TOTAL_SIZE (VIDEO_MAX_STREAM_SIZE + VIDEO_SOURCE_SIZE) /* 0xD00000 = 13M*/
36281+#define VIDEO2_DE_TOTAL_SIZE (VIDEO1_DE_TOTAL_SIZE)
36282+#define VIDEO_STATION_SIZE (VIDEO1_DE_TOTAL_SIZE + VIDEO2_DE_TOTAL_SIZE) /* 26M */
36283+
36284+#define VIDEO1_DE_BASE VIDEO_HOST_SIZE
36285+#define VIDEO2_DE_BASE (VIDEO1_DE_BASE + VIDEO1_DE_TOTAL_SIZE)
36286+#define VIDEO_ALL_SIZE (VIDEO_HOST_SIZE + VIDEO_STATION_SIZE) //Host and Station
36287+
36288+#define OutdwmBankModeHost(offset,data) WriteMemoryLongHost(DRAM_BASE,offset,data)
36289+#define IndwmBankModeHost(offset) ReadMemoryLongHost(DRAM_BASE,offset)
36290+
36291+ULONG UnlockVideoRegHost(ULONG MMIOBase, ULONG Key);
36292+BOOL CheckOnStartHost(void);
36293+BOOL CheckOnStartClient(void);
36294+void StartVideoCaptureTriggerHost(ULONG MMIOBase, ULONG offset);
36295+void StartVideoCaptureTriggerHost(ULONG MMIOBase, ULONG offset);
36296+void StartVideoCodecTriggerHost(ULONG MMIOBase, ULONG offset);
36297+ULONG UnlockSCURegHost(ULONG MMIOBase, ULONG Key);
36298+ULONG UnlockSCURegHost(ULONG MMIOBase, ULONG Key);
36299+void StartModeDetectionTriggerHost(ULONG MMIOBase, ULONG offset);
36300+void ClearVideoInterruptHost(ULONG MMIOBase, ULONG value);
36301+BOOL ReadVideoInterruptHost(ULONG MMIOBase, ULONG value);
36302+void StopModeDetectionTriggerHost(ULONG MMIOBase, ULONG offset);
36303+void ResetVideoHost(void);
36304+ULONG InitializeVideoEngineHost (ULONG MMIOBase,
36305+ int nVideo,
36306+ BOOL HorPolarity,
36307+ BOOL VerPolarity);
36308+ULONG InitializeVideoEngineClient (ULONG MMIOBase,
36309+ int nVideo);
36310+BYTE GetI2CRegClient(ULONG MMIOBase,
36311+ BYTE DeviceSelect,
36312+ BYTE DeviceAddress,
36313+ BYTE RegisterIndex);
36314+
36315+ULONG SetI2CRegClient(ULONG MMIOBase,
36316+ BYTE DeviceSelect,
36317+ BYTE DeviceAddress,
36318+ BYTE RegisterIndex,
36319+ BYTE RegisterValue);
36320+#endif //_VFUN_H_
36321+
36322diff --git a/board/aspeed/ast2400/vgahw.h b/board/aspeed/ast2400/vgahw.h
36323new file mode 100755
36324index 0000000..7cbba0d
36325--- /dev/null
36326+++ b/board/aspeed/ast2400/vgahw.h
36327@@ -0,0 +1,175 @@
36328+/*
36329+ * This program is distributed in the hope that it will be useful,
36330+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
36331+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36332+ * GNU General Public License for more details.
36333+ *
36334+ * You should have received a copy of the GNU General Public License
36335+ * along with this program; if not, write to the Free Software
36336+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36337+ */
36338+/******************************************************************************
36339+ * Mode Stuff
36340+ ******************************************************************************/
36341+/* Default Settings */
36342+#define CRT_LOW_THRESHOLD_VALUE 0x12
36343+#define CRT_HIGH_THRESHOLD_VALUE 0x1E
36344+
36345+/* Output Selection */
36346+#define CRT1 0x00
36347+#define CRT2 0x01
36348+#define DVI1 0x10
36349+#define DVI2 0x11
36350+#define LVDS1 0x20
36351+#define LVDS2 0x21
36352+
36353+/* Mode Limitation */
36354+#define MAX_HResolution 1600
36355+#define MAX_VResolution 1200
36356+
36357+/* Std. Table Index Definition */
36358+#define TextModeIndex 0
36359+#define EGAModeIndex 1
36360+#define VGAModeIndex 2
36361+#define HiCModeIndex 3
36362+#define TrueCModeIndex 4
36363+
36364+/* DCLK Index */
36365+#define VCLK25_175 0x00
36366+#define VCLK28_322 0x01
36367+#define VCLK31_5 0x02
36368+#define VCLK36 0x03
36369+#define VCLK40 0x04
36370+#define VCLK49_5 0x05
36371+#define VCLK50 0x06
36372+#define VCLK56_25 0x07
36373+#define VCLK65 0x08
36374+#define VCLK75 0x09
36375+#define VCLK78_75 0x0A
36376+#define VCLK94_5 0x0B
36377+#define VCLK108 0x0C
36378+#define VCLK135 0x0D
36379+#define VCLK157_5 0x0E
36380+#define VCLK162 0x0F
36381+#define VCLK119 0x10
36382+
36383+/* Flags Definition */
36384+#define Charx8Dot 0x00000001
36385+#define HalfDCLK 0x00000002
36386+#define DoubleScanMode 0x00000004
36387+#define LineCompareOff 0x00000008
36388+#define SyncPP 0x00000000
36389+#define SyncPN 0x00000040
36390+#define SyncNP 0x00000080
36391+#define SyncNN 0x000000C0
36392+#define HBorder 0x00000020
36393+#define VBorder 0x00000010
36394+#define COLORINDEX 0x00000000
36395+#define MONOINDEX 0x00000100
36396+
36397+/* DAC Definition */
36398+#define DAC_NUM_TEXT 64
36399+#define DAC_NUM_EGA 64
36400+#define DAC_NUM_VGA 256
36401+
36402+/* AST3000 Reg. Definition */
36403+#define AST3000_VGAREG_BASE 0x1e6e6000
36404+#define AST3000_VGA1_CTLREG 0x00
36405+#define AST3000_VGA1_CTLREG2 0x04
36406+#define AST3000_VGA1_STATUSREG 0x08
36407+#define AST3000_VGA1_PLL 0x0C
36408+#define AST3000_VGA1_HTREG 0x10
36409+#define AST3000_VGA1_HRREG 0x14
36410+#define AST3000_VGA1_VTREG 0x18
36411+#define AST3000_VGA1_VRREG 0x1C
36412+#define AST3000_VGA1_STARTADDR 0x20
36413+#define AST3000_VGA1_OFFSETREG 0x24
36414+#define AST3000_VGA1_THRESHOLD 0x28
36415+#define AST3000_HWC1_OFFSET 0x30
36416+#define AST3000_HWC1_XY 0x34
36417+#define AST3000_HWC1_PBase 0x38
36418+#define AST3000_OSD1_H 0x40
36419+#define AST3000_OSD1_V 0x44
36420+#define AST3000_OSD1_PBase 0x48
36421+#define AST3000_OSD1_Offset 0x4C
36422+#define AST3000_OSD1_THRESHOLD 0x50
36423+
36424+#define AST3000_VGA2_CTLREG 0x60
36425+#define AST3000_VGA2_CTLREG2 0x64
36426+#define AST3000_VGA2_STATUSREG 0x68
36427+#define AST3000_VGA2_PLL 0x6C
36428+#define AST3000_VGA2_HTREG 0x70
36429+#define AST3000_VGA2_HRREG 0x74
36430+#define AST3000_VGA2_VTREG 0x78
36431+#define AST3000_VGA2_VRREG 0x7C
36432+#define AST3000_VGA2_STARTADDR 0x80
36433+#define AST3000_VGA2_OFFSETREG 0x84
36434+#define AST3000_VGA2_THRESHOLD 0x88
36435+#define AST3000_HWC2_OFFSET 0x90
36436+#define AST3000_HWC2_XY 0x94
36437+#define AST3000_HWC2_PBase 0x98
36438+#define AST3000_OSD2_H 0xA0
36439+#define AST3000_OSD2_V 0xA4
36440+#define AST3000_OSD2_PBase 0xA8
36441+#define AST3000_OSD2_Offset 0xAC
36442+#define AST3000_OSD2_THRESHOLD 0xB0
36443+
36444+/* Data Structure */
36445+typedef struct {
36446+ UCHAR ModeName[20];
36447+ USHORT usModeIndex;
36448+ USHORT usModeID;
36449+ USHORT usColorIndex;
36450+ USHORT usRefreshRateIndex;
36451+ USHORT usWidth;
36452+ USHORT usHeight;
36453+ USHORT usBitsPerPlane;
36454+ USHORT usRefreshRate;
36455+} ModeInfoStruct;
36456+
36457+typedef struct {
36458+
36459+ UCHAR MISC;
36460+ UCHAR SEQ[4];
36461+ UCHAR CRTC[25];
36462+ UCHAR AR[20];
36463+ UCHAR GR[9];
36464+
36465+} VBIOS_STDTABLE_STRUCT, *PVBIOS_STDTABLE_STRUCT;
36466+
36467+typedef struct {
36468+
36469+ ULONG HT;
36470+ ULONG HDE;
36471+ ULONG HFP;
36472+ ULONG HSYNC;
36473+ ULONG VT;
36474+ ULONG VDE;
36475+ ULONG VFP;
36476+ ULONG VSYNC;
36477+ ULONG DCLKIndex;
36478+ ULONG Flags;
36479+
36480+ ULONG ulRefreshRate;
36481+ ULONG ulRefreshRateIndex;
36482+ ULONG ulModeID;
36483+
36484+} VBIOS_ENHTABLE_STRUCT, *PVBIOS_ENHTABLE_STRUCT;
36485+
36486+typedef struct {
36487+ UCHAR Param1;
36488+ UCHAR Param2;
36489+ UCHAR Param3;
36490+} VBIOS_DCLK_INFO, *PVBIOS_DCLK_INFO;
36491+
36492+typedef struct {
36493+ UCHAR DACR;
36494+ UCHAR DACG;
36495+ UCHAR DACB;
36496+} VBIOS_DAC_INFO, *PVBIOS_DAC_INFO;
36497+
36498+typedef struct {
36499+ PVBIOS_STDTABLE_STRUCT pStdTableEntry;
36500+ PVBIOS_ENHTABLE_STRUCT pEnhTableEntry;
36501+
36502+} VBIOS_MODE_INFO, *PVBIOS_MODE_INFO;
36503diff --git a/board/aspeed/ast2400/vhace.c b/board/aspeed/ast2400/vhace.c
36504new file mode 100755
36505index 0000000..d045cbd
36506--- /dev/null
36507+++ b/board/aspeed/ast2400/vhace.c
36508@@ -0,0 +1,66 @@
36509+/*
36510+ * This program is distributed in the hope that it will be useful,
36511+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
36512+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36513+ * GNU General Public License for more details.
36514+ *
36515+ * You should have received a copy of the GNU General Public License
36516+ * along with this program; if not, write to the Free Software
36517+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36518+ */
36519+#define HASH_GLOBALS
36520+#include "type.h"
36521+#include "vdef.h"
36522+#include "vhace.h"
36523+#include "vfun.h"
36524+
36525+void HashAst3000(ULONG ulLength, ULONG *output, ULONG ulHashMode)
36526+{
36527+ ULONG i, ulTemp, ulCommand, ulDigestLength;
36528+ ULONG ulValue;
36529+
36530+ /* Get Info */
36531+ switch (ulHashMode)
36532+ {
36533+ case VHASHMODE_MD5:
36534+ ulCommand = VHASH_ALG_SELECT_MD5;
36535+ ulDigestLength = 16;
36536+ break;
36537+ case VHASHMODE_SHA1:
36538+ ulCommand = VHASH_ALG_SELECT_SHA1;
36539+ ulDigestLength = 20;
36540+ break;
36541+ case VHASHMODE_SHA256:
36542+ ulCommand = VHASH_ALG_SELECT_SHA256;
36543+ ulDigestLength = 32;
36544+ break;
36545+ case VHASHMODE_SHA224:
36546+ ulCommand = VHASH_ALG_SELECT_SHA224;
36547+ ulDigestLength = 28;
36548+ break;
36549+ }
36550+
36551+ /* Init. HW */
36552+ WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_SRC_BASE_OFFSET, g_HashSrcBuffer);
36553+ WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_DST_BASE_OFFSET, g_HashDstBuffer);
36554+ WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_LEN_OFFSET, ulLength);
36555+
36556+ /* write src */
36557+ //already fill in g_VIDEO1_COMPRESS_BUF_ADDR
36558+
36559+ /* fire cmd */
36560+ WriteMemoryLongHost(VHAC_REG_BASE, VREG_HASH_CMD_OFFSET, ulCommand);
36561+
36562+ /* get digest */
36563+ do {
36564+ ulTemp = ReadMemoryLongHost(VHAC_REG_BASE, VREG_HASH_STATUS_OFFSET);
36565+ } while (ulTemp & VHASH_BUSY);
36566+
36567+ for (i=0; i<ulDigestLength/4; i++)
36568+ {
36569+ ulValue = *(((ULONG *)g_HashDstBuffer) + i);
36570+
36571+ //output is ULONG pointer
36572+ *(output + i) = ulValue;
36573+ }
36574+}
36575diff --git a/board/aspeed/ast2400/vhace.h b/board/aspeed/ast2400/vhace.h
36576new file mode 100755
36577index 0000000..460989b
36578--- /dev/null
36579+++ b/board/aspeed/ast2400/vhace.h
36580@@ -0,0 +1,58 @@
36581+/*
36582+ * This program is distributed in the hope that it will be useful,
36583+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
36584+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36585+ * GNU General Public License for more details.
36586+ *
36587+ * You should have received a copy of the GNU General Public License
36588+ * along with this program; if not, write to the Free Software
36589+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36590+ */
36591+#ifndef _VHACE_H_
36592+#define _VHACE_H_
36593+
36594+#define VHASHMODE_MD5 0x00
36595+#define VHASHMODE_SHA1 0x01
36596+#define VHASHMODE_SHA256 0x02
36597+#define VHASHMODE_SHA224 0x03
36598+
36599+#define VHASH_ALG_SELECT_MASK 0x70
36600+#define VHASH_ALG_SELECT_MD5 0x00
36601+#define VHASH_ALG_SELECT_SHA1 0x20
36602+#define VHASH_ALG_SELECT_SHA224 0x40
36603+#define VHASH_ALG_SELECT_SHA256 0x50
36604+
36605+#define VHASH_BUSY 0x01
36606+
36607+#define VHAC_REG_BASE 0x1e6e0000
36608+#define VHAC_REG_OFFSET 0x3000
36609+
36610+#define VREG_HASH_SRC_BASE_OFFSET (0x20+VHAC_REG_OFFSET)
36611+#define VREG_HASH_DST_BASE_OFFSET (0x24+VHAC_REG_OFFSET)
36612+#define VREG_HASH_KEY_BASE_OFFSET (0x28+VHAC_REG_OFFSET)
36613+#define VREG_HASH_LEN_OFFSET (0x2C+VHAC_REG_OFFSET)
36614+#define VREG_HASH_CMD_OFFSET (0x30+VHAC_REG_OFFSET)
36615+
36616+#define VREG_HASH_STATUS_OFFSET (0x1C+VHAC_REG_OFFSET)
36617+
36618+typedef struct
36619+{
36620+ int HashMode;
36621+ int DigestLen;
36622+} HASH_METHOD;
36623+
36624+
36625+#ifdef HASH_GLOBALS
36626+#define HASH_EXT
36627+#else
36628+#define HASH_EXT extern
36629+#endif
36630+
36631+HASH_EXT HASH_METHOD g_HashMethod;
36632+HASH_EXT BYTE g_DigestBuf[32];
36633+HASH_EXT ULONG g_HashSrcBuffer;
36634+HASH_EXT ULONG g_HashDstBuffer;
36635+
36636+void HashAst3000(ULONG ulLength, ULONG *output, ULONG ulHashMode);
36637+#endif
36638+
36639diff --git a/board/aspeed/ast2400/videotest.c b/board/aspeed/ast2400/videotest.c
36640new file mode 100755
36641index 0000000..f2e4953
36642--- /dev/null
36643+++ b/board/aspeed/ast2400/videotest.c
36644@@ -0,0 +1,779 @@
36645+/*
36646+ * This program is distributed in the hope that it will be useful,
36647+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
36648+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36649+ * GNU General Public License for more details.
36650+ *
36651+ * You should have received a copy of the GNU General Public License
36652+ * along with this program; if not, write to the Free Software
36653+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36654+ * MA 02111-1307 USA
36655+ */
36656+
36657+/*
36658+ * Diagnostics support
36659+ */
36660+#include <common.h>
36661+#include <command.h>
36662+#include <malloc.h>
36663+#include <post.h>
36664+
36665+#include "slt.h"
36666+#define WIN_GLOBALS
36667+#include "type.h"
36668+#include "vreg.h"
36669+#define VESA_GLOBALS
36670+#include "vesa.h"
36671+#include "vfun.h"
36672+#include "vdef.h"
36673+#include "vhace.h"
36674+#include "crt.h"
36675+#include "videotest.h"
36676+
36677+#define VHASH_ALIGNMENT 16
36678+#define VHASH_MAX_DST (32+VHASH_ALIGNMENT)
36679+
36680+
36681+#if ((CFG_CMD_SLT & CFG_CMD_VIDEOTEST) && defined(CONFIG_SLT))
36682+#include "videotest.h"
36683+
36684+#define RAND_MAX 32767 //2^16-1
36685+
36686+ULONG randSeed = 1;
36687+
36688+void srand(ULONG seed)
36689+{
36690+ randSeed = seed;
36691+}
36692+
36693+int rand(void)
36694+{
36695+ randSeed = randSeed * 214013 + 2531011;
36696+ return (int)(randSeed >> 17); //32 -15 = 17
36697+}
36698+
36699+//static unsigned char CaptureVideo1Buf1Addr[VIDEO_SOURCE_SIZE], CaptureVideo1Buf2Addr[VIDEO_SOURCE_SIZE], Video1CompressBufAddr[CRYPTO_MAX_CONTEXT];
36700+ULONG pCaptureVideo1Buf1Addr[VIDEO_SOURCE_SIZE/4], pCaptureVideo1Buf2Addr[VIDEO_SOURCE_SIZE/4], pVideo1CompressBufAddr[VIDEO_MAX_STREAM_SIZE/4], pVideo1FlagBufAddr[VIDEO_FLAG_SIZE];
36701+ULONG pCaptureVideo2Buf1Addr[VIDEO_SOURCE_SIZE/4], pCaptureVideo2Buf2Addr[VIDEO_SOURCE_SIZE/4], pVideo2CompressBufAddr[VIDEO_MAX_STREAM_SIZE/4], pVideo2FlagBufAddr[VIDEO_FLAG_SIZE];
36702+
36703+ULONG pVHashDstBuffer[VHASH_MAX_DST/4];
36704+
36705+ULONG pVideo1DecAddr[VIDEO_SOURCE_SIZE/4];
36706+ULONG pCrt1Addr[VIDEO_SOURCE_SIZE/4];
36707+//ULONG pCap1Addr[VIDEO_SOURCE_SIZE/4];
36708+
36709+BOOL AllocateEncodeBufHost(ULONG MMIOBase, int nVideo)
36710+{
36711+ //ULONG Addr;
36712+ //ULONG dwRegOffset = nVideo * 0x100;
36713+
36714+ if (VIDEO1 == nVideo)
36715+ {
36716+
36717+ //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
36718+ //pCaptureVideo1Buf1Addr = malloc(VIDEO_SOURCE_SIZE);
36719+
36720+ g_CAPTURE_VIDEO1_BUF1_ADDR = vBufAlign((ULONG)pCaptureVideo1Buf1Addr);
36721+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, g_CAPTURE_VIDEO1_BUF1_ADDR, BUF_1_ADDR_MASK);
36722+
36723+ //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
36724+ //pCaptureVideo1Buf2Addr = malloc(VIDEO_SOURCE_SIZE);
36725+
36726+ g_CAPTURE_VIDEO1_BUF2_ADDR = vBufAlign((ULONG)pCaptureVideo1Buf2Addr);
36727+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, g_CAPTURE_VIDEO1_BUF2_ADDR, BUF_2_ADDR_MASK);
36728+
36729+ //Addr = (ULONG)malloc(pVideoInfo->uStreamBufSize.StreamBufSize.RingBufNum * pVideoInfo->uStreamBufSize.StreamBufSize.PacketSize)
36730+ //pVideo1CompressBufAddr = malloc(VIDEO_MAX_STREAM_SIZE);
36731+ g_VIDEO1_COMPRESS_BUF_ADDR = vBufAlign((ULONG)pVideo1CompressBufAddr);
36732+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_ADDR_REG, g_VIDEO1_COMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
36733+
36734+ //Addr = (ULONG)malloc((pVideoInfo->SrcHeigh/64) * pVideoInfo->SrcWidth * 8);
36735+ //g_VIDEO1_CRC_BUF_ADDR = vBufAlign((ULONG)malloc(VIDEO_MAX_STREAM_SIZE));
36736+ //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, g_VIDEO1_CRC_BUF_ADDR, BUF_2_ADDR_MASK);
36737+
36738+
36739+ //Addr = (ULONG)malloc(pVideoInfo->SrcHeigh * pVideoInfo->SrcWidth / 128 (/64*4/8));
36740+ //pVideo1FlagBufAddr = malloc(VIDEO_FLAG_SIZE);
36741+ g_VIDEO1_FLAG_BUF_ADDR = vBufAlign((ULONG)pVideo1FlagBufAddr);
36742+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_FLAG_BUF_ADDR_REG, g_VIDEO1_FLAG_BUF_ADDR, BUF_2_ADDR_MASK);
36743+ }
36744+ else if (VIDEO2 == nVideo)
36745+ {
36746+ //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
36747+ //pCaptureVideo2Buf1Addr = malloc(VIDEO_SOURCE_SIZE);
36748+ g_CAPTURE_VIDEO2_BUF1_ADDR = vBufAlign((ULONG)pCaptureVideo2Buf1Addr);
36749+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_BUF_1_ADDR_REG, g_CAPTURE_VIDEO2_BUF1_ADDR, BUF_1_ADDR_MASK);
36750+
36751+ //Addr = (ULONG)malloc(pVideoInfo->SrcWidth * pVideoInfo->SrcHeight * 4);
36752+ //pCaptureVideo2Buf2Addr = malloc(VIDEO_SOURCE_SIZE);
36753+ g_CAPTURE_VIDEO2_BUF2_ADDR = vBufAlign((ULONG)pCaptureVideo2Buf2Addr);
36754+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_BUF_2_ADDR_REG, g_CAPTURE_VIDEO2_BUF2_ADDR, BUF_2_ADDR_MASK);
36755+
36756+ //Addr = (ULONG)malloc(pVideoInfo->uStreamBufSize.StreamBufSize.RingBufNum * pVideoInfo->uStreamBufSize.StreamBufSize.PacketSize)
36757+ //pVideo2CompressBufAddr = malloc(VIDEO_MAX_STREAM_SIZE);
36758+ g_VIDEO2_COMPRESS_BUF_ADDR = vBufAlign((ULONG)pVideo2CompressBufAddr);
36759+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_COMPRESS_BUF_ADDR_REG, g_VIDEO2_COMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
36760+
36761+ //Addr = (ULONG)malloc((pVideoInfo->SrcHeigh/64) * pVideoInfo->SrcWidth * 8);
36762+ //g_VIDEO1_CRC_BUF_ADDR = vBufAlign((ULONG)malloc(VIDEO_MAX_STREAM_SIZE));
36763+ //WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, g_VIDEO1_CRC_BUF_ADDR, BUF_2_ADDR_MASK);
36764+
36765+
36766+ //Addr = (ULONG)malloc(pVideoInfo->SrcHeigh * pVideoInfo->SrcWidth / 128 (/64*4/8));
36767+ //pVideo2FlagBufAddr = malloc(VIDEO_FLAG_SIZE);
36768+ g_VIDEO2_FLAG_BUF_ADDR = vBufAlign((ULONG)pVideo2FlagBufAddr);
36769+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO2_FLAG_BUF_ADDR_REG, g_VIDEO2_FLAG_BUF_ADDR, BUF_2_ADDR_MASK);
36770+ }
36771+
36772+}
36773+
36774+/********************************************************/
36775+/* 1. product random data to encode */
36776+/* 2. use hash to verify encode function */
36777+/* 3. use encode stream to decompress original data */
36778+/********************************************************/
36779+int CodecTest(void)
36780+{
36781+ int num, i=0, j=0;
36782+ ULONG ulTemp = 0, ulTemp2;
36783+ int dwValue;
36784+ ULONG ulHWWp;
36785+ ULONG ulHWPt;
36786+
36787+ //max size
36788+ ULONG tArray[32/4];
36789+
36790+ //mode detection
36791+ BOOL bExternal = TRUE;
36792+ BOOL bAnalog = TRUE;
36793+ ULONG Status;
36794+
36795+#if defined(CONFIG_AST2300)
36796+ ULONG ulHashSha1[5] = {0x3f0c2ad6,0xc8eb7074,0xa9929352,0xfcd5b8b0,0x76fa8461};
36797+ ULONG aHashDecode[5] = {0xb23b62bb,0xd22a602b,0x113038a0,0x7217c6ab,0xcb156f06};
36798+#else
36799+ ULONG ulHashSha1[5] = {0x2a19e99f,0x99b1bb2d,0x9ac82862,0x49205e43,0x6bc4b4d7};
36800+ ULONG aHashDecode[5] = {0x2907a827,0xaf337079,0x47817f1f,0xb0b7cd68,0x8d33bd2};
36801+#endif
36802+
36803+ //Load pattern to src1 & src2 buffer
36804+ srand(1);
36805+
36806+ //Total size : DefWidth*DeHeight*4
36807+ //rand function: 16 bits one time is equal to 2 bytes
36808+ //OutdwmBankMode: 32 bits one time is equal to 4 bytes
36809+ for (i=0; i<g_DefWidth*g_DefHeight*2; i++)
36810+ {
36811+ if (i%2)
36812+ {
36813+ ulTemp2 = rand();
36814+ ulTemp = (ulTemp2 << 16) | ulTemp;
36815+ //WriteMemoryLongHost(DRAM_BASE, g_CAPTURE_VIDEO1_BUF1_ADDR + ((i-1)/2)*4, ulTemp);
36816+ *(((ULONG *)g_CAPTURE_VIDEO1_BUF1_ADDR) + (i-1)/2) = ulTemp;
36817+ ulTemp = 0;
36818+ }
36819+ else
36820+ {
36821+ ulTemp = rand();
36822+ }
36823+ }
36824+
36825+ /* init encoder engine */
36826+ InitializeVideoEngineHost (0,
36827+ VIDEO1,
36828+ vModeTable[2].HorPolarity,
36829+ vModeTable[2].VerPolarity);
36830+
36831+ /* reset offset pointer register*/
36832+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, VIDEO_CODEC_TRIGGER | VIDEO_CAPTURE_TRIGGER);
36833+
36834+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_READ_OFFSET_REG, 0, COMPRESS_BUF_READ_OFFSET_MASK);
36835+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ, 0, BUF_CODEC_OFFSET_MASK);
36836+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG, 0, COMPRESS_BUF_PROCESS_OFFSET_MASK);
36837+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_FRAME_END_READ, 0, COMPRESS_FRAME_END_READ_MASK);
36838+
36839+ /* start compress stream */
36840+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, MODE_DETECTION_TRIGGER, MODE_DETECTION_TRIGGER);
36841+ //Stream mode: set CODEC trigger first
36842+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, VIDEO_CODEC_TRIGGER, VIDEO_CODEC_TRIGGER);
36843+
36844+ //Stream mode: start trigger (only trigger capture bit)
36845+ StartVideoCaptureTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
36846+
36847+ //stop engine
36848+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, 0xFF);
36849+#if defined(CONFIG_AST2300)
36850+ do { /* wait compress engine idle */
36851+ ulTemp = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
36852+ } while (!(ulTemp & 0x40000));
36853+#endif
36854+
36855+ //read 30 times to get HW write pointer
36856+ for (i=0; i<30000; i++)
36857+ ulHWWp = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ);
36858+
36859+ g_HashSrcBuffer = g_VIDEO1_COMPRESS_BUF_ADDR + 128; //skip encode data 128 byte
36860+ g_HashDstBuffer = v16byteAlign((unsigned long)pVHashDstBuffer);
36861+ ulTemp = 300;
36862+
36863+ //Enable hash clock
36864+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_HACE, STOP_HACE_MASK);
36865+ g_HashMethod.HashMode = VHASHMODE_SHA1;
36866+ g_HashMethod.DigestLen = 20;
36867+ HashAst3000(ulTemp, tArray, g_HashMethod.HashMode);
36868+
36869+ if (strncmp((const char *)tArray, (const char *)ulHashSha1, g_HashMethod.DigestLen))
36870+ {
36871+ printf("[VIDEO] Encoder Test: Wrong\n");
36872+ //ExitVideoTest();
36873+ return VIDEO_ENCODE_FAIL;
36874+ }
36875+ else
36876+ {
36877+ printf("[VIDEO] Encoder Test: Pass\n");
36878+ }
36879+
36880+#if 0
36881+ /******** prepare for next decoding test at the same chip ***********/
36882+ ResetVideoHost();
36883+
36884+ dwValue=0;
36885+
36886+ do
36887+ {
36888+ dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
36889+ i++;
36890+ }
36891+ while ((VIDEO_UNLOCK != dwValue) && (i<10));
36892+
36893+ if (VIDEO_UNLOCK != dwValue)
36894+ {
36895+ printf("[VIDEO] Video register is locked");
36896+ return VIDEO_UNLOCK_FAIL;
36897+ }
36898+
36899+ // allocate decoding buffer
36900+ //Use Compress buffer last time, and Don't need to allocate
36901+ g_VIDEO1_DECODE_BUF_1_ADDR = g_VIDEO1_COMPRESS_BUF_ADDR;
36902+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, g_VIDEO1_DECODE_BUF_1_ADDR, BUF_1_ADDR_MASK);
36903+
36904+ // pVideo1DecAddr = malloc(VIDEO_SOURCE_SIZE);
36905+ g_VIDEO1_DECOMPRESS_BUF_ADDR = vBufAlign((unsigned long)pVideo1DecAddr);
36906+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_ADDR_REG, g_VIDEO1_DECOMPRESS_BUF_ADDR, COMPRESS_BUF_ADDR_MASK);
36907+
36908+ //Addr = (ULONG)malloc(256);
36909+ //g_VIDEO1_RC4_BUF_ADDR = Addr;
36910+ //g_VIDEO1_DECODE_RC4_BUF_ADDR = g_VIDEO1_DECOMPRESS_BUF_ADDR + 0x800000; //assume video size is 8MB for umcompressed buf;
36911+ //WriteMemoryLongWithMASKClient(VIDEO_REG_BASE, VIDEO1_RC4_TABLE_ADDR, g_VIDEO1_DECODE_RC4_BUF_ADDR, RC4_TABLE_ADDR_MASK);
36912+
36913+ //HW recommanded value
36914+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, g_VIDEO1_DECOMPRESS_BUF_ADDR, BUF_2_ADDR_MASK);
36915+ //WriteMemoryLongWithMASKClient(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, 0, BUF_2_ADDR_MASK);
36916+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CRC_BUF_ADDR_REG, 0, BUF_2_ADDR_MASK);
36917+
36918+ /* init encoder engine */
36919+ InitializeVideoEngineClient (0, VIDEO1);
36920+
36921+ /* reset offset pointer register*/
36922+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, 0, VIDEO_CODEC_TRIGGER | VIDEO_CAPTURE_TRIGGER);
36923+
36924+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_READ_OFFSET_REG, 0, COMPRESS_BUF_READ_OFFSET_MASK);
36925+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ, 0, BUF_CODEC_OFFSET_MASK);
36926+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG, 0, COMPRESS_BUF_PROCESS_OFFSET_MASK);
36927+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_COMPRESS_FRAME_END_READ, 0, COMPRESS_FRAME_END_READ_MASK);
36928+
36929+ StartVideoCodecTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
36930+
36931+ //wrtie SW write pointer
36932+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_DECOMPRESS_BUF_PROCESS_OFFSET_REG, ulHWWp, COMPRESS_BUF_READ_OFFSET_MASK);
36933+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_DECOMPRESS_BUF_WRITE_OFFSET_REG, ulHWWp, COMPRESS_BUF_READ_OFFSET_MASK);
36934+
36935+ i = 0;
36936+
36937+ do
36938+ {
36939+ ulHWPt = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_BUF_CODEC_OFFSET_READ);
36940+ i++;
36941+ }while((ulHWPt != ulHWWp) && (i<10000));
36942+
36943+ if (10000 > i)
36944+ {
36945+ printf("[VIDEO] Decoder Pointer cannot move!!! /n");
36946+ //ExitVideoTest();
36947+ return VIDEO_DECODE_FAIL;
36948+ }
36949+
36950+ //8*8 YUVA block
36951+ for (i=24; i<g_DefWidth*g_DefHeight; i=i+32)
36952+ {
36953+ *(((ULONG *)g_VIDEO1_DECOMPRESS_BUF_ADDR) + i) = 0x0;
36954+ *(((ULONG *)g_VIDEO1_DECOMPRESS_BUF_ADDR) + i+1) = 0x0;
36955+ }
36956+
36957+ g_HashSrcBuffer = g_VIDEO1_DECOMPRESS_BUF_ADDR;
36958+ //g_HashDstBuffer = VIDEO1_EN_BASE + VIDEO_ALL_SIZE; //config forward
36959+
36960+ ulTemp = 300;
36961+
36962+ //Enable hash clock
36963+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, EN_HACE, STOP_HACE_MASK);
36964+ g_HashMethod.HashMode = VHASHMODE_SHA1;
36965+ g_HashMethod.DigestLen = 20;
36966+ HashAst3000(ulTemp, tArray, g_HashMethod.HashMode);
36967+
36968+ if (strncmp((const char *)tArray, (const char *)aHashDecode, g_HashMethod.DigestLen))
36969+ {
36970+ printf("[VIDEO] Decoder Test: Wrong\n");
36971+ //ExitVideoTest();
36972+ return VIDEO_DECODE_FAIL;
36973+ }
36974+ else
36975+ {
36976+ printf("[VIDEO] Decoder Test: Pass\n");
36977+ }
36978+#endif
36979+
36980+ return VIDEO_TEST_OK;
36981+}
36982+
36983+/********************************************************/
36984+/* Only used in the host */
36985+/* test function: Mode detection and Capture pattern */
36986+/********************************************************/
36987+int CapTest(void)
36988+{
36989+ ULONG dwValue, Status;
36990+ int i;
36991+ BOOL bAnalog;
36992+ ULONG HStart, HEnd, VStart, VEnd;
36993+ USHORT usCRTHor, usCRTVer;
36994+ ULONG ulHor, ulVer;
36995+ ULONG ulVGABaseAddr, ulCapAddr;
36996+ ULONG ulFlag;
36997+
36998+ printf("\n --------- Mode Detection Test --------- \n");
36999+ //clear clear register
37000+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG, 0);
37001+ dwValue = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG);
37002+
37003+ // Note: Current mode detection procedure has to set signal input 1st
37004+ //Note: Clear and enable interrupt Encode
37005+ ClearVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_CLEAR);
37006+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_INT_CONTROL_EN_REG, VIDEO1_MODE_DETECTION_READY_INT_EN, VIDEO1_MODE_DETECTION_READY_INT_EN);
37007+ // Set input signal
37008+ dwValue |= EXTERNAL_VGA_SOURCE;
37009+
37010+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_CONTROL_REG, (dwValue <<EXTERNAL_SOURCE_BIT), EXTERNAL_SOURCE_MASK);
37011+
37012+// Set H/V stable maximum
37013+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_VERTICAL_STABLE_MAXIMUM << VER_STABLE_MAX_BIT), 0x000F0000);
37014+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_HORIZONTAL_STABLE_MAXIMUM << HOR_STABLE_MAX_BIT), HOR_STABLE_MAX_BIT_MASK);
37015+// Set H/V stable threshold
37016+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_VERTICAL_STABLE_THRESHOLD << VER_STABLE_THRES_BIT), VER_STABLE_THRES_BIT_MASK);
37017+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO_MODE_DETECTION_PARAM_REG, (MODEDETECTION_HORIZONTAL_STABLE_THRESHOLD << HOR_STABLE_THRES_BIT), HOR_STABLE_THRES_BIT_MASK);
37018+
37019+ //Trigger mode detection
37020+ // turn off WATCH_DOG first
37021+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, (WATCH_DOG_OFF << WATCH_DOG_ENABLE_BIT), WATCH_DOG_EN_MASK);
37022+
37023+ // Note: Clear mode detection ready interrupt
37024+ //ClearVideoInterrupt(MMIOBase, MODE_DETECTION_READY_CLEAR);
37025+ StartModeDetectionTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
37026+
37027+
37028+// Note: Polling mode detection ready interrupt
37029+ //it sometime take a long time, especially during change mode,
37030+ //so the loop count must be big, or you can't pull it by timer
37031+ i = 0;
37032+ do {
37033+
37034+ Status = ReadVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_READ);
37035+ i++;
37036+ } while ((!Status) & (i<500000));
37037+
37038+ if (!Status)
37039+ {
37040+ printf("[VIDEO] Mode detection error\n");
37041+ //ExitVideoTest();
37042+ return VIDEO_TEST_FAIL;
37043+ }
37044+
37045+ HStart = (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_H_REG) & LEFT_EDGE_LOCATION_MASK) >> LEFT_EDGE_LOCATION_BIT;
37046+ HEnd = (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_H_REG) & RIGHT_EDGE_LOCATION_MASK) >> RIGHT_EDGE_LOCATION_BIT;
37047+
37048+ VStart = (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_V_REG) & TOP_EDGE_LOCATION_MASK) >> TOP_EDGE_LOCATION_BIT;
37049+ VEnd = (ReadMemoryLongHost(VIDEO_REG_BASE, VIDE1_MODE_DETECTION_EDGE_V_REG) & BOTTOM_EDGE_LOCATION_MASK) >> BOTTOM_EDGE_LOCATION_BIT;
37050+
37051+ ulHor = HEnd-HStart+1;
37052+ ulVer = VEnd-VStart+1;
37053+
37054+ printf("[VIDEO] Resolution: H[%d] * V[%d]\n", ulHor, ulVer);
37055+
37056+ if ((g_DefWidth == ulHor) & (g_DefHeight == ulVer))
37057+ {
37058+ printf("[VIDEO] Mode detection PASS\n");
37059+ }
37060+ else
37061+ {
37062+ printf("[VIDEO] Mode detection FAIL\n");
37063+ return VIDEO_TEST_FAIL;
37064+ }
37065+
37066+ if(!((ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_MODE_DETECTION_STATUS_READ_REG) & ANALONG_DIGITAL_READ) >> ANALONG_DIGITAL_READ_BIT))
37067+ bAnalog = FALSE;
37068+ else
37069+ bAnalog = TRUE;
37070+
37071+ // Note: Clear mode detection ready interrupt
37072+ ClearVideoInterruptHost(0, VIDEO1_MODE_DETECTION_READY_CLEAR);
37073+
37074+ printf("\n --------- Capture Test --------- \n");
37075+
37076+ //capture engine
37077+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, (HEnd << VIDEO_HDE_END_BIT), VIDEO_HDE_END_MASK);
37078+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, (HStart << VIDEO_HDE_START_BIT), VIDEO_HDE_START_MASK);
37079+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_V_REG, (VEnd << VIDEO_VDE_END_BIT), VIDEO_VDE_END_MASK);
37080+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_V_REG, (VStart << VIDEO_VDE_START_BIT), VIDEO_VDE_START_MASK);
37081+
37082+ ulCapAddr = vBufAlign2((ULONG)pCaptureVideo1Buf1Addr);
37083+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_1_ADDR_REG, ulCapAddr, BUF_1_ADDR_MASK);
37084+
37085+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_BUF_2_ADDR_REG, 0, BUF_2_ADDR_MASK);
37086+
37087+ InitializeVideoEngineHost (0,
37088+ VIDEO1,
37089+ vModeTable[2].HorPolarity,
37090+ vModeTable[2].VerPolarity);
37091+
37092+ WriteMemoryLongHost(VIDEO_REG_BASE, 0x04, 0x01);
37093+ WriteMemoryLongHost(VIDEO_REG_BASE, 0x300, 0x0);
37094+#if defined(CONFIG_AST2300)
37095+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0x0880, 0x0ec0);
37096+#elif defined(CONFIG_AST3000)
37097+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0x2800, 0x2800);
37098+#else
37099+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, 0x8, 0xa00, 0x2a80); //tile mode
37100+#endif
37101+
37102+ WriteMemoryLongWithMASKHost(VIDEO_REG_BASE, VIDEO1_TIMEING_GEN_HOR_REG, 0xa0000000, 0xa0000000);
37103+
37104+ //only trigger capture, in source buffer (vr44), the front of data is correct.
37105+ //StartVideoCaptureTriggerHost(0, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG);
37106+ WriteMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG, VIDEO_CAPTURE_TRIGGER);
37107+
37108+ i = 0;
37109+ do {
37110+ Status = ReadMemoryLongHost(VIDEO_REG_BASE, VIDEO1_ENGINE_SEQUENCE_CONTROL_REG) & CAPTURE_READY_MASK;
37111+ i++;
37112+ } while ((!Status) & (i<500000));
37113+
37114+ if (!Status)
37115+ {
37116+ printf("[VIDEO] Capture is not READY\n");
37117+ return VIDEO_TEST_FAIL;
37118+ }
37119+
37120+#if !defined(CONFIG_AST2300)
37121+ ulVGABaseAddr = ulCapAddr + 0x1000;
37122+
37123+ /* check pattern */
37124+ ulFlag = 0; //no 0 is error
37125+
37126+ for (i=0; i<100; i++)
37127+ {
37128+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32);
37129+ if (0x32323232 != dwValue)
37130+ {
37131+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
37132+ printf("[VIDEO]1 i=%d value=%x\n", i, dwValue);
37133+ ulFlag = 1;
37134+ break;
37135+ }
37136+
37137+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 4);
37138+ if (0x32323232 != dwValue)
37139+ {
37140+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
37141+ printf("[VIDEO]2 i=%d value=%x\n", i, dwValue);
37142+ ulFlag = 1;
37143+ break;
37144+ }
37145+
37146+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 8);
37147+ if (0x80808080 != dwValue)
37148+ {
37149+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
37150+ printf("[VIDEO]3 i=%d value=%x\n", i, dwValue);
37151+ ulFlag = 1;
37152+ break;
37153+ }
37154+
37155+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 12);
37156+ if (0x80808080 != dwValue)
37157+ {
37158+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
37159+ printf("4 i=%d value=%x\n", i, dwValue);
37160+ ulFlag = 1;
37161+ break;
37162+ }
37163+
37164+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 16);
37165+ if (0x80808080 != dwValue)
37166+ {
37167+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
37168+ printf("5 i=%d value=%x\n", i, dwValue);
37169+ ulFlag = 1;
37170+ break;
37171+ }
37172+
37173+ dwValue = *(ULONG *)(ulVGABaseAddr + i*32 + 20);
37174+ if (0x80808080 != dwValue)
37175+ {
37176+ printf("[VIDEO] Capture Test fail -- capture data doesn't match source \n");
37177+ printf("6 i=%d value=%x\n", i, dwValue);
37178+ ulFlag = 1;
37179+ break;
37180+ }
37181+ }
37182+#endif
37183+
37184+ if (!ulFlag)
37185+ {
37186+ printf("[VIDEO] Capture Test OK\n");
37187+ }
37188+ else
37189+ {
37190+ printf("[VIDEO] Capture Test FAIL\n");
37191+ return VIDEO_TEST_FAIL;
37192+ }
37193+
37194+ return VIDEO_TEST_OK;
37195+}
37196+
37197+/********************************************************/
37198+/* Only used in the station */
37199+/********************************************************/
37200+int CRTTest(void)
37201+{
37202+ ULONG ulVGABaseAddr;
37203+ BYTE btCRTCenterMode, btCRTColorFmt;
37204+ USHORT usCRTHor, usCRTVer;
37205+ ULONG ulData;
37206+
37207+ int i,j;
37208+
37209+ //printf("\n --------- Turn on CRT --------- \n");
37210+
37211+ //Enable CRT1 first
37212+ ulVGABaseAddr = vBufAlign((unsigned long)pCrt1Addr);
37213+
37214+ btCRTCenterMode = 0;
37215+ btCRTColorFmt = YUV_444;
37216+ usCRTHor = g_DefWidth;
37217+ usCRTVer = g_DefHeight;
37218+
37219+ CheckOnStartClient();
37220+
37221+ /* Fill Pattern */
37222+ for (i=0; i<usCRTHor; i++)
37223+ {
37224+ for (j=0; j<usCRTVer/8; j++)
37225+ {
37226+ //Y
37227+ //ulData = 0x10101010;
37228+ ulData = 0x32323232;
37229+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32)) = ulData;
37230+ //ulData = 0x10101010;
37231+ ulData = 0x32323232;
37232+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +4) = ulData;
37233+ //U
37234+ ulData = 0x80808080;
37235+ //ulData = 0x77777777;
37236+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +8) = ulData;
37237+ ulData = 0x80808080;
37238+ //ulData = 0x77777777;
37239+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +12) = ulData;
37240+ //V
37241+ ulData = 0x80808080;
37242+ //ulData = 0x11111111;
37243+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +16) = ulData;
37244+ ulData = 0x80808080;
37245+ //ulData = 0x11111111;
37246+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +20) = ulData;
37247+ //A
37248+ ulData = 0xFFFFFFFFF;
37249+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +24) = ulData;
37250+ ulData = 0xFFFFFFFFF;
37251+ *(ULONG *)(ulVGABaseAddr + (i*usCRTVer*4+j*32) +28) = ulData;
37252+ }
37253+ } /* ~Fill Pattern */
37254+
37255+#if defined(CONFIG_AST2300)
37256+ if(!ASTSetModeV (0, CRT_2, ulVGABaseAddr, usCRTHor, usCRTVer, btCRTColorFmt, btCRTCenterMode))
37257+#else
37258+ if(!ASTSetModeV (0, CRT_1, ulVGABaseAddr, usCRTHor, usCRTVer, btCRTColorFmt, btCRTCenterMode))
37259+#endif
37260+ {
37261+ printf("[VIDEO] The resolution is not in mode table list\n");
37262+ return CRT_FAIL;
37263+ }
37264+
37265+ //printf("[VIDEO] CRT turn on\n");
37266+
37267+ return VIDEO_TEST_OK;
37268+}
37269+
37270+int do_videotest (void)
37271+{
37272+ int dwValue=0;
37273+ int i = 0;
37274+ int iRet;
37275+ ULONG ulRestore1, ulTemp;
37276+ BOOL bClient;
37277+
37278+
37279+ //InitVideoTest();
37280+ g_DefWidth = 640;
37281+ g_DefHeight= 480;
37282+
37283+ printf("\n --------- Codec Test --------- \n");
37284+
37285+#if defined(CONFIG_AST2300)
37286+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, 0x00002000, 0x00002000);
37287+#endif
37288+
37289+ CheckOnStartHost();
37290+
37291+ do
37292+ {
37293+ dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
37294+ i++;
37295+ }
37296+ while ((VIDEO_UNLOCK != dwValue) && (i<1000));
37297+
37298+ if (VIDEO_UNLOCK != dwValue)
37299+ {
37300+ printf("[VIDEO] Video register is locked \n");
37301+ return VIDEO_TEST_FAIL;
37302+ }
37303+ AllocateEncodeBufHost(0, VIDEO1);
37304+
37305+ iRet = CodecTest();
37306+ if (iRet)
37307+ return VIDEO_TEST_FAIL;
37308+
37309+#if defined(CONFIG_AST2300)
37310+ /* Init SCU */
37311+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x2c + SCU_OFFSET), 0x00040000, 0x00040010); /* Enable D2-PLL */
37312+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CLOCK_STOP_REG, 0, 0x00000400); /* Enable D2CLK */
37313+ udelay(10);
37314+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_CONTROL_REG, 0, 0x00002000);
37315+
37316+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x90 + SCU_OFFSET), 0x20, 0x00000030); /* enable video mode single edge */
37317+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x84 + SCU_OFFSET), 0xfffe0000, 0xfffe0000); /* multi-pins */
37318+ WriteMemoryLongWithMASKHost(SCU_BASE, (0x88 + SCU_OFFSET), 0x000fffff, 0x000fffff); /* multi-pins */
37319+
37320+ iRet = CRTTest();
37321+ if (iRet)
37322+ {
37323+ printf("[VIDEO] CRT Test Failed \n");
37324+ return VIDEO_TEST_FAIL;
37325+ }
37326+
37327+ iRet = CapTest();
37328+ if (iRet)
37329+ {
37330+ printf("[VIDEO] Capture Test Failed \n");
37331+ return VIDEO_TEST_FAIL;
37332+ }
37333+#else
37334+ //Host or Client
37335+ bClient = ((ReadMemoryLong(SCU_BASE, SCU_HW_TRAPPING_REG) & CLIENT_MODE_EN_MASK)?TRUE:FALSE);
37336+ //reset video for another testing
37337+ ResetVideoHost();
37338+ dwValue=0;
37339+ i = 0;
37340+ do
37341+ {
37342+ dwValue = UnlockVideoRegHost(0, VIDEO_UNLOCK_KEY);
37343+ i++;
37344+ }
37345+ while ((VIDEO_UNLOCK != dwValue) && (i<10));
37346+
37347+ if (VIDEO_UNLOCK != dwValue)
37348+ {
37349+ printf("[VIDEO] Video register is locked");
37350+ return VIDEO_UNLOCK_FAIL;
37351+ }
37352+
37353+ //check if 1e6e0008[3,0] is 0
37354+ ulRestore1 = ReadMemoryLongHost(0x1e6e0000, 8);
37355+ dwValue = ReadMemoryLongHost(0x1e6e0000, 8)&0xF;
37356+
37357+ //set 1e6e0008[3,0] to 0
37358+ if (dwValue)
37359+ {
37360+ WriteMemoryLongHost(0x1e6e0000, 0, 0xfc600309);
37361+
37362+ i=0;
37363+ do
37364+ {
37365+ i++;
37366+ dwValue = ReadMemoryLongHost(0x1e6e0000,0);
37367+ }while((1 != dwValue)&& (i<10));
37368+
37369+ if (1 != dwValue)
37370+ {
37371+ printf("0x1e6e0000 is locked");
37372+ return VIDEO_UNLOCK_FAIL;
37373+ }
37374+ }
37375+
37376+ //only clear 1e6e0008[3,0]
37377+ WriteMemoryLongWithMASKHost(0x1e6e0000, 8, 0, 0xf);
37378+
37379+ bClient = 0;
37380+ if (!bClient)
37381+ {
37382+ //To turn on crt, must be the client mode
37383+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_CLIENT_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
37384+
37385+ iRet = CRTTest();
37386+
37387+ if (iRet)
37388+ {
37389+ //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
37390+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
37391+ //restore value
37392+ WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
37393+ //lock register
37394+ WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678);
37395+ return VIDEO_TEST_FAIL;
37396+ }
37397+
37398+ iRet = CapTest();
37399+
37400+ if (iRet)
37401+ {
37402+ //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
37403+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
37404+ //restore value
37405+ WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
37406+ //lock register
37407+ WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678);
37408+
37409+ return VIDEO_TEST_FAIL;
37410+ }
37411+ //WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
37412+ }
37413+ //trapping to host, the Vsync of CRT can't output and the host doesn't have video sync input
37414+ WriteMemoryLongWithMASKHost(SCU_BASE, SCU_HW_TRAPPING_REG, (BE_HOST_CHIP << CLIENT_MODE_EN_BIT), CLIENT_MODE_EN_MASK);
37415+ //restore value
37416+ WriteMemoryLongHost(0x1e6e0000, 8, ulRestore1);
37417+ //lock register
37418+ WriteMemoryLongHost(0x1e6e0000, 0, 0x12345678);
37419+#endif
37420+
37421+ return VIDEO_TEST_OK;
37422+}
37423+#endif /* CONFIG_SLT */
37424diff --git a/board/aspeed/ast2400/videotest.h b/board/aspeed/ast2400/videotest.h
37425new file mode 100755
37426index 0000000..79b8dd9
37427--- /dev/null
37428+++ b/board/aspeed/ast2400/videotest.h
37429@@ -0,0 +1,24 @@
37430+/*
37431+ * This program is distributed in the hope that it will be useful,
37432+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
37433+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37434+ * GNU General Public License for more details.
37435+ *
37436+ * You should have received a copy of the GNU General Public License
37437+ * along with this program; if not, write to the Free Software
37438+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37439+ */
37440+/* VideoTest.h */
37441+#ifndef _VIDEOTEST_H_
37442+#define _VIDEOTEST_H_
37443+
37444+#define VIDEO_TEST_OK 0
37445+#define VIDEO_TEST_FAIL 1
37446+
37447+#define VIDEO_UNLOCK_FAIL 1
37448+#define VIDEO_ENCODE_FAIL 2
37449+#define VIDEO_DECODE_FAIL 3
37450+#define CRT_FAIL 4
37451+
37452+#endif /* _VIDEOTEST_H_ */
37453+
37454diff --git a/board/aspeed/ast2400/vreg.h b/board/aspeed/ast2400/vreg.h
37455new file mode 100755
37456index 0000000..9738548
37457--- /dev/null
37458+++ b/board/aspeed/ast2400/vreg.h
37459@@ -0,0 +1,845 @@
37460+/*
37461+ * This program is distributed in the hope that it will be useful,
37462+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
37463+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37464+ * GNU General Public License for more details.
37465+ *
37466+ * You should have received a copy of the GNU General Public License
37467+ * along with this program; if not, write to the Free Software
37468+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37469+ */
37470+#ifndef _VREG_H_
37471+#define _VREG_H_
37472+
37473+/********************************************************/
37474+/* CRT register */
37475+/********************************************************/
37476+#define CRT_BASE_ADDRESS 0x000400
37477+#define VGA_GRAPH_BASE_ADDRESS 0x600000
37478+#define VGA_CURSOR_BASE_ADDRESS 0x300000
37479+#define VGA_OSD_BASE_ADDRESS 0x300000
37480+#define RGB_565 0x0
37481+#define RGB_888 0x1
37482+#define YUV_444 0x2
37483+#define NO_SUPPORTED_CRT_FMT 0x3
37484+#define CRT_LOW_THRESHOLD_VALUE 0x12
37485+#define CRT_HIGH_THRESHOLD_VALUE 0x1E
37486+
37487+// AST3000's Registers
37488+#ifdef Watcom
37489+#define VIDEOBASE_OFFSET 0x10000
37490+#else
37491+#define VIDEOBASE_OFFSET 0x0
37492+#endif
37493+
37494+#define KEY_CONTROL_REG 0x00 + VIDEOBASE_OFFSET
37495+ #define VIDEO_LOCKED 0
37496+ #define VIDEO_UNLOCK 1
37497+
37498+// Registers for video1 and video2
37499+#define VIDEO1_ENGINE_SEQUENCE_CONTROL_REG 0x04 + VIDEOBASE_OFFSET
37500+#define VIDEO2_ENGINE_SEQUENCE_CONTROL_REG 0x104 + VIDEOBASE_OFFSET
37501+ #define MODE_DETECTION_TRIGGER 0x00000001 //Bit[0] trigger HW auto mode detection
37502+ #define VIDEO_CAPTURE_TRIGGER 0x00000002 //Bit[1] trigger HW to capture video
37503+ #define FORCE_HW_IDLE_MASK (1<<2) //Bit[2] Force engine into ready(idle) state
37504+ #define ENGINE_RESET (0<<2)
37505+ #define ENGINE_IDLE (1<<2)
37506+ #define VIDEO_CAPTURE_AUTO_MODE 0x00000008 //Bit[3]
37507+ #define CAPTURE_FRAME_MODE 0
37508+ #define CAPTURE_AUTO_MODE 1
37509+ #define CAPTURE_AUTO_MODE_BIT 3
37510+ #define CAPTURE_AUTO_MODE_MASK 0x00000008
37511+ #define VIDEO_CODEC_TRIGGER 0x00000010 //Bit[4] trigger HW to compress or decompress video
37512+ #define CODEC_TRIGGER_BIT 4
37513+ #define CODEC_TRIGGER_MASK 0x00000010
37514+ #define CLEAR_CODEC_TRIGGER 0
37515+ #define EN_CODEC_TRIGGER 1
37516+ #define VIDEO_CODEC_AUTO_MODE 0x00000020 //Bit[5]
37517+ #define CODEC_FRAME_MODE 0
37518+ #define CODEC_AUTO_MODE 1
37519+ #define CODEC_AUTO_MODE_BIT 5
37520+ #define CODEC_AUTO_MODE_MASK 0x00000020
37521+ #define INSERT_FULL_FRAME_MASK (1<<6) //Bit[6] Insert full frame compression
37522+ #define INSERT_FULL_FRAME_EN (1<<6)
37523+ #define INSERT_FULL_FRAME_OFF (0<<6)
37524+ #define WATCH_DOG_ENABLE 0x00000080 //Bit[7] Video Enable watch dog for mode change detection
37525+ #define WATCH_DOG_ENABLE_BIT 7
37526+ #define WATCH_DOG_OFF 0
37527+ #define WATCH_DOG_EN 1
37528+ #define WATCH_DOG_EN_MASK 0x00000080
37529+ #define VIDEO_CRT_SELECTION 0x00000100 //Bit[8]
37530+ #define CRT1 0
37531+ #define CRT2 1
37532+ #define ANTI_TEARING_ENABLE 0x00000200 //Bit[9] Anti-tearing mode enable for decoding
37533+ #define ANTI_TEARING_EN 1
37534+ #define STREAM_DATA_MODE 0x00000400 //Bit[11:10] Buffer and Stream Data type
37535+ #define STREAM_DATA_MODE_BIT 10
37536+ #define STREAM_DATA_MODE_MASK 0x00000C00
37537+ #define YUV444_MODE 0
37538+ #define YUV420_MODE 1
37539+ #define YUV420_MODE_WITH_AST2000 2 //AST2000 compatible
37540+ #define VIDEO_CAPTURE_READY 0x00010000 //Bit[16] Video capture ready status read back(read only)
37541+ #define CAPTURE_READY_MASK 0x00010000
37542+ #define HW_BUSY 0
37543+ #define HW_IDLE 1
37544+ #define VIDEO_CODEC_READY 0x00040000 //Bit[18] Video codec ready status read back(read only)
37545+ #define CODEC_READY_MASK 0x00040000
37546+ //#define HW_BUSY 0
37547+ //#define HW_IDLE 1
37548+
37549+#define VIDEO1_CONTROL_REG 0x08 + VIDEOBASE_OFFSET
37550+#define VIDEO2_CONTROL_REG 0x108 + VIDEOBASE_OFFSET
37551+ #define VIDEO_HSYNC_POLARITY 0x00000001 //Bit[0] Video source hsync polarity
37552+ #define VIDEO_HSYNC_POLARITY_BIT 0
37553+ #define NO_INVERSE_POL 0
37554+ #define INVERSE_POL 1
37555+ #define VIDEO_VSYNC_POLARITY 0x00000002 //Bit[1] Video source vsync polarity
37556+ #define VIDEO_VSYNC_POLARITY_BIT 1
37557+ //Setting defination the same as VIDEO_HSYNC_POLARITY
37558+ #define VIDEO_EXTERNAL_SOURCE 0x00000004 //Bit[2] Video external source
37559+ #define EXTERNAL_SOURCE_BIT 2
37560+ #define INTERNAL_VGA_SOURCE 0
37561+ #define EXTERNAL_VGA_SOURCE 1
37562+ #define EXTERNAL_SOURCE_MASK 0x00000004
37563+ #define VIDEO_ANALONG_EXTERNAL_SOURCE 0x00000008 //Bit[3] Video Analog external source
37564+ #define ANALONG_EXTERNAL_SOURCE_BIT 3
37565+ #define DVI_SOURCE 0
37566+ #define ANALOG_RGB_SOURCE 1
37567+ #define VIDEO_INTERNAL_TIMING_GEN 0x00000010 //Bit[4] Video Use internal timing generator
37568+ #define INTERNAL_TIMING_GEN_BIT 4
37569+ #define EXTERNAL_DE_SIGNAL 0 //DVI only
37570+ #define VR0C_VR10_DE_SINGAL 1 //use VR0C and VR10 for generate VDE signal
37571+ /****** Video2 Only from DAC ******/
37572+ #define VIDEO1_CAPTURE_FROM 0x00000020 //Bit[5] Video1 capture data direct from VGA frame buffer(internal VGA only)
37573+ #define FROM_DAC_PORT 0
37574+ #define FROM_FRAME_BUFFER 1
37575+ #define WRITE_DATA_FORMAT 0x00000040 //Bit[7:6] Write data format
37576+ #define WRITE_DATA_FORMAT_BIT 6
37577+ #define WRTIE_DATA_FORMAT_MASK 0x000000C0
37578+ #define CCIR601_2_YUV_FORMAT 0
37579+ #define FULL_YUV_FORMAT 1
37580+ #define RGB_FORMAT 2
37581+ #define VGA_CURSOR_DISABLE 0x00000100 //Bit[8] External video port slection
37582+ #define VGA_CURSOR_NORMAL 0
37583+ #define VGA_CURSOR_OFF 1
37584+ #define VIDEO_CAPTURE_LINEAR_MODE 0x00000200 //Bit[9] VIDEO_CAPTURE_LINEAR_MODE
37585+ #define LINEAR_MODE 0
37586+ #define TILE_MODE 1
37587+ #define VIDEO_CLOCK_DELAY 0x00000400 //Bit[11:10] Video clock delay control
37588+ #define VIDEO_CLOCK_DELAY_BIT 10
37589+ #define VIDEO_CLOCK_DELAY_MASK 0x00000C00
37590+ #define DELAY_0_NS 0
37591+ #define DELAY_1_NS 1
37592+ #define INV_AND_DELAY_0_NS 2
37593+ #define INV_AND_DELAY_1_NS 3
37594+ #define VIDEO_CCIR656_SOURCE_MODE 0x00001000 //Bit[12] Video CCIR656 source mode
37595+ #define RGB_SOURCE_MODE 0
37596+ #define CCIR656_SOURCE_MODE 1
37597+ #define SOURCE_PORT_CLOCK_MODE 0x00002000 //Bit[13] Video Source port clock mode
37598+ #define SINGLE_EDGE_MODE 0
37599+ #define DUAL_EDGE_MODE 1
37600+ #define EXTERNAL_PORT_SELECTION 0x00004000 //Bit[14] External video port slection
37601+ #define VIDEO_PORT_A 0
37602+ #define VIDEO_PORT_B 1
37603+ #define VIDEO_CAPTURE_FRAME_RATE 0x00010000 //Bit[23:16] Video capture frame rate control
37604+ #define VIDEO_CAPTURE_FRAME_RATE_BIT 16
37605+ #define VIDEO_CAPTURE_FRAME_RATE_MASK 0x00FF0000 //Maximum frame rate = XX * SourceFPS / 60
37606+
37607+#define VIDEO1_TIMEING_GEN_HOR_REG 0x0C + VIDEOBASE_OFFSET
37608+#define VIDEO2_TIMEING_GEN_HOR_REG 0x10C + VIDEOBASE_OFFSET
37609+ #define VIDEO_HDE_END 0x00000000 //Bit[12:0] Video HDE End timing generator
37610+ #define VIDEO_HDE_END_BIT 0 //Number of pixels from rising edge of Hsync for first active pixel
37611+ #define VIDEO_HDE_END_MASK 0x00001FFF
37612+ #define VIDEO_HDE_START 0x00010000 //Bit[28:16] Video HDE Start timing generator
37613+ #define VIDEO_HDE_START_BIT 16 //Number of pixels from rising edge of Hsync for last active pixel
37614+ #define VIDEO_HDE_START_MASK 0x1FFF0000
37615+ #define FRAME_RATE_OFF 0
37616+
37617+#define VIDEO1_TIMEING_GEN_V_REG 0x10 + VIDEOBASE_OFFSET
37618+#define VIDEO2_TIMEING_GEN_V_REG 0x110 + VIDEOBASE_OFFSET
37619+ #define VIDEO_VDE_END 0x00000001 //Bit[11:0] Video VDE End timing generator
37620+ #define VIDEO_VDE_END_BIT 0 //Number of pixels from rising edge of Vsync for first active pixel
37621+ #define VIDEO_VDE_END_MASK 0x00000FFF
37622+ #define VIDEO_VDE_START 0x00010000 //Bit[27:16] Video VDE Start timing generator
37623+ #define VIDEO_VDE_START_BIT 16 //Number of pixels from rising edge of Vsync for last active pixel
37624+ #define VIDEO_VDE_START_MASK 0x0FFF0000
37625+
37626+#define VIDEO1_SCALE_FACTOR_REG 0x14 + VIDEOBASE_OFFSET
37627+#define VIDEO2_SCALE_FACTOR_REG 0x114 + VIDEOBASE_OFFSET
37628+ #define HOR_SCALING_FACTOR 0x00000001 //Bit[15:0] Video Horizontal scaling factor
37629+ #define HOR_SCALING_FACTOR_BIT 0 //The formula=4096/(Horizontal scaling facotr)
37630+ #define HOR_SCALING_FACTOR_MASK 0x0000FFFF
37631+ #define VER_SCALING_FACTOR 0x00000000 //Bit[31:16] Video Vertical scaling factor
37632+ #define VER_SCALING_FACTOR_BIT 16 //The formula=4096/(Vertical scaling facotr)
37633+ #define VER_SCALING_FACTOR_MASK 0xFFFF0000
37634+
37635+#define VIDEO1_SCALE_FACTOR_PARAMETER0_REG 0x18 + VIDEOBASE_OFFSET //Scaling Parameters F00, F01, F02, F03
37636+#define VIDEO2_SCALE_FACTOR_PARAMETER0_REG 0x118 + VIDEOBASE_OFFSET
37637+
37638+#define VIDEO1_SCALE_FACTOR_PARAMETER1_REG 0x1C + VIDEOBASE_OFFSET //Scaling Parameters F10, F11, F12, F13
37639+#define VIDEO2_SCALE_FACTOR_PARAMETER1_REG 0x11C + VIDEOBASE_OFFSET
37640+
37641+#define VIDEO1_SCALE_FACTOR_PARAMETER2_REG 0x20 + VIDEOBASE_OFFSET //Scaling Parameters F20, F21, F22, F23
37642+#define VIDEO2_SCALE_FACTOR_PARAMETER2_REG 0x120 + VIDEOBASE_OFFSET
37643+
37644+#define VIDEO1_SCALE_FACTOR_PARAMETER3_REG 0x24 + VIDEOBASE_OFFSET //Scaling Parameters F30, F31, F32, F33
37645+#define VIDEO2_SCALE_FACTOR_PARAMETER3_REG 0x124 + VIDEOBASE_OFFSET
37646+
37647+#define VIDEO1_BCD_CONTROL_REG 0x2C + VIDEOBASE_OFFSET
37648+#define VIDEO2_BCD_CONTROL_REG 0x12C + VIDEOBASE_OFFSET
37649+ #define BCD_ENABLE 0x00000001 //Bit[0] Enable block change detection(BCD)
37650+ #define BCD_ENABLE_BIT 0
37651+ #define BCD_ENABLE_MASK 0x00000001
37652+ #define BCD_TOLERANCE 0x00010000 //Bit[23:16]
37653+ #define BCD_TOLERANCE_BIT 16 //flag as changed block when the video data difference greater
37654+ #define BCD_TOLERANCE_MASK 0x00FF0000
37655+
37656+#define VIDEO1_CAPTURE_WINDOWS_REG 0x30 + VIDEOBASE_OFFSET
37657+#define VIDEO2_CAPTURE_WINDOWS_REG 0x130 + VIDEOBASE_OFFSET
37658+ #define CAPTURE_VER_LINE 0x00000001 //Bit[10:0] Video compression vertical line total
37659+ #define CAPTURE_VER_LINE_BIT 0
37660+ #define CAPTURE_VER_LINE_MASK 0x000007FF
37661+ #define CAPTURE_HOR_PIXEL 0x00010000 //Bit[26:16] Video compression vertical line total
37662+ #define CAPTURE_HOR_PIXEL_BIT 16
37663+ #define CAPTURE_HOR_PIXEL_MASK 0x07FF0000
37664+
37665+#define VIDEO1_COMPRESS_WINDOWS_REG 0x34 + VIDEOBASE_OFFSET
37666+#define VIDEO2_COMPRESS_WINDOWS_REG 0x134 + VIDEOBASE_OFFSET
37667+ #define COMPRESS_VER_LINE 0x00000001 //Bit[10:0] Video compression vertical line total
37668+ #define COMPRESS_VER_LINE_BIT 0
37669+ #define COMPRESS_VER_LINE_MASK 0x000007FF
37670+ #define COMPRESS_HOR_PIXEL 0x00010000 //Bit[26:16] Video compression vertical line total
37671+ #define COMPRESS_HOR_PIXEL_BIT 16
37672+ #define COMPRESS_HOR_PIXEL_MASK 0x07FF0000
37673+
37674+#define VIDEO1_COMPRESS_BUF_PROCESS_OFFSET_REG 0x38
37675+#define VIDEO2_COMPRESS_BUF_PROCESS_OFFSET_REG 0x138
37676+ #define COMPRESS_BUF_PROCESS_OFFSET_ALIGN 127 //128 byte alignment
37677+ #define COMPRESS_BUF_PROCESS_OFFSET_MASK 0xFFFFFF
37678+
37679+#define VIDEO1_DECOMPRESS_BUF_PROCESS_OFFSET_REG 0x38
37680+#define VIDEO2_DECOMPRESS_BUF_PROCESS_OFFSET_REG 0x138
37681+ #define DECOMPRESS_BUF_PROCESS_OFFSET_ALIGN 127 //128 byte alignment
37682+ #define DECOMPRESS_BUF_PROCESS_OFFSET_MASK 0xFFFFFF
37683+
37684+
37685+//For Compression
37686+#define VIDEO1_COMPRESS_BUF_READ_OFFSET_REG 0x3C + VIDEOBASE_OFFSET //For stream mode
37687+#define VIDEO2_COMPRESS_BUF_READ_OFFSET_REG 0x13C + VIDEOBASE_OFFSET
37688+ #define COMPRESS_BUF_READ_OFFSET_ALIGN 127 //128 byte alignment
37689+ #define COMPRESS_BUF_READ_OFFSET_MASK 0x00FFFFFF
37690+//For Decompression
37691+#define VIDEO1_DECOMPRESS_BUF_WRITE_OFFSET_REG 0x3C + VIDEOBASE_OFFSET //For stream mode
37692+#define VIDEO2_DECOMPRESS_BUF_WRITE_OFFSET_REG 0x13C + VIDEOBASE_OFFSET
37693+ #define DECOMPRESS_BUF_WRITE_OFFSET_ALIGN 127 //128 byte alignment
37694+ #define DECOMPRESS_BUF_WRITE_OFFSET_MASK 0x00FFFFFF
37695+
37696+#define VIDEO1_CRC_BUF_ADDR_REG 0x40 + VIDEOBASE_OFFSET
37697+#define VIDEO2_CRC_BUF_ADDR_REG 0x140 + VIDEOBASE_OFFSET
37698+ #define CRC_BUF_ADDR_ALIGN 7 //8 byte alignment
37699+ #define CRC_BUF_ADDR_MASK 0x0FFFFFFF
37700+
37701+#define VIDEO1_BUF_1_ADDR_REG 0x44 + VIDEOBASE_OFFSET //For Source Buffer in frame mode
37702+#define VIDEO2_BUF_1_ADDR_REG 0x144 + VIDEOBASE_OFFSET
37703+ #define BUF_1_ADDR_ALIGN 255 //256 byte alignment
37704+ #define BUF_1_ADDR_MASK 0x1FFFFFFF
37705+
37706+#define VIDEO1_BUF_LINE_OFFSET_REG 0x48 + VIDEOBASE_OFFSET //Must set both in Frame/Stream mode
37707+#define VIDEO2_BUF_LINE_OFFSET_REG 0x148 + VIDEOBASE_OFFSET
37708+ #define BUF_LINE_OFFSET_ALIGN 7 //8 byte alignment
37709+ #define BUF_LINE_OFFSET_MASK 0x00003FFF
37710+
37711+#define VIDEO1_BUF_2_ADDR_REG 0x4C + VIDEOBASE_OFFSET //For BCD Buffer in frame mode
37712+#define VIDEO2_BUF_2_ADDR_REG 0x14C + VIDEOBASE_OFFSET
37713+ #define BUF_2_ADDR_ALIGN 255 //256 byte alignment
37714+ #define BUF_2_ADDR_MASK 0x1FFFFFFF
37715+
37716+#define VIDEO1_FLAG_BUF_ADDR_REG 0x50 + VIDEOBASE_OFFSET //For block change flag buffer
37717+#define VIDEO2_FLAG_BUF_ADDR_REG 0x150 + VIDEOBASE_OFFSET
37718+ #define FLAG_BUF_ADDR_ALIGN 7 //8 byte alignment
37719+ #define FLAG_BUF_ADDR_MASK 0x1FFFFFFF
37720+
37721+#define VIDEO1_COMPRESS_BUF_ADDR_REG 0x54 + VIDEOBASE_OFFSET //For stream mode
37722+#define VIDEO2_COMPRESS_BUF_ADDR_REG 0x154 + VIDEOBASE_OFFSET
37723+ #define COMPRESS_BUF_ADDR_ALIGN 127 //128 byte alignment
37724+ #define COMPRESS_BUF_ADDR_MASK 0x1FFFFFFF
37725+
37726+#define VIDEO1_STREAM_BUF_SIZE 0x58 + VIDEOBASE_OFFSET //For stream mode
37727+#define VIDEO2_STREAM_BUF_SIZE 0x158 + VIDEOBASE_OFFSET
37728+ #define STREAM_PACKET_SIZE 0x00000001
37729+ #define STREAM_PACKET_SIZE_BIT 0
37730+ #define STREAM_PACKET_SIZE_MASK 0x00000007
37731+ #define PACKET_SIZE_1KB 0
37732+ #define PACKET_SIZE_2KB 1
37733+ #define PACKET_SIZE_4KB 2
37734+ #define PACKET_SIZE_8KB 3
37735+ #define PACKET_SIZE_16KB 4
37736+ #define PACKET_SIZE_32KB 5
37737+ #define PACKET_SIZE_64KB 6
37738+ #define PACKET_SIZE_128KB 7
37739+ #define RING_BUF_PACKET_NUM 0x00000008
37740+ #define RING_BUF_PACKET_NUM_BIT 3
37741+ #define RING_BUF_PACKET_NUM_MASK 0x00000018
37742+ #define PACKETS_4 0
37743+ #define PACKETS_8 1
37744+ #define PACKETS_16 2
37745+ #define PACKETS_32 3
37746+ #define SKIP_HIGH_MB_THRES 0x00010000 //Bit[22:16] Skip high quality macro block threshold
37747+ #define SKIP_HIGH_MB_THRES_BIT 16
37748+ #define SKIP_HIGH_MB_THRES_MASK 0x007F0000
37749+ #define SKIP_TEST_MODE 0x00800000 //Bit[24:23] Skip test mode
37750+ #define SKIP_TEST_MODE_BIT 23
37751+ #define SKIP_TEST_MODE_MASK 0x01800000
37752+ #define YUV_TEST 2 //recommend
37753+
37754+#define VIDEO1_BUF_CODEC_OFFSET_READ 0x5C + VIDEOBASE_OFFSET //For stream mode,
37755+#define VIDEO2_BUF_CODEC_OFFSET_READ 0x15C + VIDEOBASE_OFFSET //Video stream buffer offset read back(HW)
37756+ #define BUF_CODEC_OFFSET_ALIGN 255 //256 byte alignment
37757+ #define BUF_CODEC_OFFSET_MASK 0x00FFFFFF
37758+
37759+#define VIDEO1_COMPRESS_CONTROL_REG 0x60 + VIDEOBASE_OFFSET
37760+#define VIDEO2_COMPRESS_CONTROL_REG 0x160 + VIDEOBASE_OFFSET
37761+ #define JPEG_ONLY_ENCODE 0x00000001 //Bit[0] JPEG only encoding
37762+ #define JPEG_ONLY_BIT 0
37763+ #define JPEG_MIX_MODE 0 //Enable JPEG/VQ mix mode encoding
37764+ #define JPEG_ONLY_MODE 1 //JPEG encoding mode only
37765+ #define VQ_4_COLOR_ENCODE 0x00000002 //Bit[1] Enable 4 color VQ encoding
37766+ #define VQ_4_COLOR_BIT 1
37767+ #define VQ_1_2_COLOR_MODE 0 //1 and 2 color mode VQ encoding
37768+ #define VQ_4_COLOR_MODE 1 //1, 2 and 4 color VQ encoding
37769+ #define QUALITY_CODEC_SETTING 0x00000004 //Bit[2] High and best video quality codec mode setting
37770+ #define QUALITY_CODEC_SETTING_BIT 2
37771+ #define JPEG_CODEC_MODE 0 //not supported in best video quality mode
37772+ #define QUANTI_CODEC_MODE 1
37773+ #define JPEG_DUAL_QUALITY_EN 0x00000008 //Bit[3] JPEG dual quality mode
37774+ #define EN_JPEG_DUAL_QUALITY 1 //enable(only for normal video quality mode)
37775+ #define BEST_QUALITY_EN 0x00000010 //Bit[4] Best quality video mode enable
37776+ #define BEST_QUALITY_EN_BIT 4
37777+ #define EN_BEST_QUALITY 1 //enable(only for quantization codec mode)
37778+ #define RC4_CRYPT_EN 0x00000020 //Bit[5] Enable RC4 encryption/decryption
37779+ #define RC4_CRYPT_EN_BIT 5
37780+ #define RC4_CRYPT_EN_MASK 0x00000020
37781+ #define RC4_CRYPT_ON 1 //enable
37782+ #define NORMAL_QUANTI_CHROMI_TABLE 0x00000040 //Bit[10:6] Normal video quality mode JPEG DCT chromi quantination table
37783+ #define NORMAL_QUANTI_CHROMI_TABLE_BIT 6
37784+ #define NORMAL_QUANTI_CHROMI_TABLE_MASK 0x000007C0
37785+ #define NORMAL_QUANTI_LUMI_TABLE 0x00000800 //Bit[15:11] Normal video quality mode JPEG DCT lumi quantination table
37786+ #define NORMAL_QUANTI_LUMI_TABLE_BIT 11
37787+ #define NORMAL_QUANTI_LUMI_TABLE_MASK 0x0000F800
37788+ #define HIGH_QUALITY_EN 0x00010000 //Bit[16] High video quality mode enable
37789+ #define HIGH_QUALITY_EN_BIT 16
37790+ #define EN_HIGH_QUALITY 1 //Enable
37791+ #define UV_CIR656_FORMAT 0x00080000 //Bit[19] UV fromat
37792+ #define UV_CIR656_FORMAT_BIT 19
37793+ #define USE_UV_CIR656 1 //recommand
37794+ #define HUFFMAN_TABLE_SELECT 0x00100000 //Bit[20] JPEG Huffman table combination
37795+ #define DUAL_TABLE 0 //Dual Y, UV table
37796+ #define SINGLE_TABLE 1 //Single Y table
37797+ #define SINGLE_UV_TABLE 0x00200000 //1x: Single UV table
37798+ #define HIGH_QUANTI_CHROMI_TABLE 0x00400000 //Bit[26:22] High quality JPEG DCT chromi quantization table
37799+ #define HIGH_QUANTI_CHROMI_TABLE_BIT 22
37800+ #define HIGH_QUANTI_CHROMI_TABLE_MASK 0x07C00000
37801+ #define HIGH_DEQUANTI_VALUE 0x00400000 //Bit[26:22] High quality de-quantization value
37802+ #define HIGH_DEQUANTI_VALUE_BIT 22
37803+ #define HIGH_DEQUANTI_VALUE_MASK 0x07C00000
37804+ #define HIGH_QUANTI_LUMI_TABLE 0x08000000 //Bit[31:27] High quality JPEG DCT lumi quantization table
37805+ #define HIGH_QUANTI_LUMI_TABLE_BIT 27
37806+ #define HIGH_QUANTI_LUMI_TABLE_MASK 0xF8000000
37807+ #define BEST_DEQUANTI_VALUE 0x08000000 //Bit[31:27] Best quality de-quantization value
37808+ #define BEST_DEQUANTI_VALUE_BIT 27
37809+ #define BEST_DEQUANTI_VALUE_MASK 0xF8000000
37810+
37811+
37812+#define VIDEO1_QUANTI_TABLE_LOW_REG 0x64 + VIDEOBASE_OFFSET //Match with 0x60 Bit[10:6], Bit[15:11]
37813+#define VIDEO2_QUANTI_TABLE_LOW_REG 0x164 + VIDEOBASE_OFFSET
37814+ #define QUANTI_CHROMI_TABLE_LOW 0x00000001 //Bit[4:0] Normal video low quality block chromi quantization table
37815+ #define QUANTI_CHROMI_TABLE_LOW_BIT 0
37816+ #define QUANTI_CHROMI_TABLE_LOW_MASK 0x0000001F
37817+ #define QUANTI_LUMI_TABLE_LOW 0x00000020 //Bit[9:5] Normal video low quality block lumi quantization table
37818+ #define QUANTI_LUMI_TABLE_LOW_BIT 5
37819+ #define QUANTI_LUMI_TABLE_LOW_MASK 0x000003E0
37820+
37821+#define VIDEO1_QUANTI_VALUE_REG 0x68 + VIDEOBASE_OFFSET //Match with 0x60 Bit[26:22],Bit[31:27]
37822+#define VIDEO2_QUANTI_VALUE_REG 0x168 + VIDEOBASE_OFFSET
37823+ #define HIGH_QUANTI_VALUE 0x00000001 //Bit[14:0] High quality quantization value. Format is 1.14
37824+ #define HIGH_QUANTI_VALUE_BIT 0
37825+ #define HIGH_QUANTI_VALUE_MASK 0x00007FFF
37826+ #define BEST_QUANTI_VALUE 0x00010000 //Bit[30:16] Best quality quantization value. Format is 1.14
37827+ #define BEST_QUANTI_VALUE_BIT 16
37828+ #define BEST_QUANTI_VALUE_MASK 0x7FFF0000
37829+
37830+#define VIDEO1_BSD_PARA_REG 0x6C + VIDEOBASE_OFFSET //Video BSD Parameters Register
37831+#define VIDEO2_BSD_PARA_REG 0x16C + VIDEOBASE_OFFSET
37832+ #define BSD_HIGH_THRES 0x00000001 //Bit[7:0] Block sharpness detection high threshold
37833+ #define BSD_HIGH_THRES_BIT 0
37834+ #define BSD_HIGH_THRES_MASK 0x000000FF
37835+ #define BSD_LOW_THRES 0x00000100 //Bit[15:8] Block shaprpness detection low threshold
37836+ #define BSD_LOW_THRES_BIT 8
37837+ #define BSD_LOW_THRES_MASK 0x0000FF00
37838+ #define BSD_HIGH_COUNTS 0x00010000 //Bit[21:16] Block sharpness detection high counts threshold
37839+ #define BSD_HIGH_COUNTS_BIT 16
37840+ #define BSD_HIGH_COUNTS_MASK 0x003F0000
37841+ #define BSD_LOW_COUNTS 0x00400000 //Bit[27:22] Block sharpness detection low counts threshold
37842+ #define BSD_LOW_COUNTS_BIT 22
37843+ #define BSD_LOW_COUNTS_MASK 0x0FC00000
37844+
37845+#define VIDEO1_COMPRESS_FRAME_SIZE_REG 0x70 + VIDEOBASE_OFFSET
37846+#define VIDEO2_COMPRESS_FRAME_SIZE_REG 0x170 + VIDEOBASE_OFFSET
37847+ #define COMPRESS_FRAME_SIZE_READ 0x00000001 //Bit[19:0] Video compression frame size read back(number of DW)
37848+ #define COMPRESS_FRAME_SIZE_READ_BIT 0
37849+ #define COMPRESS_FRAME_SIZE_READ_MASK 0x003FFFFF
37850+
37851+#define VIDEO1_COMPRESS_BLOCK_COUNT_REG 0x74 + VIDEOBASE_OFFSET
37852+#define VIDEO2_COMPRESS_BLOCK_COUNT_REG 0x174 + VIDEOBASE_OFFSET
37853+ #define PROCESS_BLOCK_COUNT_READ_BIT 0
37854+ #define PROCESS_BLOCK_COUNT_READ_MASK 0x00003FFF //Bit[13:0] Video processed total block counter read back(number of blocks)
37855+ #define COMPRESS_BLOCK_COUNT_READ_BIT 16
37856+ #define COMPRESS_BLOCK_COUNT_READ_MASK 0xFFFF0000 //Bit[29:16] Video processed total block counter read back(number of blocks)
37857+
37858+#define VIDEO1_COMPRESS_FRAME_END_READ 0x78 + VIDEOBASE_OFFSET //Video compression stream frame end pointer
37859+#define VIDEO2_COMPRESS_FRAME_END_READ 0x178 + VIDEOBASE_OFFSET
37860+ #define COMPRESS_FRAME_END_READ_ALIGN 7
37861+ #define COMPRESS_FRAME_END_READ_MASK 0x00FFFFFF
37862+
37863+#define VIDEO1_COMPRESS_FRAME_COUNT_READ 0x7C + VIDEOBASE_OFFSET
37864+#define VIDEO2_COMPRESS_FRAME_COUNT_READ 0x17C + VIDEOBASE_OFFSET
37865+ #define COMPRESS_FRAME_COUNT_READ 0x00000001 //Bit[15:0] Video compression frame count read back(number of frame)
37866+ #define COMPRESS_FRAME_COUNT_READ_BIT 0
37867+ #define COMPRESS_FRAME_COUNT_READ_MASK 0xFFFFFFFF
37868+
37869+#define VIDEO1_USER_DEFINE_HEADER 0x80 + VIDEOBASE_OFFSET
37870+#define VIDEO2_USER_DEFINE_HEADER 0x180 + VIDEOBASE_OFFSET
37871+ #define USER_DEFINE_HEADER 0x00000001 //Bit[15:0] Video user defined header parameter
37872+ #define USER_DEFINE_HEADER_BIT 0
37873+ #define USER_DEFINE_HEADER_MASK 0x0000FFFF
37874+
37875+#define VIDE1_MODE_DETECTION_EDGE_H_REG 0x90 + VIDEOBASE_OFFSET
37876+#define VIDE2_MODE_DETECTION_EDGE_H_REG 0x190 + VIDEOBASE_OFFSET
37877+ #define LEFT_EDGE_LOCATION 0x00000001 //Bit[11:0] Video source left edge location from sync rising edge
37878+ #define LEFT_EDGE_LOCATION_BIT 0
37879+ #define LEFT_EDGE_LOCATION_MASK 0x00000FFF
37880+ #define NO_VER_SYNC (1 << 12) //Bit[12] No Vertical sync detected
37881+ #define NO_HOR_SYNC (1 << 13) //Bit[13] No horizontal sync detected
37882+ #define NO_ACTIVE_DISP (1 << 14) //Bit[14] No active display detected
37883+ #define NO_DISP_CLOCK (1 << 15)
37884+ #define RIGHT_EDGE_LOCATION 0x00010000 //Bit[27:16] Video source right edge location from sync rising edge
37885+ #define RIGHT_EDGE_LOCATION_BIT 16
37886+ #define RIGHT_EDGE_LOCATION_MASK 0x0FFF0000
37887+
37888+#define VIDE1_MODE_DETECTION_EDGE_V_REG 0x94 + VIDEOBASE_OFFSET
37889+#define VIDE2_MODE_DETECTION_EDGE_V_REG 0x194 + VIDEOBASE_OFFSET
37890+ #define TOP_EDGE_LOCATION 0x00000001 //Bit[11:0] Video source top edge location from sync rising edge
37891+ #define TOP_EDGE_LOCATION_BIT 0
37892+ #define TOP_EDGE_LOCATION_MASK 0x00000FFF
37893+ #define BOTTOM_EDGE_LOCATION 0x00010000 //Bit[27:16] Video source bottom edge location from sync rising edge
37894+ #define BOTTOM_EDGE_LOCATION_BIT 16
37895+ #define BOTTOM_EDGE_LOCATION_MASK 0x0FFF0000
37896+
37897+#define VIDEO1_MODE_DETECTION_STATUS_READ_REG 0x98 + VIDEOBASE_OFFSET
37898+#define VIDEO2_MODE_DETECTION_STATUS_READ_REG 0x198 + VIDEOBASE_OFFSET
37899+ #define MODE_DETECTION_HOR_TIME_READ 0x00000001 //Bit[11:0] Mode detection Horizontal time read back (read only)
37900+ #define MODE_DETECTION_HOR_TIME_READ_BIT 0
37901+ #define MODE_DETECTION_HOR_TIME_READ_MASK 0x00000FFF
37902+ #define ANALONG_DIGITAL_READ 0x00001000 //Bit[12] Auto detection for external analog or digital source read back
37903+ #define ANALONG_DIGITAL_READ_BIT 12
37904+ #define DVI_SIGNAL 0
37905+ #define ADC_SIGNAL 1
37906+ #define MODE_DETECTION_HOR_STABLE_READ 0x00002000 //Bit[13] Mode detection horizontal stable read back
37907+ #define HOR_STABLE 1
37908+ #define MODE_DETECTION_VER_STABLE_READ 0x00004000 //Bit[14] Mode detection vertical stable read back
37909+ #define VER_STABLE 1
37910+ #define OUT_LOCK_READ 0x00008000 //Bit[15] Mode detection out of lock read back
37911+ #define SIGNAL_OUT_LOCK 1
37912+ #define MODE_DETECTION_VER_LINE_READ 0x00010000 //Bit[27:16] Mode detection Vertical lines read back
37913+ #define MODE_DETECTION_VER_LINE_READ_BIT 16
37914+ #define MODE_DETECTION_VER_LINE_READ_MASK 0x0FFF0000
37915+ #define VSYNC_POLARITY_READ 0x10000000 //Bit[28] Vsync polarity read back
37916+ #define HSYNC_POLARITY_READ 0x20000000 //Bit[29] Hsync polarity read back
37917+ #define MODE_DETECTION_VSYNC_READY 0x40000000 //Bit[30] Mode detection Vsync ready
37918+ #define MODE_DETECTION_HSYNC_READY 0x80000000 //Bit[31] Mode detection Hsync ready
37919+
37920+/****** VIDEO MEMAGER SETTING ******/
37921+#define VIDEOM_ENGINE_SEQUENCE_CONTROL_REG 0x204 + VIDEOBASE_OFFSET
37922+ #define VIDEOM_CAPTURE_TRIGGER 0x00000002 //Bit[1] trigger HW to capture video
37923+ #define VIDEOM_AUTO_MODE 0x00000008 //Bit[3]
37924+ #define DISABLE_AUTO_MODE 0
37925+ #define AUTO_COMPRESS 1
37926+ #define VIDEOM_CODEC_TRIGGER 0x00000010 //Bit[4] trigger HW to compress or decompress video
37927+ #define VIDEOM_SOURCE_SELECTION 0x00000100 //Bit[8]
37928+ #define VIDEO1 0
37929+ #define VIDEO2 1
37930+ //#define STREAM_DATA_MODE 0x00000400 //Bit[11:10] Buffer and Stream Data type
37931+ // #define STREAM_DATA_MODE_BIT 10
37932+ // #define STREAM_DATA_MODE_MASK 0x00000C00
37933+ // #define YUV444_MODE 0
37934+ // #define YUV420_MODE 1
37935+ // #define YUV420_MODE_WITH_AST2000 2 //AST2000 compatible
37936+ #define VIDEOM_CAPTURE_READY 0x00010000 //Bit[16] Video capture ready status read back(read only)
37937+ //#define HW_BUSY 0
37938+ //#define HW_IDLE 1
37939+ #define VIDEOM_CODEC_READY 0x00040000 //Bit[18] Video codec ready status read back(read only)
37940+ //#define HW_BUSY 0
37941+ //#define HW_IDLE 1
37942+
37943+#define VIDEOM_SCALE_FACTOR_REG 0x214 + VIDEOBASE_OFFSET
37944+// #define HOR_SCALING_FACTOR 0x00000001 //Bit[15:0] Video Horizontal scaling factor
37945+// #define HOR_SCALING_FACTOR_BIT 0 //The formula=4096/(Horizontal scaling facotr)
37946+// #define HOR_SCALING_FACTOR_MASK 0x0000FFFF
37947+// #define VER_SCALING_FACTOR 0x00000000 //Bit[31:16] Video Vertical scaling factor
37948+// #define VER_SCALING_FACTOR_BIT 16 //The formula=4096/(Vertical scaling facotr)
37949+// #define VER_SCALING_FACTOR_MASK 0xFFFF0000
37950+
37951+#define VIDEOM_SCALE_FACTOR_PARAMETER0_REG 0x218 + VIDEOBASE_OFFSET //Scaling Parameters F00, F01, F02, F03
37952+
37953+#define VIDEOM_SCALE_FACTOR_PARAMETER1_REG 0x21C + VIDEOBASE_OFFSET //Scaling Parameters F10, F11, F12, F13
37954+
37955+#define VIDEOM_SCALE_FACTOR_PARAMETER2_REG 0x220 + VIDEOBASE_OFFSET //Scaling Parameters F20, F21, F22, F23
37956+
37957+#define VIDEOM_SCALE_FACTOR_PARAMETER3_REG 0x224 + VIDEOBASE_OFFSET //Scaling Parameters F30, F31, F32, F33
37958+
37959+#define VIDEOM_BCD_CONTROL_REG 0x22C + VIDEOBASE_OFFSET
37960+ //#define BCD_ENABLE 0x00000001 //Bit[0] Enable block change detection(BCD)
37961+ //#define BCD_TOLERANCE 0x00010000 //Bit[23:16]
37962+ // #define BCD_TOLERANCE_BIT 16 //flag as changed block when the video data difference greater
37963+ // #define BCD_TOLERANCE_MASK 0x00FF0000
37964+
37965+#define VIDEOM_CAPTURE_WINDOWS_REG 0x230 + VIDEOBASE_OFFSET
37966+ //#define RC4_TABLE_ADDR_ALIGN 7 //8 byte alignment
37967+ //#define RC4_TABLE_ADDR_MASK 0x0FFFFFFF
37968+
37969+#define VIDEOM_COMPRESS_WINDOWS_REG 0x234 + VIDEOBASE_OFFSET
37970+ //#define COMPRESS_VER_LINE 0x00000001 //Bit[12:0] Video compression vertical line total
37971+ //#define COMPRESS_VER_LINE_BIT 0
37972+ //#define COMPRESS_VER_LINE_MASK 0x00001FFF
37973+ //#define COMPRESS_HOR_PIXEL 0x00010000 //Bit[12:0] Video compression vertical line total
37974+ //#define COMPRESS_HOR_PIXEL_BIT 16
37975+ //#define COMPRESS_HOR_PIXEL_MASK 0x1FFF0000
37976+
37977+#define VIDEOM_COMPRESS_BUF_PROCESS_OFFSET_REG 0x238
37978+ //#define COMPRESS_BUF_PROCESS_OFFSET_ALIGN 127 //128 byte alignment
37979+ //#define COMPRESS_BUF_PROCESS_OFFSET_MASK 0x3FFFFF
37980+
37981+
37982+//For Compression
37983+#define VIDEOM_COMPRESS_BUF_READ_OFFSET_REG 0x23C + VIDEOBASE_OFFSET //For stream mode
37984+ //#define COMPRESS_BUF_READ_OFFSET_ALIGN 127 //128 byte alignment
37985+ //#define COMPRESS_BUF_READ_OFFSET_MASK 0x003FFFFF
37986+//For Decompression
37987+#define VIDEOM_DECOMPRESS_BUF_WRITE_OFFSET_REG 0x23C + VIDEOBASE_OFFSET //For stream mode
37988+ //#define DECOMPRESS_BUF_WRITE_OFFSET_ALIGN 127 //128 byte alignment
37989+ //#define DECOMPRESS_BUF_WRITE_OFFSET_MASK 0x003FFFFF
37990+
37991+#define VIDEOM_BUF_1_ADDR_REG 0x244 + VIDEOBASE_OFFSET //For Source Buffer in frame mode
37992+ //#define BUF_1_ADDR_ALIGN 255 //256 byte alignment
37993+ //#define BUF_1_ADDR_MASK 0x0FFFFFFF
37994+
37995+#define VIDEOM_BUF_LINE_OFFSET_REG 0x248 + VIDEOBASE_OFFSET //Must set both in Frame/Stream mode
37996+ //#define BUF_LINE_OFFSET_ALIGN 7 //8 byte alignment
37997+ //#define BUF_LINE_OFFSET_MASK 0x00003FFF
37998+
37999+#define VIDEOM_BUF_2_ADDR_REG 0x24C + VIDEOBASE_OFFSET //For BCD Buffer in frame mode
38000+ //#define BUF_2_ADDR_ALIGN 255 //256 byte alignment
38001+ //#define BUF_2_ADDR_MASK 0x0FFFFFFF
38002+
38003+#define VIDEOM_FLAG_BUF_ADDR_REG 0x250 + VIDEOBASE_OFFSET //For block change flag buffer
38004+ //#define FLAG_BUF_ADDR_ALIGN 7 //8 byte alignment
38005+ //#define FLAG_BUF_ADDR_MASK 0x0FFFFFFF
38006+
38007+#define VIDEOM_COMPRESS_BUF_ADDR_REG 0x254 + VIDEOBASE_OFFSET //For stream mode
38008+ //#define FLAG_BUF_ADDR_ALIGN 7 //8 byte alignment
38009+ //#define FLAG_BUF_ADDR_MASK 0x0FFFFFFF
38010+
38011+#define VIDEOM_BUF_CODEC_OFFSET_READ 0x25C + VIDEOBASE_OFFSET //For stream mode,
38012+ //#define BUF_CODEC_OFFSET_ALIGN 255 //256 byte alignment
38013+ //#define BUF_CODEC_OFFSET_MASK 0x003FFFFF
38014+
38015+#define VIDEOM_COMPRESS_CONTROL_REG 0x260 + VIDEOBASE_OFFSET
38016+ //#define JPEG_ONLY_ENCODE 0x00000001 //Bit[0] JPEG only encoding
38017+ // #define JPEG_MIX_MODE 0 //Enable JPEG/VQ mix mode encoding
38018+ // #define JPEG_ONLY_MODE 1 //JPEG encoding mode only
38019+ //#define VQ_4_COLOR_ENCODE 0x00000002 //Bit[1] Enable 4 color VQ encoding
38020+ // #define VQ_1_2_COLOR_MODE 0 //1 and 2 color mode VQ encoding
38021+ // #define VQ_4_COLOR_MODE 1 //1, 2 and 4 color VQ encoding
38022+ //#define QUALITY_CODEC_SETTING 0x00000004 //Bit[2] High and best video quality codec mode setting
38023+ // #define JPEG_CODEC_MODE 0 //not supported in best video quality mode
38024+ // #define QUANTI_CODEC_MODE 1
38025+ //#define JPEG_DUAL_QUALITY_EN 0x00000008 //Bit[3] JPEG dual quality mode
38026+ // #define EN_JPEG_DUAL_QUALITY 1 //enable(only for normal video quality mode)
38027+ //#define BEST_QUALITY_EN 0x00000010 //Bit[4] Best quality video mode enable
38028+ // #define EN_BEST_QUALITY 1 //enable(only for quantization codec mode)
38029+ //#define RC4_CRYPT_EN 0x00000020 //Bit[5] Enable RC4 encryption/decryption
38030+ // #define EN_RC4_CRYPT 1 //enable
38031+ //#define NORMAL_QUANTI_CHROMI_TABLE 0x00000040 //Bit[10:6] Normal video quality mode JPEG DCT chromi quantination table
38032+ // #define NORMAL_QUANTI_CHROMI_TABLE_BIT 6
38033+ // #define NORMAL_QUANTI_CHROMI_TABLE_MASK 0x000007C0
38034+ //#define NORMAL_QUANTI_LUMI_TABLE 0x00000800 //Bit[15:11] Normal video quality mode JPEG DCT lumi quantination table
38035+ // #define NORMAL_QUANTI_LUMI_TABLE_BIT 11
38036+ // #define NORMAL_QUANTI_LUMI_TABLE_MASK 0x0000F800
38037+ //#define HIGH_QUALITY_EN 0x00010000 //Bit[16] High video quality mode enable
38038+ // #define EN_HIGH_QUALITY 1 //Enable
38039+ //#define UV_CIR656_FORMAT 0x00080000 //Bit[19] UV fromat
38040+ // #define USE_UV_CIR656 1 //recommand
38041+ //#define HUFFMAN_TABLE_SELECT 0x00100000 //Bit[20] JPEG Huffman table combination
38042+ // #define DUAL_TABLE 0 //Dual Y, UV table
38043+ // #define SINGLE_TABLE 1 //Single Y table
38044+ // #define SINGLE_UV_TABLE 0x00200000 //1x: Single UV table
38045+ //#define HIGH_QUANTI_CHROMI_TABLE 0x00400000 //Bit[26:22] High quality JPEG DCT chromi quantization table
38046+ // #define HIGH_QUANTI_CHROMI_TABLE_BIT 22
38047+ // #define HIGH_QUANTI_CHROMI_TABLE_MASK 0x07C00000
38048+ //#define HIGH_DEQUANTI_VALUE 0x00400000 //Bit[26:22] High quality de-quantization value
38049+ // #define HIGH_DEQUANTI_VALUE_BIT 22
38050+ // #define HIGH_DEQUANTI_VALUE_MASK 0x07C00000
38051+ //#define HIGH_QUANTI_LUMI_TABLE 0x08000000 //Bit[31:27] High quality JPEG DCT lumi quantization table
38052+ // #define HIGH_QUANTI_LUMI_TABLE_BIT 27
38053+ // #define HIGH_QUANTI_LUMI_TABLE_MASK 0xF8000000
38054+ //#define BEST_DEQUANTI_VALUE 0x08000000 //Bit[31:27] Best quality de-quantization value
38055+ // #define BEST_QUANTI_VALUE_BIT 27
38056+ // #define BEST_QUANTI_VALUE_MASK 0xF8000000
38057+
38058+#define VIDEOM_QUANTI_TABLE_LOW_REG 0x264 + VIDEOBASE_OFFSET //Match with 0x60 Bit[10:6], Bit[15:11]
38059+// #define QUANTI_CHROMI_TABLE_LOW 0x00000001 //Bit[4:0] Normal video low quality block chromi quantization table
38060+// #define QUANTI_CHROMI_TABLE_LOW_BIT 0
38061+// #define QUANTI_CHROMI_TABLE_LOW_MASK 0x0000001F
38062+// #define QUANTI_LUMI_TABLE_LOW 0x00000020 //Bit[9:5] Normal video low quality block lumi quantization table
38063+// #define QUANTI_CHROMI_TABLE_LOW_BIT 5
38064+// #define QUANTI_CHROMI_TABLE_LOW_MASK 0x000003E0
38065+
38066+#define VIDEOM_QUANTI_VALUE_REG 0x268 + VIDEOBASE_OFFSET //Match with 0x60 Bit[26:22],Bit[31:27]
38067+// #define HIGH_QUANTI_VALUE 0x00000001 //Bit[14:0] High quality quantization value. Format is 1.14
38068+// #define HIGH_QUANTI_VALUE_BIT 0
38069+// #define HIGH_QUANTI_VALUE_MASK 0x00007FFF
38070+// #define BEST_QUANTI_VALUE 0x00010000 //Bit[30:16] Best quality quantization value. Format is 1.14
38071+// #define BEST_QUANTI_VALUE_BIT 16
38072+// #define BEST_QUANTI_VALUE_MASK 0x7FFF0000
38073+
38074+#define VIDEOM_BSD_PARA_REG 0x26C + VIDEOBASE_OFFSET //Video BSD Parameters Register
38075+// #define BSD_HIGH_THRES 0x00000001 //Bit[7:0] Block sharpness detection high threshold
38076+// #define BSD_HIGH_THRES_BIT 0
38077+// #define BSD_HIGH_THRES_MASK 0x000000FF
38078+// #define BSD_LOW_THRES 0x00000100 //Bit[15:8] Block shaprpness detection low threshold
38079+// #define BSD_LOW_THRES_BIT 8
38080+// #define BSD_LOW_THRES_MASK 0x0000FF00
38081+// #define BSD_HIGH_COUNTS 0x00010000 //Bit[21:16] Block sharpness detection high counts threshold
38082+// #define BSD_HIGH_COUNTS_BIT 16
38083+// #define BSD_HIGH_COUNTS_MASK 0x003F0000
38084+// #define BSD_LOW_COUNTS 0x01000000 //Bit[27:24] Block sharpness detection low counts threshold
38085+// #define BSD_LOW_COUNTS_BIT 24
38086+// #define BSD_LOW_COUNTS_MASK 0x3F000000
38087+
38088+#define VIDEOM_COMPRESS_FRAME_SIZE_REG 0x270 + VIDEOBASE_OFFSET
38089+// #define COMPRESS_FRAME_SIZE_READ 0x00000001 //Bit[19:0] Video compression frame size read back(number of DW)
38090+// #define COMPRESS_FRAME_SIZE_READ_BIT 0
38091+// #define COMPRESS_FRAME_SIZE_READ_MASK 0x000FFFFF
38092+
38093+#define VIDEOM_COMPRESS_BLOCK_COUNT_REG 0x274 + VIDEOBASE_OFFSET
38094+// #define COMPRESS_BLOCK_COUNT_READ 0x00000001 //Bit[15:0] Video compress block counter read back(number of blocks)
38095+// #define COMPRESS_BLOCK_COUNT_READ_BIT 0
38096+// #define COMPRESS_BLOCK_COUNT_READ_MASK 0x0000FFFF
38097+
38098+#define VIDEOM_COMPRESS_FRAME_END_READ 0x278 + VIDEOBASE_OFFSET //Video compression stream frame end pointer
38099+ //#define COMPRESS_FRAME_END_READ_ALIGN 7
38100+ //#define COMPRESS_FRAME_END_READ_MASK 0x003FFFFF
38101+
38102+#define VIDEOM_USER_DEFINE_HEADER_REG 0x280 + VIDEOBASE_OFFSET
38103+// #define USER_DEFINE_HEADER 0x00000001 //Bit[15:0] Video user defined header parameter
38104+// #define USER_DEFINE_HEADER_BIT 0
38105+// #define USER_DEFINE_HEADER_MASK 0x0000FFFF
38106+
38107+/****** VR300-VR3FC: General Control registers *****/
38108+#define VIDEO_CONTROL_REG 0x300 + VIDEOBASE_OFFSET
38109+ #define CODEC_DECOMPRESS_MODE 0x00000001 //Bit[0] Codec in de-compression mode
38110+ #define CODEC_DECOMPRESS_MODE_BIT 0
38111+ #define CODEC_DECOMPRESS_MODE_MASK 0x00000001
38112+ #define COMPRESS_MODE 0
38113+ #define DECOMPRESS_MODE 1
38114+ #define VIDEO_SAFE_MODE 0x00000002 //Bit[1] VIDEO SAFE MODE
38115+ #define VIDEO_SAFE_MODE_BIT 1
38116+ #define VIDEO_SAFE_MODE_OFF 0
38117+ #define VIDEO_SAFE_MODE_ON 1
38118+ #define DELAY_VSYNC 0x00000004 //Bit[2] Delay Internal VSYNC
38119+ #define DELAY_VSYNC_BIT 2
38120+ #define DELAY_VSYNC_MASK (1<<2)
38121+ #define DELAY_VSYNC_OFF (0<<2)
38122+ #define DELAY_VSYNC_EN (1<<2)
38123+ #define VER_DOWNSCALING_LINE_BUFFER_EN 0x00000010 //Bit[5:4] Video vertical downscaling line buffer enable
38124+ #define VER_LINE_BUFFER_MASK (3<<4)
38125+ #define LINE_BUFFER_OFF (0<<4)
38126+ #define LINE_BUFFER_VIDEO1 1
38127+ #define LINE_BUFFER_VIDEO2 2
38128+ #define LINE_BUFFER_VIDEOM 3
38129+ #define RC4_KEY_BUFFER_SELECTION (1UL<<6) //Bit[7:6] RC4 Key Buffer Selection
38130+ #define RC4_KEY_BUFFER_SELECTION_BIT 6
38131+ #define RC4_KEY_BUFFER_SELECTION_MASK (3UL<<6)
38132+ #define RC4_KEY_BUFFER_VIDEO1 0
38133+ #define RC4_KEY_BUFFER_VIDEO2 1
38134+ #define RC4_KEY_BUFFER_VIDEOM 2
38135+ #define RC4_INIT_RESET (1UL<<8) //Bit[8] RC4 initial reset
38136+ #define RC4_INIT_RESET_BIT 8
38137+ #define RC4_INIT_RESET_MASK (1UL<<8)
38138+ #define RC4_NORMAL_MODE 0
38139+ #define RC4_RESET_COUNTER 1
38140+ #define RC4_TEST_MODE (1UL<<9) //Bit[9] RC4 test mode
38141+ #define RC4_TEST_MODE_BIT 9
38142+ #define RC4_TEST_OFF 0
38143+ #define RC4_TEST_ON 1
38144+ #define RC4_SAVE_MODE (1UL<<14) //Bit[14] RC4 save mode
38145+ #define RC4_SAVE_MODE_BIT 14
38146+ #define RC4_SAVE_MODE_MASK (1UL<<14)
38147+ #define RC4_SAVE_MODE_OFF 0
38148+ #define RC4_SAVE_MODE_ON 1
38149+ #define RC4_NO_RESET_FRAME (1UL<<15) //Bit[15] RC4 no reset when frame completed
38150+ #define RC4_NO_RESET_FRAME_BIT 15
38151+ #define RC4_NO_RESET_FRAME_MASK (1UL<<15)
38152+ #define RC4_NO_RESET_FRAME_OFF 0 //Always reset
38153+ #define RC4_NO_RESET_FRAME_ON 1
38154+
38155+#define VIDEO_INT_CONTROL_EN_REG 0x304 + VIDEOBASE_OFFSET
38156+ #define VIDEO1_WATCH_DOG_INT_EN 0x00000001 //Bit[0] Enable Video1 mode detection watch dog out of lock interrupt
38157+ #define VIDEO1_INPUT_COMPLETE_INT_EN 0x00000002 //Bit[1] Enable Video1 video input complete interrupt (frame complete only for frame mode)
38158+ #define VIDEO1_PACKET_READY_INT_EN 0x00000004 //Bit[2] Enable Video1 packet ready interrupt
38159+ #define VIDEO1_COMPRESS_COMPLETE_INT_EN 0x00000008 //Bit[3] Enable Video1 compression complete interrupt
38160+ #define VIDEO1_MODE_DETECTION_READY_INT_EN 0x00000010 //Bit[4] Enable video1 mode detection ready interrupt
38161+ #define VIDEO1_FRAME_COMPLETE_INT_EN 0x00000020 //Bit[5] Enable Video1 frame complete interrupt (only for stream mode)
38162+ #define VIDEO1_STREAM_ERR_INT_EN 0x00000040 //Bit[6] Enable Video1 decode stream error interrupt
38163+ #define VIDEO2_WATCH_DOG_INT_EN 0x00000100 //Bit[8] Enable Video2 mode detection watch dog out of lock interrupt
38164+ #define VIDEO2_INPUT_COMPLETE_INT_EN 0x00000200 //Bit[9] Enable Video2 video input complete interrupt (frame complete only for frame mode)
38165+ #define VIDEO2_PACKET_READY_INT_EN 0x00000400 //Bit[10] Enable Video2 packet ready interrupt
38166+ #define VIDEO2_COMPRESS_COMPLETE_INT_EN 0x00000800 //Bit[11] Enable Video2 compression complete interrupt
38167+ #define VIDEO2_MODE_DETECTION_READY_INT_EN 0x00001000 //Bit[12] Enable video2 mode detection ready interrupt
38168+ #define VIDEO2_FRAME_COMPLETE_INT_EN 0x00002000 //Bit[13] Enable Video2 frame complete interrupt (only for stream mode)
38169+ #define VIDEO2_STREAM_ERR_INT_EN 0x00004000 //Bit[14] Enable Video2 decode stream error interrupt
38170+ #define VIDEOM_INPUT_COMPLETE_INT_EN 0x00010000 //Bit[16] Enable VideoM video input complete interrupt
38171+ #define VIDEOM_COMPRESS_COMPLETE_INT_EN 0x00020000 //Bit[17] Enable VideoM compression complete interrupt
38172+ #define VIDEOM_PACKET_READY_INT_EN 0x00040000 //Bit[18] Enable VideoM packet ready interrupt
38173+ #define VIDEOM_FRAME_COMPLETE_INT_EN 0x00080000 //Bit[19] Enable VideoM frame complete interrupt (only for stream mode)
38174+
38175+#define VIDEO_INT_CONTROL_READ_REG 0x308 + VIDEOBASE_OFFSET //Clear when write 1
38176+ #define VIDEO1_WATCH_DOG_READ 0x00000001 //Bit[0] Video1 mode detection watch dog out of lock interrupt status read back
38177+ #define VIDEO1_WATCH_DOG_BIT 0
38178+ #define VIDEO1_WATCH_DOG_MASK 0x00000001
38179+ #define VIDEO1_INPUT_COMPLETE_READ 0x00000002 //Bit[1] Video1 video input complete interrupt status read back (frame complete only for frame mode)
38180+ #define VIDEO1_INPUT_COMPLETE_BIT 1
38181+ #define VIDEO1_INPUT_COMPLETE_MASK 0x00000002
38182+ #define VIDEO1_PACKET_READY_READ 0x00000004 //Bit[2] Video1 packet ready interrupt status read back
38183+ #define VIDEO1_PACKET_READY_BIT 2
38184+ #define VIDEO1_PACKET_READY_MASK 0x00000004
38185+ #define VIDEO1_COMPRESS_COMPLETE_READ 0x00000008 //Bit[3] Video1 compression complete interrupt status read back
38186+ #define VIDEO1_COMPRESS_COMPLETE_BIT 3
38187+ #define VIDEO1_COMPRESS_COMPLETE_MASK 0x00000008
38188+ #define VIDEO1_MODE_DETECTION_READY_READ 0x00000010 //Bit[4] Video1 mode detection ready interrupt status read back
38189+ #define VIDEO1_MODE_DETECTION_READY_BIT 4
38190+ #define VIDEO1_FRAME_COMPLETE_READ 0x00000020 //Bit[5] Video1 frame complete interrupt status read back
38191+ #define VIDEO1_FRAME_COMPLETE_BIT 5
38192+ #define VIDEO1_FRAME_COMPLETE_MASK 0x00000020
38193+ #define VIDEO1_STREAM_ERR_READ 0x00000040 //Bit[6] Video1 decode stream error interrupt status read back
38194+ #define VIDEO1_STREAM_ERR_BIT 6
38195+ #define VIDEO1_STREAM_ERR_MASK 0x00000040
38196+ #define VIDEO2_WATCH_DOG_READ 0x00000100 //Bit[8] Video2 mode detection watch dog out of lock interrupt status read back
38197+ #define VIDEO2_WATCH_DOG_BIT 8
38198+ #define VIDEO2_WATCH_DOG_MASK 0x00000100
38199+ #define VIDEO2_INPUT_COMPLETE_READ 0x00000200 //Bit[9] Video2 video input complete interrupt status read back (frame complete only for frame mode)
38200+ #define VIDEO2_INPUT_COMPLETE_BIT 9
38201+ #define VIDEO2_INPUT_COMPLETE_MASK 0x00000200
38202+ #define VIDEO2_PACKET_READY_READ 0x00000400 //Bit[10] Video2 packet ready interrupt status read back
38203+ #define VIDEO2_PACKET_READY_BIT 10
38204+ #define VIDEO2_PACKET_READY_MASK 0x00000400
38205+ #define VIDEO2_COMPRESS_COMPLETE_READ 0x00000800 //Bit[11] Video2 compression complete interrupt status read back
38206+ #define VIDEO2_COMPRESS_COMPLETE_BIT 11
38207+ #define VIDEO2_COMPRESS_COMPLETE_MASK 0x00000800
38208+ #define VIDEO2_MODE_DETECTION_READY_READ 0x00001000 //Bit[12] Video2 mode detection ready interrupt status read back
38209+ #define VIDEO2_MODE_DETECTION_READY_BIT 12
38210+ #define VIDEO2_FRAME_COMPLETE_READ 0x00002000 //Bit[13] Video2 frame complete interrupt status read back
38211+ #define VIDEO2_FRAME_COMPLETE_BIT 13
38212+ #define VIDEO2_FRAME_COMPLETE_MASK 0x00002000
38213+ #define VIDEO2_STREAM_ERR_READ 0x00004000 //Bit[14] Video2 decode stream error interrupt status read back
38214+ #define VIDEO2_STREAM_ERR_BIT 14
38215+ #define VIDEO2_STREAM_ERR_MASK 0x00004000
38216+ //need check spec
38217+ #define VIDEOM_INPUT_COMPLETE_READ 0x00010000 //Bit[16] VideoM video input complete interrupt status read back
38218+ #define VIDEOM_INPUT_COMPLETE_BIT 16
38219+ #define VIDEOM_INPUT_COMPLETE_MASK 0x00010000
38220+ #define VIDEOM_COMPRESS_COMPLETE_READ 0x00020000 //Bit[17] VideoM compression complete interrupt status read back
38221+ #define VIDEOM_COMPRESS_COMPLETE_BIT 17
38222+ #define VIDEOM_COMPRESS_COMPLETE_MASK 0x00020000
38223+ #define VIDEOM_PACKET_READY_READ 0x00040000 //Bit[18] Clear Packet ready interrupt when write 1
38224+ #define VIDEOM_PACKET_READY_BIT 18
38225+ #define VIDEOM_PACKET_READY_MASK 0x00040000
38226+ #define VIDEOM_FRAME_COMPLETE_READ 0x00080000 //Bit[19] Clear Frame complete interrupt when write 1
38227+ #define VIDEOM_FRAME_COMPLETE_BIT 19
38228+ #define VIDEOM_FRAME_COMPLETE_MASK 0x00080000
38229+
38230+#define VIDEO_INT_CONTROL_CLEAR_REG 0x308 + VIDEOBASE_OFFSET //Clear when write 1
38231+ //Clear when write 1
38232+ #define VIDEO1_WATCH_DOG_CLEAR 0x00000001 //Bit[0] Clear mode detection watch dog out of lock interrupt when write 1
38233+ #define VIDEO1_INPUT_COMPLETE_CLEAR 0x00000002 //Bit[1] Clear video input complete interrupt when write 1 (frame complete only for frame mode)
38234+ #define VIDEO1_PACKET_READY_CLEAR 0x00000004 //Bit[2] Clear Packet ready interrupt when write 1
38235+ #define VIDEO1_PACKET_READY_CLEAR_BIT 2
38236+ #define VIDEO1_PACKET_READY_CLEAR_MASK 0x00000004
38237+ #define VIDEO1_COMPRESS_COMPLETE_CLEAR 0x00000008 //Bit[3] Clear video compression interrupt when write 1
38238+ #define VIDEO1_MODE_DETECTION_READY_CLEAR 0x00000010 //Bit[4] Clear Video1 Mode detection ready interrupt when write 1
38239+ #define VIDEO1_FRAME_COMPLETE_CLEAR 0x00000020 //Bit[5] Clear Frame complete interrupt when write 1
38240+ #define VIDEO1_FRAME_COMPLETE_CLEAR_BIT 5
38241+ #define VIDEO1_FRAME_COMPLETE_CLEAR_MASK 0x00000020
38242+ #define VIDEO1_STREAM_ERR_CLEAR 0x00000040 //Bit[6] Clear decode stream error interrupt when write 1
38243+ #define VIDEO2_WATCH_DOG_CLEAR 0x00000100 //Bit[8] Clear Mode detection interrupt when write 1
38244+ #define VIDEO2_INPUT_COMPLETE_CLEAR 0x00000200 //Bit[9] Clear video input complete interrupt when write 1
38245+ #define VIDEO2_PACKET_READY_CLEAR 0x00000400 //Bit[10] Clear packet ready interrupt when write 1
38246+ #define VIDEO2_COMPRESS_COMPLETE_CLEAR 0x00000800 //Bit[11] Clear video compression complete interrupt when write 1
38247+ #define VIDEO2_MODE_DETECTION_READY_CLEAR 0x00001000 //Bit[12] Clear Video2 Mode detection ready interrupt when write 1
38248+ #define VIDEO2_FRAME_COMPLETE_CLEAR 0x00002000 //Bit[13] Clear Frame complete interrupt when write 1 (frame complete only for frame mode)
38249+ #define VIDEO2_STREAM_ERR_CLEAR 0x00004000 //Bit[14] Clear Decode stream error interrupt when write 1
38250+ //need check spec
38251+ #define VIDEOM_INPUT_COMPLETE_CLEAR 0x00010000 //Bit[16] Clear video input complete interrupt when write 1
38252+ #define VIDEOM_COMPRESS_COMPLETE_CLEAR 0x00020000 //Bit[17] Clear compression complete interrupt when write 1
38253+ #define VIDEOM_COMPRESS_COMPLETE_CLEAR_BIT 17
38254+ #define VIDEOM_COMPRESS_COMPLETE_CLEAR_MASK 0x00020000
38255+ #define VIDEOM_PACKET_READY_CLEAR 0x00040000 //Bit[18] Clear compression complete interrupt when write 1
38256+ #define VIDEOM_PACKET_READY_CLEAR_BIT 18
38257+ #define VIDEOM_PACKET_READY_CLEAR_MASK 0x00040000
38258+ #define VIDEOM_FRAME_COMPLETE_CLEAR 0x00100000 //Bit[20] Clear Frame complete interrupt when write 1
38259+ #define VIDEOM_FRAME_COMPLETE_CLEAR_BIT 20
38260+ #define VIDEOM_FRAME_COMPLETE_CLEAR_MASK 0x00100000
38261+ #define VIDEOM_STREAM_ERR_CLEAR 0x00200000 //Bit[21] Clear decode stream error interrupt when write 1
38262+
38263+#define VIDEO_MODE_DETECTION_PARAM_REG 0x30C + VIDEOBASE_OFFSET
38264+ #define EDGE_PIXEL_THRES_BIT 8 //Bit[15:8] Mode detection edge pixel threshold
38265+ #define EDGE_PIXEL_THRES_MASK 0x0000FF00
38266+ #define VER_STABLE_MAX_BIT 16 //Bit[19:16] Mode detection vertical stable maximum
38267+ #define VER_STABLE_MAX_BIT_MASK 0x000F0000
38268+ #define HOR_STABLE_MAX_BIT 20 //Bit[23:20] Mode detection horizontal stable maximum
38269+ #define HOR_STABLE_MAX_BIT_MASK 0x00F00000
38270+ #define VER_STABLE_THRES_BIT 24 //Bit[27:24] Mode detection vertical stable threshold
38271+ #define VER_STABLE_THRES_BIT_MASK 0x0F000000
38272+ #define HOR_STABLE_THRES_BIT 28 //Bit[31:28] Mode detection horizontal stable threshold
38273+ #define HOR_STABLE_THRES_BIT_MASK 0xF0000000
38274+
38275+#define VIDEO_CRC_PRIMARY_REG 0x320 + VIDEOBASE_OFFSET
38276+ #define CRC_CHECK_EN 0x00000001 //Bit[0] Video port 1/2 Enable video capture write CRC check
38277+ #define CRC_CHECK_EN_BIT 0
38278+ #define CRC_CHECK_HIGH 0x00000002 //Bit[1] Video port 1/2 CRC check high bit only
38279+ #define CRC_CHECK_HIGH_BIT 1
38280+ #define SKIP_COUNT_MAX 0x00000004 //Bit[7:2] Video port 1/2 Max capture write skip count
38281+ #define SKIP_COUNT_MAX_BIT 2
38282+ #define SKIP_COUNT_MAX_MASK 0x000000FC
38283+ #define CRC_PRIMARY_POLY_LOW 0x00000100 //Bit[15:8] Primary CRC low 8-bit polynomial
38284+ #define CRC_RIMARY_POLY_LOW_BIT 8
38285+ #define CRC_RIMARY_POLY_LOW_MASK 0x0000FF00
38286+ #define CRC_PRIMARY_POLY_HIGH 0x00010000 //Bit[31:16] Primary CRC high 8-bit polynomial
38287+ #define CRC_RIMARY_POLY_HIGH_BIT 16
38288+ #define CRC_RIMARY_POLY_HIGH_MASK 0xFFFF0000
38289+
38290+
38291+#define VIDEO_CRC_SECOND_REG 0x324 + VIDEOBASE_OFFSET
38292+ #define CRC_SECOND_POLY_LOW 0x00000100 //Bit[15:8] Secondary CRC low 8-bit polynomial
38293+ #define CRC_SECOND_POLY_LOW_BIT 8
38294+ #define CRC_SECOND_POLY_LOW_MASK 0x0000FF00
38295+ #define CRC_SECOND_POLY_HIGH 0x00010000 //Bit[31:16] Secondary CRC high 8-bit polynomial
38296+ #define CRC_SECOND_POLY_HIGH_BIT 16
38297+ #define CRC_SECOND_POLY_HIGH_MASK 0xFFFF0000
38298+
38299+#define VIDEO1_RC4_KEYS_REG 0x400 + VIDEOBASE_OFFSET //Total Video1 RC4 Keys
38300+#define VIDEO2_RC4_KEYS_REG 0x500 + VIDEOBASE_OFFSET //Total Video2 RC4 Keys
38301+#define VIDEOM_RC4_KEYS_REG 0x600 + VIDEOBASE_OFFSET //Total VideoM RC4 Keys
38302+
38303+#endif /* end of _VREG_H_ */
38304+
38305diff --git a/boards.cfg b/boards.cfg
38306index 6a368de..674896b 100644
38307--- a/boards.cfg
38308+++ b/boards.cfg
38309@@ -72,6 +72,7 @@ mini2440 arm arm920t mini2440 friendl
38310 VCMA9 arm arm920t vcma9 mpl s3c24x0
38311 smdk2410 arm arm920t - samsung s3c24x0
38312 omap1510inn arm arm925t - ti
38313+ast2400 arm arm926ejs ast2400 aspeed aspeed
38314 integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_S
38315 integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S
38316 aspenite arm arm926ejs - Marvell armada100
38317diff --git a/common/Makefile b/common/Makefile
38318index 53c92ef..6ba5f38 100644
38319--- a/common/Makefile
38320+++ b/common/Makefile
38321@@ -190,6 +190,8 @@ COBJS-$(CONFIG_CMD_ZIP) += cmd_zip.o
38322 COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
38323
38324 # others
38325+OBJS-$(CONFIG_CMD_NETTEST) += cmd_nettest.o
38326+COBJS-$(CONFIG_CMD_SLT) += cmd_slt.o
38327 COBJS-$(CONFIG_BOOTSTAGE) += bootstage.o
38328 COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
38329 COBJS-y += flash.o
38330diff --git a/common/cmd_nettest.c b/common/cmd_nettest.c
38331new file mode 100644
38332index 0000000..249d7b6
38333--- /dev/null
38334+++ b/common/cmd_nettest.c
38335@@ -0,0 +1,214 @@
38336+/*
38337+ * This program is distributed in the hope that it will be useful,
38338+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
38339+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38340+ * GNU General Public License for more details.
38341+ *
38342+ * You should have received a copy of the GNU General Public License
38343+ * along with this program; if not, write to the Free Software
38344+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38345+*/
38346+
38347+#include <common.h>
38348+#include <command.h>
38349+#include <COMMINF.H>
38350+
38351+#ifdef SLT_UBOOT
38352+extern int main_function(int argc, char *argv[]);
38353+
38354+int do_mactest (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
38355+{
38356+ ModeSwitch = MODE_DEDICATED;
38357+ return main_function( argc, argv);
38358+}
38359+
38360+int do_ncsitest (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
38361+{
38362+ ModeSwitch = MODE_NSCI;
38363+ return main_function( argc, argv);
38364+}
38365+
38366+U_BOOT_CMD(
38367+ mactest, CONFIG_SYS_MAXARGS, 0, do_mactest,
38368+ "mactest - Dedicated LAN test program \n",
38369+ NULL
38370+);
38371+U_BOOT_CMD(
38372+ ncsitest, CONFIG_SYS_MAXARGS, 0, do_ncsitest,
38373+ "ncsitest- Share LAN (NC-SI) test program \n",
38374+ NULL
38375+);
38376+
38377+// ------------------------------------------------------------------------------
38378+int do_phyread (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
38379+{
38380+ int MACnum;
38381+ int PHYreg;
38382+ ULONG result_data;
38383+ int ret = 0;
38384+ int PHYaddr;
38385+ int timeout = 0;
38386+
38387+ do {
38388+ if ( argc != 4 ) {
38389+ printf(" Wrong parameter number.\n" );
38390+ printf(" phyr mac addr reg\n" );
38391+ printf(" mac : 0 or 1. [hex]\n" );
38392+ printf(" PHY addr: 0 to 31. [hex]\n" );
38393+ printf(" register: 0 to 0xFF.[hex]\n" );
38394+ printf(" example: phyr 0 0 1\n" );
38395+ ret = -1;
38396+ break;
38397+ }
38398+
38399+ MACnum = strtoul(argv[1], NULL, 16);
38400+ PHYaddr = strtoul(argv[2], NULL, 16);
38401+ PHYreg = strtoul(argv[3], NULL, 16);
38402+
38403+ if ( MACnum == 0 ) {
38404+ // Set MAC 0
38405+ H_MAC_BASE = MAC_BASE1;
38406+ }
38407+ else if ( MACnum == 1 ) {
38408+ // Set MAC 1
38409+ H_MAC_BASE = MAC_BASE2;
38410+ }
38411+ else {
38412+ printf("wrong parameter (mac number)\n");
38413+ ret = -1;
38414+ break;
38415+ }
38416+ MAC_PHYBASE = H_MAC_BASE;
38417+
38418+ if ( ( PHYaddr < 0 ) || ( PHYaddr > 31 ) ) {
38419+ printf("wrong parameter (PHY address)\n");
38420+ ret = -1;
38421+ break;
38422+ }
38423+
38424+ MAC_40h_old = ReadSOC_DD( H_MAC_BASE + 0x40 );
38425+ AST2300_NewMDIO = (MAC_40h_old & 0x80000000) ? 1 : 0;
38426+
38427+ if ( AST2300_NewMDIO ) {
38428+ WriteSOC_DD( MAC_PHYBASE + 0x60, MAC_PHYRd_New | (PHYaddr << 5) | ( PHYreg & 0x1f ) );
38429+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYBusy_New ) {
38430+ if ( ++timeout > TIME_OUT_PHY_RW ) {
38431+ ret = -1;
38432+ break;
38433+ }
38434+ }
38435+ DELAY(Delay_PHYRd);
38436+ result_data = ReadSOC_DD( MAC_PHYBASE + 0x64 ) & 0xffff;
38437+ }
38438+ else {
38439+ WriteSOC_DD( MAC_PHYBASE + 0x60, MDC_Thres | MAC_PHYRd | (PHYaddr << 16) | ((PHYreg & 0x1f) << 21) );
38440+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYRd ) {
38441+ if ( ++timeout > TIME_OUT_PHY_RW ) {
38442+ ret = -1;
38443+ break;
38444+ }
38445+ }
38446+ DELAY( Delay_PHYRd );
38447+ result_data = ReadSOC_DD( MAC_PHYBASE + 0x64 ) >> 16;
38448+ }
38449+ printf(" PHY[%d] reg[%2X] = %08lX\n", PHYaddr, PHYreg, result_data );
38450+ } while ( 0 );
38451+
38452+ return ret;
38453+}
38454+
38455+
38456+int do_phywrite (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
38457+{
38458+ int MACnum;
38459+ int PHYreg;
38460+ int PHYaddr;
38461+ ULONG reg_data;
38462+ int ret = 0;
38463+ int timeout = 0;
38464+
38465+ do {
38466+ if ( argc != 5 )
38467+ {
38468+ printf(" Wrong parameter number.\n" );
38469+ printf(" phyw mac addr reg data\n" );
38470+ printf(" mac : 0 or 1. [hex]\n" );
38471+ printf(" PHY addr: 0 to 31. [hex]\n" );
38472+ printf(" register: 0 to 0xFF. [hex]\n" );
38473+ printf(" data : 0 to 0xFFFF.[hex]\n" );
38474+ printf(" example: phyw 0 0 0 610\n" );
38475+ ret = -1;
38476+ break;
38477+ }
38478+
38479+ MACnum = strtoul(argv[1], NULL, 16);
38480+ PHYaddr = strtoul(argv[2], NULL, 16);
38481+ PHYreg = strtoul(argv[3], NULL, 16);
38482+ reg_data = strtoul(argv[4], NULL, 16);
38483+
38484+ if ( MACnum == 0 ) {
38485+ // Set MAC 0
38486+ H_MAC_BASE = MAC_BASE1;
38487+ }
38488+ else if ( MACnum == 1 ) {
38489+ // Set MAC 1
38490+ H_MAC_BASE = MAC_BASE2;
38491+ }
38492+ else {
38493+ printf("wrong parameter (mac number)\n");
38494+ ret = -1;
38495+ break;
38496+ }
38497+ MAC_PHYBASE = H_MAC_BASE;
38498+
38499+ if ( ( PHYaddr < 0 ) || ( PHYaddr > 31 ) ) {
38500+ printf("wrong parameter (PHY address)\n");
38501+ ret = -1;
38502+ break;
38503+ }
38504+
38505+ MAC_40h_old = ReadSOC_DD( H_MAC_BASE + 0x40 );
38506+ AST2300_NewMDIO = (MAC_40h_old & 0x80000000) ? 1 : 0;
38507+
38508+ if (AST2300_NewMDIO) {
38509+ WriteSOC_DD( MAC_PHYBASE + 0x60, ( reg_data << 16 ) | MAC_PHYWr_New | (PHYaddr<<5) | (PHYreg & 0x1f));
38510+
38511+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYBusy_New ) {
38512+ if ( ++timeout > TIME_OUT_PHY_RW ) {
38513+ ret = -1;
38514+ break;
38515+ }
38516+ }
38517+ }
38518+ else {
38519+ WriteSOC_DD( MAC_PHYBASE + 0x64, reg_data );
38520+ WriteSOC_DD( MAC_PHYBASE + 0x60, MDC_Thres | MAC_PHYWr | (PHYaddr<<16) | ((PHYreg & 0x1f) << 21));
38521+
38522+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYWr ) {
38523+ if ( ++timeout > TIME_OUT_PHY_RW ) {
38524+ ret = -1;
38525+ break;
38526+ }
38527+ }
38528+ } // End if (AST2300_NewMDIO)
38529+
38530+ printf("Write: PHY[%d] reg[%2X] = %08lX\n", PHYaddr, PHYreg, reg_data );
38531+ } while ( 0 );
38532+
38533+ return ret;
38534+}
38535+
38536+U_BOOT_CMD(
38537+ phyr, CONFIG_SYS_MAXARGS, 0, do_phyread,
38538+ "phyr - Read PHY register. (phyr mac addr reg)\n",
38539+ NULL
38540+);
38541+
38542+U_BOOT_CMD(
38543+ phyw, CONFIG_SYS_MAXARGS, 0, do_phywrite,
38544+ "phyw - Write PHY register. (phyw mac addr reg data)\n",
38545+ NULL
38546+);
38547+
38548+#endif // End SLT_UBOOT
38549+
38550diff --git a/common/cmd_slt.c b/common/cmd_slt.c
38551new file mode 100644
38552index 0000000..9763692
38553--- /dev/null
38554+++ b/common/cmd_slt.c
38555@@ -0,0 +1,49 @@
38556+/*
38557+ * This program is distributed in the hope that it will be useful,
38558+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
38559+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38560+ * GNU General Public License for more details.
38561+ *
38562+ * You should have received a copy of the GNU General Public License
38563+ * along with this program; if not, write to the Free Software
38564+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38565+*/
38566+
38567+#include <command.h>
38568+
38569+extern int pll_function(int argc, char *argv[]);
38570+extern int trap_function(int argc, char *argv[]);
38571+extern int dram_stress_function(int argc, char *argv[]);
38572+
38573+int do_plltest (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
38574+{
38575+ return pll_function( argc, argv);
38576+}
38577+
38578+U_BOOT_CMD(
38579+ plltest, CONFIG_SYS_MAXARGS, 0, do_plltest,
38580+ "plltest - PLLTest [pll mode] [err rate] \n",
38581+ NULL
38582+);
38583+
38584+int do_traptest (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
38585+{
38586+ return trap_function( argc, argv);
38587+}
38588+
38589+U_BOOT_CMD(
38590+ traptest, CONFIG_SYS_MAXARGS, 0, do_traptest,
38591+ "traptest- Check hardware trap for CPU clock and CPU\\AHB ratio.\n",
38592+ NULL
38593+);
38594+
38595+int do_dramtest (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
38596+{
38597+ return dram_stress_function( argc, argv);
38598+}
38599+
38600+U_BOOT_CMD(
38601+ dramtest, CONFIG_SYS_MAXARGS, 0, do_dramtest,
38602+ "dramtest- Stress DRAM.\n",
38603+ NULL
38604+);
38605diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
38606index 72e85a3..2b35587 100644
38607--- a/drivers/i2c/Makefile
38608+++ b/drivers/i2c/Makefile
38609@@ -43,6 +43,7 @@ COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
38610 COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
38611 COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o
38612 COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
38613+COBJS-$(CONFIG_DRIVER_ASPEED_I2C) += aspeed_i2c.o
38614 COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
38615 COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
38616 COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
38617diff --git a/drivers/i2c/aspeed_i2c.c b/drivers/i2c/aspeed_i2c.c
38618new file mode 100755
38619index 0000000..ff6c756
38620--- /dev/null
38621+++ b/drivers/i2c/aspeed_i2c.c
38622@@ -0,0 +1,286 @@
38623+/*
38624+ * This program is distributed in the hope that it will be useful,
38625+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
38626+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38627+ * GNU General Public License for more details.
38628+ *
38629+ * You should have received a copy of the GNU General Public License
38630+ * along with this program; if not, write to the Free Software
38631+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38632+ */
38633+
38634+#include <common.h>
38635+#include <asm/arch/aspeed_i2c.h>
38636+
38637+#ifdef CONFIG_DRIVER_ASPEED_I2C
38638+
38639+void i2c_init (int speed, int slaveadd)
38640+{
38641+ unsigned long SCURegister;
38642+//I2C Reset
38643+ SCURegister = inl (SCU_BASE + SCU_RESET_CONTROL);
38644+ outl (SCURegister & ~(0x04), SCU_BASE + SCU_RESET_CONTROL);
38645+//I2C Multi-Pin
38646+ SCURegister = inl (SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL5_REG);
38647+ outl ((SCURegister | 0x30000), SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL5_REG);
38648+//Reset
38649+ outl (0, I2C_FUNCTION_CONTROL_REGISTER);
38650+//Set AC Timing, we use fix AC timing for eeprom in u-boot
38651+ outl (AC_TIMING, I2C_AC_TIMING_REGISTER_1);
38652+ outl (0, I2C_AC_TIMING_REGISTER_2);
38653+//Clear Interrupt
38654+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38655+//Enable Master Mode
38656+ outl (MASTER_ENABLE, I2C_FUNCTION_CONTROL_REGISTER);
38657+//Enable Interrupt, STOP Interrupt has bug in AST2000
38658+ outl (0xAF, I2C_INTERRUPT_CONTROL_REGISTER);
38659+//Set Slave address, should not use for eeprom
38660+ outl (slaveadd, I2C_DEVICE_ADDRESS_REGISTER);
38661+}
38662+
38663+static int i2c_read_byte (u8 devaddr, u16 regoffset, u8 * value, int alen)
38664+{
38665+ int i2c_error = 0;
38666+ u32 status, count = 0;
38667+
38668+//Start and Send Device Address
38669+ outl (devaddr, I2C_BYTE_BUFFER_REGISTER);
38670+ outl (MASTER_START_COMMAND | MASTER_TX_COMMAND, I2C_COMMAND_REGISTER);
38671+//Wait Tx ACK
38672+ do {
38673+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & (TX_ACK | TX_NACK));
38674+ count++;
38675+ if (count == LOOP_COUNT) {
38676+ i2c_error = 1;
38677+ printf ("Start and Send Device Address can't get ACK back\n");
38678+ return i2c_error;
38679+ }
38680+ } while (status != TX_ACK);
38681+ count = 0;
38682+//Clear Interrupt
38683+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38684+//Check if address length equals to 16bits
38685+ if (alen != 1) {
38686+//Send Device Register Offset (HIGH BYTE)
38687+ outl ((regoffset & 0xFF00) >> 8, I2C_BYTE_BUFFER_REGISTER);
38688+ outl (MASTER_TX_COMMAND, I2C_COMMAND_REGISTER);
38689+//Wait Tx ACK
38690+ do {
38691+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & (TX_ACK | TX_NACK));
38692+ count++;
38693+ if (count == LOOP_COUNT) {
38694+ i2c_error = 1;
38695+ printf ("Send Device Register Offset can't get ACK back\n");
38696+ return i2c_error;
38697+ }
38698+ } while (status != TX_ACK);
38699+ count = 0;
38700+//Clear Interrupt
38701+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38702+ }
38703+//Send Device Register Offset(LOW)
38704+ outl (regoffset & 0xFF, I2C_BYTE_BUFFER_REGISTER);
38705+ outl (MASTER_TX_COMMAND, I2C_COMMAND_REGISTER);
38706+//Wait Tx ACK
38707+ do {
38708+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & (TX_ACK | TX_NACK));
38709+ count++;
38710+ if (count == LOOP_COUNT) {
38711+ i2c_error = 1;
38712+ printf ("Send Device Register Offset can't get ACK back\n");
38713+ return i2c_error;
38714+ }
38715+ } while (status != TX_ACK);
38716+ count = 0;
38717+//Clear Interrupt
38718+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38719+//Start, Send Device Address + 1 (Read Mode), Receive Data
38720+ outl (devaddr + 1, I2C_BYTE_BUFFER_REGISTER);
38721+ outl (MASTER_START_COMMAND | MASTER_TX_COMMAND | MASTER_RX_COMMAND | RX_COMMAND_LIST, I2C_COMMAND_REGISTER);
38722+//Wait Rx Done
38723+ do {
38724+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & RX_DONE);
38725+ count++;
38726+ if (count == LOOP_COUNT) {
38727+ i2c_error = 1;
38728+ printf ("Can't get RX_DONE back\n");
38729+ return i2c_error;
38730+ }
38731+ } while (status != RX_DONE);
38732+ count = 0;
38733+//Clear Interrupt
38734+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38735+//Enable Interrupt + Stop Interrupt
38736+ outl (0xBF, I2C_INTERRUPT_CONTROL_REGISTER);
38737+//Issue Stop Command
38738+ outl (MASTER_STOP_COMMAND, I2C_COMMAND_REGISTER);
38739+//Wait Stop
38740+ do {
38741+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & STOP_DONE);
38742+ count++;
38743+ if (count == LOOP_COUNT) {
38744+ i2c_error = 1;
38745+ printf ("Can't get STOP back\n");
38746+ return i2c_error;
38747+ }
38748+ } while (status != STOP_DONE);
38749+//Disable Stop Interrupt
38750+ outl (0xAF, I2C_INTERRUPT_CONTROL_REGISTER);
38751+//Clear Interrupt
38752+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38753+//Read Received Data
38754+ *value = ((inl (I2C_BYTE_BUFFER_REGISTER) & 0xFF00) >> 8);
38755+
38756+ return i2c_error;
38757+}
38758+
38759+static int i2c_write_byte (u8 devaddr, u16 regoffset, u8 value, int alen)
38760+{
38761+ int i2c_error = 0;
38762+ u32 status, count = 0;
38763+
38764+//Start and Send Device Address
38765+ outl (devaddr, I2C_BYTE_BUFFER_REGISTER);
38766+ outl (MASTER_START_COMMAND | MASTER_TX_COMMAND, I2C_COMMAND_REGISTER);
38767+//Wait Tx ACK
38768+ do {
38769+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & (TX_ACK | TX_NACK));
38770+ count++;
38771+ if (status == TX_NACK) {
38772+//Clear Interrupt
38773+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38774+//Re-send Start and Send Device Address while NACK return
38775+ outl (devaddr, I2C_BYTE_BUFFER_REGISTER);
38776+ outl (MASTER_START_COMMAND | MASTER_TX_COMMAND, I2C_COMMAND_REGISTER);
38777+ }
38778+ else {
38779+ if (count == LOOP_COUNT) {
38780+ i2c_error = 1;
38781+ printf ("Start and Send Device Address can't get ACK back\n");
38782+ return i2c_error;
38783+ }
38784+ }
38785+ } while (status != TX_ACK);
38786+ count = 0;
38787+//Clear Interrupt
38788+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38789+//Check if address length equals to 16bits
38790+ if (alen != 1) {
38791+//Send Device Register Offset (HIGH BYTE)
38792+ outl ((regoffset & 0xFF00) >> 8, I2C_BYTE_BUFFER_REGISTER);
38793+ outl (MASTER_TX_COMMAND, I2C_COMMAND_REGISTER);
38794+//Wait Tx ACK
38795+ do {
38796+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & (TX_ACK | TX_NACK));
38797+ count++;
38798+ if (count == LOOP_COUNT) {
38799+ i2c_error = 1;
38800+ printf ("Send Device Register Offset can't get ACK back\n");
38801+ return i2c_error;
38802+ }
38803+ } while (status != TX_ACK);
38804+ count = 0;
38805+//Clear Interrupt
38806+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38807+ }
38808+//Send Device Register Offset
38809+ outl (regoffset & 0xFF, I2C_BYTE_BUFFER_REGISTER);
38810+ outl (MASTER_TX_COMMAND, I2C_COMMAND_REGISTER);
38811+//Wait Tx ACK
38812+ do {
38813+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & (TX_ACK | TX_NACK));
38814+ count++;
38815+ if (count == LOOP_COUNT) {
38816+ i2c_error = 1;
38817+ printf ("Send Device Register Offset can't get ACK back\n");
38818+ return i2c_error;
38819+ }
38820+ } while (status != TX_ACK);
38821+ count = 0;
38822+//Clear Interrupt
38823+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38824+//Send Device Register Value
38825+ outl (value, I2C_BYTE_BUFFER_REGISTER);
38826+ outl (MASTER_TX_COMMAND, I2C_COMMAND_REGISTER);
38827+//Wait Tx ACK
38828+ do {
38829+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & (TX_ACK | TX_NACK));
38830+ count++;
38831+ if (count == LOOP_COUNT) {
38832+ i2c_error = 1;
38833+ printf ("Send Device Register Value can't get ACK back\n");
38834+ return i2c_error;
38835+ }
38836+ } while (status != TX_ACK);
38837+ count = 0;
38838+//Clear Interrupt
38839+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38840+//Enable Interrupt + Stop Interrupt
38841+ outl (0xBF, I2C_INTERRUPT_CONTROL_REGISTER);
38842+//Issue Stop Command
38843+ outl (MASTER_STOP_COMMAND, I2C_COMMAND_REGISTER);
38844+//Wait Stop
38845+ do {
38846+ status = (inl (I2C_INTERRUPT_STATUS_REGISTER) & STOP_DONE);
38847+ count++;
38848+ if (count == LOOP_COUNT) {
38849+ i2c_error = 1;
38850+ printf ("Can't get STOP back\n");
38851+ return i2c_error;
38852+ }
38853+ } while (status != STOP_DONE);
38854+//Disable Stop Interrupt
38855+ outl (0xAF, I2C_INTERRUPT_CONTROL_REGISTER);
38856+//Clear Interrupt
38857+ outl (ALL_CLEAR, I2C_INTERRUPT_STATUS_REGISTER);
38858+
38859+ return i2c_error;
38860+}
38861+
38862+int i2c_probe (uchar chip)
38863+{
38864+//Suppose IP is always on chip
38865+ int res = 0;
38866+
38867+ return res;
38868+}
38869+
38870+int i2c_read (uchar device_addr, uint register_offset, int alen, uchar * buffer, int len)
38871+{
38872+ int i;
38873+
38874+ if ((alen == 1) && ((register_offset + len) > 256)) {
38875+ printf ("Register index overflow\n");
38876+ }
38877+
38878+ for (i = 0; i < len; i++) {
38879+ if (i2c_read_byte (device_addr, register_offset + i, &buffer[i], alen)) {
38880+ printf ("I2C read: I/O error\n");
38881+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
38882+ return 1;
38883+ }
38884+ }
38885+
38886+ return 0;
38887+}
38888+
38889+int i2c_write (uchar device_addr, uint register_offset, int alen, uchar * buffer, int len)
38890+{
38891+ int i;
38892+
38893+ if ((alen == 1) && ((register_offset + len) > 256)) {
38894+ printf ("Register index overflow\n");
38895+ }
38896+
38897+ for (i = 0; i < len; i++) {
38898+ if (i2c_write_byte (device_addr, register_offset + i, buffer[i], alen)) {
38899+ printf ("I2C read: I/O error\n");
38900+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
38901+ return 1;
38902+ }
38903+ }
38904+
38905+ return 0;
38906+}
38907+
38908+#endif /* CONFIG_DRIVER_ASPEED_I2C */
38909diff --git a/drivers/net/Makefile b/drivers/net/Makefile
38910index 9cf2983..a1d19ca 100644
38911--- a/drivers/net/Makefile
38912+++ b/drivers/net/Makefile
38913@@ -68,6 +68,7 @@ COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
38914 COBJS-$(CONFIG_RTL8139) += rtl8139.o
38915 COBJS-$(CONFIG_RTL8169) += rtl8169.o
38916 COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
38917+COBJS-$(CONFIG_ASPEEDNIC) += aspeednic.o
38918 COBJS-$(CONFIG_SMC91111) += smc91111.o
38919 COBJS-$(CONFIG_SMC911X) += smc911x.o
38920 COBJS-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
38921diff --git a/drivers/net/aspeednic.c b/drivers/net/aspeednic.c
38922new file mode 100644
38923index 0000000..6b1ce05
38924--- /dev/null
38925+++ b/drivers/net/aspeednic.c
38926@@ -0,0 +1,1528 @@
38927+/*
38928+ * This program is distributed in the hope that it will be useful,
38929+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
38930+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38931+ * GNU General Public License for more details.
38932+ *
38933+ * You should have received a copy of the GNU General Public License
38934+ * along with this program; if not, write to the Free Software
38935+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38936+ */
38937+
38938+#include <common.h>
38939+
38940+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && defined(CONFIG_ASPEEDNIC)
38941+
38942+#include <malloc.h>
38943+#include <net.h>
38944+#include <pci.h>
38945+
38946+
38947+/*
38948+ SCU88 D[31]: MAC1 MDIO
38949+ SCU88 D[30]: MAC1 MDC
38950+ SCU90 D[2]: MAC2 MDC/MDIO
38951+ SCU80 D[0]: MAC1 Link
38952+ SCU80 D[1]: MAC2 Link
38953+*/
38954+#define pci_find_devices NULL
38955+#define pci_read_config_dword NULL
38956+#if defined(CONFIG_AST1300)
38957+#define SCU_BASE CONFIG_SCUREG_BASE
38958+#else
38959+#define SCU_BASE 0x1E6E2000
38960+#endif
38961+#define SCU_RESET_CONTROL 0x04
38962+#define SCU_CLOCK_SELECTION 0x08
38963+#define SCU_CLOCK_CONTROL 0x0C
38964+#define SCU_MAC_CLOCK_DELAY 0x48
38965+#define SCU_SCRATCH_REGISTER 0x40
38966+#define SCU_HARDWARE_TRAPPING 0x70
38967+#define SCU_PIN_MUX 0x74
38968+#define SCU_MULTIFUNCTION_PIN_CTL1_REG 0x80
38969+#define SCU_MULTIFUNCTION_PIN_CTL3_REG 0x88
38970+#define SCU_MULTIFUNCTION_PIN_CTL5_REG 0x90
38971+#define MAC_INTERFACE 0x1C0
38972+#define GMII 0x0
38973+#define MII 0x40
38974+#define MAC1_CLOCK_ENABLE (1 << 20)
38975+#define MAC2_CLOCK_ENABLE (1 << 21)
38976+#define MAC_AHB_CLOCK_DIVIDER (0x07 << 16)
38977+#if defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST2300) || defined(CONFIG_AST3100) || defined(CONFIG_AST2400)
38978+#define MAC1_MDIO (1 << 31)
38979+#define MAC1_MDC (1 << 30)
38980+#define MAC1_PHY_LINK (1 << 0)
38981+#define MAC2_MDC_MDIO (1 << 2)
38982+#define MAC1_PHY_LINK (1 << 0)
38983+#define MAC2_PHY_LINK (1 << 1)
38984+#else
38985+#define MAC2_MDC_MDIO (1 << 20)
38986+#define MAC2_MII (1 << 21)
38987+#define MAC1_PHY_LINK (1 << 25)
38988+#define MAC2_PHY_LINK (1 << 26)
38989+#endif
38990+
38991+#if defined(CONFIG_AST1300)
38992+unsigned int aspeednic_iobase[1] = {CONFIG_MACREG_BASE};
38993+#else
38994+unsigned int aspeednic_iobase[CONFIG_ASPEED_MAC_NUMBER] = {
38995+ 0x1E660000, 0x1E680000};
38996+#endif
38997+
38998+#undef DEBUG_SROM
38999+#undef DEBUG_SROM2
39000+
39001+#undef UPDATE_SROM
39002+
39003+/* PCI Registers.
39004+ */
39005+#define PCI_CFDA_PSM 0x43
39006+
39007+#define CFRV_RN 0x000000f0 /* Revision Number */
39008+
39009+#define WAKEUP 0x00 /* Power Saving Wakeup */
39010+#define SLEEP 0x80 /* Power Saving Sleep Mode */
39011+
39012+#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
39013+
39014+/* MAC chip register */
39015+#define ISR_REG 0x00 // interrups status register
39016+#define IER_REG 0x04 // interrupt maks register
39017+#define MAC_MADR_REG 0x08 // MAC address (Most significant)
39018+#define MAC_LADR_REG 0x0c // MAC address (Least significant)
39019+
39020+#define MAHT0_REG 0x10 // Multicast Address Hash Table 0 register
39021+#define MAHT1_REG 0x14 // Multicast Address Hash Table 1 register
39022+#define TXPD_REG 0x18 // Transmit Poll Demand register
39023+#define RXPD_REG 0x1c // Receive Poll Demand register
39024+#define TXR_BADR_REG 0x20 // Transmit Ring Base Address register
39025+#define RXR_BADR_REG 0x24 // Receive Ring Base Address register
39026+
39027+#define HPTXPD_REG 0x28 //
39028+#define HPTXR_BADR_REG 0x2c //
39029+
39030+#define ITC_REG 0x30 // interrupt timer control register
39031+#define APTC_REG 0x34 // Automatic Polling Timer control register
39032+#define DBLAC_REG 0x38 // DMA Burst Length and Arbitration control register
39033+
39034+#define DMAFIFOS_REG 0x3c //
39035+#define FEAR_REG 0x44 //
39036+#define TPAFCR_REG 0x48 //
39037+#define RBSR_REG 0x4c //for NC Body
39038+#define MACCR_REG 0x50 // MAC control register
39039+#define MACSR_REG 0x54 // MAC status register
39040+#define PHYCR_REG 0x60 // PHY control register
39041+#define PHYDATA_REG 0x64 // PHY Write Data register
39042+#define FCR_REG 0x68 // Flow Control register
39043+#define BPR_REG 0x6c // back pressure register
39044+#define WOLCR_REG 0x70 // Wake-On-Lan control register
39045+#define WOLSR_REG 0x74 // Wake-On-Lan status register
39046+#define WFCRC_REG 0x78 // Wake-up Frame CRC register
39047+#define WFBM1_REG 0x80 // wake-up frame byte mask 1st double word register
39048+#define WFBM2_REG 0x84 // wake-up frame byte mask 2nd double word register
39049+#define WFBM3_REG 0x88 // wake-up frame byte mask 3rd double word register
39050+#define WFBM4_REG 0x8c // wake-up frame byte mask 4th double word register
39051+
39052+
39053+// --------------------------------------------------------------------
39054+// MACCR_REG
39055+// --------------------------------------------------------------------
39056+
39057+#define SW_RST_bit (1UL<<31) // software reset/
39058+#define DIRPATH_bit (1UL<<21)
39059+#define RX_IPCS_FAIL_bit (1UL<<20) //
39060+#define RX_TCPCS_FAIL_bit (1UL<<19) //
39061+#define SPEED_100M_MODE_bit (1UL<<19)
39062+#define RX_UDPCS_FAIL_bit (1UL<<18) //
39063+#define RX_BROADPKT_bit (1UL<<17) // Receiving broadcast packet
39064+#define RX_MULTIPKT_bit (1UL<<16) // receiving multicast packet
39065+#define RX_HT_EN_bit (1UL<<15)
39066+#define RX_ALLADR_bit (1UL<<14) // not check incoming packet's destination address
39067+#define JUMBO_LF_bit (1UL<<13) //
39068+#define RX_RUNT_bit (1UL<<12) // Store incoming packet even its length is les than 64 byte
39069+#define CRC_CHK_bit (1UL<<11) //
39070+#define CRC_APD_bit (1UL<<10) // append crc to transmit packet
39071+#define GMAC_MODE_bit (1UL<<9) //
39072+#define FULLDUP_bit (1UL<<8) // full duplex
39073+#define ENRX_IN_HALFTX_bit (1UL<<7) //
39074+#define LOOP_EN_bit (1UL<<6) // Internal loop-back
39075+#define HPTXR_EN_bit (1UL<<5) //
39076+#define REMOVE_VLAN_bit (1UL<<4) //
39077+#define RXMAC_EN_bit (1UL<<3) // receiver enable
39078+#define TXMAC_EN_bit (1UL<<2) // transmitter enable
39079+#define RXDMA_EN_bit (1UL<<1) // enable DMA receiving channel
39080+#define TXDMA_EN_bit (1UL<<0) // enable DMA transmitting channel
39081+
39082+//---------------------------------------------------
39083+// PHY R/W Register Bit
39084+//---------------------------------------------------
39085+#define MIIWR (1UL<<27)
39086+#define MIIRD (1UL<<26)
39087+#define MDC_CYCTHR 0x34
39088+#define PHY_SPEED_MASK 0xC000
39089+#define PHY_DUPLEX_MASK 0x2000
39090+#define SPEED_1000M 0x02
39091+#define SPEED_100M 0x01
39092+#define SPEED_10M 0x00
39093+#define DUPLEX_FULL 0x01
39094+#define DUPLEX_HALF 0x00
39095+#define RESOLVED_BIT 0x800
39096+
39097+#define PHY_SPEED_DUPLEX_MASK 0x01E0
39098+#define PHY_100M_DUPLEX 0x0100
39099+#define PHY_100M_HALF 0x0080
39100+#define PHY_10M_DUPLEX 0x0040
39101+#define PHY_10M_HALF 0x0020
39102+
39103+
39104+
39105+/* Descriptor bits.
39106+ */
39107+#define TXDMA_OWN 0x80000000 /* Own Bit */
39108+#define RXPKT_RDY 0x00000000
39109+#define RXPKT_STATUS 0x80000000
39110+//#define EDORR 0x00008000 /* Receive End Of Ring */
39111+#define EDORR 0x40000000 /* Receive End Of Ring */
39112+#define LRS 0x10000000 /* Last Descriptor */
39113+#define RD_ES 0x00008000 /* Error Summary */
39114+//#define EDOTR 0x00008000 /* Transmit End Of Ring */
39115+#define EDOTR 0x40000000 /* Transmit End Of Ring */
39116+#define T_OWN 0x80000000 /* Own Bit */
39117+#define LTS 0x10000000 /* Last Segment */
39118+#define FTS 0x20000000 /* First Segment */
39119+#define CRC_ERR 0x00080000
39120+#define TD_ES 0x00008000 /* Error Summary */
39121+#define TD_SET 0x08000000 /* Setup Packet */
39122+#define RX_ERR 0x00040000
39123+#define FTL 0x00100000
39124+#define RUNT 0x00200000
39125+#define RX_ODD_NB 0x00400000
39126+
39127+#define POLL_DEMAND 1
39128+#define RESET_DE4X5(dev) { \
39129+ int i; \
39130+ i=INL(dev, MACCR_REG); \
39131+ udelay(1000); \
39132+ OUTL(dev, i | SW_RST_bit, MACCR_REG); \
39133+ for (; (INL(dev, MACCR_REG ) & SW_RST_bit) != 0; ) {udelay(1000);} \
39134+ OUTL(dev, 0, IER_REG ); \
39135+ }
39136+
39137+#define START_MAC(dev) { \
39138+ s32 omr; \
39139+ omr = INL(dev, MACCR_REG); \
39140+ omr |= RXMAC_EN_bit | TXMAC_EN_bit | RXDMA_EN_bit | TXDMA_EN_bit; \
39141+ OUTL(dev, omr, MACCR_REG); /* Enable the TX and/or RX */ \
39142+ }
39143+
39144+#define STOP_MAC(dev) { \
39145+ s32 omr; \
39146+ omr = INL(dev, MACCR_REG); \
39147+ omr &= ~(RXMAC_EN_bit | TXMAC_EN_bit | RXDMA_EN_bit | TXDMA_EN_bit); \
39148+ OUTL(dev, omr, MACCR_REG); /* Disable the TX and/or RX */ \
39149+ }
39150+
39151+#define NUM_RX_DESC PKTBUFSRX
39152+#define NUM_TX_DESC 1 /* Number of TX descriptors */
39153+#define RX_BUFF_SZ PKTSIZE_ALIGN
39154+#define TX_BUFF_SZ 1514
39155+
39156+#define TOUT_LOOP 1000000
39157+#define PHY_LOOP 250
39158+#define ETH_ALEN 6
39159+#define NCSI_LOOP 1500000
39160+#define RETRY_COUNT 1
39161+
39162+struct de4x5_desc {
39163+ volatile s32 status;
39164+ u32 des1;
39165+ u32 reserved;
39166+ u32 buf;
39167+};
39168+
39169+//PHY Information
39170+#define PHYID_VENDOR_MASK 0xfffffc00
39171+#define PHYID_VENDOR_MODEL_MASK 0xfffffff0
39172+#define PHYID_VENDOR_MARVELL 0x01410c00
39173+#define PHYID_VENDOR_BROADCOM 0x00406000
39174+#define PHYID_VENDOR_REALTEK 0x001cc800
39175+#define PHYID_RTL8201EL 0x001cc810
39176+#define PHYID_RTL8211 0x001cc910
39177+#define PHYID_BCM54612E 0x03625E6A
39178+
39179+//NCSI define & structure
39180+//NC-SI Command Packet
39181+typedef struct {
39182+//Ethernet Header
39183+ unsigned char DA[6];
39184+ unsigned char SA[6];
39185+ unsigned short EtherType; //DMTF NC-SI
39186+//NC-SI Control Packet
39187+ unsigned char MC_ID; //Management Controller should set this field to 0x00
39188+ unsigned char Header_Revision; //For NC-SI 1.0 spec, this field has to set 0x01
39189+ unsigned char Reserved_1; //Reserved has to set to 0x00
39190+ unsigned char IID; //Instance ID
39191+ unsigned char Command;
39192+ unsigned char Channel_ID;
39193+ unsigned short Payload_Length; //Payload Length = 12 bits, 4 bits are reserved
39194+ unsigned long Reserved_2;
39195+ unsigned long Reserved_3;
39196+} NCSI_Command_Packet;
39197+
39198+unsigned char Payload_Data[16];
39199+unsigned char Payload_Pad[4] = {0x00, 0x00, 0x00, 0x00};
39200+unsigned long Payload_Checksum = 0x00000000;
39201+
39202+
39203+//Command and Response Type
39204+#define CLEAR_INITIAL_STATE 0x00 //M
39205+#define SELECT_PACKAGE 0x01 //M
39206+#define DESELECT_PACKAGE 0x02 //M
39207+#define ENABLE_CHANNEL 0x03 //M
39208+#define DISABLE_CHANNEL 0x04 //M
39209+#define RESET_CHANNEL 0x05 //M
39210+#define ENABLE_CHANNEL_NETWORK_TX 0x06 //M
39211+#define DISABLE_CHANNEL_NETWORK_TX 0x07 //M
39212+#define AEN_ENABLE 0x08
39213+#define SET_LINK 0x09 //M
39214+#define GET_LINK_STATUS 0x0A //M
39215+#define SET_VLAN_FILTER 0x0B //M
39216+#define ENABLE_VLAN 0x0C //M
39217+#define DISABLE_VLAN 0x0D //M
39218+#define SET_MAC_ADDRESS 0x0E //M
39219+#define ENABLE_BROADCAST_FILTERING 0x10 //M
39220+#define DISABLE_BROADCAST_FILTERING 0x11 //M
39221+#define ENABLE_GLOBAL_MULTICAST_FILTERING 0x12
39222+#define DISABLE_GLOBAL_MULTICAST_FILTERING 0x13
39223+#define SET_NCSI_FLOW_CONTROL 0x14
39224+#define GET_VERSION_ID 0x15 //M
39225+#define GET_CAPABILITIES 0x16 //M
39226+#define GET_PARAMETERS 0x17 //M
39227+#define GET_CONTROLLER_PACKET_STATISTICS 0x18
39228+#define GET_NCSI_STATISTICS 0x19
39229+#define GET_NCSI_PASS_THROUGH_STATISTICS 0x1A
39230+
39231+//NC-SI Response Packet
39232+typedef struct {
39233+ unsigned char DA[6];
39234+ unsigned char SA[6];
39235+ unsigned short EtherType; //DMTF NC-SI
39236+//NC-SI Control Packet
39237+ unsigned char MC_ID; //Management Controller should set this field to 0x00
39238+ unsigned char Header_Revision; //For NC-SI 1.0 spec, this field has to set 0x01
39239+ unsigned char Reserved_1; //Reserved has to set to 0x00
39240+ unsigned char IID; //Instance ID
39241+ unsigned char Command;
39242+ unsigned char Channel_ID;
39243+ unsigned short Payload_Length; //Payload Length = 12 bits, 4 bits are reserved
39244+ unsigned short Reserved_2;
39245+ unsigned short Reserved_3;
39246+ unsigned short Reserved_4;
39247+ unsigned short Reserved_5;
39248+ unsigned short Response_Code;
39249+ unsigned short Reason_Code;
39250+ unsigned char Payload_Data[64];
39251+} NCSI_Response_Packet;
39252+
39253+NCSI_Command_Packet NCSI_Request;
39254+NCSI_Response_Packet NCSI_Respond;
39255+
39256+//Standard Response Code
39257+#define COMMAND_COMPLETED 0x00
39258+#define COMMAND_FAILED 0x01
39259+#define COMMAND_UNAVAILABLE 0x02
39260+#define COMMAND_UNSUPPORTED 0x03
39261+
39262+//Standard Reason Code
39263+#define NO_ERROR 0x0000
39264+#define INTERFACE_INITIALIZATION_REQUIRED 0x0001
39265+#define PARAMETER_IS_INVALID 0x0002
39266+#define CHANNEL_NOT_READY 0x0003
39267+#define PACKAGE_NOT_READY 0x0004
39268+#define INVALID_PAYLOAD_LENGTH 0x0005
39269+#define UNKNOWN_COMMAND_TYPE 0x7FFF
39270+
39271+
39272+struct AEN_Packet {
39273+//Ethernet Header
39274+ unsigned char DA[6];
39275+ unsigned char SA[6]; //Network Controller SA = FF:FF:FF:FF:FF:FF
39276+ unsigned short EtherType; //DMTF NC-SI
39277+//AEN Packet Format
39278+ unsigned char MC_ID; //Network Controller should set this field to 0x00
39279+ unsigned char Header_Revision; //For NC-SI 1.0 spec, this field has to set 0x01
39280+ unsigned char Reserved_1; //Reserved has to set to 0x00
39281+// unsigned char IID = 0x00; //Instance ID = 0 in Network Controller
39282+// unsigned char Command = 0xFF; //AEN = 0xFF
39283+ unsigned char Channel_ID;
39284+// unsigned short Payload_Length = 0x04; //Payload Length = 4 in Network Controller AEN Packet
39285+ unsigned long Reserved_2;
39286+ unsigned long Reserved_3;
39287+ unsigned char AEN_Type;
39288+// unsigned char Reserved_4[3] = {0x00, 0x00, 0x00};
39289+ unsigned long Optional_AEN_Data;
39290+ unsigned long Payload_Checksum;
39291+};
39292+
39293+//AEN Type
39294+#define LINK_STATUS_CHANGE 0x0
39295+#define CONFIGURATION_REQUIRED 0x1
39296+#define HOST_NC_DRIVER_STATUS_CHANGE 0x2
39297+
39298+typedef struct {
39299+ unsigned char Package_ID;
39300+ unsigned char Channel_ID;
39301+ unsigned long Capabilities_Flags;
39302+ unsigned long Broadcast_Packet_Filter_Capabilities;
39303+ unsigned long Multicast_Packet_Filter_Capabilities;
39304+ unsigned long Buffering_Capabilities;
39305+ unsigned long AEN_Control_Support;
39306+} NCSI_Capability;
39307+NCSI_Capability NCSI_Cap;
39308+
39309+//SET_MAC_ADDRESS
39310+#define UNICAST (0x00 << 5)
39311+#define MULTICAST (0x01 << 5)
39312+#define DISABLE_MAC_ADDRESS_FILTER 0x00
39313+#define ENABLE_MAC_ADDRESS_FILTER 0x01
39314+
39315+//GET_LINK_STATUS
39316+#define LINK_DOWN 0
39317+#define LINK_UP 1
39318+
39319+static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
39320+static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
39321+static int rx_new; /* RX descriptor ring pointer */
39322+static int tx_new; /* TX descriptor ring pointer */
39323+static unsigned char tx_buffer[NUM_TX_DESC][TX_BUFF_SZ] __attribute__ ((aligned(32)));
39324+static unsigned char rx_buffer[NUM_RX_DESC][RX_BUFF_SZ] __attribute__ ((aligned(32)));
39325+
39326+
39327+static char rxRingSize;
39328+static char txRingSize;
39329+static unsigned int InstanceID = 0;
39330+static int Retry = 0;
39331+
39332+static int aspeednic_init(struct eth_device* dev, bd_t* bis);
39333+static int aspeednic_send(struct eth_device* dev, volatile void *packet, int length);
39334+static int aspeednic_recv(struct eth_device* dev);
39335+static void aspeednic_halt(struct eth_device* dev);
39336+static void set_mac_address (struct eth_device* dev, bd_t* bis);
39337+static void phy_write_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address, u16 PHY_Data);
39338+static u16 phy_read_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address);
39339+static void set_mac_control_register(struct eth_device* dev);
39340+
39341+#if defined(CONFIG_E500)
39342+#define phys_to_bus(a) (a)
39343+#else
39344+#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
39345+#endif
39346+
39347+static int INL(struct eth_device* dev, u_long addr)
39348+{
39349+ return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
39350+}
39351+
39352+static void OUTL(struct eth_device* dev, int command, u_long addr)
39353+{
39354+ *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
39355+}
39356+
39357+
39358+struct eth_device aspeednic_device[CONFIG_ASPEED_MAC_NUMBER];
39359+
39360+void NCSI_Struct_Initialize(void)
39361+{
39362+ unsigned long i;
39363+
39364+ for (i = 0; i < 6; i++) {
39365+ NCSI_Request.DA[i] = 0xFF;
39366+ NCSI_Respond.DA[i] = 0xFF;
39367+ NCSI_Respond.SA[i] = 0xFF;
39368+ }
39369+ NCSI_Request.EtherType = 0xF888;
39370+ NCSI_Request.MC_ID = 0;
39371+ NCSI_Request.Header_Revision = 0x01;
39372+ NCSI_Request.Reserved_1 = 0;
39373+ NCSI_Request.Reserved_2 = 0;
39374+ NCSI_Request.Reserved_3 = 0;
39375+ NCSI_Respond.EtherType = 0xF888;
39376+ NCSI_Respond.MC_ID = 0;
39377+ NCSI_Respond.Header_Revision = 0x01;
39378+ NCSI_Respond.Reserved_1 = 0;
39379+ NCSI_Respond.Reserved_2 = 0;
39380+ NCSI_Respond.Reserved_3 = 0;
39381+}
39382+
39383+int aspeednic_initialize(bd_t *bis)
39384+{
39385+ int card_number = 0;
39386+ unsigned int iobase, SCURegister;
39387+ struct eth_device* dev;
39388+
39389+#if defined(CONFIG_AST2300_FPGA_2) || defined(CONFIG_AST2300) || defined(CONFIG_AST3100) || defined(CONFIG_AST2400)
39390+//AST2300
39391+//MAC1 CLOCK/RESET/PHY_LINK/MDC_MDIO in SCU
39392+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL));
39393+ *(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL) = cpu_to_le32(SCURegister | 0x800);
39394+ udelay(100);
39395+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_CLOCK_CONTROL));
39396+ *(volatile u_long *)(SCU_BASE + SCU_CLOCK_CONTROL) = cpu_to_le32(SCURegister & ~(MAC1_CLOCK_ENABLE));
39397+ udelay(10000);
39398+//Add Clock Selection in AST2300 A1, Please check the datasheet for more detail
39399+//The current sample code uses 0: H-PLL/2 because all EVBs have RGMII interface
39400+// SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_CLOCK_SELECTION));
39401+// *(volatile u_long *)(SCU_BASE + SCU_CLOCK_SELECTION) = cpu_to_le32(SCURegister & ~(MAC_AHB_CLOCK_DIVIDER));
39402+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL));
39403+ *(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL) = cpu_to_le32(SCURegister & ~(0x800));
39404+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL3_REG));
39405+ *(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL3_REG) = cpu_to_le32(SCURegister | (MAC1_MDIO | MAC1_MDC));
39406+// SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_MAC_CLOCK_DELAY));
39407+//Currently we use fix value in MAC timing on EVB
39408+// *(volatile u_long *)(SCU_BASE + SCU_MAC_CLOCK_DELAY) = CONFIG_MAC_INTERFACE_CLOCK_DELAY;
39409+#ifdef CONFIG_MAC1_PHY_LINK_INTERRUPT
39410+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL1_REG));
39411+ *(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL1_REG) = cpu_to_le32(SCURegister | (MAC1_PHY_LINK));
39412+#endif
39413+
39414+//MAC2 CLOCK/RESET/PHY_LINK/MDC_MDIO
39415+#ifdef CONFIG_MAC2_ENABLE
39416+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL));
39417+ *(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL) = cpu_to_le32(SCURegister | 0x1000);
39418+ udelay(10);
39419+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_CLOCK_CONTROL));
39420+ *(volatile u_long *)(SCU_BASE + SCU_CLOCK_CONTROL) = cpu_to_le32(SCURegister & ~(MAC2_CLOCK_ENABLE));
39421+ udelay(10000);
39422+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL));
39423+ *(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL) = cpu_to_le32(SCURegister & ~(0x1000));
39424+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL5_REG));
39425+ *(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL5_REG) = cpu_to_le32(SCURegister | (MAC2_MDC_MDIO));
39426+#endif
39427+#ifdef CONFIG_MAC2_PHY_LINK_INTERRUPT
39428+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL1_REG));
39429+ *(volatile u_long *)(SCU_BASE + SCU_MULTIFUNCTION_PIN_CTL1_REG) = cpu_to_le32(SCURegister | (MAC2_PHY_LINK));
39430+#endif
39431+#else
39432+//AST1100/AST2050/AST2100
39433+//MAC1 RESET/PHY_LINK in SCU
39434+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL));
39435+ *(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL) = cpu_to_le32(SCURegister & ~(0x800));
39436+#ifdef CONFIG_MAC1_PHY_LINK_INTERRUPT
39437+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_PIN_MUX));
39438+ *(volatile u_long *)(SCU_BASE + SCU_PIN_MUX) = cpu_to_le32(SCURegister | (MAC1_PHY_LINK));
39439+#endif
39440+
39441+//MAC2
39442+#ifdef CONFIG_MAC2_ENABLE
39443+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL));
39444+ *(volatile u_long *)(SCU_BASE + SCU_RESET_CONTROL) = cpu_to_le32(SCURegister & ~(0x1000));
39445+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_PIN_MUX));
39446+ *(volatile u_long *)(SCU_BASE + SCU_PIN_MUX) = cpu_to_le32(SCURegister | (MAC2_MDC_MDIO));
39447+#endif
39448+#ifdef CONFIG_MAC2_MII_ENABLE
39449+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_PIN_MUX));
39450+ *(volatile u_long *)(SCU_BASE + SCU_PIN_MUX) = cpu_to_le32(SCURegister | (MAC2_MII));
39451+#endif
39452+#ifdef CONFIG_MAC2_PHY_LINK_INTERRUPT
39453+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_PIN_MUX));
39454+ *(volatile u_long *)(SCU_BASE + SCU_PIN_MUX) = cpu_to_le32(SCURegister | (MAC2_PHY_LINK));
39455+#endif
39456+#endif
39457+
39458+ iobase = aspeednic_iobase[card_number];
39459+
39460+ dev = &aspeednic_device[card_number];
39461+
39462+
39463+ sprintf(dev->name, "aspeednic#%d", card_number);
39464+
39465+ dev->iobase = iobase;
39466+
39467+ if (CONFIG_MAC1_PHY_SETTING >= 1) {
39468+//NCSI Struct Initialize
39469+ NCSI_Struct_Initialize();
39470+ }
39471+//Set Scratch register (0x1E6E2040 D[15:14])(0x1E6E2041 D[7:6]) to inform kernel MAC1 driver
39472+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_SCRATCH_REGISTER));
39473+ *(volatile u_long *)(SCU_BASE + SCU_SCRATCH_REGISTER) = cpu_to_le32((SCURegister & ~(0xc000)) | (CONFIG_MAC1_PHY_SETTING << 14));
39474+//Set Scratch register (0x1E6E2040 D[13:12])(0x1E6E2041 D[5:4]) to inform kernel MAC2 driver
39475+ SCURegister = le32_to_cpu(*(volatile u_long *)(SCU_BASE + SCU_SCRATCH_REGISTER));
39476+ *(volatile u_long *)(SCU_BASE + SCU_SCRATCH_REGISTER) = cpu_to_le32((SCURegister & ~(0x3000)) | (CONFIG_MAC2_PHY_SETTING << 12));
39477+
39478+
39479+ dev->init = aspeednic_init;
39480+ dev->halt = aspeednic_halt;
39481+ dev->send = aspeednic_send;
39482+ dev->recv = aspeednic_recv;
39483+
39484+ /* Ensure we're not sleeping. */
39485+ if (CONFIG_MAC1_PHY_SETTING >= 1) {
39486+ udelay(2000000); //2.0 sec
39487+ }
39488+ else {
39489+ udelay(10 * 1000);
39490+ }
39491+
39492+
39493+ dev->init(dev, bis);
39494+
39495+ eth_register(dev);
39496+
39497+
39498+ return card_number;
39499+}
39500+
39501+void Calculate_Checksum(unsigned char *buffer_base, int Length)
39502+{
39503+ unsigned int i, CheckSum = 0;
39504+ unsigned int Data, Data1;
39505+
39506+ for (i = 0; i < ((Length - 14) / 2); i++) {
39507+ Data = buffer_base[i * 2];
39508+ Data1 = buffer_base[i * 2 + 1];
39509+ CheckSum += ((Data << 8) + Data1);
39510+ }
39511+ Payload_Checksum = (~(CheckSum) + 1); //2's complement
39512+//Inverse for insert into buffer
39513+ Data = (Payload_Checksum & 0xFF000000) >> 24;
39514+ Data1 = (Payload_Checksum & 0x000000FF) << 24;
39515+ Payload_Checksum = (Payload_Checksum & 0x00FFFF00) + Data + Data1;
39516+ Data = (Payload_Checksum & 0x00FF0000) >> 8;
39517+ Data1 = (Payload_Checksum & 0x0000FF00) << 8;
39518+ Payload_Checksum = (Payload_Checksum & 0xFF0000FF) + Data + Data1;
39519+}
39520+
39521+void copy_data (int Length)
39522+{
39523+ memcpy ((unsigned char *)(tx_ring[tx_new].buf + 30), &Payload_Data, Length);
39524+ Calculate_Checksum((unsigned char *)(tx_ring[tx_new].buf + 14), 30 + Length);
39525+ memcpy ((unsigned char *)(tx_ring[tx_new].buf + 30 + Length), &Payload_Checksum, 4);
39526+}
39527+
39528+void NCSI_Rx (void)
39529+{
39530+ unsigned long status, length, i = 0;
39531+
39532+ do {
39533+ status = (s32)le32_to_cpu(rx_ring[rx_new].status);
39534+ i++;
39535+ } while (!(((status & RXPKT_STATUS) != 0) || (i >= NCSI_LOOP)));
39536+
39537+ if (i < NCSI_LOOP) {
39538+ if (status & LRS) {
39539+ length = (le32_to_cpu(rx_ring[rx_new].status) & 0x3FFF);
39540+ memcpy (&NCSI_Respond, (unsigned char *)rx_ring[rx_new].buf, length);
39541+ }
39542+ rx_ring[rx_new].status &= cpu_to_le32(0x7FFFFFFF);
39543+ rx_new = (rx_new + 1) % rxRingSize;
39544+ }
39545+}
39546+
39547+void DeSelect_Package (struct eth_device* dev, int Package_ID)
39548+{
39549+ unsigned long Combined_Channel_ID;
39550+
39551+//TX
39552+ do {
39553+ InstanceID++;
39554+ NCSI_Request.IID = InstanceID;
39555+ NCSI_Request.Command = DESELECT_PACKAGE;
39556+ Combined_Channel_ID = (Package_ID << 5) + 0x1F; //Internal Channel ID = 0x1F, 0x1F means all channel
39557+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39558+ NCSI_Request.Payload_Length = 0;
39559+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39560+ copy_data (NCSI_Request.Payload_Length);
39561+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39562+//RX
39563+ NCSI_Rx();
39564+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (DESELECT_PACKAGE | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39565+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39566+ Retry++;
39567+ InstanceID--;
39568+ }
39569+ else {
39570+ Retry = 0;
39571+ }
39572+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39573+ Retry = 0;
39574+}
39575+
39576+int Select_Package (struct eth_device* dev, int Package_ID)
39577+{
39578+ unsigned long Combined_Channel_ID, Found = 0;
39579+
39580+//TX
39581+ do {
39582+ InstanceID++;
39583+ NCSI_Request.IID = InstanceID;
39584+ NCSI_Request.Command = SELECT_PACKAGE;
39585+ Combined_Channel_ID = (Package_ID << 5) + 0x1F; //Internal Channel ID = 0x1F
39586+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39587+ NCSI_Request.Payload_Length = (4 << 8);
39588+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39589+ NCSI_Request.Payload_Length = 4;
39590+ memset ((void *)Payload_Data, 0, 4);
39591+ Payload_Data[3] = 1; //Arbitration Disable
39592+ copy_data (NCSI_Request.Payload_Length);
39593+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39594+//RX
39595+ NCSI_Rx();
39596+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (SELECT_PACKAGE | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39597+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39598+ Retry++;
39599+ Found = 0;
39600+ InstanceID--;
39601+ }
39602+ else {
39603+ Retry = 0;
39604+ Found = 1;
39605+ }
39606+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39607+ Retry = 0;
39608+
39609+ return Found;
39610+}
39611+
39612+void DeSelect_Active_Package (struct eth_device* dev)
39613+{
39614+ unsigned long Combined_Channel_ID;
39615+//TX
39616+ do {
39617+ InstanceID++;
39618+ NCSI_Request.IID = InstanceID;
39619+ NCSI_Request.Command = DESELECT_PACKAGE;
39620+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + 0x1F; //Internal Channel ID = 0x1F, 0x1F means all channel
39621+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39622+ NCSI_Request.Payload_Length = 0;
39623+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39624+ copy_data (NCSI_Request.Payload_Length);
39625+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39626+//RX
39627+ NCSI_Rx();
39628+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (DESELECT_PACKAGE | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39629+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39630+ Retry++;
39631+ InstanceID--;
39632+ }
39633+ else {
39634+ Retry = 0;
39635+ }
39636+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39637+ Retry = 0;
39638+}
39639+
39640+int Select_Active_Package (struct eth_device* dev)
39641+{
39642+ unsigned long Combined_Channel_ID, Found = 0;
39643+//TX
39644+ do {
39645+ InstanceID++;
39646+ NCSI_Request.IID = InstanceID;
39647+ NCSI_Request.Command = SELECT_PACKAGE;
39648+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + 0x1F; //Internal Channel ID = 0x1F
39649+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39650+ NCSI_Request.Payload_Length = (4 << 8);
39651+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39652+ NCSI_Request.Payload_Length = 4;
39653+ memset ((void *)Payload_Data, 0, 4);
39654+ Payload_Data[3] = 1; //Arbitration Disable
39655+ copy_data (NCSI_Request.Payload_Length);
39656+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39657+//RX
39658+ NCSI_Rx();
39659+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (SELECT_PACKAGE | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39660+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39661+ Retry++;
39662+ Found = 0;
39663+ InstanceID--;
39664+ }
39665+ else {
39666+ Retry = 0;
39667+ Found = 1;
39668+ }
39669+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39670+ Retry = 0;
39671+
39672+ return Found;
39673+}
39674+
39675+int Clear_Initial_State (struct eth_device* dev, int Channel_ID)
39676+{
39677+ unsigned long Combined_Channel_ID, Found = 0;
39678+//TX
39679+ do {
39680+ InstanceID++;
39681+ NCSI_Request.IID = InstanceID;
39682+ NCSI_Request.Command = CLEAR_INITIAL_STATE;
39683+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + Channel_ID; //Internal Channel ID = 0
39684+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39685+ NCSI_Request.Payload_Length = 0;
39686+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39687+ copy_data (NCSI_Request.Payload_Length);
39688+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39689+//RX
39690+ NCSI_Rx();
39691+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (CLEAR_INITIAL_STATE | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39692+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39693+ Retry++;
39694+ Found = 0;
39695+ InstanceID--;
39696+ }
39697+ else {
39698+ Retry = 0;
39699+ Found = 1;
39700+ }
39701+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39702+ Retry = 0;
39703+
39704+ return Found;
39705+}
39706+
39707+void Get_Version_ID (struct eth_device* dev)
39708+{
39709+ unsigned long Combined_Channel_ID;
39710+//TX
39711+ do {
39712+ InstanceID++;
39713+ NCSI_Request.IID = InstanceID;
39714+ NCSI_Request.Command = GET_VERSION_ID;
39715+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39716+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39717+ NCSI_Request.Payload_Length = 0;
39718+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39719+ copy_data (NCSI_Request.Payload_Length);
39720+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39721+//RX
39722+ NCSI_Rx();
39723+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (GET_VERSION_ID | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39724+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39725+ Retry++;
39726+ InstanceID--;
39727+ }
39728+ else {
39729+ Retry = 0;
39730+ }
39731+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39732+ Retry = 0;
39733+}
39734+
39735+void Get_Capabilities (struct eth_device* dev)
39736+{
39737+ unsigned long Combined_Channel_ID;
39738+//TX
39739+ do {
39740+ InstanceID++;
39741+ NCSI_Request.IID = InstanceID;
39742+ NCSI_Request.Command = GET_CAPABILITIES;
39743+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39744+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39745+ NCSI_Request.Payload_Length = 0;
39746+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39747+ copy_data (NCSI_Request.Payload_Length);
39748+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39749+//RX
39750+ NCSI_Rx();
39751+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (GET_CAPABILITIES | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39752+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39753+ Retry++;
39754+ InstanceID--;
39755+ }
39756+ else {
39757+ Retry = 0;
39758+ NCSI_Cap.Capabilities_Flags = NCSI_Respond.Payload_Data[0];
39759+ NCSI_Cap.Broadcast_Packet_Filter_Capabilities = NCSI_Respond.Payload_Data[1];
39760+ NCSI_Cap.Multicast_Packet_Filter_Capabilities = NCSI_Respond.Payload_Data[2];
39761+ NCSI_Cap.Buffering_Capabilities = NCSI_Respond.Payload_Data[3];
39762+ NCSI_Cap.AEN_Control_Support = NCSI_Respond.Payload_Data[4];
39763+ }
39764+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39765+ Retry = 0;
39766+}
39767+
39768+void Enable_Set_MAC_Address (struct eth_device* dev)
39769+{
39770+ unsigned long Combined_Channel_ID, i;
39771+//TX
39772+ do {
39773+ InstanceID++;
39774+ NCSI_Request.IID = InstanceID;
39775+ NCSI_Request.Command = SET_MAC_ADDRESS;
39776+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39777+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39778+ NCSI_Request.Payload_Length = (8 << 8);
39779+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39780+ NCSI_Request.Payload_Length = 8;
39781+ for (i = 0; i < 6; i++) {
39782+ Payload_Data[i] = NCSI_Request.SA[i];
39783+ }
39784+ Payload_Data[6] = 1; //MAC Address Num = 1 --> address filter 1, fixed in sample code
39785+ Payload_Data[7] = UNICAST + 0 + ENABLE_MAC_ADDRESS_FILTER; //AT + Reserved + E
39786+ copy_data (NCSI_Request.Payload_Length);
39787+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39788+//RX
39789+ NCSI_Rx();
39790+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (SET_MAC_ADDRESS | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39791+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39792+ Retry++;
39793+ InstanceID--;
39794+ }
39795+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39796+ Retry = 0;
39797+}
39798+
39799+void Enable_Broadcast_Filter (struct eth_device* dev)
39800+{
39801+ unsigned long Combined_Channel_ID;
39802+//TX
39803+ do {
39804+ InstanceID++;
39805+ NCSI_Request.IID = InstanceID;
39806+ NCSI_Request.Command = ENABLE_BROADCAST_FILTERING;
39807+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39808+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39809+ NCSI_Request.Payload_Length = (4 << 8);
39810+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39811+ NCSI_Request.Payload_Length = 4;
39812+ memset ((void *)Payload_Data, 0, 4);
39813+ Payload_Data[3] = 0xF; //ARP, DHCP, NetBIOS
39814+ copy_data (NCSI_Request.Payload_Length);
39815+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39816+//RX
39817+ NCSI_Rx();
39818+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (ENABLE_BROADCAST_FILTERING | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39819+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39820+ Retry++;
39821+ InstanceID--;
39822+ }
39823+ else {
39824+ Retry = 0;
39825+ }
39826+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39827+ Retry = 0;
39828+}
39829+
39830+void Enable_AEN (struct eth_device* dev)
39831+{
39832+ unsigned long Combined_Channel_ID;
39833+//TX
39834+ do {
39835+ InstanceID++;
39836+ NCSI_Request.IID = InstanceID;
39837+ NCSI_Request.Command = AEN_ENABLE;
39838+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39839+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39840+ NCSI_Request.Payload_Length = (8 << 8);
39841+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39842+ NCSI_Request.Payload_Length = 8;
39843+ memset ((void *)Payload_Data, 0, 8);
39844+ Payload_Data[3] = 0x00; //MC ID
39845+ Payload_Data[7] = 0x01; //Link Status only
39846+ copy_data (NCSI_Request.Payload_Length);
39847+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39848+//RX
39849+ NCSI_Rx();
39850+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (AEN_ENABLE | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39851+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39852+ Retry++;
39853+ InstanceID--;
39854+ }
39855+ else {
39856+ Retry = 0;
39857+ }
39858+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39859+ Retry = 0;
39860+}
39861+
39862+void Enable_Network_TX (struct eth_device* dev)
39863+{
39864+ unsigned long Combined_Channel_ID;
39865+//TX
39866+ do {
39867+ InstanceID++;
39868+ NCSI_Request.IID = InstanceID;
39869+ NCSI_Request.Command = ENABLE_CHANNEL_NETWORK_TX;
39870+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39871+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39872+ NCSI_Request.Payload_Length = 0;
39873+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39874+ copy_data (NCSI_Request.Payload_Length);
39875+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39876+//RX
39877+ NCSI_Rx();
39878+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (ENABLE_CHANNEL_NETWORK_TX | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39879+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39880+ Retry++;
39881+ InstanceID--;
39882+ }
39883+ else {
39884+ Retry = 0;
39885+ }
39886+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39887+ Retry = 0;
39888+}
39889+
39890+void Disable_Network_TX (struct eth_device* dev)
39891+{
39892+ unsigned long Combined_Channel_ID;
39893+//TX
39894+ do {
39895+ InstanceID++;
39896+ NCSI_Request.IID = InstanceID;
39897+ NCSI_Request.Command = DISABLE_CHANNEL_NETWORK_TX;
39898+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39899+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39900+ NCSI_Request.Payload_Length = 0;
39901+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39902+ copy_data (NCSI_Request.Payload_Length);
39903+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39904+//RX
39905+ NCSI_Rx();
39906+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (DISABLE_CHANNEL_NETWORK_TX | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39907+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39908+ Retry++;
39909+ InstanceID--;
39910+ }
39911+ else {
39912+ Retry = 0;
39913+ }
39914+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39915+ Retry = 0;
39916+}
39917+
39918+void Enable_Channel (struct eth_device* dev)
39919+{
39920+ unsigned long Combined_Channel_ID;
39921+//TX
39922+ do {
39923+ InstanceID++;
39924+ NCSI_Request.IID = InstanceID;
39925+ NCSI_Request.Command = ENABLE_CHANNEL;
39926+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39927+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39928+ NCSI_Request.Payload_Length = 0;
39929+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39930+ copy_data (NCSI_Request.Payload_Length);
39931+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39932+//RX
39933+ NCSI_Rx();
39934+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (ENABLE_CHANNEL | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39935+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39936+ Retry++;
39937+ InstanceID--;
39938+ }
39939+ else {
39940+ Retry = 0;
39941+ }
39942+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39943+ Retry = 0;
39944+}
39945+
39946+void Disable_Channel (struct eth_device* dev)
39947+{
39948+ unsigned long Combined_Channel_ID;
39949+//TX
39950+ do {
39951+ InstanceID++;
39952+ NCSI_Request.IID = InstanceID;
39953+ NCSI_Request.Command = DISABLE_CHANNEL;
39954+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39955+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39956+ NCSI_Request.Payload_Length = (4 << 8);
39957+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39958+ NCSI_Request.Payload_Length = 4;
39959+ memset ((void *)Payload_Data, 0, 4);
39960+ Payload_Data[3] = 0x1; //ALD
39961+ copy_data (NCSI_Request.Payload_Length);
39962+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39963+//RX
39964+ NCSI_Rx();
39965+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (DISABLE_CHANNEL | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39966+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39967+ Retry++;
39968+ InstanceID--;
39969+ }
39970+ else {
39971+ Retry = 0;
39972+ }
39973+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
39974+ Retry = 0;
39975+}
39976+
39977+int Get_Link_Status (struct eth_device* dev)
39978+{
39979+ unsigned long Combined_Channel_ID;
39980+//TX
39981+ do {
39982+ InstanceID++;
39983+ NCSI_Request.IID = InstanceID;
39984+ NCSI_Request.Command = GET_LINK_STATUS;
39985+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
39986+ NCSI_Request.Channel_ID = Combined_Channel_ID;
39987+ NCSI_Request.Payload_Length = 0;
39988+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
39989+ copy_data (NCSI_Request.Payload_Length);
39990+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
39991+//RX
39992+ NCSI_Rx();
39993+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (GET_LINK_STATUS | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
39994+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
39995+ Retry++;
39996+ InstanceID--;
39997+ }
39998+ else {
39999+ Retry = 0;
40000+ }
40001+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
40002+ Retry = 0;
40003+ if (NCSI_Respond.Payload_Data[3] & 0x40) {
40004+ return (NCSI_Respond.Payload_Data[3] & 0x01); //Link Up or Not
40005+ }
40006+ else {
40007+ return 0; //Auto Negotiate did not finish
40008+ }
40009+}
40010+
40011+void Set_Link (struct eth_device* dev)
40012+{
40013+ unsigned long Combined_Channel_ID;
40014+//TX
40015+ do {
40016+ InstanceID++;
40017+ NCSI_Request.IID = InstanceID;
40018+ NCSI_Request.Command = SET_LINK;
40019+ Combined_Channel_ID = (NCSI_Cap.Package_ID << 5) + NCSI_Cap.Channel_ID;
40020+ NCSI_Request.Channel_ID = Combined_Channel_ID;
40021+ NCSI_Request.Payload_Length = (8 << 8);
40022+ memcpy ((unsigned char *)tx_ring[tx_new].buf, &NCSI_Request, 30);
40023+ NCSI_Request.Payload_Length = 8;
40024+ memset ((void *)Payload_Data, 0, 8);
40025+ Payload_Data[2] = 0x02; //full duplex
40026+ Payload_Data[3] = 0x04; //100M, auto-disable
40027+ copy_data (NCSI_Request.Payload_Length);
40028+ aspeednic_send (dev, (void *)tx_ring[tx_new].buf, 30 + NCSI_Request.Payload_Length + 4);
40029+//RX
40030+ NCSI_Rx();
40031+ if ((NCSI_Respond.IID != InstanceID) || (NCSI_Respond.Command != (SET_LINK | 0x80)) || (NCSI_Respond.Response_Code != COMMAND_COMPLETED)) {
40032+ printf ("Retry: Command = %x, Response_Code = %x\n", NCSI_Request.Command, NCSI_Respond.Response_Code);
40033+ Retry++;
40034+ InstanceID--;
40035+ }
40036+ else {
40037+ Retry = 0;
40038+ }
40039+ } while ((Retry != 0) && (Retry <= RETRY_COUNT));
40040+ Retry = 0;
40041+}
40042+
40043+static int aspeednic_init(struct eth_device* dev, bd_t* bis)
40044+{
40045+ unsigned long i, Package_Found = 0, Channel_Found = 0, Re_Send = 0, Link_Status;
40046+
40047+ RESET_DE4X5(dev);
40048+ set_mac_address (dev, bis);
40049+ set_mac_control_register (dev);
40050+
40051+ for (i = 0; i < NUM_RX_DESC; i++) {
40052+ rx_ring[i].status = cpu_to_le32(RXPKT_RDY + RX_BUFF_SZ);
40053+ rx_ring[i].buf = (u32)(&rx_buffer[i]);
40054+ rx_ring[i].reserved = 0;
40055+ }
40056+
40057+ for (i=0; i < NUM_TX_DESC; i++) {
40058+ tx_ring[i].status = 0;
40059+ tx_ring[i].des1 = 0;
40060+ tx_ring[i].buf = (u32)(&tx_buffer[i]);
40061+ tx_ring[i].reserved = 0;
40062+ }
40063+
40064+ rxRingSize = NUM_RX_DESC;
40065+ txRingSize = NUM_TX_DESC;
40066+
40067+ rx_ring[rxRingSize - 1].status |= cpu_to_le32(EDORR);
40068+ tx_ring[txRingSize - 1].status |= cpu_to_le32(EDOTR);
40069+
40070+ OUTL(dev, ((u32) &tx_ring), TXR_BADR_REG);
40071+ OUTL(dev, ((u32) &rx_ring), RXR_BADR_REG);
40072+
40073+ START_MAC(dev);
40074+
40075+ tx_new = 0;
40076+ rx_new = 0;
40077+
40078+ if (CONFIG_MAC1_PHY_SETTING >= 1) {
40079+//NCSI Start
40080+//DeSelect Package/ Select Package
40081+ for (i = 0; i < 4; i++) {
40082+ DeSelect_Package (dev, i);
40083+ Package_Found = Select_Package (dev, i);
40084+ if (Package_Found == 1) {
40085+//AST2100/AST2050/AST1100 supports 1 package only in current firmware version
40086+ NCSI_Cap.Package_ID = i;
40087+// Package_Found = 0;
40088+ break;
40089+ }
40090+ }
40091+ if (Package_Found != 0) {
40092+//Initiali State
40093+ for (i = 0; i < 2; i++) { //Suppose 2 channels in current version, You could modify it to 0x1F to support 31 channels
40094+ Channel_Found = Clear_Initial_State(dev, i);
40095+ if (Channel_Found == 1) {
40096+ NCSI_Cap.Channel_ID = i;
40097+ printf ("Found NCSI Network Controller at (%d, %d)\n", NCSI_Cap.Package_ID, NCSI_Cap.Channel_ID);
40098+//Get Version and Capabilities
40099+ Get_Version_ID(dev);
40100+ Get_Capabilities(dev);
40101+ Select_Active_Package(dev);
40102+//Configuration
40103+ Enable_Set_MAC_Address(dev);
40104+ Enable_Broadcast_Filter(dev);
40105+//Enable TX
40106+ Enable_Network_TX(dev);
40107+//Enable Channel
40108+ Enable_Channel(dev);
40109+//Get Link Status
40110+ Re_Get_Link_Status:
40111+ Link_Status = Get_Link_Status(dev);
40112+ if (Link_Status == LINK_UP) {
40113+ printf ("Using NCSI Network Controller (%d, %d)\n", NCSI_Cap.Package_ID, NCSI_Cap.Channel_ID);
40114+ break;
40115+ }
40116+ else if ((Link_Status == LINK_DOWN) && (Re_Send < 2)) {
40117+ Re_Send++;
40118+ goto Re_Get_Link_Status;
40119+ }
40120+//Disable TX
40121+ Disable_Network_TX(dev);
40122+//Disable Channel
40123+// Disable_Channel(dev);
40124+ Re_Send = 0;
40125+ Channel_Found = 0;
40126+ }
40127+ }
40128+ }
40129+ }
40130+ return 1;
40131+}
40132+
40133+static int aspeednic_send(struct eth_device* dev, volatile void *packet, int length)
40134+{
40135+ int status = -1, oldlength = 0, fail = 0;
40136+ int i;
40137+
40138+ if (length <= 0) {
40139+ printf("%s: bad packet size: %d\n", dev->name, length);
40140+ goto Done;
40141+ }
40142+
40143+
40144+ for(i = 0; (tx_ring[tx_new].status & cpu_to_le32(TXDMA_OWN)) == 0x80000000; i++) {
40145+ if (i >= TOUT_LOOP) {
40146+ printf("%s: tx error buffer not ready\n", dev->name);
40147+ fail = 1;
40148+ goto Done;
40149+ }
40150+ }
40151+
40152+
40153+ if (length < 60) {
40154+ oldlength = length;
40155+// memset ((void *)cpu_to_le32((u32) (packet + length)), 0, 60 - length);
40156+ length = 60;
40157+ }
40158+ tx_ring[tx_new].buf = cpu_to_le32(((u32) packet));
40159+ tx_ring[tx_new].status &= (~(0x3FFF));
40160+ tx_ring[tx_new].status |= cpu_to_le32(LTS | FTS | length);
40161+ tx_ring[tx_new].status |= cpu_to_le32(TXDMA_OWN);
40162+
40163+ OUTL(dev, POLL_DEMAND, TXPD_REG);
40164+
40165+ for (i = 0; (tx_ring[tx_new].status & cpu_to_le32(TXDMA_OWN)) == 0x80000000; i++)
40166+ {
40167+ if (i >= TOUT_LOOP)
40168+ {
40169+ printf(".%s: tx buffer not ready\n", dev->name);
40170+ fail = 1;
40171+ goto Done;
40172+ }
40173+ }
40174+
40175+ if (fail != 1) {
40176+ status = oldlength;
40177+ }
40178+
40179+ Done:
40180+ tx_new = (tx_new+1) % NUM_TX_DESC;
40181+
40182+ return status;
40183+}
40184+
40185+static int aspeednic_recv(struct eth_device* dev)
40186+{
40187+ s32 status;
40188+ int length = 0;
40189+
40190+ for ( ; ; )
40191+ {
40192+ status = (s32)le32_to_cpu(rx_ring[rx_new].status);
40193+
40194+ if ((status & RXPKT_STATUS) == 0) {
40195+ break;
40196+ }
40197+
40198+ if (status & LRS) {
40199+ /* Valid frame status.
40200+ */
40201+ if (status & (RX_ERR | CRC_ERR | FTL | RUNT | RX_ODD_NB)) {
40202+
40203+ /* There was an error.
40204+ */
40205+ printf("RX error status = 0x%08X\n", status);
40206+ } else {
40207+ /* A valid frame received.
40208+ */
40209+ length = (le32_to_cpu(rx_ring[rx_new].status) & 0x3FFF);
40210+ debug("%s(): RX buffer %d, %x received\n",
40211+ __func__, rx_new, length);
40212+
40213+
40214+ /* Pass the packet up to the protocol
40215+ * layers.
40216+ */
40217+ NetReceive(rx_buffer[rx_new], length - 4);
40218+ }
40219+
40220+ /* Change buffer ownership for this frame, back
40221+ * to the adapter.
40222+ */
40223+ rx_ring[rx_new].status &= cpu_to_le32(0x7FFFFFFF);
40224+// rx_ring[rx_new].status = cpu_to_le32(RXPKT_RDY);
40225+ }
40226+
40227+ /* Update entry information.
40228+ */
40229+ rx_new = (rx_new + 1) % rxRingSize;
40230+ }
40231+
40232+ return length;
40233+}
40234+
40235+static void aspeednic_halt(struct eth_device* dev)
40236+{
40237+ STOP_MAC(dev);
40238+}
40239+
40240+static void set_mac_address (struct eth_device* dev, bd_t* bis)
40241+{
40242+ unsigned char mac_address[6]; // 6 bytes mac address
40243+ unsigned char ethaddress[20]; // string for setenv function
40244+ char *s;
40245+ int i, env; // env variable 0: eeprom, 1: environment parameters
40246+
40247+ s = getenv ("eeprom");
40248+ env = (s && (*s == 'y')) ? 0 : 1;
40249+
40250+ if (env == 0) {
40251+ env = 1;
40252+ eeprom_init ();
40253+ eeprom_read (0xA0, 0, mac_address, 6);
40254+
40255+ for (i = 0; i < 6; i++) {
40256+ if (mac_address[i] != 0xFF) {
40257+ env = 0; //Suppose not all 0xFF is valid
40258+ }
40259+ }
40260+ }
40261+
40262+ if (env == 0) { // EEPROM
40263+ sprintf (ethaddress, "%02X:%02X:%02X:%02X:%02X:%02X", mac_address[0], mac_address[1], mac_address[2], mac_address[3], mac_address[4], mac_address[5]);
40264+ setenv ("ethaddr", ethaddress);
40265+ OUTL(dev, ((mac_address[2] << 24) | (mac_address[3] << 16) | (mac_address[4] << 8) | mac_address[5]), MAC_LADR_REG);
40266+ OUTL(dev, ((mac_address[0] << 8) | mac_address[1]), MAC_MADR_REG);
40267+ if (CONFIG_MAC1_PHY_SETTING >= 1) {
40268+ for (i = 0; i < 6; i++) {
40269+ NCSI_Request.SA[i] = mac_address[i];
40270+ }
40271+ }
40272+ }
40273+ else { // Environment Parameters
40274+ OUTL(dev, ((bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5]), MAC_LADR_REG);
40275+ OUTL(dev, ((bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]), MAC_MADR_REG);
40276+ if (CONFIG_MAC1_PHY_SETTING >= 1) {
40277+ for (i = 0; i < 6; i++) {
40278+ NCSI_Request.SA[i] = bis->bi_enetaddr[i];
40279+ }
40280+ }
40281+ }
40282+
40283+}
40284+
40285+
40286+static u16 phy_read_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address)
40287+{
40288+ u32 Data, Status = 0, Loop_Count = 0, PHY_Ready = 1;
40289+ u16 Return_Data;
40290+
40291+#ifdef REALTEK_PHY_SUPPORT
40292+ PHY_Address = 0x01;
40293+#endif
40294+//20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
40295+ OUTL(dev, (PHY_Register << 21) + (PHY_Address << 16) + MIIRD + MDC_CYCTHR, PHYCR_REG);
40296+ do {
40297+ udelay(20);
40298+ Status = (INL (dev, PHYCR_REG) & MIIRD);
40299+ Loop_Count++;
40300+ if (Loop_Count >= 100) {
40301+ PHY_Ready = 0;
40302+ break;
40303+ }
40304+ } while (Status == MIIRD);
40305+
40306+ if (PHY_Ready == 0) {
40307+ printf ("PHY NOT REDAY ");
40308+ return 0;
40309+ }
40310+ Data = INL (dev, PHYDATA_REG);
40311+ Return_Data = (Data >> 16);
40312+
40313+ return Return_Data;
40314+}
40315+
40316+
40317+static void phy_write_register (struct eth_device* dev, u8 PHY_Register, u8 PHY_Address, u16 PHY_Data)
40318+{
40319+ u32 Status = 0, Loop_Count = 0, PHY_Ready = 1;
40320+
40321+#ifdef REALTEK_PHY_SUPPORT
40322+ PHY_Address = 0x01;
40323+#endif
40324+//20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
40325+ OUTL(dev, PHY_Data, PHYDATA_REG);
40326+ OUTL(dev, (PHY_Register << 21) + (PHY_Address << 16) + MIIWR + MDC_CYCTHR, PHYCR_REG);
40327+ do {
40328+ udelay(20);
40329+ Status = (INL (dev, PHYCR_REG) & MIIWR);
40330+ Loop_Count++;
40331+ if (Loop_Count >= 100) {
40332+ PHY_Ready = 0;
40333+ break;
40334+ }
40335+ } while (Status == MIIWR);
40336+ if (PHY_Ready == 0) {
40337+ printf ("PHY NOT REDAY ");
40338+ }
40339+}
40340+
40341+static void set_mac_control_register (struct eth_device* dev)
40342+{
40343+ unsigned long MAC_CR_Register = 0;
40344+ unsigned long Loop_Count = 0, PHY_Ready = 1, Chip_ID;
40345+ u16 PHY_Status, PHY_Speed, PHY_Duplex, Resolved_Status = 0, Advertise, Link_Partner;
40346+
40347+ if (CONFIG_MAC1_PHY_SETTING >= 1) {
40348+ MAC_CR_Register = SPEED_100M_MODE_bit | RX_BROADPKT_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit;
40349+ }
40350+ else {
40351+ MAC_CR_Register = SPEED_100M_MODE_bit | FULLDUP_bit | RXMAC_EN_bit | RXDMA_EN_bit | TXMAC_EN_bit | TXDMA_EN_bit | CRC_APD_bit;
40352+ }
40353+
40354+ if (CONFIG_MAC1_PHY_SETTING != 2) {
40355+ Chip_ID = ((phy_read_register (dev, 0x02, 0)) << 16);
40356+ Chip_ID |= (phy_read_register (dev, 0x03, 0) & 0xffff);
40357+ if (((Chip_ID & PHYID_VENDOR_MASK) == PHYID_VENDOR_BROADCOM) ||
40358+ ((Chip_ID & PHYID_VENDOR_MODEL_MASK) == PHYID_RTL8201EL)) {
40359+ Advertise = phy_read_register (dev, 0x04, 0);
40360+ Link_Partner = phy_read_register (dev, 0x05, 0);
40361+ Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK);
40362+ Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK);
40363+ if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) {
40364+ MAC_CR_Register |= SPEED_100M_MODE_bit;
40365+ MAC_CR_Register |= FULLDUP_bit;
40366+ }
40367+ else if ((Advertise & Link_Partner) & PHY_100M_HALF) {
40368+ MAC_CR_Register |= SPEED_100M_MODE_bit;
40369+ MAC_CR_Register &= ~FULLDUP_bit;
40370+ }
40371+ else if ((Advertise & Link_Partner) & PHY_10M_DUPLEX) {
40372+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
40373+ MAC_CR_Register |= FULLDUP_bit;
40374+ }
40375+ else if ((Advertise & Link_Partner) & PHY_10M_HALF) {
40376+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
40377+ MAC_CR_Register &= ~FULLDUP_bit;
40378+ }
40379+ }
40380+ else if (((Chip_ID & PHYID_VENDOR_MASK) == PHYID_VENDOR_MARVELL) ||
40381+ ((Chip_ID & PHYID_VENDOR_MODEL_MASK) == PHYID_RTL8211)) {
40382+//Max waiting time = (20 + 2)ms * 250(PHY_LOOP) = 5.5s
40383+ do {
40384+ udelay (20000);
40385+ Resolved_Status = (phy_read_register (dev, 0x11, 0) & RESOLVED_BIT);
40386+ Loop_Count++;
40387+ if (Loop_Count >= PHY_LOOP) {
40388+ PHY_Ready = 0;
40389+ printf ("PHY NOT READY ");
40390+ break;
40391+ }
40392+ } while (Resolved_Status != RESOLVED_BIT);
40393+
40394+ if (PHY_Ready == 1) {
40395+ PHY_Status = phy_read_register (dev, 0x11, 0);
40396+ PHY_Speed = (PHY_Status & PHY_SPEED_MASK) >> 14;
40397+ PHY_Duplex = (PHY_Status & PHY_DUPLEX_MASK) >> 13;
40398+
40399+ if (PHY_Speed == SPEED_1000M) {
40400+ MAC_CR_Register |= GMAC_MODE_bit;
40401+ }
40402+ else {
40403+ MAC_CR_Register &= ~GMAC_MODE_bit;
40404+ if (PHY_Speed == SPEED_10M) {
40405+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
40406+ }
40407+ }
40408+ if (PHY_Duplex == DUPLEX_HALF) {
40409+ MAC_CR_Register &= ~FULLDUP_bit;
40410+ }
40411+ }
40412+//LED Control
40413+// if (Chip_ID == 0x1C) {
40414+// PHY_Status = phy_read_register (dev, 0x18, 0);
40415+// phy_write_register (dev, 0x18, 0, (PHY_Status | 0x09));
40416+// }
40417+//LED Control D[0], D[6]
40418+// if (Chip_ID == 0x141) {
40419+// PHY_Status = phy_read_register (dev, 0x18, 0);
40420+// phy_write_register (dev, 0x18, 0, ((PHY_Status & ~(0x41)) | 0x01));
40421+// }
40422+ }
40423+ else if (Chip_ID == PHYID_BCM54612E ) {
40424+ phy_write_register ( dev, 0x1C, 1, 0x8C00 ); // Disable GTXCLK Clock Delay Enable
40425+ phy_write_register ( dev, 0x18, 1, 0xF0E7 ); // Disable RGMII RXD to RXC Skew
40426+
40427+ Advertise = phy_read_register (dev, 0x04, 1);
40428+ Link_Partner = phy_read_register (dev, 0x05, 1);
40429+ Advertise = (Advertise & PHY_SPEED_DUPLEX_MASK);
40430+ Link_Partner = (Link_Partner & PHY_SPEED_DUPLEX_MASK);
40431+ if ((Advertise & Link_Partner) & PHY_100M_DUPLEX) {
40432+ MAC_CR_Register |= SPEED_100M_MODE_bit;
40433+ MAC_CR_Register |= FULLDUP_bit;
40434+ }
40435+ else if ((Advertise & Link_Partner) & PHY_100M_HALF) {
40436+ MAC_CR_Register |= SPEED_100M_MODE_bit;
40437+ MAC_CR_Register &= ~FULLDUP_bit;
40438+ }
40439+ else if ((Advertise & Link_Partner) & PHY_10M_DUPLEX) {
40440+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
40441+ MAC_CR_Register |= FULLDUP_bit;
40442+ }
40443+ else if ((Advertise & Link_Partner) & PHY_10M_HALF) {
40444+ MAC_CR_Register &= ~SPEED_100M_MODE_bit;
40445+ MAC_CR_Register &= ~FULLDUP_bit;
40446+ }
40447+ }else {
40448+ printf("Unknow Chip_ID %x\n",Chip_ID);
40449+ }
40450+ }
40451+ OUTL(dev, MAC_CR_Register, MACCR_REG);
40452+}
40453+
40454+#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_ASPEEDMAC */
40455diff --git a/include/configs/ast1100.h b/include/configs/ast1100.h
40456new file mode 100755
40457index 0000000..dbd656e
40458--- /dev/null
40459+++ b/include/configs/ast1100.h
40460@@ -0,0 +1,257 @@
40461+/*
40462+ * (C) Copyright 2004
40463+ * Peter Chen <peterc@socle-tech.com.tw>
40464+ *
40465+ * This program is free software; you can redistribute it and/or
40466+ * modify it under the terms of the GNU General Public License as
40467+ * published by the Free Software Foundation; either version 2 of
40468+ * the License, or (at your option) any later version.
40469+ *
40470+ * This program is distributed in the hope that it will be useful,
40471+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
40472+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40473+ * GNU General Public License for more details.
40474+ *
40475+ * You should have received a copy of the GNU General Public License
40476+ * along with this program; if not, write to the Free Software
40477+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40478+ * MA 02111-1307 USA
40479+ */
40480+
40481+#ifndef __CONFIG_H
40482+#define __CONFIG_H
40483+
40484+/*
40485+ * Version Identity
40486+ */
40487+#define CONFIG_IDENT_STRING " ASPEED (v.0.12) "
40488+
40489+/*
40490+ * High Level Configuration Options
40491+ * (easy to change)
40492+ */
40493+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
40494+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
40495+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
40496+#define CONFIG_ASPEED 1
40497+#define CONFIG_AST1100 1
40498+//#define CONFIG_AST1100_FPGA
40499+#undef CONFIG_AST1100_FPGA /* undef if real chip */
40500+//#define CONFIG_AST1100A2_PATCH
40501+#undef CONFIG_AST1100A2_PATCH
40502+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */ /* Not ready */
40503+#undef CONFIG_2SPIFLASH
40504+#undef CONFIG_DDR512_200
40505+#define CONFIG_DDRII1G_200 1
40506+#undef CONFIG_ASPEED_SLT
40507+
40508+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
40509+#define CONFIG_MISC_INIT_R
40510+
40511+/*
40512+ * Environment Config
40513+ */
40514+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
40515+#define CONFIG_SETUP_MEMORY_TAGS 1
40516+#define CONFIG_INITRD_TAG 1
40517+#define CONFIG_BOOTARGS "debug console=ttyS1,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
40518+#ifdef CONFIG_ASPEED_SLT
40519+#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */
40520+#else
40521+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
40522+#endif
40523+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
40524+#define CONFIG_BOOTFILE "all.bin"
40525+#define CONFIG_ENV_OVERWRITE
40526+
40527+/*
40528+ * Command line configuration.
40529+ */
40530+#include <config_cmd_default.h>
40531+
40532+#define CONFIG_CMD_DFL
40533+#define CONFIG_CMD_ENV
40534+#define CONFIG_CMD_FLASH
40535+#define CONFIG_CMD_NET
40536+#define CONFIG_CMD_PING
40537+#define CONFIG_CMD_I2C
40538+#define CONFIG_CMD_EEPROM
40539+
40540+/*
40541+ * CPU Setting
40542+ */
40543+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
40544+
40545+/*
40546+ * Size of malloc() pool
40547+ */
40548+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
40549+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
40550+
40551+/*
40552+ * Stack sizes, The stack sizes are set up in start.S using the settings below
40553+ */
40554+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
40555+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
40556+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
40557+
40558+/*
40559+ * Memory Configuration
40560+ */
40561+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
40562+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
40563+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
40564+
40565+#define CONFIG_SYS_SDRAM_BASE 0x40000000
40566+
40567+/*
40568+ * FLASH Configuration
40569+ */
40570+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
40571+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
40572+#define PHYS_FLASH_2_BASE 0x10000000
40573+
40574+#ifdef CONFIG_2SPIFLASH
40575+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
40576+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
40577+#define CONFIG_SYS_MAX_FLASH_BANKS 2
40578+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
40579+
40580+#define CONFIG_ENV_IS_IN_FLASH 1
40581+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
40582+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
40583+#else
40584+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
40585+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
40586+#define CONFIG_SYS_MAX_FLASH_BANKS 1
40587+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
40588+
40589+#define CONFIG_ENV_IS_IN_FLASH 1
40590+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
40591+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
40592+#endif
40593+
40594+#define __LITTLE_ENDIAN
40595+#define CONFIG_FLASH_SPI
40596+
40597+#define CONFIG_MONITOR_BASE TEXT_BASE
40598+#define CONFIG_MONITOR_LEN (192 << 10)
40599+
40600+/* timeout values are in ticks */
40601+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
40602+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
40603+
40604+/*
40605+ * Miscellaneous configurable options
40606+ */
40607+#define CONFIG_SYS_LONGHELP /* undef to save memory */
40608+
40609+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
40610+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
40611+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
40612+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
40613+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
40614+
40615+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
40616+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
40617+
40618+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
40619+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
40620+
40621+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
40622+
40623+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
40624+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
40625+
40626+/*
40627+ * Serial Configuration
40628+ */
40629+#define CONFIG_SYS_NS16550
40630+#define CONFIG_SYS_NS16550_SERIAL
40631+#define CONFIG_SYS_NS16550_REG_SIZE 4
40632+#define CONFIG_SYS_NS16550_CLK 24000000
40633+#define CONFIG_SYS_NS16550_COM1 0x1e783000
40634+#define CONFIG_SYS_NS16550_COM2 0x1e784000
40635+#define CONFIG_SYS_LOADS_BAUD_CHANGE
40636+#define CONFIG_SERIAL1 1
40637+#define CONFIG_CONS_INDEX 2
40638+#define CONFIG_BAUDRATE 115200
40639+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
40640+
40641+/*
40642+ * USB device configuration
40643+ */
40644+/*
40645+#define CONFIG_USB_DEVICE 1
40646+#define CONFIG_USB_TTY 1
40647+
40648+#define CONFIG_USBD_VENDORID 0x1234
40649+#define CONFIG_USBD_PRODUCTID 0x5678
40650+#define CONFIG_USBD_MANUFACTURER "Siemens"
40651+#define CONFIG_USBD_PRODUCT_NAME "SX1"
40652+*/
40653+
40654+/*
40655+ * I2C configuration
40656+ */
40657+#define CONFIG_HARD_I2C
40658+#define CONFIG_SYS_I2C_SPEED 100000
40659+#define CONFIG_SYS_I2C_SLAVE 1
40660+#define CONFIG_DRIVER_ASPEED_I2C
40661+
40662+/*
40663+* EEPROM configuration
40664+*/
40665+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
40666+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
40667+
40668+/*
40669+ * NIC configuration
40670+ */
40671+#define __BYTE_ORDER __LITTLE_ENDIAN
40672+#define __LITTLE_ENDIAN_BITFIELD
40673+#define CONFIG_MAC_PARTITION
40674+#define CONFIG_ASPEEDNIC
40675+//#define CONFIG_MAC1_PHY_LINK_INTERRUPT
40676+//#define CONFIG_MAC2_ENABLE
40677+//#define CONFIG_MAC2_MII_ENABLE
40678+//#define CONFIG_MAC2_PHY_LINK_INTERRUPT
40679+
40680+/*
40681+*-------------------------------------------------------------------------------
40682+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
40683+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
40684+* inform kernel driver.
40685+* The meanings of the 2 bits are:
40686+* 00(0): Dedicated PHY
40687+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
40688+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
40689+* 11: Reserved
40690+*
40691+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
40692+* 0: Dedicated PHY
40693+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
40694+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
40695+* 3: Reserved
40696+*-------------------------------------------------------------------------------
40697+*/
40698+#define CONFIG_MAC1_PHY_SETTING 0
40699+#define CONFIG_MAC2_PHY_SETTING 0
40700+#define CONFIG_NET_MULTI
40701+#define CONFIG_ETHACT aspeednic#0
40702+#define CONFIG_GATEWAYIP 192.168.0.1
40703+#define CONFIG_NETMASK 255.255.255.0
40704+#define CONFIG_IPADDR 192.168.0.188
40705+#define CONFIG_SERVERIP 192.168.0.126
40706+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
40707+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
40708+
40709+/*
40710+ * SLT
40711+ */
40712+/*
40713+#define CONFIG_SLT
40714+#define CFG_CMD_SLT (CFG_CMD_REGTEST | CFG_CMD_MACTEST | CFG_CMD_VIDEOTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
40715+*/
40716+
40717+#endif /* __CONFIG_H */
40718diff --git a/include/configs/ast2100.h b/include/configs/ast2100.h
40719new file mode 100644
40720index 0000000..07733b9
40721--- /dev/null
40722+++ b/include/configs/ast2100.h
40723@@ -0,0 +1,272 @@
40724+/*
40725+ * (C) Copyright 2004
40726+ * Peter Chen <peterc@socle-tech.com.tw>
40727+ *
40728+ * This program is free software; you can redistribute it and/or
40729+ * modify it under the terms of the GNU General Public License as
40730+ * published by the Free Software Foundation; either version 2 of
40731+ * the License, or (at your option) any later version.
40732+ *
40733+ * This program is distributed in the hope that it will be useful,
40734+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
40735+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40736+ * GNU General Public License for more details.
40737+ *
40738+ * You should have received a copy of the GNU General Public License
40739+ * along with this program; if not, write to the Free Software
40740+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40741+ * MA 02111-1307 USA
40742+ */
40743+
40744+#ifndef __CONFIG_H
40745+#define __CONFIG_H
40746+
40747+/*
40748+ * High Level Configuration Options
40749+ * (easy to change)
40750+ */
40751+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
40752+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
40753+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
40754+#define CONFIG_ASPEED 1
40755+#define CONFIG_AST2100 1
40756+//#define CONFIG_AST2100_FPGA
40757+#undef CONFIG_AST2100_FPGA /* undef if real chip */
40758+//#define CONFIG_AST2100A2_PATCH
40759+#undef CONFIG_AST2100A2_PATCH
40760+#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
40761+//#define CONFIG_FLASH_SPI
40762+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
40763+#undef CONFIG_DDRII1G_266
40764+#undef CONFIG_2SPIFLASH
40765+#undef CONFIG_ASPEED_SLT
40766+
40767+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
40768+#define CONFIG_MISC_INIT_R
40769+
40770+/*
40771+ * Environment Config
40772+ */
40773+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
40774+#define CONFIG_SETUP_MEMORY_TAGS 1
40775+#define CONFIG_INITRD_TAG 1
40776+#define CONFIG_BOOTARGS "debug console=ttyS1,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
40777+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
40778+#ifdef CONFIG_SYS_FLASH_CFI
40779+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
40780+#else
40781+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
40782+#endif
40783+#define CONFIG_BOOTFILE "all.bin"
40784+#define CONFIG_ENV_OVERWRITE
40785+
40786+/*
40787+ * Command line configuration.
40788+ */
40789+#include <config_cmd_default.h>
40790+
40791+#define CONFIG_CMD_DFL
40792+#define CONFIG_CMD_ENV
40793+#define CONFIG_CMD_FLASH
40794+#define CONFIG_CMD_NET
40795+#define CONFIG_CMD_PING
40796+#define CONFIG_CMD_I2C
40797+#define CONFIG_CMD_EEPROM
40798+
40799+/*
40800+ * CPU Setting
40801+ */
40802+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
40803+
40804+/*
40805+ * Size of malloc() pool
40806+ */
40807+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
40808+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
40809+
40810+/*
40811+ * Stack sizes, The stack sizes are set up in start.S using the settings below
40812+ */
40813+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
40814+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
40815+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
40816+
40817+/*
40818+ * Memory Configuration
40819+ */
40820+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
40821+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
40822+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
40823+
40824+#define CONFIG_SYS_SDRAM_BASE 0x40000000
40825+
40826+/*
40827+ * FLASH Configuration
40828+ */
40829+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
40830+
40831+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
40832+
40833+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
40834+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
40835+
40836+#define CONFIG_SYS_MAX_FLASH_BANKS 1
40837+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
40838+
40839+#define CONFIG_ENV_IS_IN_FLASH 1
40840+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
40841+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
40842+
40843+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
40844+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
40845+
40846+#else /* SPI Flash */
40847+
40848+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
40849+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
40850+#define PHYS_FLASH_2_BASE 0x10000000
40851+
40852+#ifdef CONFIG_2SPIFLASH
40853+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
40854+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
40855+#define CONFIG_SYS_MAX_FLASH_BANKS 2
40856+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
40857+
40858+#define CONFIG_ENV_IS_IN_FLASH 1
40859+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
40860+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
40861+#else
40862+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
40863+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
40864+#define CONFIG_SYS_MAX_FLASH_BANKS 1
40865+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
40866+
40867+#define CONFIG_ENV_IS_IN_FLASH 1
40868+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
40869+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
40870+#endif
40871+
40872+#endif
40873+
40874+#define __LITTLE_ENDIAN
40875+
40876+#define CONFIG_MONITOR_BASE TEXT_BASE
40877+#define CONFIG_MONITOR_LEN (192 << 10)
40878+
40879+/* timeout values are in ticks */
40880+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
40881+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
40882+
40883+/*
40884+ * Miscellaneous configurable options
40885+ */
40886+#define CONFIG_SYS_LONGHELP /* undef to save memory */
40887+
40888+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
40889+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
40890+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
40891+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
40892+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
40893+
40894+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
40895+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
40896+
40897+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
40898+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
40899+
40900+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
40901+
40902+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
40903+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
40904+
40905+/*
40906+ * Serial Configuration
40907+ */
40908+#define CONFIG_SYS_NS16550
40909+#define CONFIG_SYS_NS16550_SERIAL
40910+#define CONFIG_SYS_NS16550_REG_SIZE 4
40911+#define CONFIG_SYS_NS16550_CLK 24000000
40912+#define CONFIG_SYS_NS16550_COM1 0x1e783000
40913+#define CONFIG_SYS_NS16550_COM2 0x1e784000
40914+#define CONFIG_SYS_LOADS_BAUD_CHANGE
40915+#define CONFIG_SERIAL1 1
40916+#define CONFIG_CONS_INDEX 2
40917+#define CONFIG_BAUDRATE 115200
40918+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
40919+
40920+/*
40921+ * USB device configuration
40922+ */
40923+/*
40924+#define CONFIG_USB_DEVICE 1
40925+#define CONFIG_USB_TTY 1
40926+
40927+#define CONFIG_USBD_VENDORID 0x1234
40928+#define CONFIG_USBD_PRODUCTID 0x5678
40929+#define CONFIG_USBD_MANUFACTURER "Siemens"
40930+#define CONFIG_USBD_PRODUCT_NAME "SX1"
40931+*/
40932+
40933+/*
40934+ * I2C configuration
40935+ */
40936+#define CONFIG_HARD_I2C
40937+#define CONFIG_SYS_I2C_SPEED 100000
40938+#define CONFIG_SYS_I2C_SLAVE 1
40939+#define CONFIG_DRIVER_ASPEED_I2C
40940+
40941+/*
40942+* EEPROM configuration
40943+*/
40944+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
40945+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
40946+
40947+/*
40948+ * NIC configuration
40949+ */
40950+#define __BYTE_ORDER __LITTLE_ENDIAN
40951+#define __LITTLE_ENDIAN_BITFIELD
40952+#define CONFIG_MAC_PARTITION
40953+#define CONFIG_ASPEEDNIC
40954+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
40955+#define CONFIG_MAC2_ENABLE
40956+#define CONFIG_MAC2_MII_ENABLE
40957+//#define CONFIG_MAC2_PHY_LINK_INTERRUPT
40958+/*
40959+*-------------------------------------------------------------------------------
40960+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
40961+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
40962+* inform kernel driver.
40963+* The meanings of the 2 bits are:
40964+* 00(0): Dedicated PHY
40965+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
40966+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
40967+* 11: Reserved
40968+*
40969+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
40970+* 0: Dedicated PHY
40971+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
40972+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
40973+* 3: Reserved
40974+*-------------------------------------------------------------------------------
40975+*/
40976+#define CONFIG_MAC1_PHY_SETTING 0
40977+#define CONFIG_MAC2_PHY_SETTING 0
40978+#define CONFIG_NET_MULTI
40979+#define CONFIG_ETHACT aspeednic#0
40980+#define CONFIG_GATEWAYIP 192.168.0.1
40981+#define CONFIG_NETMASK 255.255.255.0
40982+#define CONFIG_IPADDR 192.168.0.188
40983+#define CONFIG_SERVERIP 192.168.0.106
40984+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
40985+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
40986+
40987+/*
40988+ * SLT
40989+ */
40990+/*
40991+#define CONFIG_SLT
40992+#define CONFIG_CMD_SLT (CONFIG_CMD_REGTEST | CONFIG_CMD_MACTEST | CONFIG_CMD_VIDEOTEST | CONFIG_CMD_HACTEST | CONFIG_CMD_MICTEST)
40993+*/
40994+
40995+#endif /* __CONFIG_H */
40996diff --git a/include/configs/ast2300.h b/include/configs/ast2300.h
40997new file mode 100644
40998index 0000000..678e7c3
40999--- /dev/null
41000+++ b/include/configs/ast2300.h
41001@@ -0,0 +1,325 @@
41002+/*
41003+ * (C) Copyright 2004
41004+ * Peter Chen <peterc@socle-tech.com.tw>
41005+ *
41006+ * This program is free software; you can redistribute it and/or
41007+ * modify it under the terms of the GNU General Public License as
41008+ * published by the Free Software Foundation; either version 2 of
41009+ * the License, or (at your option) any later version.
41010+ *
41011+ * This program is distributed in the hope that it will be useful,
41012+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
41013+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41014+ * GNU General Public License for more details.
41015+ *
41016+ * You should have received a copy of the GNU General Public License
41017+ * along with this program; if not, write to the Free Software
41018+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41019+ * MA 02111-1307 USA
41020+ */
41021+
41022+#ifndef __CONFIG_H
41023+#define __CONFIG_H
41024+
41025+/*
41026+ * High Level Configuration Options
41027+ * (easy to change)
41028+ */
41029+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
41030+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
41031+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
41032+#define CONFIG_ASPEED 1
41033+#define CONFIG_AST2300 1
41034+//#define CONFIG_AST1070 1
41035+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
41036+#define CONFIG_FLASH_SPI
41037+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
41038+#undef CONFIG_2SPIFLASH
41039+#undef CONFIG_ASPEED_SLT
41040+#define CONFIG_FLASH_AST2300
41041+#define CONFIG_FLASH_AST2300_DMA
41042+//#define CONFIG_FLASH_SPIx2_Dummy
41043+//#define CONFIG_FLASH_SPIx4_Dummy
41044+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
41045+
41046+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41047+#define CONFIG_MISC_INIT_R
41048+
41049+/*
41050+ * DRAM Config
41051+ *
41052+ * 1. DRAM Size //
41053+ * CONFIG_DRAM_512MBIT // 512M bit
41054+ * CONFIG_DRAM_1GBIT // 1G bit (default)
41055+ * CONFIG_DRAM_2GBIT // 2G bit
41056+ * CONFIG_DRAM_4GBIT // 4G bit
41057+ * 2. DRAM Speed //
41058+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
41059+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
41060+ * 3. VGA Mode
41061+ * CONFIG_CRT_DISPLAY // define to disable VGA function
41062+ * 4. ECC Function enable
41063+ * CONFIG_DRAM_ECC // define to enable ECC function
41064+ * 5. UART Debug Message
41065+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
41066+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
41067+ */
41068+
41069+//1. DRAM Size
41070+//#define CONFIG_DRAM_512MBIT
41071+#define CONFIG_DRAM_1GBIT
41072+//#define CONFIG_DRAM_2GBIT
41073+//#define CONFIG_DRAM_4GBIT
41074+//2. DRAM Speed
41075+//#define CONFIG_DRAM_336
41076+#define CONFIG_DRAM_408
41077+//3. VGA Mode
41078+//#define CONFIG_CRT_DISPLAY
41079+//4. ECC Function enable
41080+//#define CONFIG_DRAM_ECC
41081+//5. UART Debug Message
41082+#define CONFIG_DRAM_UART_OUT
41083+//#define CONFIG_DRAM_UART_38400
41084+
41085+
41086+
41087+/*
41088+ * Environment Config
41089+ */
41090+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41091+#define CONFIG_SETUP_MEMORY_TAGS 1
41092+#define CONFIG_INITRD_TAG 1
41093+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
41094+#define CONFIG_UPDATE "tftp 40800000 ast2300.scr; so 40800000'"
41095+
41096+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
41097+#ifdef CONFIG_FLASH_AST2300
41098+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
41099+#else
41100+#ifdef CONFIG_SYS_FLASH_CFI
41101+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
41102+#else
41103+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
41104+#endif
41105+#endif
41106+#define CONFIG_BOOTFILE "all.bin"
41107+#define CONFIG_ENV_OVERWRITE
41108+
41109+/*
41110+ * Command line configuration.
41111+ */
41112+#include <config_cmd_default.h>
41113+
41114+#define CONFIG_CMD_DFL
41115+#define CONFIG_CMD_ENV
41116+#define CONFIG_CMD_FLASH
41117+#define CONFIG_CMD_NET
41118+#define CONFIG_CMD_PING
41119+#define CONFIG_CMD_I2C
41120+#define CONFIG_CMD_EEPROM
41121+
41122+/*
41123+ * CPU Setting
41124+ */
41125+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
41126+
41127+/*
41128+ * Size of malloc() pool
41129+ */
41130+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
41131+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
41132+
41133+/*
41134+ * Stack sizes, The stack sizes are set up in start.S using the settings below
41135+ */
41136+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
41137+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
41138+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
41139+
41140+/*
41141+ * Memory Configuration
41142+ */
41143+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
41144+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
41145+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
41146+
41147+#define CONFIG_SYS_SDRAM_BASE 0x40000000
41148+
41149+/*
41150+ * FLASH Configuration
41151+ */
41152+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
41153+
41154+#ifdef CONFIG_FLASH_AST2300
41155+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
41156+#else
41157+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
41158+#endif
41159+
41160+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
41161+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
41162+
41163+#define CONFIG_SYS_MAX_FLASH_BANKS 1
41164+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
41165+
41166+#define CONFIG_ENV_IS_IN_FLASH 1
41167+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
41168+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
41169+
41170+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
41171+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
41172+
41173+#else /* SPI Flash */
41174+
41175+#ifdef CONFIG_FLASH_AST2300
41176+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
41177+#else
41178+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
41179+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
41180+#define PHYS_FLASH_2_BASE 0x10000000
41181+#endif
41182+
41183+#ifdef CONFIG_2SPIFLASH
41184+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
41185+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
41186+#define CONFIG_SYS_MAX_FLASH_BANKS 2
41187+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
41188+
41189+#define CONFIG_ENV_IS_IN_FLASH 1
41190+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
41191+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
41192+#else
41193+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
41194+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
41195+#define CONFIG_SYS_MAX_FLASH_BANKS 1
41196+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
41197+
41198+#define CONFIG_ENV_IS_IN_FLASH 1
41199+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
41200+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
41201+#endif
41202+
41203+#endif
41204+
41205+#define __LITTLE_ENDIAN
41206+
41207+#define CONFIG_MONITOR_BASE TEXT_BASE
41208+#define CONFIG_MONITOR_LEN (192 << 10)
41209+
41210+/* timeout values are in ticks */
41211+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
41212+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
41213+
41214+/*
41215+ * Miscellaneous configurable options
41216+ */
41217+#define CONFIG_SYS_LONGHELP /* undef to save memory */
41218+
41219+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
41220+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
41221+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
41222+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
41223+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
41224+
41225+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
41226+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
41227+
41228+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
41229+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
41230+
41231+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
41232+
41233+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
41234+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
41235+
41236+/*
41237+ * Serial Configuration
41238+ */
41239+#define CONFIG_SYS_NS16550
41240+#define CONFIG_SYS_NS16550_SERIAL
41241+#define CONFIG_SYS_NS16550_REG_SIZE 4
41242+#define CONFIG_SYS_NS16550_CLK 24000000
41243+#define CONFIG_SYS_NS16550_COM1 0x1e783000
41244+#define CONFIG_SYS_NS16550_COM2 0x1e784000
41245+#define CONFIG_SYS_LOADS_BAUD_CHANGE
41246+#define CONFIG_SERIAL1 1
41247+#define CONFIG_CONS_INDEX 2
41248+#define CONFIG_BAUDRATE 115200
41249+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
41250+
41251+/*
41252+ * USB device configuration
41253+ */
41254+/*
41255+#define CONFIG_USB_DEVICE 1
41256+#define CONFIG_USB_TTY 1
41257+
41258+#define CONFIG_USBD_VENDORID 0x1234
41259+#define CONFIG_USBD_PRODUCTID 0x5678
41260+#define CONFIG_USBD_MANUFACTURER "Siemens"
41261+#define CONFIG_USBD_PRODUCT_NAME "SX1"
41262+*/
41263+
41264+/*
41265+ * I2C configuration
41266+ */
41267+#define CONFIG_HARD_I2C
41268+#define CONFIG_SYS_I2C_SPEED 100000
41269+#define CONFIG_SYS_I2C_SLAVE 1
41270+#define CONFIG_DRIVER_ASPEED_I2C
41271+
41272+/*
41273+* EEPROM configuration
41274+*/
41275+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
41276+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
41277+
41278+/*
41279+ * NIC configuration
41280+ */
41281+#define __BYTE_ORDER __LITTLE_ENDIAN
41282+#define __LITTLE_ENDIAN_BITFIELD
41283+#define CONFIG_MAC_PARTITION
41284+#define CONFIG_ASPEEDNIC
41285+//#define CONFIG_MAC1_PHY_LINK_INTERRUPT
41286+#define CONFIG_MAC2_ENABLE
41287+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
41288+/*
41289+*-------------------------------------------------------------------------------
41290+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
41291+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
41292+* inform kernel driver.
41293+* The meanings of the 2 bits are:
41294+* 00(0): Dedicated PHY
41295+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
41296+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
41297+* 11: Reserved
41298+*
41299+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
41300+* 0: Dedicated PHY
41301+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
41302+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
41303+* 3: Reserved
41304+*-------------------------------------------------------------------------------
41305+*/
41306+#define CONFIG_MAC1_PHY_SETTING 2
41307+#define CONFIG_MAC2_PHY_SETTING 0
41308+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
41309+#define CONFIG_NET_MULTI
41310+#define CONFIG_ETHACT aspeednic#0
41311+#define CONFIG_GATEWAYIP 192.168.0.1
41312+#define CONFIG_NETMASK 255.255.255.0
41313+#define CONFIG_IPADDR 192.168.0.45
41314+#define CONFIG_SERVERIP 192.168.0.81
41315+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
41316+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
41317+
41318+/*
41319+ * SLT
41320+ */
41321+/*
41322+#define CONFIG_SLT
41323+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
41324+*/
41325+
41326+#endif /* __CONFIG_H */
41327diff --git a/include/configs/ast2300_ast1070.h b/include/configs/ast2300_ast1070.h
41328new file mode 100644
41329index 0000000..a7abdf5
41330--- /dev/null
41331+++ b/include/configs/ast2300_ast1070.h
41332@@ -0,0 +1,323 @@
41333+/*
41334+ * (C) Copyright 2004
41335+ * Peter Chen <peterc@socle-tech.com.tw>
41336+ *
41337+ * This program is free software; you can redistribute it and/or
41338+ * modify it under the terms of the GNU General Public License as
41339+ * published by the Free Software Foundation; either version 2 of
41340+ * the License, or (at your option) any later version.
41341+ *
41342+ * This program is distributed in the hope that it will be useful,
41343+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
41344+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41345+ * GNU General Public License for more details.
41346+ *
41347+ * You should have received a copy of the GNU General Public License
41348+ * along with this program; if not, write to the Free Software
41349+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41350+ * MA 02111-1307 USA
41351+ */
41352+
41353+#ifndef __CONFIG_H
41354+#define __CONFIG_H
41355+
41356+/*
41357+ * High Level Configuration Options
41358+ * (easy to change)
41359+ */
41360+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
41361+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
41362+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
41363+#define CONFIG_ASPEED 1
41364+#define CONFIG_AST2300 1
41365+#define CONFIG_AST1070 1
41366+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
41367+#define CONFIG_FLASH_SPI
41368+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
41369+#undef CONFIG_2SPIFLASH
41370+#undef CONFIG_ASPEED_SLT
41371+#define CONFIG_FLASH_AST2300
41372+#define CONFIG_FLASH_AST2300_DMA
41373+//#define CONFIG_FLASH_SPIx2_Dummy
41374+//#define CONFIG_FLASH_SPIx4_Dummy
41375+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
41376+
41377+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41378+#define CONFIG_MISC_INIT_R
41379+
41380+/*
41381+ * DRAM Config
41382+ *
41383+ * 1. DRAM Size //
41384+ * CONFIG_DRAM_512MBIT // 512M bit
41385+ * CONFIG_DRAM_1GBIT // 1G bit (default)
41386+ * CONFIG_DRAM_2GBIT // 2G bit
41387+ * CONFIG_DRAM_4GBIT // 4G bit
41388+ * 2. DRAM Speed //
41389+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
41390+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
41391+ * 3. VGA Mode
41392+ * CONFIG_CRT_DISPLAY // define to disable VGA function
41393+ * 4. ECC Function enable
41394+ * CONFIG_DRAM_ECC // define to enable ECC function
41395+ * 5. UART Debug Message
41396+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
41397+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
41398+ */
41399+
41400+//1. DRAM Size
41401+//#define CONFIG_DRAM_512MBIT
41402+#define CONFIG_DRAM_1GBIT
41403+//#define CONFIG_DRAM_2GBIT
41404+//#define CONFIG_DRAM_4GBIT
41405+//2. DRAM Speed
41406+//#define CONFIG_DRAM_336
41407+#define CONFIG_DRAM_408
41408+//3. VGA Mode
41409+//#define CONFIG_CRT_DISPLAY
41410+//4. ECC Function enable
41411+//#define CONFIG_DRAM_ECC
41412+//5. UART Debug Message
41413+#define CONFIG_DRAM_UART_OUT
41414+//#define CONFIG_DRAM_UART_38400
41415+
41416+
41417+
41418+/*
41419+ * Environment Config
41420+ */
41421+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41422+#define CONFIG_SETUP_MEMORY_TAGS 1
41423+#define CONFIG_INITRD_TAG 1
41424+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
41425+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
41426+#ifdef CONFIG_FLASH_AST2300
41427+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
41428+#else
41429+#ifdef CONFIG_SYS_FLASH_CFI
41430+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
41431+#else
41432+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
41433+#endif
41434+#endif
41435+#define CONFIG_BOOTFILE "all.bin"
41436+#define CONFIG_ENV_OVERWRITE
41437+
41438+/*
41439+ * Command line configuration.
41440+ */
41441+#include <config_cmd_default.h>
41442+
41443+#define CONFIG_CMD_DFL
41444+#define CONFIG_CMD_ENV
41445+#define CONFIG_CMD_FLASH
41446+#define CONFIG_CMD_NET
41447+#define CONFIG_CMD_PING
41448+#define CONFIG_CMD_I2C
41449+#define CONFIG_CMD_EEPROM
41450+
41451+/*
41452+ * CPU Setting
41453+ */
41454+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
41455+
41456+/*
41457+ * Size of malloc() pool
41458+ */
41459+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
41460+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
41461+
41462+/*
41463+ * Stack sizes, The stack sizes are set up in start.S using the settings below
41464+ */
41465+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
41466+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
41467+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
41468+
41469+/*
41470+ * Memory Configuration
41471+ */
41472+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
41473+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
41474+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
41475+
41476+#define CONFIG_SYS_SDRAM_BASE 0x40000000
41477+
41478+/*
41479+ * FLASH Configuration
41480+ */
41481+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
41482+
41483+#ifdef CONFIG_FLASH_AST2300
41484+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
41485+#else
41486+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
41487+#endif
41488+
41489+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
41490+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
41491+
41492+#define CONFIG_SYS_MAX_FLASH_BANKS 1
41493+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
41494+
41495+#define CONFIG_ENV_IS_IN_FLASH 1
41496+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
41497+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
41498+
41499+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
41500+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
41501+
41502+#else /* SPI Flash */
41503+
41504+#ifdef CONFIG_FLASH_AST2300
41505+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
41506+#else
41507+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
41508+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
41509+#define PHYS_FLASH_2_BASE 0x10000000
41510+#endif
41511+
41512+#ifdef CONFIG_2SPIFLASH
41513+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
41514+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
41515+#define CONFIG_SYS_MAX_FLASH_BANKS 2
41516+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
41517+
41518+#define CONFIG_ENV_IS_IN_FLASH 1
41519+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
41520+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
41521+#else
41522+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
41523+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
41524+#define CONFIG_SYS_MAX_FLASH_BANKS 1
41525+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
41526+
41527+#define CONFIG_ENV_IS_IN_FLASH 1
41528+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
41529+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
41530+#endif
41531+
41532+#endif
41533+
41534+#define __LITTLE_ENDIAN
41535+
41536+#define CONFIG_MONITOR_BASE TEXT_BASE
41537+#define CONFIG_MONITOR_LEN (192 << 10)
41538+
41539+/* timeout values are in ticks */
41540+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
41541+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
41542+
41543+/*
41544+ * Miscellaneous configurable options
41545+ */
41546+#define CONFIG_SYS_LONGHELP /* undef to save memory */
41547+
41548+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
41549+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
41550+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
41551+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
41552+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
41553+
41554+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
41555+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
41556+
41557+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
41558+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
41559+
41560+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
41561+
41562+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
41563+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
41564+
41565+/*
41566+ * Serial Configuration
41567+ */
41568+#define CONFIG_SYS_NS16550
41569+#define CONFIG_SYS_NS16550_SERIAL
41570+#define CONFIG_SYS_NS16550_REG_SIZE 4
41571+#define CONFIG_SYS_NS16550_CLK 24000000
41572+#define CONFIG_SYS_NS16550_COM1 0x1e783000
41573+#define CONFIG_SYS_NS16550_COM2 0x1e784000
41574+#define CONFIG_SYS_LOADS_BAUD_CHANGE
41575+#define CONFIG_SERIAL1 1
41576+#define CONFIG_CONS_INDEX 2
41577+#define CONFIG_BAUDRATE 115200
41578+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
41579+
41580+/*
41581+ * USB device configuration
41582+ */
41583+/*
41584+#define CONFIG_USB_DEVICE 1
41585+#define CONFIG_USB_TTY 1
41586+
41587+#define CONFIG_USBD_VENDORID 0x1234
41588+#define CONFIG_USBD_PRODUCTID 0x5678
41589+#define CONFIG_USBD_MANUFACTURER "Siemens"
41590+#define CONFIG_USBD_PRODUCT_NAME "SX1"
41591+*/
41592+
41593+/*
41594+ * I2C configuration
41595+ */
41596+#define CONFIG_HARD_I2C
41597+#define CONFIG_SYS_I2C_SPEED 100000
41598+#define CONFIG_SYS_I2C_SLAVE 1
41599+#define CONFIG_DRIVER_ASPEED_I2C
41600+
41601+/*
41602+* EEPROM configuration
41603+*/
41604+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
41605+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
41606+
41607+/*
41608+ * NIC configuration
41609+ */
41610+#define __BYTE_ORDER __LITTLE_ENDIAN
41611+#define __LITTLE_ENDIAN_BITFIELD
41612+#define CONFIG_MAC_PARTITION
41613+#define CONFIG_ASPEEDNIC
41614+//#define CONFIG_MAC1_PHY_LINK_INTERRUPT
41615+#define CONFIG_MAC2_ENABLE
41616+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
41617+/*
41618+*-------------------------------------------------------------------------------
41619+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
41620+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
41621+* inform kernel driver.
41622+* The meanings of the 2 bits are:
41623+* 00(0): Dedicated PHY
41624+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
41625+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
41626+* 11: Reserved
41627+*
41628+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
41629+* 0: Dedicated PHY
41630+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
41631+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
41632+* 3: Reserved
41633+*-------------------------------------------------------------------------------
41634+*/
41635+#define CONFIG_MAC1_PHY_SETTING 0
41636+#define CONFIG_MAC2_PHY_SETTING 0
41637+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
41638+#define CONFIG_NET_MULTI
41639+#define CONFIG_ETHACT aspeednic#0
41640+#define CONFIG_GATEWAYIP 192.168.0.1
41641+#define CONFIG_NETMASK 255.255.255.0
41642+#define CONFIG_IPADDR 192.168.0.45
41643+#define CONFIG_SERVERIP 192.168.0.81
41644+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
41645+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
41646+
41647+/*
41648+ * SLT
41649+ */
41650+/*
41651+#define CONFIG_SLT
41652+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
41653+*/
41654+
41655+#endif /* __CONFIG_H */
41656diff --git a/include/configs/ast2300_nor.h b/include/configs/ast2300_nor.h
41657new file mode 100644
41658index 0000000..77b8fe3
41659--- /dev/null
41660+++ b/include/configs/ast2300_nor.h
41661@@ -0,0 +1,322 @@
41662+/*
41663+ * (C) Copyright 2004
41664+ * Peter Chen <peterc@socle-tech.com.tw>
41665+ *
41666+ * This program is free software; you can redistribute it and/or
41667+ * modify it under the terms of the GNU General Public License as
41668+ * published by the Free Software Foundation; either version 2 of
41669+ * the License, or (at your option) any later version.
41670+ *
41671+ * This program is distributed in the hope that it will be useful,
41672+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
41673+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41674+ * GNU General Public License for more details.
41675+ *
41676+ * You should have received a copy of the GNU General Public License
41677+ * along with this program; if not, write to the Free Software
41678+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41679+ * MA 02111-1307 USA
41680+ */
41681+
41682+#ifndef __CONFIG_H
41683+#define __CONFIG_H
41684+
41685+/*
41686+ * High Level Configuration Options
41687+ * (easy to change)
41688+ */
41689+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
41690+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
41691+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
41692+#define CONFIG_ASPEED 1
41693+#define CONFIG_AST2300 1
41694+#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
41695+//#define CONFIG_FLASH_SPI
41696+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
41697+#undef CONFIG_2SPIFLASH
41698+#undef CONFIG_ASPEED_SLT
41699+#define CONFIG_FLASH_AST2300
41700+#define CONFIG_FLASH_AST2300_DMA
41701+//#define CONFIG_FLASH_SPIx2_Dummy
41702+//#define CONFIG_FLASH_SPIx4_Dummy
41703+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
41704+
41705+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41706+#define CONFIG_MISC_INIT_R
41707+
41708+/*
41709+ * DRAM Config
41710+ *
41711+ * 1. DRAM Size //
41712+ * CONFIG_DRAM_512MBIT // 512M bit
41713+ * CONFIG_DRAM_1GBIT // 1G bit (default)
41714+ * CONFIG_DRAM_2GBIT // 2G bit
41715+ * CONFIG_DRAM_4GBIT // 4G bit
41716+ * 2. DRAM Speed //
41717+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
41718+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
41719+ * 3. VGA Mode
41720+ * CONFIG_CRT_DISPLAY // define to disable VGA function
41721+ * 4. ECC Function enable
41722+ * CONFIG_DRAM_ECC // define to enable ECC function
41723+ * 5. UART Debug Message
41724+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
41725+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
41726+ */
41727+
41728+//1. DRAM Size
41729+//#define CONFIG_DRAM_512MBIT
41730+#define CONFIG_DRAM_1GBIT
41731+//#define CONFIG_DRAM_2GBIT
41732+//#define CONFIG_DRAM_4GBIT
41733+//2. DRAM Speed
41734+//#define CONFIG_DRAM_336
41735+#define CONFIG_DRAM_408
41736+//3. VGA Mode
41737+//#define CONFIG_CRT_DISPLAY
41738+//4. ECC Function enable
41739+//#define CONFIG_DRAM_ECC
41740+//5. UART Debug Message
41741+#define CONFIG_DRAM_UART_OUT
41742+//#define CONFIG_DRAM_UART_38400
41743+
41744+
41745+
41746+/*
41747+ * Environment Config
41748+ */
41749+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41750+#define CONFIG_SETUP_MEMORY_TAGS 1
41751+#define CONFIG_INITRD_TAG 1
41752+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
41753+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
41754+#ifdef CONFIG_FLASH_AST2300
41755+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
41756+#else
41757+#ifdef CONFIG_SYS_FLASH_CFI
41758+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
41759+#else
41760+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
41761+#endif
41762+#endif
41763+#define CONFIG_BOOTFILE "all.bin"
41764+#define CONFIG_ENV_OVERWRITE
41765+
41766+/*
41767+ * Command line configuration.
41768+ */
41769+#include <config_cmd_default.h>
41770+
41771+#define CONFIG_CMD_DFL
41772+#define CONFIG_CMD_ENV
41773+#define CONFIG_CMD_FLASH
41774+#define CONFIG_CMD_NET
41775+#define CONFIG_CMD_PING
41776+#define CONFIG_CMD_I2C
41777+#define CONFIG_CMD_EEPROM
41778+
41779+/*
41780+ * CPU Setting
41781+ */
41782+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
41783+
41784+/*
41785+ * Size of malloc() pool
41786+ */
41787+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
41788+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
41789+
41790+/*
41791+ * Stack sizes, The stack sizes are set up in start.S using the settings below
41792+ */
41793+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
41794+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
41795+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
41796+
41797+/*
41798+ * Memory Configuration
41799+ */
41800+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
41801+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
41802+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
41803+
41804+#define CONFIG_SYS_SDRAM_BASE 0x40000000
41805+
41806+/*
41807+ * FLASH Configuration
41808+ */
41809+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
41810+
41811+#ifdef CONFIG_FLASH_AST2300
41812+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
41813+#else
41814+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
41815+#endif
41816+
41817+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
41818+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
41819+
41820+#define CONFIG_SYS_MAX_FLASH_BANKS 1
41821+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
41822+
41823+#define CONFIG_ENV_IS_IN_FLASH 1
41824+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
41825+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
41826+
41827+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
41828+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
41829+
41830+#else /* SPI Flash */
41831+
41832+#ifdef CONFIG_FLASH_AST2300
41833+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
41834+#else
41835+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
41836+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
41837+#define PHYS_FLASH_2_BASE 0x10000000
41838+#endif
41839+
41840+#ifdef CONFIG_2SPIFLASH
41841+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
41842+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
41843+#define CONFIG_SYS_MAX_FLASH_BANKS 2
41844+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
41845+
41846+#define CONFIG_ENV_IS_IN_FLASH 1
41847+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
41848+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
41849+#else
41850+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
41851+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
41852+#define CONFIG_SYS_MAX_FLASH_BANKS 1
41853+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
41854+
41855+#define CONFIG_ENV_IS_IN_FLASH 1
41856+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
41857+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
41858+#endif
41859+
41860+#endif
41861+
41862+#define __LITTLE_ENDIAN
41863+
41864+#define CONFIG_MONITOR_BASE TEXT_BASE
41865+#define CONFIG_MONITOR_LEN (192 << 10)
41866+
41867+/* timeout values are in ticks */
41868+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
41869+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
41870+
41871+/*
41872+ * Miscellaneous configurable options
41873+ */
41874+#define CONFIG_SYS_LONGHELP /* undef to save memory */
41875+
41876+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
41877+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
41878+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
41879+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
41880+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
41881+
41882+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
41883+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
41884+
41885+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
41886+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
41887+
41888+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
41889+
41890+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
41891+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
41892+
41893+/*
41894+ * Serial Configuration
41895+ */
41896+#define CONFIG_SYS_NS16550
41897+#define CONFIG_SYS_NS16550_SERIAL
41898+#define CONFIG_SYS_NS16550_REG_SIZE 4
41899+#define CONFIG_SYS_NS16550_CLK 24000000
41900+#define CONFIG_SYS_NS16550_COM1 0x1e783000
41901+#define CONFIG_SYS_NS16550_COM2 0x1e784000
41902+#define CONFIG_SYS_LOADS_BAUD_CHANGE
41903+#define CONFIG_SERIAL1 1
41904+#define CONFIG_CONS_INDEX 2
41905+#define CONFIG_BAUDRATE 115200
41906+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
41907+
41908+/*
41909+ * USB device configuration
41910+ */
41911+/*
41912+#define CONFIG_USB_DEVICE 1
41913+#define CONFIG_USB_TTY 1
41914+
41915+#define CONFIG_USBD_VENDORID 0x1234
41916+#define CONFIG_USBD_PRODUCTID 0x5678
41917+#define CONFIG_USBD_MANUFACTURER "Siemens"
41918+#define CONFIG_USBD_PRODUCT_NAME "SX1"
41919+*/
41920+
41921+/*
41922+ * I2C configuration
41923+ */
41924+#define CONFIG_HARD_I2C
41925+#define CONFIG_SYS_I2C_SPEED 100000
41926+#define CONFIG_SYS_I2C_SLAVE 1
41927+#define CONFIG_DRIVER_ASPEED_I2C
41928+
41929+/*
41930+* EEPROM configuration
41931+*/
41932+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
41933+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
41934+
41935+/*
41936+ * NIC configuration
41937+ */
41938+#define __BYTE_ORDER __LITTLE_ENDIAN
41939+#define __LITTLE_ENDIAN_BITFIELD
41940+#define CONFIG_MAC_PARTITION
41941+#define CONFIG_ASPEEDNIC
41942+//#define CONFIG_MAC1_PHY_LINK_INTERRUPT
41943+#define CONFIG_MAC2_ENABLE
41944+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
41945+/*
41946+*-------------------------------------------------------------------------------
41947+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
41948+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
41949+* inform kernel driver.
41950+* The meanings of the 2 bits are:
41951+* 00(0): Dedicated PHY
41952+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
41953+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
41954+* 11: Reserved
41955+*
41956+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
41957+* 0: Dedicated PHY
41958+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
41959+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
41960+* 3: Reserved
41961+*-------------------------------------------------------------------------------
41962+*/
41963+#define CONFIG_MAC1_PHY_SETTING 0
41964+#define CONFIG_MAC2_PHY_SETTING 0
41965+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
41966+#define CONFIG_NET_MULTI
41967+#define CONFIG_ETHACT aspeednic#0
41968+#define CONFIG_GATEWAYIP 192.168.0.1
41969+#define CONFIG_NETMASK 255.255.255.0
41970+#define CONFIG_IPADDR 192.168.0.188
41971+#define CONFIG_SERVERIP 192.168.0.106
41972+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
41973+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
41974+
41975+/*
41976+ * SLT
41977+ */
41978+/*
41979+#define CONFIG_SLT
41980+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
41981+*/
41982+
41983+#endif /* __CONFIG_H */
41984diff --git a/include/configs/ast2300_spi.h b/include/configs/ast2300_spi.h
41985new file mode 100644
41986index 0000000..bc65530
41987--- /dev/null
41988+++ b/include/configs/ast2300_spi.h
41989@@ -0,0 +1,322 @@
41990+/*
41991+ * (C) Copyright 2004
41992+ * Peter Chen <peterc@socle-tech.com.tw>
41993+ *
41994+ * This program is free software; you can redistribute it and/or
41995+ * modify it under the terms of the GNU General Public License as
41996+ * published by the Free Software Foundation; either version 2 of
41997+ * the License, or (at your option) any later version.
41998+ *
41999+ * This program is distributed in the hope that it will be useful,
42000+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
42001+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42002+ * GNU General Public License for more details.
42003+ *
42004+ * You should have received a copy of the GNU General Public License
42005+ * along with this program; if not, write to the Free Software
42006+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42007+ * MA 02111-1307 USA
42008+ */
42009+
42010+#ifndef __CONFIG_H
42011+#define __CONFIG_H
42012+
42013+/*
42014+ * High Level Configuration Options
42015+ * (easy to change)
42016+ */
42017+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
42018+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
42019+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
42020+#define CONFIG_ASPEED 1
42021+#define CONFIG_AST2300 1
42022+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
42023+#define CONFIG_FLASH_SPI
42024+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
42025+#undef CONFIG_2SPIFLASH
42026+#undef CONFIG_ASPEED_SLT
42027+#define CONFIG_FLASH_AST2300
42028+#define CONFIG_FLASH_AST2300_DMA
42029+//#define CONFIG_FLASH_SPIx2_Dummy
42030+//#define CONFIG_FLASH_SPIx4_Dummy
42031+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
42032+
42033+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42034+#define CONFIG_MISC_INIT_R
42035+
42036+/*
42037+ * DRAM Config
42038+ *
42039+ * 1. DRAM Size //
42040+ * CONFIG_DRAM_512MBIT // 512M bit
42041+ * CONFIG_DRAM_1GBIT // 1G bit (default)
42042+ * CONFIG_DRAM_2GBIT // 2G bit
42043+ * CONFIG_DRAM_4GBIT // 4G bit
42044+ * 2. DRAM Speed //
42045+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
42046+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
42047+ * 3. VGA Mode
42048+ * CONFIG_CRT_DISPLAY // define to disable VGA function
42049+ * 4. ECC Function enable
42050+ * CONFIG_DRAM_ECC // define to enable ECC function
42051+ * 5. UART Debug Message
42052+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
42053+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
42054+ */
42055+
42056+//1. DRAM Size
42057+//#define CONFIG_DRAM_512MBIT
42058+#define CONFIG_DRAM_1GBIT
42059+//#define CONFIG_DRAM_2GBIT
42060+//#define CONFIG_DRAM_4GBIT
42061+//2. DRAM Speed
42062+//#define CONFIG_DRAM_336
42063+#define CONFIG_DRAM_408
42064+//3. VGA Mode
42065+//#define CONFIG_CRT_DISPLAY
42066+//4. ECC Function enable
42067+//#define CONFIG_DRAM_ECC
42068+//5. UART Debug Message
42069+#define CONFIG_DRAM_UART_OUT
42070+//#define CONFIG_DRAM_UART_38400
42071+
42072+
42073+
42074+/*
42075+ * Environment Config
42076+ */
42077+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42078+#define CONFIG_SETUP_MEMORY_TAGS 1
42079+#define CONFIG_INITRD_TAG 1
42080+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
42081+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
42082+#ifdef CONFIG_FLASH_AST2300
42083+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
42084+#else
42085+#ifdef CONFIG_SYS_FLASH_CFI
42086+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
42087+#else
42088+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
42089+#endif
42090+#endif
42091+#define CONFIG_BOOTFILE "all.bin"
42092+#define CONFIG_ENV_OVERWRITE
42093+
42094+/*
42095+ * Command line configuration.
42096+ */
42097+#include <config_cmd_default.h>
42098+
42099+#define CONFIG_CMD_DFL
42100+#define CONFIG_CMD_ENV
42101+#define CONFIG_CMD_FLASH
42102+#define CONFIG_CMD_NET
42103+#define CONFIG_CMD_PING
42104+#define CONFIG_CMD_I2C
42105+#define CONFIG_CMD_EEPROM
42106+
42107+/*
42108+ * CPU Setting
42109+ */
42110+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
42111+
42112+/*
42113+ * Size of malloc() pool
42114+ */
42115+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
42116+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
42117+
42118+/*
42119+ * Stack sizes, The stack sizes are set up in start.S using the settings below
42120+ */
42121+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
42122+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
42123+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
42124+
42125+/*
42126+ * Memory Configuration
42127+ */
42128+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
42129+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
42130+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
42131+
42132+#define CONFIG_SYS_SDRAM_BASE 0x40000000
42133+
42134+/*
42135+ * FLASH Configuration
42136+ */
42137+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
42138+
42139+#ifdef CONFIG_FLASH_AST2300
42140+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
42141+#else
42142+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
42143+#endif
42144+
42145+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
42146+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
42147+
42148+#define CONFIG_SYS_MAX_FLASH_BANKS 1
42149+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
42150+
42151+#define CONFIG_ENV_IS_IN_FLASH 1
42152+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
42153+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
42154+
42155+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
42156+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
42157+
42158+#else /* SPI Flash */
42159+
42160+#ifdef CONFIG_FLASH_AST2300
42161+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
42162+#else
42163+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
42164+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
42165+#define PHYS_FLASH_2_BASE 0x10000000
42166+#endif
42167+
42168+#ifdef CONFIG_2SPIFLASH
42169+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
42170+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
42171+#define CONFIG_SYS_MAX_FLASH_BANKS 2
42172+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
42173+
42174+#define CONFIG_ENV_IS_IN_FLASH 1
42175+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
42176+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
42177+#else
42178+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
42179+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
42180+#define CONFIG_SYS_MAX_FLASH_BANKS 1
42181+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
42182+
42183+#define CONFIG_ENV_IS_IN_FLASH 1
42184+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
42185+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
42186+#endif
42187+
42188+#endif
42189+
42190+#define __LITTLE_ENDIAN
42191+
42192+#define CONFIG_MONITOR_BASE TEXT_BASE
42193+#define CONFIG_MONITOR_LEN (192 << 10)
42194+
42195+/* timeout values are in ticks */
42196+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
42197+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
42198+
42199+/*
42200+ * Miscellaneous configurable options
42201+ */
42202+#define CONFIG_SYS_LONGHELP /* undef to save memory */
42203+
42204+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
42205+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
42206+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
42207+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
42208+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
42209+
42210+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
42211+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
42212+
42213+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
42214+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
42215+
42216+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
42217+
42218+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
42219+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
42220+
42221+/*
42222+ * Serial Configuration
42223+ */
42224+#define CONFIG_SYS_NS16550
42225+#define CONFIG_SYS_NS16550_SERIAL
42226+#define CONFIG_SYS_NS16550_REG_SIZE 4
42227+#define CONFIG_SYS_NS16550_CLK 24000000
42228+#define CONFIG_SYS_NS16550_COM1 0x1e783000
42229+#define CONFIG_SYS_NS16550_COM2 0x1e784000
42230+#define CONFIG_SYS_LOADS_BAUD_CHANGE
42231+#define CONFIG_SERIAL1 1
42232+#define CONFIG_CONS_INDEX 2
42233+#define CONFIG_BAUDRATE 115200
42234+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
42235+
42236+/*
42237+ * USB device configuration
42238+ */
42239+/*
42240+#define CONFIG_USB_DEVICE 1
42241+#define CONFIG_USB_TTY 1
42242+
42243+#define CONFIG_USBD_VENDORID 0x1234
42244+#define CONFIG_USBD_PRODUCTID 0x5678
42245+#define CONFIG_USBD_MANUFACTURER "Siemens"
42246+#define CONFIG_USBD_PRODUCT_NAME "SX1"
42247+*/
42248+
42249+/*
42250+ * I2C configuration
42251+ */
42252+#define CONFIG_HARD_I2C
42253+#define CONFIG_SYS_I2C_SPEED 100000
42254+#define CONFIG_SYS_I2C_SLAVE 1
42255+#define CONFIG_DRIVER_ASPEED_I2C
42256+
42257+/*
42258+* EEPROM configuration
42259+*/
42260+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
42261+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
42262+
42263+/*
42264+ * NIC configuration
42265+ */
42266+#define __BYTE_ORDER __LITTLE_ENDIAN
42267+#define __LITTLE_ENDIAN_BITFIELD
42268+#define CONFIG_MAC_PARTITION
42269+#define CONFIG_ASPEEDNIC
42270+//#define CONFIG_MAC1_PHY_LINK_INTERRUPT
42271+#define CONFIG_MAC2_ENABLE
42272+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
42273+/*
42274+*-------------------------------------------------------------------------------
42275+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
42276+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
42277+* inform kernel driver.
42278+* The meanings of the 2 bits are:
42279+* 00(0): Dedicated PHY
42280+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
42281+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
42282+* 11: Reserved
42283+*
42284+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
42285+* 0: Dedicated PHY
42286+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
42287+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
42288+* 3: Reserved
42289+*-------------------------------------------------------------------------------
42290+*/
42291+#define CONFIG_MAC1_PHY_SETTING 0
42292+#define CONFIG_MAC2_PHY_SETTING 0
42293+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
42294+#define CONFIG_NET_MULTI
42295+#define CONFIG_ETHACT aspeednic#0
42296+#define CONFIG_GATEWAYIP 192.168.0.1
42297+#define CONFIG_NETMASK 255.255.255.0
42298+#define CONFIG_IPADDR 192.168.0.188
42299+#define CONFIG_SERVERIP 192.168.0.106
42300+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
42301+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
42302+
42303+/*
42304+ * SLT
42305+ */
42306+/*
42307+#define CONFIG_SLT
42308+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
42309+*/
42310+
42311+#endif /* __CONFIG_H */
42312diff --git a/include/configs/ast2400.h b/include/configs/ast2400.h
42313new file mode 100644
42314index 0000000..670fcfd
42315--- /dev/null
42316+++ b/include/configs/ast2400.h
42317@@ -0,0 +1,328 @@
42318+/*
42319+ * (C) Copyright 2004
42320+ * Peter Chen <peterc@socle-tech.com.tw>
42321+ *
42322+ * This program is free software; you can redistribute it and/or
42323+ * modify it under the terms of the GNU General Public License as
42324+ * published by the Free Software Foundation; either version 2 of
42325+ * the License, or (at your option) any later version.
42326+ *
42327+ * This program is distributed in the hope that it will be useful,
42328+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
42329+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42330+ * GNU General Public License for more details.
42331+ *
42332+ * You should have received a copy of the GNU General Public License
42333+ * along with this program; if not, write to the Free Software
42334+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42335+ * MA 02111-1307 USA
42336+ */
42337+
42338+#ifndef __CONFIG_H
42339+#define __CONFIG_H
42340+
42341+/*
42342+ * High Level Configuration Options
42343+ * (easy to change)
42344+ */
42345+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
42346+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
42347+//#define CONFIG_FPGA_ASPEED 1
42348+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
42349+#define CONFIG_ASPEED 1
42350+#define CONFIG_AST2400 1
42351+//#define CONFIG_AST1070 1
42352+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
42353+#define CONFIG_FLASH_SPI
42354+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
42355+#undef CONFIG_2SPIFLASH
42356+#undef CONFIG_ASPEED_SLT
42357+#define CONFIG_FLASH_AST2300
42358+//#define CONFIG_FLASH_AST2300_DMA
42359+//#define CONFIG_FLASH_SPIx2_Dummy
42360+//#define CONFIG_FLASH_SPIx4_Dummy
42361+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
42362+
42363+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42364+#define CONFIG_MISC_INIT_R
42365+
42366+/*
42367+ * DRAM Config
42368+ *
42369+ * 1. DRAM Size //
42370+ * CONFIG_DRAM_512MBIT // 512M bit
42371+ * CONFIG_DRAM_1GBIT // 1G bit (default)
42372+ * CONFIG_DRAM_2GBIT // 2G bit
42373+ * CONFIG_DRAM_4GBIT // 4G bit
42374+ * 2. DRAM Speed //
42375+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
42376+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
42377+ * 3. VGA Mode
42378+ * CONFIG_CRT_DISPLAY // define to disable VGA function
42379+ * 4. ECC Function enable
42380+ * CONFIG_DRAM_ECC // define to enable ECC function
42381+ * 5. UART Debug Message
42382+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
42383+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
42384+ */
42385+
42386+//1. DRAM Size
42387+//#define CONFIG_DRAM_512MBIT
42388+#define CONFIG_DRAM_1GBIT
42389+//#define CONFIG_DRAM_2GBIT
42390+//#define CONFIG_DRAM_4GBIT
42391+//2. DRAM Speed
42392+//#define CONFIG_DRAM_336
42393+#define CONFIG_DRAM_408
42394+//3. VGA Mode
42395+//#define CONFIG_CRT_DISPLAY
42396+//4. ECC Function enable
42397+//#define CONFIG_DRAM_ECC
42398+//5. UART Debug Message
42399+#define CONFIG_DRAM_UART_OUT
42400+//#define CONFIG_DRAM_UART_38400
42401+
42402+
42403+
42404+/*
42405+ * Environment Config
42406+ */
42407+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42408+#define CONFIG_SETUP_MEMORY_TAGS 1
42409+#define CONFIG_INITRD_TAG 1
42410+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
42411+#define CONFIG_UPDATE "tftp 40800000 ast2400.scr; so 40800000'"
42412+
42413+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
42414+#ifdef CONFIG_FLASH_AST2300
42415+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
42416+#else
42417+#ifdef CONFIG_SYS_FLASH_CFI
42418+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
42419+#else
42420+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
42421+#endif
42422+#endif
42423+#define CONFIG_BOOTFILE "all.bin"
42424+#define CONFIG_ENV_OVERWRITE
42425+
42426+/*
42427+ * Command line configuration.
42428+ */
42429+#include <config_cmd_default.h>
42430+
42431+#define CONFIG_CMD_DFL
42432+#define CONFIG_CMD_ENV
42433+#define CONFIG_CMD_FLASH
42434+#define CONFIG_CMD_NET
42435+#define CONFIG_CMD_PING
42436+#define CONFIG_CMD_I2C
42437+#define CONFIG_CMD_EEPROM
42438+#define CONFIG_CMD_NETTEST
42439+#define CONFIG_CMD_SLT
42440+
42441+/*
42442+ * CPU Setting
42443+ */
42444+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
42445+
42446+/*
42447+ * Size of malloc() pool
42448+ */
42449+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
42450+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
42451+
42452+/*
42453+ * Stack sizes, The stack sizes are set up in start.S using the settings below
42454+ */
42455+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
42456+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
42457+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
42458+
42459+/*
42460+ * Memory Configuration
42461+ */
42462+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
42463+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
42464+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
42465+
42466+#define CONFIG_SYS_SDRAM_BASE 0x40000000
42467+
42468+/*
42469+ * FLASH Configuration
42470+ */
42471+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
42472+
42473+#ifdef CONFIG_FLASH_AST2300
42474+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
42475+#else
42476+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
42477+#endif
42478+
42479+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
42480+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
42481+
42482+#define CONFIG_SYS_MAX_FLASH_BANKS 1
42483+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
42484+
42485+#define CONFIG_ENV_IS_IN_FLASH 1
42486+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
42487+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
42488+
42489+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
42490+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
42491+
42492+#else /* SPI Flash */
42493+
42494+#ifdef CONFIG_FLASH_AST2300
42495+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
42496+#else
42497+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
42498+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
42499+#define PHYS_FLASH_2_BASE 0x10000000
42500+#endif
42501+
42502+#ifdef CONFIG_2SPIFLASH
42503+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
42504+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
42505+#define CONFIG_SYS_MAX_FLASH_BANKS 2
42506+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
42507+
42508+#define CONFIG_ENV_IS_IN_FLASH 1
42509+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
42510+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
42511+#else
42512+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
42513+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
42514+#define CONFIG_SYS_MAX_FLASH_BANKS 1
42515+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
42516+
42517+#define CONFIG_ENV_IS_IN_FLASH 1
42518+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
42519+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
42520+#endif
42521+
42522+#endif
42523+
42524+#define __LITTLE_ENDIAN
42525+
42526+#define CONFIG_MONITOR_BASE TEXT_BASE
42527+#define CONFIG_MONITOR_LEN (192 << 10)
42528+
42529+/* timeout values are in ticks */
42530+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
42531+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
42532+
42533+/*
42534+ * Miscellaneous configurable options
42535+ */
42536+#define CONFIG_SYS_LONGHELP /* undef to save memory */
42537+
42538+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
42539+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
42540+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
42541+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
42542+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
42543+
42544+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
42545+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
42546+
42547+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
42548+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
42549+
42550+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
42551+
42552+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
42553+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
42554+
42555+/*
42556+ * Serial Configuration
42557+ */
42558+#define CONFIG_SYS_NS16550
42559+#define CONFIG_SYS_NS16550_SERIAL
42560+#define CONFIG_SYS_NS16550_REG_SIZE 4
42561+#define CONFIG_SYS_NS16550_CLK 24000000
42562+#define CONFIG_SYS_NS16550_COM1 0x1e783000
42563+#define CONFIG_SYS_NS16550_COM2 0x1e784000
42564+#define CONFIG_SYS_LOADS_BAUD_CHANGE
42565+#define CONFIG_SERIAL1 1
42566+#define CONFIG_CONS_INDEX 2
42567+#define CONFIG_BAUDRATE 115200
42568+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
42569+
42570+/*
42571+ * USB device configuration
42572+ */
42573+/*
42574+#define CONFIG_USB_DEVICE 1
42575+#define CONFIG_USB_TTY 1
42576+
42577+#define CONFIG_USBD_VENDORID 0x1234
42578+#define CONFIG_USBD_PRODUCTID 0x5678
42579+#define CONFIG_USBD_MANUFACTURER "Siemens"
42580+#define CONFIG_USBD_PRODUCT_NAME "SX1"
42581+*/
42582+
42583+/*
42584+ * I2C configuration
42585+ */
42586+#define CONFIG_HARD_I2C
42587+#define CONFIG_SYS_I2C_SPEED 100000
42588+#define CONFIG_SYS_I2C_SLAVE 1
42589+#define CONFIG_DRIVER_ASPEED_I2C
42590+
42591+/*
42592+* EEPROM configuration
42593+*/
42594+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
42595+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
42596+
42597+/*
42598+ * NIC configuration
42599+ */
42600+#define __BYTE_ORDER __LITTLE_ENDIAN
42601+#define __LITTLE_ENDIAN_BITFIELD
42602+#define CONFIG_MAC_PARTITION
42603+#define CONFIG_ASPEEDNIC
42604+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
42605+#define CONFIG_MAC2_ENABLE
42606+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
42607+/*
42608+*-------------------------------------------------------------------------------
42609+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
42610+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
42611+* inform kernel driver.
42612+* The meanings of the 2 bits are:
42613+* 00(0): Dedicated PHY
42614+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
42615+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
42616+* 11: Reserved
42617+*
42618+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
42619+* 0: Dedicated PHY
42620+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
42621+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
42622+* 3: Reserved
42623+*-------------------------------------------------------------------------------
42624+*/
42625+#define CONFIG_MAC1_PHY_SETTING 0
42626+#define CONFIG_MAC2_PHY_SETTING 0
42627+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
42628+#define CONFIG_NET_MULTI
42629+#define CONFIG_ETHACT aspeednic#0
42630+#define CONFIG_GATEWAYIP 192.168.0.1
42631+#define CONFIG_NETMASK 255.255.255.0
42632+#define CONFIG_IPADDR 192.168.0.45
42633+#define CONFIG_SERVERIP 192.168.0.81
42634+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
42635+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
42636+
42637+/*
42638+ * SLT
42639+ */
42640+/*
42641+#define CONFIG_SLT
42642+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
42643+*/
42644+
42645+#endif /* __CONFIG_H */
42646diff --git a/include/configs/ast2400_ast1070.h b/include/configs/ast2400_ast1070.h
42647new file mode 100644
42648index 0000000..df6c44b
42649--- /dev/null
42650+++ b/include/configs/ast2400_ast1070.h
42651@@ -0,0 +1,326 @@
42652+/*
42653+ * (C) Copyright 2004
42654+ * Peter Chen <peterc@socle-tech.com.tw>
42655+ *
42656+ * This program is free software; you can redistribute it and/or
42657+ * modify it under the terms of the GNU General Public License as
42658+ * published by the Free Software Foundation; either version 2 of
42659+ * the License, or (at your option) any later version.
42660+ *
42661+ * This program is distributed in the hope that it will be useful,
42662+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
42663+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42664+ * GNU General Public License for more details.
42665+ *
42666+ * You should have received a copy of the GNU General Public License
42667+ * along with this program; if not, write to the Free Software
42668+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42669+ * MA 02111-1307 USA
42670+ */
42671+
42672+#ifndef __CONFIG_H
42673+#define __CONFIG_H
42674+
42675+/*
42676+ * High Level Configuration Options
42677+ * (easy to change)
42678+ */
42679+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
42680+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
42681+//#define CONFIG_FPGA_ASPEED 1
42682+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
42683+#define CONFIG_ASPEED 1
42684+#define CONFIG_AST2400 1
42685+#define CONFIG_AST1070 1
42686+//#define CONFIG_CALIBRATION 1
42687+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
42688+#define CONFIG_FLASH_SPI
42689+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
42690+#undef CONFIG_2SPIFLASH
42691+#undef CONFIG_ASPEED_SLT
42692+#define CONFIG_FLASH_AST2300
42693+#define CONFIG_FLASH_AST2300_DMA
42694+//#define CONFIG_FLASH_SPIx2_Dummy
42695+//#define CONFIG_FLASH_SPIx4_Dummy
42696+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
42697+
42698+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42699+#define CONFIG_MISC_INIT_R
42700+
42701+/*
42702+ * DRAM Config
42703+ *
42704+ * 1. DRAM Size //
42705+ * CONFIG_DRAM_512MBIT // 512M bit
42706+ * CONFIG_DRAM_1GBIT // 1G bit (default)
42707+ * CONFIG_DRAM_2GBIT // 2G bit
42708+ * CONFIG_DRAM_4GBIT // 4G bit
42709+ * 2. DRAM Speed //
42710+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
42711+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
42712+ * 3. VGA Mode
42713+ * CONFIG_CRT_DISPLAY // define to disable VGA function
42714+ * 4. ECC Function enable
42715+ * CONFIG_DRAM_ECC // define to enable ECC function
42716+ * 5. UART Debug Message
42717+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
42718+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
42719+ */
42720+
42721+//1. DRAM Size
42722+//#define CONFIG_DRAM_512MBIT
42723+#define CONFIG_DRAM_1GBIT
42724+//#define CONFIG_DRAM_2GBIT
42725+//#define CONFIG_DRAM_4GBIT
42726+//2. DRAM Speed
42727+//#define CONFIG_DRAM_336
42728+#define CONFIG_DRAM_408
42729+//3. VGA Mode
42730+//#define CONFIG_CRT_DISPLAY
42731+//4. ECC Function enable
42732+//#define CONFIG_DRAM_ECC
42733+//5. UART Debug Message
42734+#define CONFIG_DRAM_UART_OUT
42735+//#define CONFIG_DRAM_UART_38400
42736+
42737+
42738+
42739+/*
42740+ * Environment Config
42741+ */
42742+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42743+#define CONFIG_SETUP_MEMORY_TAGS 1
42744+#define CONFIG_INITRD_TAG 1
42745+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
42746+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
42747+#ifdef CONFIG_FLASH_AST2300
42748+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
42749+#else
42750+#ifdef CONFIG_SYS_FLASH_CFI
42751+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
42752+#else
42753+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
42754+#endif
42755+#endif
42756+#define CONFIG_BOOTFILE "all.bin"
42757+#define CONFIG_ENV_OVERWRITE
42758+
42759+/*
42760+ * Command line configuration.
42761+ */
42762+#include <config_cmd_default.h>
42763+
42764+#define CONFIG_CMD_DFL
42765+#define CONFIG_CMD_ENV
42766+#define CONFIG_CMD_FLASH
42767+#define CONFIG_CMD_NET
42768+#define CONFIG_CMD_PING
42769+#define CONFIG_CMD_I2C
42770+#define CONFIG_CMD_EEPROM
42771+#define CONFIG_CMD_NETTEST
42772+
42773+/*
42774+ * CPU Setting
42775+ */
42776+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
42777+
42778+/*
42779+ * Size of malloc() pool
42780+ */
42781+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
42782+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
42783+
42784+/*
42785+ * Stack sizes, The stack sizes are set up in start.S using the settings below
42786+ */
42787+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
42788+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
42789+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
42790+
42791+/*
42792+ * Memory Configuration
42793+ */
42794+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
42795+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
42796+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
42797+
42798+#define CONFIG_SYS_SDRAM_BASE 0x40000000
42799+
42800+/*
42801+ * FLASH Configuration
42802+ */
42803+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
42804+
42805+#ifdef CONFIG_FLASH_AST2300
42806+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
42807+#else
42808+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
42809+#endif
42810+
42811+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
42812+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
42813+
42814+#define CONFIG_SYS_MAX_FLASH_BANKS 1
42815+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
42816+
42817+#define CONFIG_ENV_IS_IN_FLASH 1
42818+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
42819+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
42820+
42821+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
42822+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
42823+
42824+#else /* SPI Flash */
42825+
42826+#ifdef CONFIG_FLASH_AST2300
42827+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
42828+#else
42829+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
42830+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
42831+#define PHYS_FLASH_2_BASE 0x10000000
42832+#endif
42833+
42834+#ifdef CONFIG_2SPIFLASH
42835+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
42836+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
42837+#define CONFIG_SYS_MAX_FLASH_BANKS 2
42838+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
42839+
42840+#define CONFIG_ENV_IS_IN_FLASH 1
42841+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
42842+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
42843+#else
42844+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
42845+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
42846+#define CONFIG_SYS_MAX_FLASH_BANKS 1
42847+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
42848+
42849+#define CONFIG_ENV_IS_IN_FLASH 1
42850+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
42851+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
42852+#endif
42853+
42854+#endif
42855+
42856+#define __LITTLE_ENDIAN
42857+
42858+#define CONFIG_MONITOR_BASE TEXT_BASE
42859+#define CONFIG_MONITOR_LEN (192 << 10)
42860+
42861+/* timeout values are in ticks */
42862+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
42863+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
42864+
42865+/*
42866+ * Miscellaneous configurable options
42867+ */
42868+#define CONFIG_SYS_LONGHELP /* undef to save memory */
42869+
42870+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
42871+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
42872+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
42873+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
42874+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
42875+
42876+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
42877+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
42878+
42879+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
42880+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
42881+
42882+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
42883+
42884+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
42885+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
42886+
42887+/*
42888+ * Serial Configuration
42889+ */
42890+#define CONFIG_SYS_NS16550
42891+#define CONFIG_SYS_NS16550_SERIAL
42892+#define CONFIG_SYS_NS16550_REG_SIZE 4
42893+#define CONFIG_SYS_NS16550_CLK 24000000
42894+#define CONFIG_SYS_NS16550_COM1 0x1e783000
42895+#define CONFIG_SYS_NS16550_COM2 0x1e784000
42896+#define CONFIG_SYS_LOADS_BAUD_CHANGE
42897+#define CONFIG_SERIAL1 1
42898+#define CONFIG_CONS_INDEX 2
42899+#define CONFIG_BAUDRATE 115200
42900+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
42901+
42902+/*
42903+ * USB device configuration
42904+ */
42905+/*
42906+#define CONFIG_USB_DEVICE 1
42907+#define CONFIG_USB_TTY 1
42908+
42909+#define CONFIG_USBD_VENDORID 0x1234
42910+#define CONFIG_USBD_PRODUCTID 0x5678
42911+#define CONFIG_USBD_MANUFACTURER "Siemens"
42912+#define CONFIG_USBD_PRODUCT_NAME "SX1"
42913+*/
42914+
42915+/*
42916+ * I2C configuration
42917+ */
42918+#define CONFIG_HARD_I2C
42919+#define CONFIG_SYS_I2C_SPEED 100000
42920+#define CONFIG_SYS_I2C_SLAVE 1
42921+#define CONFIG_DRIVER_ASPEED_I2C
42922+
42923+/*
42924+* EEPROM configuration
42925+*/
42926+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
42927+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
42928+
42929+/*
42930+ * NIC configuration
42931+ */
42932+#define __BYTE_ORDER __LITTLE_ENDIAN
42933+#define __LITTLE_ENDIAN_BITFIELD
42934+#define CONFIG_MAC_PARTITION
42935+#define CONFIG_ASPEEDNIC
42936+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
42937+#define CONFIG_MAC2_ENABLE
42938+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
42939+/*
42940+*-------------------------------------------------------------------------------
42941+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
42942+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
42943+* inform kernel driver.
42944+* The meanings of the 2 bits are:
42945+* 00(0): Dedicated PHY
42946+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
42947+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
42948+* 11: Reserved
42949+*
42950+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
42951+* 0: Dedicated PHY
42952+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
42953+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
42954+* 3: Reserved
42955+*-------------------------------------------------------------------------------
42956+*/
42957+#define CONFIG_MAC1_PHY_SETTING 0
42958+#define CONFIG_MAC2_PHY_SETTING 0
42959+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
42960+#define CONFIG_NET_MULTI
42961+#define CONFIG_ETHACT aspeednic#0
42962+#define CONFIG_GATEWAYIP 192.168.0.1
42963+#define CONFIG_NETMASK 255.255.255.0
42964+#define CONFIG_IPADDR 192.168.0.41
42965+#define CONFIG_SERVERIP 192.168.0.81
42966+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
42967+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
42968+
42969+/*
42970+ * SLT
42971+ */
42972+/*
42973+#define CONFIG_SLT
42974+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
42975+*/
42976+
42977+#endif /* __CONFIG_H */
42978diff --git a/include/configs/ast2400_ast10701.h b/include/configs/ast2400_ast10701.h
42979new file mode 100644
42980index 0000000..4553535
42981--- /dev/null
42982+++ b/include/configs/ast2400_ast10701.h
42983@@ -0,0 +1,327 @@
42984+/*
42985+ * (C) Copyright 2004
42986+ * Peter Chen <peterc@socle-tech.com.tw>
42987+ *
42988+ * This program is free software; you can redistribute it and/or
42989+ * modify it under the terms of the GNU General Public License as
42990+ * published by the Free Software Foundation; either version 2 of
42991+ * the License, or (at your option) any later version.
42992+ *
42993+ * This program is distributed in the hope that it will be useful,
42994+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
42995+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42996+ * GNU General Public License for more details.
42997+ *
42998+ * You should have received a copy of the GNU General Public License
42999+ * along with this program; if not, write to the Free Software
43000+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43001+ * MA 02111-1307 USA
43002+ */
43003+
43004+#ifndef __CONFIG_H
43005+#define __CONFIG_H
43006+
43007+/*
43008+ * High Level Configuration Options
43009+ * (easy to change)
43010+ */
43011+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
43012+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
43013+//#define CONFIG_FPGA_ASPEED 1
43014+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
43015+#define CONFIG_ASPEED 1
43016+#define CONFIG_AST2400 1
43017+#define CONFIG_AST1070 1
43018+#define CONFIG_LPC_PLUS 1
43019+//#define CONFIG_CALIBRATION 1
43020+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
43021+#define CONFIG_FLASH_SPI
43022+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
43023+#undef CONFIG_2SPIFLASH
43024+#undef CONFIG_ASPEED_SLT
43025+#define CONFIG_FLASH_AST2300
43026+#define CONFIG_FLASH_AST2300_DMA
43027+//#define CONFIG_FLASH_SPIx2_Dummy
43028+//#define CONFIG_FLASH_SPIx4_Dummy
43029+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
43030+
43031+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
43032+#define CONFIG_MISC_INIT_R
43033+
43034+/*
43035+ * DRAM Config
43036+ *
43037+ * 1. DRAM Size //
43038+ * CONFIG_DRAM_512MBIT // 512M bit
43039+ * CONFIG_DRAM_1GBIT // 1G bit (default)
43040+ * CONFIG_DRAM_2GBIT // 2G bit
43041+ * CONFIG_DRAM_4GBIT // 4G bit
43042+ * 2. DRAM Speed //
43043+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
43044+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
43045+ * 3. VGA Mode
43046+ * CONFIG_CRT_DISPLAY // define to disable VGA function
43047+ * 4. ECC Function enable
43048+ * CONFIG_DRAM_ECC // define to enable ECC function
43049+ * 5. UART Debug Message
43050+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
43051+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
43052+ */
43053+
43054+//1. DRAM Size
43055+//#define CONFIG_DRAM_512MBIT
43056+#define CONFIG_DRAM_1GBIT
43057+//#define CONFIG_DRAM_2GBIT
43058+//#define CONFIG_DRAM_4GBIT
43059+//2. DRAM Speed
43060+//#define CONFIG_DRAM_336
43061+#define CONFIG_DRAM_408
43062+//3. VGA Mode
43063+//#define CONFIG_CRT_DISPLAY
43064+//4. ECC Function enable
43065+//#define CONFIG_DRAM_ECC
43066+//5. UART Debug Message
43067+#define CONFIG_DRAM_UART_OUT
43068+//#define CONFIG_DRAM_UART_38400
43069+
43070+
43071+
43072+/*
43073+ * Environment Config
43074+ */
43075+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
43076+#define CONFIG_SETUP_MEMORY_TAGS 1
43077+#define CONFIG_INITRD_TAG 1
43078+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
43079+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
43080+#ifdef CONFIG_FLASH_AST2300
43081+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
43082+#else
43083+#ifdef CONFIG_SYS_FLASH_CFI
43084+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
43085+#else
43086+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
43087+#endif
43088+#endif
43089+#define CONFIG_BOOTFILE "all.bin"
43090+#define CONFIG_ENV_OVERWRITE
43091+
43092+/*
43093+ * Command line configuration.
43094+ */
43095+#include <config_cmd_default.h>
43096+
43097+#define CONFIG_CMD_DFL
43098+#define CONFIG_CMD_ENV
43099+#define CONFIG_CMD_FLASH
43100+#define CONFIG_CMD_NET
43101+#define CONFIG_CMD_PING
43102+#define CONFIG_CMD_I2C
43103+#define CONFIG_CMD_EEPROM
43104+#define CONFIG_CMD_NETTEST
43105+
43106+/*
43107+ * CPU Setting
43108+ */
43109+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
43110+
43111+/*
43112+ * Size of malloc() pool
43113+ */
43114+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
43115+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
43116+
43117+/*
43118+ * Stack sizes, The stack sizes are set up in start.S using the settings below
43119+ */
43120+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
43121+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
43122+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
43123+
43124+/*
43125+ * Memory Configuration
43126+ */
43127+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
43128+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
43129+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
43130+
43131+#define CONFIG_SYS_SDRAM_BASE 0x40000000
43132+
43133+/*
43134+ * FLASH Configuration
43135+ */
43136+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
43137+
43138+#ifdef CONFIG_FLASH_AST2300
43139+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
43140+#else
43141+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
43142+#endif
43143+
43144+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
43145+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
43146+
43147+#define CONFIG_SYS_MAX_FLASH_BANKS 1
43148+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
43149+
43150+#define CONFIG_ENV_IS_IN_FLASH 1
43151+#define CONFIG_ENV_OFFSET 0xFE0000 /* environment starts here */
43152+#define CONFIG_ENV_SIZE 0x020000 /* Total Size of Environment Sector */
43153+
43154+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
43155+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
43156+
43157+#else /* SPI Flash */
43158+
43159+#ifdef CONFIG_FLASH_AST2300
43160+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
43161+#else
43162+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
43163+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
43164+#define PHYS_FLASH_2_BASE 0x10000000
43165+#endif
43166+
43167+#ifdef CONFIG_2SPIFLASH
43168+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
43169+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
43170+#define CONFIG_SYS_MAX_FLASH_BANKS 2
43171+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
43172+
43173+#define CONFIG_ENV_IS_IN_FLASH 1
43174+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
43175+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
43176+#else
43177+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
43178+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
43179+#define CONFIG_SYS_MAX_FLASH_BANKS 1
43180+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
43181+
43182+#define CONFIG_ENV_IS_IN_FLASH 1
43183+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
43184+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
43185+#endif
43186+
43187+#endif
43188+
43189+#define __LITTLE_ENDIAN
43190+
43191+#define CONFIG_MONITOR_BASE TEXT_BASE
43192+#define CONFIG_MONITOR_LEN (192 << 10)
43193+
43194+/* timeout values are in ticks */
43195+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
43196+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
43197+
43198+/*
43199+ * Miscellaneous configurable options
43200+ */
43201+#define CONFIG_SYS_LONGHELP /* undef to save memory */
43202+
43203+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
43204+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
43205+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
43206+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
43207+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
43208+
43209+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
43210+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
43211+
43212+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
43213+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
43214+
43215+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
43216+
43217+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
43218+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
43219+
43220+/*
43221+ * Serial Configuration
43222+ */
43223+#define CONFIG_SYS_NS16550
43224+#define CONFIG_SYS_NS16550_SERIAL
43225+#define CONFIG_SYS_NS16550_REG_SIZE 4
43226+#define CONFIG_SYS_NS16550_CLK 24000000
43227+#define CONFIG_SYS_NS16550_COM1 0x1e783000
43228+#define CONFIG_SYS_NS16550_COM2 0x1e784000
43229+#define CONFIG_SYS_LOADS_BAUD_CHANGE
43230+#define CONFIG_SERIAL1 1
43231+#define CONFIG_CONS_INDEX 2
43232+#define CONFIG_BAUDRATE 115200
43233+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
43234+
43235+/*
43236+ * USB device configuration
43237+ */
43238+/*
43239+#define CONFIG_USB_DEVICE 1
43240+#define CONFIG_USB_TTY 1
43241+
43242+#define CONFIG_USBD_VENDORID 0x1234
43243+#define CONFIG_USBD_PRODUCTID 0x5678
43244+#define CONFIG_USBD_MANUFACTURER "Siemens"
43245+#define CONFIG_USBD_PRODUCT_NAME "SX1"
43246+*/
43247+
43248+/*
43249+ * I2C configuration
43250+ */
43251+#define CONFIG_HARD_I2C
43252+#define CONFIG_SYS_I2C_SPEED 100000
43253+#define CONFIG_SYS_I2C_SLAVE 1
43254+#define CONFIG_DRIVER_ASPEED_I2C
43255+
43256+/*
43257+* EEPROM configuration
43258+*/
43259+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
43260+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
43261+
43262+/*
43263+ * NIC configuration
43264+ */
43265+#define __BYTE_ORDER __LITTLE_ENDIAN
43266+#define __LITTLE_ENDIAN_BITFIELD
43267+#define CONFIG_MAC_PARTITION
43268+#define CONFIG_ASPEEDNIC
43269+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
43270+#define CONFIG_MAC2_ENABLE
43271+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
43272+/*
43273+*-------------------------------------------------------------------------------
43274+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
43275+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
43276+* inform kernel driver.
43277+* The meanings of the 2 bits are:
43278+* 00(0): Dedicated PHY
43279+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
43280+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
43281+* 11: Reserved
43282+*
43283+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
43284+* 0: Dedicated PHY
43285+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
43286+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
43287+* 3: Reserved
43288+*-------------------------------------------------------------------------------
43289+*/
43290+#define CONFIG_MAC1_PHY_SETTING 0
43291+#define CONFIG_MAC2_PHY_SETTING 0
43292+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
43293+#define CONFIG_NET_MULTI
43294+#define CONFIG_ETHACT aspeednic#0
43295+#define CONFIG_GATEWAYIP 192.168.0.1
43296+#define CONFIG_NETMASK 255.255.255.0
43297+#define CONFIG_IPADDR 192.168.0.45
43298+#define CONFIG_SERVERIP 192.168.0.53
43299+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
43300+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
43301+
43302+/*
43303+ * SLT
43304+ */
43305+/*
43306+#define CONFIG_SLT
43307+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
43308+*/
43309+
43310+#endif /* __CONFIG_H */
43311diff --git a/include/configs/ast2400_nor.h b/include/configs/ast2400_nor.h
43312new file mode 100644
43313index 0000000..5b10b36
43314--- /dev/null
43315+++ b/include/configs/ast2400_nor.h
43316@@ -0,0 +1,322 @@
43317+/*
43318+ * (C) Copyright 2004
43319+ * Peter Chen <peterc@socle-tech.com.tw>
43320+ *
43321+ * This program is free software; you can redistribute it and/or
43322+ * modify it under the terms of the GNU General Public License as
43323+ * published by the Free Software Foundation; either version 2 of
43324+ * the License, or (at your option) any later version.
43325+ *
43326+ * This program is distributed in the hope that it will be useful,
43327+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
43328+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43329+ * GNU General Public License for more details.
43330+ *
43331+ * You should have received a copy of the GNU General Public License
43332+ * along with this program; if not, write to the Free Software
43333+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43334+ * MA 02111-1307 USA
43335+ */
43336+
43337+#ifndef __CONFIG_H
43338+#define __CONFIG_H
43339+
43340+/*
43341+ * High Level Configuration Options
43342+ * (easy to change)
43343+ */
43344+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
43345+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
43346+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
43347+#define CONFIG_ASPEED 1
43348+#define CONFIG_AST2400 1
43349+#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
43350+//#define CONFIG_FLASH_SPI
43351+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
43352+#undef CONFIG_2SPIFLASH
43353+#undef CONFIG_ASPEED_SLT
43354+#define CONFIG_FLASH_AST2300
43355+#define CONFIG_FLASH_AST2300_DMA
43356+//#define CONFIG_FLASH_SPIx2_Dummy
43357+//#define CONFIG_FLASH_SPIx4_Dummy
43358+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
43359+
43360+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
43361+#define CONFIG_MISC_INIT_R
43362+
43363+/*
43364+ * DRAM Config
43365+ *
43366+ * 1. DRAM Size //
43367+ * CONFIG_DRAM_512MBIT // 512M bit
43368+ * CONFIG_DRAM_1GBIT // 1G bit (default)
43369+ * CONFIG_DRAM_2GBIT // 2G bit
43370+ * CONFIG_DRAM_4GBIT // 4G bit
43371+ * 2. DRAM Speed //
43372+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
43373+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
43374+ * 3. VGA Mode
43375+ * CONFIG_CRT_DISPLAY // define to disable VGA function
43376+ * 4. ECC Function enable
43377+ * CONFIG_DRAM_ECC // define to enable ECC function
43378+ * 5. UART Debug Message
43379+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
43380+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
43381+ */
43382+
43383+//1. DRAM Size
43384+//#define CONFIG_DRAM_512MBIT
43385+#define CONFIG_DRAM_1GBIT
43386+//#define CONFIG_DRAM_2GBIT
43387+//#define CONFIG_DRAM_4GBIT
43388+//2. DRAM Speed
43389+//#define CONFIG_DRAM_336
43390+#define CONFIG_DRAM_408
43391+//3. VGA Mode
43392+//#define CONFIG_CRT_DISPLAY
43393+//4. ECC Function enable
43394+//#define CONFIG_DRAM_ECC
43395+//5. UART Debug Message
43396+#define CONFIG_DRAM_UART_OUT
43397+//#define CONFIG_DRAM_UART_38400
43398+
43399+
43400+
43401+/*
43402+ * Environment Config
43403+ */
43404+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
43405+#define CONFIG_SETUP_MEMORY_TAGS 1
43406+#define CONFIG_INITRD_TAG 1
43407+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
43408+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
43409+#ifdef CONFIG_FLASH_AST2300
43410+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
43411+#else
43412+#ifdef CONFIG_SYS_FLASH_CFI
43413+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
43414+#else
43415+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
43416+#endif
43417+#endif
43418+#define CONFIG_BOOTFILE "all.bin"
43419+#define CONFIG_ENV_OVERWRITE
43420+
43421+/*
43422+ * Command line configuration.
43423+ */
43424+#include <config_cmd_default.h>
43425+
43426+#define CONFIG_CMD_DFL
43427+#define CONFIG_CMD_ENV
43428+#define CONFIG_CMD_FLASH
43429+#define CONFIG_CMD_NET
43430+#define CONFIG_CMD_PING
43431+#define CONFIG_CMD_I2C
43432+#define CONFIG_CMD_EEPROM
43433+
43434+/*
43435+ * CPU Setting
43436+ */
43437+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
43438+
43439+/*
43440+ * Size of malloc() pool
43441+ */
43442+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
43443+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
43444+
43445+/*
43446+ * Stack sizes, The stack sizes are set up in start.S using the settings below
43447+ */
43448+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
43449+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
43450+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
43451+
43452+/*
43453+ * Memory Configuration
43454+ */
43455+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
43456+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
43457+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
43458+
43459+#define CONFIG_SYS_SDRAM_BASE 0x40000000
43460+
43461+/*
43462+ * FLASH Configuration
43463+ */
43464+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
43465+
43466+#ifdef CONFIG_FLASH_AST2300
43467+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
43468+#else
43469+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
43470+#endif
43471+
43472+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
43473+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
43474+
43475+#define CONFIG_SYS_MAX_FLASH_BANKS 1
43476+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
43477+
43478+#define CONFIG_ENV_IS_IN_FLASH 1
43479+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
43480+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
43481+
43482+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
43483+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
43484+
43485+#else /* SPI Flash */
43486+
43487+#ifdef CONFIG_FLASH_AST2300
43488+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
43489+#else
43490+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
43491+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
43492+#define PHYS_FLASH_2_BASE 0x10000000
43493+#endif
43494+
43495+#ifdef CONFIG_2SPIFLASH
43496+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
43497+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
43498+#define CONFIG_SYS_MAX_FLASH_BANKS 2
43499+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
43500+
43501+#define CONFIG_ENV_IS_IN_FLASH 1
43502+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
43503+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
43504+#else
43505+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
43506+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
43507+#define CONFIG_SYS_MAX_FLASH_BANKS 1
43508+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
43509+
43510+#define CONFIG_ENV_IS_IN_FLASH 1
43511+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
43512+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
43513+#endif
43514+
43515+#endif
43516+
43517+#define __LITTLE_ENDIAN
43518+
43519+#define CONFIG_MONITOR_BASE TEXT_BASE
43520+#define CONFIG_MONITOR_LEN (192 << 10)
43521+
43522+/* timeout values are in ticks */
43523+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
43524+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
43525+
43526+/*
43527+ * Miscellaneous configurable options
43528+ */
43529+#define CONFIG_SYS_LONGHELP /* undef to save memory */
43530+
43531+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
43532+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
43533+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
43534+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
43535+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
43536+
43537+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
43538+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
43539+
43540+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
43541+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
43542+
43543+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
43544+
43545+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
43546+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
43547+
43548+/*
43549+ * Serial Configuration
43550+ */
43551+#define CONFIG_SYS_NS16550
43552+#define CONFIG_SYS_NS16550_SERIAL
43553+#define CONFIG_SYS_NS16550_REG_SIZE 4
43554+#define CONFIG_SYS_NS16550_CLK 24000000
43555+#define CONFIG_SYS_NS16550_COM1 0x1e783000
43556+#define CONFIG_SYS_NS16550_COM2 0x1e784000
43557+#define CONFIG_SYS_LOADS_BAUD_CHANGE
43558+#define CONFIG_SERIAL1 1
43559+#define CONFIG_CONS_INDEX 2
43560+#define CONFIG_BAUDRATE 115200
43561+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
43562+
43563+/*
43564+ * USB device configuration
43565+ */
43566+/*
43567+#define CONFIG_USB_DEVICE 1
43568+#define CONFIG_USB_TTY 1
43569+
43570+#define CONFIG_USBD_VENDORID 0x1234
43571+#define CONFIG_USBD_PRODUCTID 0x5678
43572+#define CONFIG_USBD_MANUFACTURER "Siemens"
43573+#define CONFIG_USBD_PRODUCT_NAME "SX1"
43574+*/
43575+
43576+/*
43577+ * I2C configuration
43578+ */
43579+#define CONFIG_HARD_I2C
43580+#define CONFIG_SYS_I2C_SPEED 100000
43581+#define CONFIG_SYS_I2C_SLAVE 1
43582+#define CONFIG_DRIVER_ASPEED_I2C
43583+
43584+/*
43585+* EEPROM configuration
43586+*/
43587+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
43588+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
43589+
43590+/*
43591+ * NIC configuration
43592+ */
43593+#define __BYTE_ORDER __LITTLE_ENDIAN
43594+#define __LITTLE_ENDIAN_BITFIELD
43595+#define CONFIG_MAC_PARTITION
43596+#define CONFIG_ASPEEDNIC
43597+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
43598+#define CONFIG_MAC2_ENABLE
43599+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
43600+/*
43601+*-------------------------------------------------------------------------------
43602+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
43603+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
43604+* inform kernel driver.
43605+* The meanings of the 2 bits are:
43606+* 00(0): Dedicated PHY
43607+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
43608+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
43609+* 11: Reserved
43610+*
43611+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
43612+* 0: Dedicated PHY
43613+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
43614+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
43615+* 3: Reserved
43616+*-------------------------------------------------------------------------------
43617+*/
43618+#define CONFIG_MAC1_PHY_SETTING 0
43619+#define CONFIG_MAC2_PHY_SETTING 0
43620+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
43621+#define CONFIG_NET_MULTI
43622+#define CONFIG_ETHACT aspeednic#0
43623+#define CONFIG_GATEWAYIP 192.168.0.1
43624+#define CONFIG_NETMASK 255.255.255.0
43625+#define CONFIG_IPADDR 192.168.0.188
43626+#define CONFIG_SERVERIP 192.168.0.106
43627+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
43628+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
43629+
43630+/*
43631+ * SLT
43632+ */
43633+/*
43634+#define CONFIG_SLT
43635+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
43636+*/
43637+
43638+#endif /* __CONFIG_H */
43639diff --git a/include/configs/ast2400_slt.h b/include/configs/ast2400_slt.h
43640new file mode 100644
43641index 0000000..cfa1c31
43642--- /dev/null
43643+++ b/include/configs/ast2400_slt.h
43644@@ -0,0 +1,329 @@
43645+/*
43646+ * (C) Copyright 2004
43647+ * Peter Chen <peterc@socle-tech.com.tw>
43648+ *
43649+ * This program is free software; you can redistribute it and/or
43650+ * modify it under the terms of the GNU General Public License as
43651+ * published by the Free Software Foundation; either version 2 of
43652+ * the License, or (at your option) any later version.
43653+ *
43654+ * This program is distributed in the hope that it will be useful,
43655+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
43656+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43657+ * GNU General Public License for more details.
43658+ *
43659+ * You should have received a copy of the GNU General Public License
43660+ * along with this program; if not, write to the Free Software
43661+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43662+ * MA 02111-1307 USA
43663+ */
43664+
43665+#ifndef __CONFIG_H
43666+#define __CONFIG_H
43667+
43668+/*
43669+ * High Level Configuration Options
43670+ * (easy to change)
43671+ */
43672+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
43673+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
43674+//#define CONFIG_FPGA_ASPEED 1
43675+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
43676+#define CONFIG_ASPEED 1
43677+#define CONFIG_AST2400 1
43678+#define CONFIG_SLT_ASPEED 1
43679+//#define CONFIG_AST1070 1
43680+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
43681+#define CONFIG_FLASH_SPI
43682+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
43683+#undef CONFIG_2SPIFLASH
43684+#undef CONFIG_ASPEED_SLT
43685+#define CONFIG_FLASH_AST2300
43686+//#define CONFIG_FLASH_AST2300_DMA
43687+//#define CONFIG_FLASH_SPIx2_Dummy
43688+//#define CONFIG_FLASH_SPIx4_Dummy
43689+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
43690+
43691+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
43692+#define CONFIG_MISC_INIT_R
43693+
43694+/*
43695+ * DRAM Config
43696+ *
43697+ * 1. DRAM Size //
43698+ * CONFIG_DRAM_512MBIT // 512M bit
43699+ * CONFIG_DRAM_1GBIT // 1G bit (default)
43700+ * CONFIG_DRAM_2GBIT // 2G bit
43701+ * CONFIG_DRAM_4GBIT // 4G bit
43702+ * 2. DRAM Speed //
43703+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
43704+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
43705+ * 3. VGA Mode
43706+ * CONFIG_CRT_DISPLAY // define to disable VGA function
43707+ * 4. ECC Function enable
43708+ * CONFIG_DRAM_ECC // define to enable ECC function
43709+ * 5. UART Debug Message
43710+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
43711+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
43712+ */
43713+
43714+//1. DRAM Size
43715+//#define CONFIG_DRAM_512MBIT
43716+#define CONFIG_DRAM_1GBIT
43717+//#define CONFIG_DRAM_2GBIT
43718+//#define CONFIG_DRAM_4GBIT
43719+//2. DRAM Speed
43720+//#define CONFIG_DRAM_336
43721+#define CONFIG_DRAM_408
43722+//3. VGA Mode
43723+//#define CONFIG_CRT_DISPLAY
43724+//4. ECC Function enable
43725+//#define CONFIG_DRAM_ECC
43726+//5. UART Debug Message
43727+#define CONFIG_DRAM_UART_OUT
43728+//#define CONFIG_DRAM_UART_38400
43729+
43730+
43731+
43732+/*
43733+ * Environment Config
43734+ */
43735+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
43736+#define CONFIG_SETUP_MEMORY_TAGS 1
43737+#define CONFIG_INITRD_TAG 1
43738+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=32M"
43739+#define CONFIG_UPDATE "tftp 40800000 ast2400.scr; so 40800000'"
43740+
43741+#define CONFIG_BOOTDELAY 0 /* autoboot after 3 seconds */
43742+#ifdef CONFIG_FLASH_AST2300
43743+#define CONFIG_BOOTCOMMAND "mactest 0 0 24 2 0 0 0; mactest 1 0 24 2 0 0 0; bootm 20080000 20300000"
43744+#else
43745+#ifdef CONFIG_SYS_FLASH_CFI
43746+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
43747+#else
43748+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
43749+#endif
43750+#endif
43751+#define CONFIG_BOOTFILE "all.bin"
43752+#define CONFIG_ENV_OVERWRITE
43753+
43754+/*
43755+ * Command line configuration.
43756+ */
43757+#include <config_cmd_default.h>
43758+
43759+#define CONFIG_CMD_DFL
43760+#define CONFIG_CMD_ENV
43761+#define CONFIG_CMD_FLASH
43762+#define CONFIG_CMD_NET
43763+#define CONFIG_CMD_PING
43764+#define CONFIG_CMD_I2C
43765+#define CONFIG_CMD_EEPROM
43766+#define CONFIG_CMD_NETTEST
43767+#define CONFIG_CMD_SLT
43768+
43769+/*
43770+ * CPU Setting
43771+ */
43772+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
43773+
43774+/*
43775+ * Size of malloc() pool
43776+ */
43777+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
43778+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
43779+
43780+/*
43781+ * Stack sizes, The stack sizes are set up in start.S using the settings below
43782+ */
43783+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
43784+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
43785+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
43786+
43787+/*
43788+ * Memory Configuration
43789+ */
43790+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
43791+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
43792+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
43793+
43794+#define CONFIG_SYS_SDRAM_BASE 0x40000000
43795+
43796+/*
43797+ * FLASH Configuration
43798+ */
43799+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
43800+
43801+#ifdef CONFIG_FLASH_AST2300
43802+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
43803+#else
43804+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
43805+#endif
43806+
43807+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
43808+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
43809+
43810+#define CONFIG_SYS_MAX_FLASH_BANKS 1
43811+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
43812+
43813+#define CONFIG_ENV_IS_IN_FLASH 1
43814+#define CONFIG_ENV_OFFSET 0xFE0000 /* environment starts here */
43815+#define CONFIG_ENV_SIZE 0x020000 /* Total Size of Environment Sector */
43816+
43817+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
43818+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
43819+
43820+#else /* SPI Flash */
43821+
43822+#ifdef CONFIG_FLASH_AST2300
43823+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
43824+#else
43825+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
43826+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
43827+#define PHYS_FLASH_2_BASE 0x10000000
43828+#endif
43829+
43830+#ifdef CONFIG_2SPIFLASH
43831+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
43832+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
43833+#define CONFIG_SYS_MAX_FLASH_BANKS 2
43834+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
43835+
43836+#define CONFIG_ENV_IS_IN_FLASH 1
43837+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
43838+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
43839+#else
43840+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
43841+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
43842+#define CONFIG_SYS_MAX_FLASH_BANKS 1
43843+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
43844+
43845+#define CONFIG_ENV_IS_IN_FLASH 1
43846+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
43847+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
43848+#endif
43849+
43850+#endif
43851+
43852+#define __LITTLE_ENDIAN
43853+
43854+#define CONFIG_MONITOR_BASE TEXT_BASE
43855+#define CONFIG_MONITOR_LEN (192 << 10)
43856+
43857+/* timeout values are in ticks */
43858+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
43859+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
43860+
43861+/*
43862+ * Miscellaneous configurable options
43863+ */
43864+#define CONFIG_SYS_LONGHELP /* undef to save memory */
43865+
43866+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
43867+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
43868+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
43869+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
43870+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
43871+
43872+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
43873+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
43874+
43875+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
43876+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
43877+
43878+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
43879+
43880+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
43881+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
43882+
43883+/*
43884+ * Serial Configuration
43885+ */
43886+#define CONFIG_SYS_NS16550
43887+#define CONFIG_SYS_NS16550_SERIAL
43888+#define CONFIG_SYS_NS16550_REG_SIZE 4
43889+#define CONFIG_SYS_NS16550_CLK 24000000
43890+#define CONFIG_SYS_NS16550_COM1 0x1e783000
43891+#define CONFIG_SYS_NS16550_COM2 0x1e784000
43892+#define CONFIG_SYS_LOADS_BAUD_CHANGE
43893+#define CONFIG_SERIAL1 1
43894+#define CONFIG_CONS_INDEX 2
43895+#define CONFIG_BAUDRATE 115200
43896+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
43897+
43898+/*
43899+ * USB device configuration
43900+ */
43901+/*
43902+#define CONFIG_USB_DEVICE 1
43903+#define CONFIG_USB_TTY 1
43904+
43905+#define CONFIG_USBD_VENDORID 0x1234
43906+#define CONFIG_USBD_PRODUCTID 0x5678
43907+#define CONFIG_USBD_MANUFACTURER "Siemens"
43908+#define CONFIG_USBD_PRODUCT_NAME "SX1"
43909+*/
43910+
43911+/*
43912+ * I2C configuration
43913+ */
43914+#define CONFIG_HARD_I2C
43915+#define CONFIG_SYS_I2C_SPEED 100000
43916+#define CONFIG_SYS_I2C_SLAVE 1
43917+#define CONFIG_DRIVER_ASPEED_I2C
43918+
43919+/*
43920+* EEPROM configuration
43921+*/
43922+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
43923+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
43924+
43925+/*
43926+ * NIC configuration
43927+ */
43928+#define __BYTE_ORDER __LITTLE_ENDIAN
43929+#define __LITTLE_ENDIAN_BITFIELD
43930+#define CONFIG_MAC_PARTITION
43931+/*#define CONFIG_ASPEEDNIC*/
43932+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
43933+#define CONFIG_MAC2_ENABLE
43934+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
43935+/*
43936+*-------------------------------------------------------------------------------
43937+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
43938+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
43939+* inform kernel driver.
43940+* The meanings of the 2 bits are:
43941+* 00(0): Dedicated PHY
43942+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
43943+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
43944+* 11: Reserved
43945+*
43946+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
43947+* 0: Dedicated PHY
43948+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
43949+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
43950+* 3: Reserved
43951+*-------------------------------------------------------------------------------
43952+*/
43953+#define CONFIG_MAC1_PHY_SETTING 0
43954+#define CONFIG_MAC2_PHY_SETTING 0
43955+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
43956+#define CONFIG_NET_MULTI
43957+#define CONFIG_ETHACT aspeednic#0
43958+#define CONFIG_GATEWAYIP 192.168.0.1
43959+#define CONFIG_NETMASK 255.255.255.0
43960+#define CONFIG_IPADDR 192.168.0.45
43961+#define CONFIG_SERVERIP 192.168.0.81
43962+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
43963+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
43964+
43965+/*
43966+ * SLT
43967+ */
43968+/*
43969+#define CONFIG_SLT
43970+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
43971+*/
43972+
43973+#endif /* __CONFIG_H */
43974diff --git a/include/configs/ast2400_spi.h b/include/configs/ast2400_spi.h
43975new file mode 100644
43976index 0000000..398e168
43977--- /dev/null
43978+++ b/include/configs/ast2400_spi.h
43979@@ -0,0 +1,322 @@
43980+/*
43981+ * (C) Copyright 2004
43982+ * Peter Chen <peterc@socle-tech.com.tw>
43983+ *
43984+ * This program is free software; you can redistribute it and/or
43985+ * modify it under the terms of the GNU General Public License as
43986+ * published by the Free Software Foundation; either version 2 of
43987+ * the License, or (at your option) any later version.
43988+ *
43989+ * This program is distributed in the hope that it will be useful,
43990+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
43991+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43992+ * GNU General Public License for more details.
43993+ *
43994+ * You should have received a copy of the GNU General Public License
43995+ * along with this program; if not, write to the Free Software
43996+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43997+ * MA 02111-1307 USA
43998+ */
43999+
44000+#ifndef __CONFIG_H
44001+#define __CONFIG_H
44002+
44003+/*
44004+ * High Level Configuration Options
44005+ * (easy to change)
44006+ */
44007+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
44008+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
44009+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
44010+#define CONFIG_ASPEED 1
44011+#define CONFIG_AST2400 1
44012+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
44013+#define CONFIG_FLASH_SPI
44014+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
44015+#undef CONFIG_2SPIFLASH
44016+#undef CONFIG_ASPEED_SLT
44017+#define CONFIG_FLASH_AST2300
44018+#define CONFIG_FLASH_AST2300_DMA
44019+//#define CONFIG_FLASH_SPIx2_Dummy
44020+//#define CONFIG_FLASH_SPIx4_Dummy
44021+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
44022+
44023+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44024+#define CONFIG_MISC_INIT_R
44025+
44026+/*
44027+ * DRAM Config
44028+ *
44029+ * 1. DRAM Size //
44030+ * CONFIG_DRAM_512MBIT // 512M bit
44031+ * CONFIG_DRAM_1GBIT // 1G bit (default)
44032+ * CONFIG_DRAM_2GBIT // 2G bit
44033+ * CONFIG_DRAM_4GBIT // 4G bit
44034+ * 2. DRAM Speed //
44035+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
44036+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
44037+ * 3. VGA Mode
44038+ * CONFIG_CRT_DISPLAY // define to disable VGA function
44039+ * 4. ECC Function enable
44040+ * CONFIG_DRAM_ECC // define to enable ECC function
44041+ * 5. UART Debug Message
44042+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
44043+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
44044+ */
44045+
44046+//1. DRAM Size
44047+//#define CONFIG_DRAM_512MBIT
44048+#define CONFIG_DRAM_1GBIT
44049+//#define CONFIG_DRAM_2GBIT
44050+//#define CONFIG_DRAM_4GBIT
44051+//2. DRAM Speed
44052+//#define CONFIG_DRAM_336
44053+#define CONFIG_DRAM_408
44054+//3. VGA Mode
44055+//#define CONFIG_CRT_DISPLAY
44056+//4. ECC Function enable
44057+//#define CONFIG_DRAM_ECC
44058+//5. UART Debug Message
44059+#define CONFIG_DRAM_UART_OUT
44060+//#define CONFIG_DRAM_UART_38400
44061+
44062+
44063+
44064+/*
44065+ * Environment Config
44066+ */
44067+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
44068+#define CONFIG_SETUP_MEMORY_TAGS 1
44069+#define CONFIG_INITRD_TAG 1
44070+#define CONFIG_BOOTARGS "debug console=ttyS0,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
44071+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
44072+#ifdef CONFIG_FLASH_AST2300
44073+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
44074+#else
44075+#ifdef CONFIG_SYS_FLASH_CFI
44076+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
44077+#else
44078+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
44079+#endif
44080+#endif
44081+#define CONFIG_BOOTFILE "all.bin"
44082+#define CONFIG_ENV_OVERWRITE
44083+
44084+/*
44085+ * Command line configuration.
44086+ */
44087+#include <config_cmd_default.h>
44088+
44089+#define CONFIG_CMD_DFL
44090+#define CONFIG_CMD_ENV
44091+#define CONFIG_CMD_FLASH
44092+#define CONFIG_CMD_NET
44093+#define CONFIG_CMD_PING
44094+#define CONFIG_CMD_I2C
44095+#define CONFIG_CMD_EEPROM
44096+
44097+/*
44098+ * CPU Setting
44099+ */
44100+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
44101+
44102+/*
44103+ * Size of malloc() pool
44104+ */
44105+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
44106+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
44107+
44108+/*
44109+ * Stack sizes, The stack sizes are set up in start.S using the settings below
44110+ */
44111+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
44112+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
44113+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
44114+
44115+/*
44116+ * Memory Configuration
44117+ */
44118+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
44119+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
44120+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
44121+
44122+#define CONFIG_SYS_SDRAM_BASE 0x40000000
44123+
44124+/*
44125+ * FLASH Configuration
44126+ */
44127+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
44128+
44129+#ifdef CONFIG_FLASH_AST2300
44130+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
44131+#else
44132+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
44133+#endif
44134+
44135+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
44136+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
44137+
44138+#define CONFIG_SYS_MAX_FLASH_BANKS 1
44139+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
44140+
44141+#define CONFIG_ENV_IS_IN_FLASH 1
44142+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
44143+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
44144+
44145+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
44146+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
44147+
44148+#else /* SPI Flash */
44149+
44150+#ifdef CONFIG_FLASH_AST2300
44151+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
44152+#else
44153+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
44154+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
44155+#define PHYS_FLASH_2_BASE 0x10000000
44156+#endif
44157+
44158+#ifdef CONFIG_2SPIFLASH
44159+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
44160+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
44161+#define CONFIG_SYS_MAX_FLASH_BANKS 2
44162+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
44163+
44164+#define CONFIG_ENV_IS_IN_FLASH 1
44165+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
44166+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
44167+#else
44168+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
44169+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
44170+#define CONFIG_SYS_MAX_FLASH_BANKS 1
44171+#define CONFIG_SYS_MAX_FLASH_SECT (1024) /* max number of sectors on one chip */
44172+
44173+#define CONFIG_ENV_IS_IN_FLASH 1
44174+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
44175+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
44176+#endif
44177+
44178+#endif
44179+
44180+#define __LITTLE_ENDIAN
44181+
44182+#define CONFIG_MONITOR_BASE TEXT_BASE
44183+#define CONFIG_MONITOR_LEN (192 << 10)
44184+
44185+/* timeout values are in ticks */
44186+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
44187+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
44188+
44189+/*
44190+ * Miscellaneous configurable options
44191+ */
44192+#define CONFIG_SYS_LONGHELP /* undef to save memory */
44193+
44194+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
44195+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
44196+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
44197+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
44198+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
44199+
44200+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
44201+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
44202+
44203+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
44204+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
44205+
44206+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
44207+
44208+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
44209+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
44210+
44211+/*
44212+ * Serial Configuration
44213+ */
44214+#define CONFIG_SYS_NS16550
44215+#define CONFIG_SYS_NS16550_SERIAL
44216+#define CONFIG_SYS_NS16550_REG_SIZE 4
44217+#define CONFIG_SYS_NS16550_CLK 24000000
44218+#define CONFIG_SYS_NS16550_COM1 0x1e783000
44219+#define CONFIG_SYS_NS16550_COM2 0x1e784000
44220+#define CONFIG_SYS_LOADS_BAUD_CHANGE
44221+#define CONFIG_SERIAL1 1
44222+#define CONFIG_CONS_INDEX 2
44223+#define CONFIG_BAUDRATE 115200
44224+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
44225+
44226+/*
44227+ * USB device configuration
44228+ */
44229+/*
44230+#define CONFIG_USB_DEVICE 1
44231+#define CONFIG_USB_TTY 1
44232+
44233+#define CONFIG_USBD_VENDORID 0x1234
44234+#define CONFIG_USBD_PRODUCTID 0x5678
44235+#define CONFIG_USBD_MANUFACTURER "Siemens"
44236+#define CONFIG_USBD_PRODUCT_NAME "SX1"
44237+*/
44238+
44239+/*
44240+ * I2C configuration
44241+ */
44242+#define CONFIG_HARD_I2C
44243+#define CONFIG_SYS_I2C_SPEED 100000
44244+#define CONFIG_SYS_I2C_SLAVE 1
44245+#define CONFIG_DRIVER_ASPEED_I2C
44246+
44247+/*
44248+* EEPROM configuration
44249+*/
44250+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
44251+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
44252+
44253+/*
44254+ * NIC configuration
44255+ */
44256+#define __BYTE_ORDER __LITTLE_ENDIAN
44257+#define __LITTLE_ENDIAN_BITFIELD
44258+#define CONFIG_MAC_PARTITION
44259+#define CONFIG_ASPEEDNIC
44260+#define CONFIG_MAC1_PHY_LINK_INTERRUPT
44261+#define CONFIG_MAC2_ENABLE
44262+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
44263+/*
44264+*-------------------------------------------------------------------------------
44265+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
44266+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
44267+* inform kernel driver.
44268+* The meanings of the 2 bits are:
44269+* 00(0): Dedicated PHY
44270+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
44271+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
44272+* 11: Reserved
44273+*
44274+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
44275+* 0: Dedicated PHY
44276+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
44277+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
44278+* 3: Reserved
44279+*-------------------------------------------------------------------------------
44280+*/
44281+#define CONFIG_MAC1_PHY_SETTING 0
44282+#define CONFIG_MAC2_PHY_SETTING 0
44283+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
44284+#define CONFIG_NET_MULTI
44285+#define CONFIG_ETHACT aspeednic#0
44286+#define CONFIG_GATEWAYIP 192.168.0.1
44287+#define CONFIG_NETMASK 255.255.255.0
44288+#define CONFIG_IPADDR 192.168.0.45
44289+#define CONFIG_SERVERIP 192.168.0.81
44290+#define CONFIG_ETHADDR 00:C0:A8:12:34:56
44291+#define CONFIG_ETH1ADDR 00:C0:A8:12:34:57
44292+
44293+/*
44294+ * SLT
44295+ */
44296+/*
44297+#define CONFIG_SLT
44298+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
44299+*/
44300+
44301+#endif /* __CONFIG_H */
44302diff --git a/include/configs/ast3100.h b/include/configs/ast3100.h
44303new file mode 100644
44304index 0000000..f2a2aed
44305--- /dev/null
44306+++ b/include/configs/ast3100.h
44307@@ -0,0 +1,325 @@
44308+/*
44309+ * (C) Copyright 2004
44310+ * Peter Chen <peterc@socle-tech.com.tw>
44311+ *
44312+ * This program is free software; you can redistribute it and/or
44313+ * modify it under the terms of the GNU General Public License as
44314+ * published by the Free Software Foundation; either version 2 of
44315+ * the License, or (at your option) any later version.
44316+ *
44317+ * This program is distributed in the hope that it will be useful,
44318+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
44319+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
44320+ * GNU General Public License for more details.
44321+ *
44322+ * You should have received a copy of the GNU General Public License
44323+ * along with this program; if not, write to the Free Software
44324+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
44325+ * MA 02111-1307 USA
44326+ */
44327+
44328+#ifndef __CONFIG_H
44329+#define __CONFIG_H
44330+
44331+/*
44332+ * High Level Configuration Options
44333+ * (easy to change)
44334+ */
44335+//#define CONFIG_INIT_CRITICAL /* define for U-BOOT 1.1.1 */
44336+#undef CONFIG_INIT_CRITICAL /* undef for U-BOOT 1.1.4 */
44337+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU */
44338+#define CONFIG_ASPEED 1
44339+//#define CONFIG_AST2300 1
44340+#define CONFIG_AST3100 1
44341+#define CONFIG_AST3100_D200 1 /* Clientron D200*/
44342+//#define CONFIG_SYS_FLASH_CFI /* CONFIG_FLASH_CFI, CONFIG_FLASH_SPI is exclusive*/
44343+#define CONFIG_FLASH_SPI
44344+//#define CONFIG_2SPIFLASH /* Boot SPI: CS2, 2nd SPI: CS0 */
44345+#undef CONFIG_2SPIFLASH
44346+#undef CONFIG_ASPEED_SLT
44347+#define CONFIG_FLASH_AST2300
44348+//#define CONFIG_FLASH_AST2300_DMA
44349+//#define CONFIG_FLASH_SPIx2_Dummy
44350+//#define CONFIG_FLASH_SPIx4_Dummy
44351+#define CONFIG_CRT_DISPLAY 1 /* undef if not support CRT */
44352+
44353+//#define CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44354+#define CONFIG_MISC_INIT_R
44355+
44356+/*
44357+ * DRAM Config
44358+ *
44359+ * 1. DRAM Size //
44360+ * CONFIG_DRAM_512MBIT // 512M bit
44361+ * CONFIG_DRAM_1GBIT // 1G bit (default)
44362+ * CONFIG_DRAM_2GBIT // 2G bit
44363+ * CONFIG_DRAM_4GBIT // 4G bit
44364+ * 2. DRAM Speed //
44365+ * CONFIG_DRAM_336 // 336MHz (DDR-667)
44366+ * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
44367+ * 3. VGA Mode
44368+ * CONFIG_CRT_DISPLAY // define to disable VGA function
44369+ * 4. ECC Function enable
44370+ * CONFIG_DRAM_ECC // define to enable ECC function
44371+ * 5. UART Debug Message
44372+ * CONFIG_DRAM_UART_OUT // enable output message at UART5
44373+ * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200
44374+ */
44375+
44376+//1. DRAM Size
44377+//#define CONFIG_DRAM_512MBIT
44378+#define CONFIG_DRAM_1GBIT
44379+//#define CONFIG_DRAM_2GBIT
44380+//#define CONFIG_DRAM_4GBIT
44381+//2. DRAM Speed
44382+//#define CONFIG_DRAM_336
44383+#define CONFIG_DRAM_408
44384+//3. VGA Mode
44385+//#define CONFIG_CRT_DISPLAY
44386+//4. ECC Function enable
44387+//#define CONFIG_DRAM_ECC
44388+//5. UART Debug Message
44389+#define CONFIG_DRAM_UART_OUT
44390+//#define CONFIG_DRAM_UART_38400
44391+
44392+
44393+
44394+/*
44395+ * Environment Config
44396+ */
44397+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
44398+#define CONFIG_SETUP_MEMORY_TAGS 1
44399+#define CONFIG_INITRD_TAG 1
44400+#define CONFIG_BOOTARGS "debug console=ttyS1,115200n8 ramdisk_size=16384 root=/dev/ram rw init=/linuxrc mem=80M"
44401+#define CONFIG_BOOTDELAY 4 /* autoboot after 4 seconds */
44402+#ifdef CONFIG_FLASH_AST2300
44403+#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
44404+#else
44405+#ifdef CONFIG_SYS_FLASH_CFI
44406+#define CONFIG_BOOTCOMMAND "bootm 10080000 10300000"
44407+#else
44408+#define CONFIG_BOOTCOMMAND "bootm 14080000 14300000"
44409+#endif
44410+#endif
44411+#define CONFIG_BOOTFILE "allc.bin"
44412+#define CONFIG_ENV_OVERWRITE
44413+
44414+/*
44415+ * Command line configuration.
44416+ */
44417+#include <config_cmd_default.h>
44418+
44419+#define CONFIG_CMD_DFL
44420+#define CONFIG_CMD_ENV
44421+#define CONFIG_CMD_FLASH
44422+#define CONFIG_CMD_NET
44423+#define CONFIG_CMD_PING
44424+#define CONFIG_CMD_I2C
44425+#define CONFIG_CMD_EEPROM
44426+
44427+/*
44428+ * CPU Setting
44429+ */
44430+#define CPU_CLOCK_RATE 18000000 /* 16.5 MHz clock for the ARM core */
44431+
44432+/*
44433+ * Size of malloc() pool
44434+ */
44435+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 768*1024)
44436+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
44437+
44438+/*
44439+ * Stack sizes, The stack sizes are set up in start.S using the settings below
44440+ */
44441+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
44442+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
44443+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
44444+
44445+/*
44446+ * Memory Configuration
44447+ */
44448+#define CONFIG_DRAM_528
44449+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
44450+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
44451+#define PHYS_SDRAM_1_SIZE 0x4000000 /* 64 MB */
44452+
44453+#define CONFIG_SYS_SDRAM_BASE 0x40000000
44454+
44455+/*
44456+ * FLASH Configuration
44457+ */
44458+#ifdef CONFIG_SYS_FLASH_CFI /* NOR Flash */
44459+
44460+#ifdef CONFIG_FLASH_AST2300
44461+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
44462+#else
44463+#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
44464+#endif
44465+
44466+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
44467+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
44468+
44469+#define CONFIG_SYS_MAX_FLASH_BANKS 1
44470+#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
44471+
44472+#define CONFIG_ENV_IS_IN_FLASH 1
44473+#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
44474+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
44475+
44476+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
44477+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
44478+
44479+#else /* SPI Flash */
44480+
44481+#ifdef CONFIG_FLASH_AST2300
44482+#define PHYS_FLASH_1 0x20000000 /* Flash Bank #1 */
44483+#else
44484+#define PHYS_FLASH_1 0x14000000 /* Flash Bank #1 */
44485+#define PHYS_FLASH_2 0x14800000 /* Flash Bank #2 */
44486+#define PHYS_FLASH_2_BASE 0x10000000
44487+#endif
44488+
44489+#ifdef CONFIG_2SPIFLASH
44490+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2_BASE
44491+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
44492+#define CONFIG_SYS_MAX_FLASH_BANKS 2
44493+#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
44494+
44495+#define CONFIG_ENV_IS_IN_FLASH 1
44496+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
44497+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
44498+#else
44499+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
44500+#define CONFIG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
44501+#define CONFIG_SYS_MAX_FLASH_BANKS 1
44502+#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
44503+
44504+#define CONFIG_ENV_IS_IN_FLASH 1
44505+#define CONFIG_ENV_OFFSET 0x7F0000 /* environment starts here */
44506+#define CONFIG_ENV_SIZE 0x010000 /* Total Size of Environment Sector */
44507+#endif
44508+
44509+#endif
44510+
44511+#define __LITTLE_ENDIAN
44512+
44513+#define CONFIG_MONITOR_BASE TEXT_BASE
44514+#define CONFIG_MONITOR_LEN (192 << 10)
44515+
44516+/* timeout values are in ticks */
44517+#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
44518+#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
44519+
44520+/*
44521+ * Miscellaneous configurable options
44522+ */
44523+#define CONFIG_SYS_LONGHELP /* undef to save memory */
44524+
44525+#define CONFIG_SYS_PROMPT "boot# " /* Monitor Command Prompt */
44526+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
44527+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
44528+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
44529+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
44530+
44531+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */
44532+#define CONFIG_SYS_MEMTEST_END 0x44FFFFFF /* 256 MB in DRAM */
44533+
44534+#define CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
44535+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
44536+
44537+#define CONFIG_SYS_LOAD_ADDR 0x43000000 /* default load address */
44538+
44539+#define CONFIG_SYS_TIMERBASE 0x1E782000 /* use timer 1 */
44540+#define CONFIG_SYS_HZ (1*1000*1000) /* use external clk (1M) */
44541+
44542+/*
44543+ * Serial Configuration
44544+ */
44545+#define CONFIG_SYS_NS16550
44546+#define CONFIG_SYS_NS16550_SERIAL
44547+#define CONFIG_SYS_NS16550_REG_SIZE 4
44548+#define CONFIG_SYS_NS16550_CLK 24000000
44549+#define CONFIG_SYS_NS16550_COM1 0x1e783000
44550+#define CONFIG_SYS_NS16550_COM2 0x1e784000
44551+#define CONFIG_SYS_LOADS_BAUD_CHANGE
44552+#define CONFIG_SERIAL1 1
44553+#define CONFIG_CONS_INDEX 2
44554+#define CONFIG_BAUDRATE 115200
44555+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
44556+
44557+/*
44558+ * USB device configuration
44559+ */
44560+/*
44561+#define CONFIG_USB_DEVICE 1
44562+#define CONFIG_USB_TTY 1
44563+
44564+#define CONFIG_USBD_VENDORID 0x1234
44565+#define CONFIG_USBD_PRODUCTID 0x5678
44566+#define CONFIG_USBD_MANUFACTURER "Siemens"
44567+#define CONFIG_USBD_PRODUCT_NAME "SX1"
44568+*/
44569+
44570+/*
44571+ * I2C configuration
44572+ */
44573+#define CONFIG_HARD_I2C
44574+#define CONFIG_SYS_I2C_SPEED 100000
44575+#define CONFIG_SYS_I2C_SLAVE 1
44576+#define CONFIG_DRIVER_ASPEED_I2C
44577+
44578+/*
44579+* EEPROM configuration
44580+*/
44581+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
44582+#define CONFIG_SYS_I2C_EEPROM_ADDR 0xa0
44583+
44584+/*
44585+ * NIC configuration
44586+ */
44587+#define __BYTE_ORDER __LITTLE_ENDIAN
44588+#define __LITTLE_ENDIAN_BITFIELD
44589+#define CONFIG_MAC_PARTITION
44590+#define CONFIG_ASPEEDNIC
44591+//#define CONFIG_MAC1_PHY_LINK_INTERRUPT
44592+#define CONFIG_MAC2_ENABLE
44593+#define CONFIG_MAC2_PHY_LINK_INTERRUPT
44594+/*
44595+*-------------------------------------------------------------------------------
44596+* NOTICE: MAC1 and MAC2 now have their own seperate PHY configuration.
44597+* We use 2 bits for each MAC in the scratch register(D[15:11] in 0x1E6E2040) to
44598+* inform kernel driver.
44599+* The meanings of the 2 bits are:
44600+* 00(0): Dedicated PHY
44601+* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA
44602+* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly
44603+* 11: Reserved
44604+*
44605+* We use CONFIG_MAC1_PHY_SETTING and CONFIG_MAC2_PHY_SETTING in U-Boot
44606+* 0: Dedicated PHY
44607+* 1: ASPEED's EVA + INTEL's NC-SI PHY chip EVA
44608+* 2: ASPEED's MAC is connected to NC-SI PHY chip directly
44609+* 3: Reserved
44610+*-------------------------------------------------------------------------------
44611+*/
44612+#define CONFIG_MAC1_PHY_SETTING 0
44613+#define CONFIG_MAC2_PHY_SETTING 0
44614+#define CONFIG_MAC_INTERFACE_CLOCK_DELAY 0x2255
44615+#define CONFIG_NET_MULTI
44616+#define CONFIG_ETHACT aspeednic#0
44617+#define CONFIG_GATEWAYIP 192.168.0.1
44618+#define CONFIG_NETMASK 255.255.255.0
44619+#define CONFIG_IPADDR 192.168.0.249
44620+#define CONFIG_SERVERIP 192.168.0.156
44621+#define CONFIG_ETHADDR 00:D0:A8:12:34:58
44622+#define CONFIG_ETH1ADDR 00:D0:A8:12:34:59
44623+
44624+/*
44625+ * SLT
44626+ */
44627+/*
44628+#define CONFIG_SLT
44629+#define CFG_CMD_SLT (CFG_CMD_VIDEOTEST | CFG_CMD_MACTEST | CFG_CMD_HACTEST | CFG_CMD_MICTEST)
44630+*/
44631+
44632+#endif /* __CONFIG_H */
44633diff --git a/include/flash.h b/include/flash.h
44634index c7acc97..e77be1f 100644
44635--- a/include/flash.h
44636+++ b/include/flash.h
44637@@ -57,6 +57,21 @@ typedef struct {
44638 ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
44639 const char *name; /* human-readable name */
44640 #endif
44641+#ifdef CONFIG_FLASH_SPI
44642+ ulong readcmd;
44643+ ulong dualport;
44644+ ulong dummybyte;
44645+ ulong tCK_Write;
44646+ ulong tCK_Erase;
44647+ ulong tCK_Read;
44648+ ulong CE;
44649+ ulong iomode;
44650+ ulong address32;
44651+ ulong quadport;
44652+ ulong dummydata;
44653+ ulong buffersize;
44654+ ulong specificspi;
44655+#endif
44656 } flash_info_t;
44657
44658 extern flash_info_t flash_info[]; /* info for FLASH chips */