blob: f38a6a49a1c7d5d77c701f7bcaae0f21f2875c6a [file] [log] [blame]
Edward A. James7bd86372017-05-15 12:28:44 -05001From patchwork Wed May 10 15:52:37 2017
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5Subject: [linux, dev-4.10, v2,
6 1/6] drivers: i2c: Add FSI-attached I2C master algorithm
7From: eajames@linux.vnet.ibm.com
8X-Patchwork-Id: 760697
9Message-Id: <1494431562-25101-2-git-send-email-eajames@linux.vnet.ibm.com>
10To: openbmc@lists.ozlabs.org
11Cc: "Edward A. James" <eajames@us.ibm.com>, cbostic@linux.vnet.ibm.com
12Date: Wed, 10 May 2017 10:52:37 -0500
13
14From: "Edward A. James" <eajames@us.ibm.com>
15
16Initial startup code for the I2C algorithm to drive the I2C master
17located on POWER CPUs over FSI bus.
18
19Signed-off-by: Edward A. James <eajames@us.ibm.com>
20---
21 drivers/Makefile | 2 +-
22 drivers/i2c/busses/Kconfig | 11 ++
23 drivers/i2c/busses/Makefile | 1 +
24 drivers/i2c/busses/i2c-fsi.c | 245 +++++++++++++++++++++++++++++++++++++++++++
25 4 files changed, 258 insertions(+), 1 deletion(-)
26 create mode 100644 drivers/i2c/busses/i2c-fsi.c
27
28diff --git a/drivers/Makefile b/drivers/Makefile
29index 67ce51d..278f109 100644
30--- a/drivers/Makefile
31+++ b/drivers/Makefile
32@@ -105,6 +105,7 @@ obj-$(CONFIG_SERIO) += input/serio/
33 obj-$(CONFIG_GAMEPORT) += input/gameport/
34 obj-$(CONFIG_INPUT) += input/
35 obj-$(CONFIG_RTC_LIB) += rtc/
36+obj-$(CONFIG_FSI) += fsi/
37 obj-y += i2c/ media/
38 obj-$(CONFIG_PPS) += pps/
39 obj-y += ptp/
40@@ -173,4 +174,3 @@ obj-$(CONFIG_STM) += hwtracing/stm/
41 obj-$(CONFIG_ANDROID) += android/
42 obj-$(CONFIG_NVMEM) += nvmem/
43 obj-$(CONFIG_FPGA) += fpga/
44-obj-$(CONFIG_FSI) += fsi/
45diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
46index 7e34901d..0c714e0 100644
47--- a/drivers/i2c/busses/Kconfig
48+++ b/drivers/i2c/busses/Kconfig
49@@ -1245,4 +1245,15 @@ config I2C_OPAL
50 This driver can also be built as a module. If so, the module will be
51 called as i2c-opal.
52
53+config I2C_FSI
54+ tristate "FSI I2C driver"
55+ depends on FSI
56+ help
57+ Driver for FSI bus attached I2C masters. These are I2C masters that
58+ are connected to the system over a FSI bus, instead of the more
59+ common PCI or MMIO interface.
60+
61+ This driver can also be built as a module. If so, the module will be
62+ called as i2c-fsi.
63+
64 endmenu
65diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
66index 5798b4e..547773b 100644
67--- a/drivers/i2c/busses/Makefile
68+++ b/drivers/i2c/busses/Makefile
69@@ -124,5 +124,6 @@ obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
70 obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
71 obj-$(CONFIG_I2C_XGENE_SLIMPRO) += i2c-xgene-slimpro.o
72 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
73+obj-$(CONFIG_I2C_FSI) += i2c-fsi.o
74
75 ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
76diff --git a/drivers/i2c/busses/i2c-fsi.c b/drivers/i2c/busses/i2c-fsi.c
77new file mode 100644
78index 0000000..3c1087d
79--- /dev/null
80+++ b/drivers/i2c/busses/i2c-fsi.c
81@@ -0,0 +1,245 @@
82+/*
83+ * Copyright 2017 IBM Corporation
84+ *
85+ * Eddie James <eajames@us.ibm.com>
86+ *
87+ * This program is free software; you can redistribute it and/or
88+ * modify it under the terms of the GNU General Public License
89+ * as published by the Free Software Foundation; either version
90+ * 2 of the License, or (at your option) any later version.
91+ */
92+
93+#include <linux/fsi.h>
94+#include <linux/i2c.h>
95+#include <linux/jiffies.h>
96+#include <linux/module.h>
97+#include <linux/of.h>
98+#include <linux/sched.h>
99+#include <linux/semaphore.h>
100+#include <linux/wait.h>
101+
102+#define FSI_ENGID_I2C_FSI 0x7
103+
104+/* Find left shift from first set bit in m */
105+#define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1ULL)
106+
107+/* Extract field m from v */
108+#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
109+
110+/* Set field m of v to val */
111+#define SETFIELD(m, v, val) \
112+ (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
113+
114+#define I2C_DEFAULT_CLK_DIV 6
115+
116+/* i2c registers */
117+#define I2C_FSI_FIFO 0x00
118+#define I2C_FSI_CMD 0x04
119+#define I2C_FSI_MODE 0x08
120+#define I2C_FSI_WATER_MARK 0x0C
121+#define I2C_FSI_INT_MASK 0x10
122+#define I2C_FSI_INT_COND 0x14
123+#define I2C_FSI_OR_INT_MASK 0x14
124+#define I2C_FSI_INTS 0x18
125+#define I2C_FSI_AND_INT_MASK 0x18
126+#define I2C_FSI_STAT 0x1C
127+#define I2C_FSI_RESET_I2C 0x1C
128+#define I2C_FSI_ESTAT 0x20
129+#define I2C_FSI_RESET_ERR 0x20
130+#define I2C_FSI_RESID_LEN 0x24
131+#define I2C_FSI_SET_SCL 0x24
132+#define I2C_FSI_PORT_BUSY 0x28
133+#define I2C_FSI_RESET_SCL 0x2C
134+#define I2C_FSI_SET_SDA 0x30
135+#define I2C_FSI_RESET_SDA 0x34
136+
137+/* cmd register */
138+#define I2C_CMD_WITH_START 0x80000000
139+#define I2C_CMD_WITH_ADDR 0x40000000
140+#define I2C_CMD_RD_CONT 0x20000000
141+#define I2C_CMD_WITH_STOP 0x10000000
142+#define I2C_CMD_FORCELAUNCH 0x08000000
143+#define I2C_CMD_ADDR 0x00fe0000
144+#define I2C_CMD_READ 0x00010000
145+#define I2C_CMD_LEN 0x0000ffff
146+
147+/* mode register */
148+#define I2C_MODE_CLKDIV 0xffff0000
149+#define I2C_MODE_PORT 0x0000fc00
150+#define I2C_MODE_ENHANCED 0x00000008
151+#define I2C_MODE_DIAG 0x00000004
152+#define I2C_MODE_PACE_ALLOW 0x00000002
153+#define I2C_MODE_WRAP 0x00000001
154+
155+/* watermark register */
156+#define I2C_WATERMARK_HI 0x0000f000
157+#define I2C_WATERMARK_LO 0x000000f0
158+
159+#define I2C_FIFO_HI_LVL 4
160+#define I2C_FIFO_LO_LVL 4
161+
162+/* interrupt register */
163+#define I2C_INT_INV_CMD 0x00008000
164+#define I2C_INT_PARITY 0x00004000
165+#define I2C_INT_BE_OVERRUN 0x00002000
166+#define I2C_INT_BE_ACCESS 0x00001000
167+#define I2C_INT_LOST_ARB 0x00000800
168+#define I2C_INT_NACK 0x00000400
169+#define I2C_INT_DAT_REQ 0x00000200
170+#define I2C_INT_CMD_COMP 0x00000100
171+#define I2C_INT_STOP_ERR 0x00000080
172+#define I2C_INT_BUSY 0x00000040
173+#define I2C_INT_IDLE 0x00000020
174+
175+#define I2C_INT_ENABLE 0x0000ff80
176+#define I2C_INT_ERR 0x0000fcc0
177+
178+/* status register */
179+#define I2C_STAT_INV_CMD 0x80000000
180+#define I2C_STAT_PARITY 0x40000000
181+#define I2C_STAT_BE_OVERRUN 0x20000000
182+#define I2C_STAT_BE_ACCESS 0x10000000
183+#define I2C_STAT_LOST_ARB 0x08000000
184+#define I2C_STAT_NACK 0x04000000
185+#define I2C_STAT_DAT_REQ 0x02000000
186+#define I2C_STAT_CMD_COMP 0x01000000
187+#define I2C_STAT_STOP_ERR 0x00800000
188+#define I2C_STAT_MAX_PORT 0x000f0000
189+#define I2C_STAT_ANY_INT 0x00008000
190+#define I2C_STAT_SCL_IN 0x00000800
191+#define I2C_STAT_SDA_IN 0x00000400
192+#define I2C_STAT_PORT_BUSY 0x00000200
193+#define I2C_STAT_SELF_BUSY 0x00000100
194+#define I2C_STAT_FIFO_COUNT 0x000000ff
195+
196+#define I2C_STAT_ERR 0xfc800000
197+#define I2C_STAT_ANY_RESP 0xff800000
198+
199+/* extended status register */
200+#define I2C_ESTAT_FIFO_SZ 0xff000000
201+#define I2C_ESTAT_SCL_IN_SY 0x00008000
202+#define I2C_ESTAT_SDA_IN_SY 0x00004000
203+#define I2C_ESTAT_S_SCL 0x00002000
204+#define I2C_ESTAT_S_SDA 0x00001000
205+#define I2C_ESTAT_M_SCL 0x00000800
206+#define I2C_ESTAT_M_SDA 0x00000400
207+#define I2C_ESTAT_HI_WATER 0x00000200
208+#define I2C_ESTAT_LO_WATER 0x00000100
209+#define I2C_ESTAT_PORT_BUSY 0x00000080
210+#define I2C_ESTAT_SELF_BUSY 0x00000040
211+#define I2C_ESTAT_VERSION 0x0000001f
212+
213+struct fsi_i2c_master {
214+ struct fsi_device *fsi;
215+ u8 fifo_size;
216+};
217+
218+static int fsi_i2c_read_reg(struct fsi_device *fsi, unsigned int reg,
219+ u32 *data)
220+{
221+ int rc;
222+ u32 raw_data;
223+
224+ rc = fsi_device_read(fsi, reg, &raw_data, sizeof(raw_data));
225+ if (rc)
226+ return rc;
227+
228+ *data = be32_to_cpu(raw_data);
229+
230+ return 0;
231+}
232+
233+static int fsi_i2c_write_reg(struct fsi_device *fsi, unsigned int reg,
234+ u32 *data)
235+{
236+ u32 raw_data = cpu_to_be32(*data);
237+
238+ return fsi_device_write(fsi, reg, &raw_data, sizeof(raw_data));
239+}
240+
241+static int fsi_i2c_dev_init(struct fsi_i2c_master *i2c)
242+{
243+ int rc;
244+ u32 mode = I2C_MODE_ENHANCED, extended_status, watermark = 0;
245+ u32 interrupt = 0;
246+
247+ /* since we use polling, disable interrupts */
248+ rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, &interrupt);
249+ if (rc)
250+ return rc;
251+
252+ mode = SETFIELD(I2C_MODE_CLKDIV, mode, I2C_DEFAULT_CLK_DIV);
253+ rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
254+ if (rc)
255+ return rc;
256+
257+ rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &extended_status);
258+ if (rc)
259+ return rc;
260+
261+ i2c->fifo_size = GETFIELD(I2C_ESTAT_FIFO_SZ, extended_status);
262+ watermark = SETFIELD(I2C_WATERMARK_HI, watermark,
263+ i2c->fifo_size - I2C_FIFO_HI_LVL);
264+ watermark = SETFIELD(I2C_WATERMARK_LO, watermark,
265+ I2C_FIFO_LO_LVL);
266+
267+ rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_WATER_MARK, &watermark);
268+
269+ return rc;
270+}
271+
272+static int fsi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
273+ int num)
274+{
275+ return -ENOSYS;
276+}
277+
278+static u32 fsi_i2c_functionality(struct i2c_adapter *adap)
279+{
280+ return I2C_FUNC_I2C | I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_10BIT_ADDR;
281+}
282+
283+static const struct i2c_algorithm fsi_i2c_algorithm = {
284+ .master_xfer = fsi_i2c_xfer,
285+ .functionality = fsi_i2c_functionality,
286+};
287+
288+static int fsi_i2c_probe(struct device *dev)
289+{
290+ struct fsi_i2c_master *i2c;
291+ int rc;
292+
293+ i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
294+ if (!i2c)
295+ return -ENOMEM;
296+
297+ i2c->fsi = to_fsi_dev(dev);
298+
299+ rc = fsi_i2c_dev_init(i2c);
300+ if (rc)
301+ return rc;
302+
303+ dev_set_drvdata(dev, i2c);
304+
305+ return 0;
306+}
307+
308+static const struct fsi_device_id fsi_i2c_ids[] = {
309+ { FSI_ENGID_I2C_FSI, FSI_VERSION_ANY },
310+ { 0 }
311+};
312+
313+static struct fsi_driver fsi_i2c_driver = {
314+ .id_table = fsi_i2c_ids,
315+ .drv = {
316+ .name = "i2c_master_fsi",
317+ .bus = &fsi_bus_type,
318+ .probe = fsi_i2c_probe,
319+ },
320+};
321+
322+module_fsi_driver(fsi_i2c_driver);
323+
324+MODULE_AUTHOR("Eddie James <eajames@us.ibm.com>");
325+MODULE_DESCRIPTION("FSI attached I2C master");
326+MODULE_LICENSE("GPL");