blob: 3ba91f5d6e41c5e91988b61b94820b925a0eac6f [file] [log] [blame]
Andrew Jeffery80d39ce2019-01-17 22:48:40 +10301From 97566253f336d85d23abef777b54dc572ca7ac9a Mon Sep 17 00:00:00 2001
Andrew Jeffery82f2db22018-07-26 14:15:21 +09302From: Andrew Jeffery <andrew@aj.id.au>
3Date: Mon, 23 Jul 2018 15:22:34 +0930
4Subject: [PATCH] aspeed: Disable unnecessary features
5
6Adjust board_init() to disable hardware features that we don't need
7available during normal BMC operation.
8
9Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
10---
Andrew Jeffery80d39ce2019-01-17 22:48:40 +103011 arch/arm/include/asm/arch-aspeed/regs-lpc.h | 29 +++++++++++
12 arch/arm/include/asm/arch-aspeed/regs-scu.h | 8 ++-
13 arch/arm/include/asm/arch-aspeed/regs-sdmc.h | 17 +++++++
14 board/aspeed/ast-g4/ast-g4.c | 46 ++++++++++++++++-
15 board/aspeed/ast-g5/ast-g5.c | 52 +++++++++++++++++++-
16 5 files changed, 149 insertions(+), 3 deletions(-)
Andrew Jeffery82f2db22018-07-26 14:15:21 +093017 create mode 100644 arch/arm/include/asm/arch-aspeed/regs-lpc.h
18
19diff --git a/arch/arm/include/asm/arch-aspeed/regs-lpc.h b/arch/arm/include/asm/arch-aspeed/regs-lpc.h
20new file mode 100644
21index 000000000000..b0162ae4f37c
22--- /dev/null
23+++ b/arch/arm/include/asm/arch-aspeed/regs-lpc.h
24@@ -0,0 +1,29 @@
25+/* arch/arm/mach-aspeed/include/mach/regs-sdmc.h
26+ *
27+ * Copyright (C) 2018 IBM Corp
28+ *
29+ * This program is free software; you can redistribute it and/or modify
30+ * it under the terms of the GNU General Public License version 2 as
31+ * published by the Free Software Foundation.
32+ *
33+ * History :
34+ * 1. 2018/07/23 Andrew Jeffery Create
35+ *
36+ ******************************************************************************/
37+#ifndef __AST_REGS_LPC_H
38+#define __AST_REGS_LPC_H
39+
40+/*
41+ * Register for LPC
42+ */
43+
44+#define AST_LPC_HICR5 0x80
45+#define AST_LPC_HICRB 0x100
46+
47+/* AST_LPC_HICR5 : 0x80 Host Interface Control Register 5 */
48+#define LPC_HICR5_ENFWH (0x1 << 10)
49+
50+/* AST_LPC_HICRB : 0x100 Host Interface Control Register B */
51+#define LPC_HICRB_ILPC2AHB (0x1 << 6)
52+
53+#endif
54diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h
55index b714fa92341d..c9b91795d1aa 100644
56--- a/arch/arm/include/asm/arch-aspeed/regs-scu.h
57+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h
58@@ -466,6 +466,7 @@
59 #define SCU_MISC_JTAG__M_TO_PCIE_EN (0x1 << 14)
60 #define SCU_MISC_VUART_TO_CTRL (0x1 << 13)
61 #define SCU_MISC_DIV13_EN (0x1 << 12)
62+#define SCU_MISC_DEBUG_UART (0x1 << 10)
63 #define SCU_MISC_Y_CLK_INVERT (0x1 << 11)
64 #define SCU_MISC_OUT_DELAY (0x1 << 9)
65 #define SCU_MISC_PCI_TO_AHB_DIS (0x1 << 8)
66@@ -548,6 +549,7 @@
67 /* AST_SCU_VGA_SCRATCH7 0x6c - VGA Scratch register */
68
69 /* AST_SCU_HW_STRAP1 0x70 - hardware strapping register */
70+#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
71 #ifdef AST_SOC_G5
72
73 #define CLK_25M_IN (0x1 << 23)
74@@ -593,7 +595,6 @@
75
76 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)
77 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)
78-#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
79 #define SCU_HW_STRAP_ACPI_DIS (0x1 << 19)
80
81 /* bit 23, 18 [1,0] */
82@@ -940,6 +941,11 @@
83
84 /* AST_SCU_UART24_REF 0x160 - Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */
85 /* AST_SCU_PCIE_CONFIG_SET 0x180 - PCI-E Configuration Setting Control Register */
86+#define SCU_PCIE_CONFIG_SET_BMC_DMA (0x1 << 14)
87+#define SCU_PCIE_CONFIG_SET_BMC_MMIO (0x1 << 9)
88+#define SCU_PCIE_CONFIG_SET_BMC_EN (0x1 << 8)
89+#define SCU_PCIE_CONFIG_SET_VGA_MMIO (0x1 << 1)
90+
91 /* AST_SCU_BMC_MMIO_DEC 0x184 - BMC MMIO Decode Setting Register */
92 /* AST_SCU_DEC_AREA1 0x188 - 1st relocated controller decode area location */
93 /* AST_SCU_DEC_AREA2 0x18C - 2nd relocated controller decode area location */
94diff --git a/arch/arm/include/asm/arch-aspeed/regs-sdmc.h b/arch/arm/include/asm/arch-aspeed/regs-sdmc.h
95index 2cc26d29aa9e..2773d3c19e5a 100644
96--- a/arch/arm/include/asm/arch-aspeed/regs-sdmc.h
97+++ b/arch/arm/include/asm/arch-aspeed/regs-sdmc.h
98@@ -13,11 +13,14 @@
99 #ifndef __AST_REGS_SDMC_H
100 #define __AST_REGS_SDMC_H
101
102+#include <asm/arch/aspeed.h>
103+
104 /*
105 * Register for SDMC
106 */
107 #define AST_SDMC_PROTECT 0x00 /* protection key register */
108 #define AST_SDMC_CONFIG 0x04 /* Configuration register */
109+#define AST_SDMC_GFX_PROT 0x08 /* Graphics protection register */
110
111 /* AST_SDMC_PROTECT: 0x00 - protection key register */
112 #define SDMC_PROTECT_UNLOCK 0xFC600309
113@@ -29,4 +32,18 @@
114 #define SDMC_CONFIG_CACHE_EN (0x1 << 10)
115 #define SDMC_CONFIG_EEC_EN (0x1 << 7)
116
117+/* AST_SDMC_GFX_PROT : 0x08 - Graphics protection register */
118+#define SDMC_GFX_PROT_VGA_CURSOR (0x1 << 0)
119+#define SDMC_GFX_PROT_VGA_CG_READ (0x1 << 1)
120+#define SDMC_GFX_PROT_VGA_ASCII_READ (0x1 << 2)
121+#define SDMC_GFX_PROT_VGA_CRT (0x1 << 3)
122+
123+#if defined(AST_SOC_G5)
124+#define SDMC_GFX_PROT_PCIE (0x1 << 16)
125+#define SDMC_GFX_PROT_XDMA (0x1 << 17)
126+#elif defined(AST_SOC_G4)
127+#define SDMC_GFX_PROT_PCIE (0x1 << 10)
128+#define SDMC_GFX_PROT_XDMA (0x1 << 16)
129+#endif
130+
131 #endif
132diff --git a/board/aspeed/ast-g4/ast-g4.c b/board/aspeed/ast-g4/ast-g4.c
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030133index 656495307b03..5b137e7d74bc 100644
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930134--- a/board/aspeed/ast-g4/ast-g4.c
135+++ b/board/aspeed/ast-g4/ast-g4.c
136@@ -1,6 +1,6 @@
137 /*
138 * (C) Copyright 2002 Ryan Chen
139- * Copyright 2016 IBM Corporation
140+ * Copyright 2016,2018 IBM Corporation
141 *
142 * SPDX-License-Identifier: GPL-2.0+
143 */
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030144@@ -12,13 +12,57 @@
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930145 #include <asm/arch/ast-sdmc.h>
146 #include <asm/arch/ast_scu.h>
147 #include <asm/arch/regs-ahbc.h>
148+#include <asm/arch/regs-lpc.h>
149 #include <asm/arch/regs-scu.h>
150+#include <asm/arch/regs-sdmc.h>
151 #include <asm/io.h>
152
153 DECLARE_GLOBAL_DATA_PTR;
154
155 int board_init(void)
156 {
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030157+ bool sdmc_unlocked;
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930158+ u32 val;
159+
160+ /* iLPC2AHB */
161+ val = readl(AST_SCU_BASE + AST_SCU_HW_STRAP1);
162+ val |= SCU_HW_STRAP_LPC_DEC_SUPER_IO;
163+ writel(val, AST_SCU_BASE + AST_SCU_HW_STRAP1);
164+
165+ val = readl(AST_LPC_BASE + AST_LPC_HICRB);
166+ val |= LPC_HICRB_ILPC2AHB;
167+ writel(val, AST_LPC_BASE + AST_LPC_HICRB);
168+
169+ /* P2A, PCIe BMC */
170+ val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
171+ val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA
172+ | SCU_PCIE_CONFIG_SET_BMC_MMIO
173+ | SCU_PCIE_CONFIG_SET_BMC_EN
174+ | SCU_PCIE_CONFIG_SET_VGA_MMIO);
175+ writel(val, AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
176+
177+ /* X-DMA */
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030178+ sdmc_unlocked = readl(AST_SDMC_BASE + AST_SDMC_PROTECT);
179+ if (!sdmc_unlocked)
180+ writel(SDMC_PROTECT_UNLOCK, AST_SDMC_BASE + AST_SDMC_PROTECT);
181+
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930182+ val = readl(AST_SDMC_BASE + AST_SDMC_GFX_PROT);
183+ val |= (SDMC_GFX_PROT_VGA_CURSOR
184+ | SDMC_GFX_PROT_VGA_CG_READ
185+ | SDMC_GFX_PROT_VGA_ASCII_READ
186+ | SDMC_GFX_PROT_VGA_CRT
187+ | SDMC_GFX_PROT_PCIE
188+ | SDMC_GFX_PROT_XDMA);
189+ writel(val, AST_SDMC_BASE + AST_SDMC_GFX_PROT);
190+
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030191+ if (!sdmc_unlocked)
192+ writel(~SDMC_PROTECT_UNLOCK, AST_SDMC_BASE + AST_SDMC_PROTECT);
193+
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930194+ /* LPC2AHB */
195+ val = readl(AST_LPC_BASE + AST_LPC_HICR5);
196+ val &= ~LPC_HICR5_ENFWH;
197+ writel(val, AST_LPC_BASE + AST_LPC_HICR5);
198+
199 /* address of boot parameters */
200 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
201 gd->flags = 0;
202diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030203index e67a4bf8b2b4..12496cea09b7 100644
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930204--- a/board/aspeed/ast-g5/ast-g5.c
205+++ b/board/aspeed/ast-g5/ast-g5.c
206@@ -1,5 +1,5 @@
207 /*
208- * Copyright 2016 IBM Corporation
209+ * Copyright 2016,2018 IBM Corporation
210 *
211 * This program is free software; you can redistribute it and/or
212 * modify it under the terms of the GNU General Public License
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030213@@ -12,12 +12,62 @@
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930214
215 #include <asm/arch/ast_scu.h>
216 #include <asm/arch/ast-sdmc.h>
217+#include <asm/arch/regs-lpc.h>
218+#include <asm/arch/regs-scu.h>
219+#include <asm/arch/regs-sdmc.h>
220 #include <asm/io.h>
221
222 DECLARE_GLOBAL_DATA_PTR;
223
224 int board_init(void)
225 {
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030226+ bool sdmc_unlocked;
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930227+ u32 val;
228+
229+ /* iLPC2AHB */
230+ val = readl(AST_SCU_BASE + AST_SCU_HW_STRAP1);
231+ val |= SCU_HW_STRAP_LPC_DEC_SUPER_IO;
232+ writel(val, AST_SCU_BASE + AST_SCU_HW_STRAP1);
233+
234+ val = readl(AST_LPC_BASE + AST_LPC_HICRB);
235+ val |= LPC_HICRB_ILPC2AHB;
236+ writel(val, AST_LPC_BASE + AST_LPC_HICRB);
237+
238+ /* P2A, PCIe BMC */
239+ val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
240+ val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA
241+ | SCU_PCIE_CONFIG_SET_BMC_MMIO
242+ | SCU_PCIE_CONFIG_SET_BMC_EN
243+ | SCU_PCIE_CONFIG_SET_VGA_MMIO);
244+ writel(val, AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
245+
246+ /* Debug UART */
247+ val = readl(AST_SCU_BASE + AST_SCU_MISC1_CTRL);
248+ val |= SCU_MISC_DEBUG_UART;
249+ writel(val, AST_SCU_BASE + AST_SCU_MISC1_CTRL);
250+
251+ /* X-DMA */
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030252+ sdmc_unlocked = readl(AST_SDMC_BASE + AST_SDMC_PROTECT);
253+ if (!sdmc_unlocked)
254+ writel(SDMC_PROTECT_UNLOCK, AST_SDMC_BASE + AST_SDMC_PROTECT);
255+
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930256+ val = readl(AST_SDMC_BASE + AST_SDMC_GFX_PROT);
257+ val |= (SDMC_GFX_PROT_VGA_CURSOR
258+ | SDMC_GFX_PROT_VGA_CG_READ
259+ | SDMC_GFX_PROT_VGA_ASCII_READ
260+ | SDMC_GFX_PROT_VGA_CRT
261+ | SDMC_GFX_PROT_PCIE
262+ | SDMC_GFX_PROT_XDMA);
263+ writel(val, AST_SDMC_BASE + AST_SDMC_GFX_PROT);
264+
Andrew Jeffery80d39ce2019-01-17 22:48:40 +1030265+ if (!sdmc_unlocked)
266+ writel(~SDMC_PROTECT_UNLOCK, AST_SDMC_BASE + AST_SDMC_PROTECT);
267+
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930268+ /* LPC2AHB */
269+ val = readl(AST_LPC_BASE + AST_LPC_HICR5);
270+ val &= ~LPC_HICR5_ENFWH;
271+ writel(val, AST_LPC_BASE + AST_LPC_HICR5);
272+
273 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
274 gd->flags = 0;
275
276--
Andrew Jeffery80d39ce2019-01-17 22:48:40 +10302772.19.1
Andrew Jeffery82f2db22018-07-26 14:15:21 +0930278