commit 09bbbcbdb73d83e9b4d0d2078948bf05c9ef592a
author deepakala-k <deepakala.karthikeyan@ibm.com> Fri Oct 14 02:48:06 2022 -0500
committer Andrew Geissler <andrew@geissonator.com> Thu Nov 17 14:20:05 2022 +0000
tree c313c432c0cf2cf0391e217c1b5ba33e57e36e2b
parent 41bd3f0bbe1b63f1015c76a1c59843cd281fe9df

openpower: ipl: srcrev bump 8fc1c2d6e3..da64b07ade

Jayanth Othayoth (1):
      libipl: Updates in the clock type selection algorithm

Marri Devender Rao (3):
      libipl: perform setup ref clock only on the primary processor
      libipl: perform clock test only on the primary processor
      configure: add include path to find p10_sbe_ext_defs header file

deepakala-k (1):
      libipl: p10: Create PEL for guard file exception

Signed-off-by: Deepakala Karthikeyan <deepakala.karthikeyan@ibm.com>
Change-Id: Iaf890d6374a6282062b34b85f305eb62dfea07d5

meta-openpower/recipes-bsp/ipl/ipl_git.bb

diff --git a/meta-openpower/recipes-bsp/ipl/ipl_git.bb b/meta-openpower/recipes-bsp/ipl/ipl_git.bb
index 003c193..8dd17da 100644
--- a/meta-openpower/recipes-bsp/ipl/ipl_git.bb
+++ b/meta-openpower/recipes-bsp/ipl/ipl_git.bb
@@ -12,7 +12,7 @@
 S = "${WORKDIR}/git"
 
 SRC_URI = "git://git@github.com/open-power/ipl;branch="main";protocol=https"
-SRCREV = "8fc1c2d6e350d0cb779db8ec916441469a0b973d"
+SRCREV = "da64b07adeb2a234c47343642c43f8aab96904a2"
 
 DEPENDS = " \
         libekb pdbg autoconf-archive guard pdata \