Add meta-xilinx subtree
Import git://git.yoctoproject.org/meta-xilinx from 5fccc46503 as
meta-xilinx subtree.
Change-Id: I3d59bcf3a57cee588aab7f5cdd0287af66450c8a
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
new file mode 100644
index 0000000..795c671
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
@@ -0,0 +1,15 @@
+FILESEXTRAPATHS_append_microblaze := "${THISDIR}/binutils-2.30:"
+SRC_URI_append_microblaze = " \
+ file://0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
+ file://0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch \
+ file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \
+ file://0004-Fix-relaxation-of-assembler-resolved-references.patch \
+ file://0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch \
+ file://0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch \
+ file://0007-Add-MicroBlaze-address-extension-instructions.patch \
+ file://0008-Add-new-MicroBlaze-bit-field-instructions.patch \
+ file://0009-Fixing-MicroBlaze-IMM-bug.patch \
+ file://0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch \
+ file://0011-Fixing-MicroBlaze-constant-range-check-issue.patch \
+ file://0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch \
+ "
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
new file mode 100644
index 0000000..878bb32
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -0,0 +1,65 @@
+From 91f39b692c48336117c092e4afd80899c97779e6 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:52 -0700
+Subject: [PATCH] MicroBlaze Add wdc.ext.clear and wdc.ext.flush insns
+
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 5 ++++-
+ opcodes/microblaze-opcm.h | 4 ++--
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index ede8af8..773dc81 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+
+ /* New Mask for msrset, msrclr insns. */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+ {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+ {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 92f3f19..7338f6a 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,8 +33,8 @@ enum microblaze_instr
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
++ brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+ bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
new file mode 100644
index 0000000..edeecfd
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
@@ -0,0 +1,64 @@
+From 8b733a61ab54ba4cedb234020562502d20eebcbb Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:53 -0700
+Subject: [PATCH] MicroBlaze add mlittle-endian and mbig-endian flags
+
+Added support in gas for mlittle-endian and mbig-endian flags
+as options.
+
+Updated show usage for MicroBlaze specific assembler options
+to include new entries.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/config/tc-microblaze.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 0194cd9..42dd7ae 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -37,6 +37,8 @@
+
+ #define OPTION_EB (OPTION_MD_BASE + 0)
+ #define OPTION_EL (OPTION_MD_BASE + 1)
++#define OPTION_LITTLE (OPTION_MD_BASE + 2)
++#define OPTION_BIG (OPTION_MD_BASE + 3)
+
+ void microblaze_generate_symbol (char *sym);
+ static bfd_boolean check_spl_reg (unsigned *);
+@@ -1837,6 +1839,8 @@ struct option md_longopts[] =
+ {
+ {"EB", no_argument, NULL, OPTION_EB},
+ {"EL", no_argument, NULL, OPTION_EL},
++ {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
++ {"mbig-endian", no_argument, NULL, OPTION_BIG},
+ { NULL, no_argument, NULL, 0}
+ };
+
+@@ -2471,9 +2475,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+ switch (c)
+ {
+ case OPTION_EB:
++ case OPTION_BIG:
+ target_big_endian = 1;
+ break;
+ case OPTION_EL:
++ case OPTION_LITTLE:
+ target_big_endian = 0;
+ break;
+ default:
+@@ -2488,6 +2494,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+ /* fprintf(stream, _("\
+ MicroBlaze options:\n\
+ -noSmall Data in the comm and data sections do not go into the small data section\n")); */
++ fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
++ fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
++ fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
+ }
+
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 0000000..2b30c46
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,34 @@
+From dac72d809be9faf9380b181df0c19a2c6d744c54 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Mon, 28 Aug 2017 19:53:54 -0700
+Subject: [PATCH] Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Inappropriate [workaround]
+
+---
+ bfd/elf-eh-frame.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index 95697c4..704121d 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -1042,10 +1042,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+ goto success;
+
+ free_no_table:
+- (*info->callbacks->einfo)
++ /* FIXME: Remove the microblaze specifics when relaxing gets fixed. */
++ if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+ /* xgettext:c-format */
+- (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
+- abfd, sec);
++ (*info->callbacks->einfo)
++ (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
++ abfd, sec);
++ }
+ hdr_info->u.dwarf.table = FALSE;
+ if (sec_info)
+ free (sec_info);
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch
new file mode 100644
index 0000000..b543c54
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch
@@ -0,0 +1,81 @@
+From 927ef228dfedf229dc915b273a308ab2c7bf9e19 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Mon, 28 Aug 2017 19:53:55 -0700
+Subject: [PATCH] Fix relaxation of assembler resolved references
+
+03/2018
+Rebased for binutils 2.30
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
+
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++++++++++
+ gas/config/tc-microblaze.c | 1 +
+ 2 files changed, 40 insertions(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index f1808bc..a1d810c 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1887,6 +1887,45 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ {
++ unsigned int val;
++
++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++ /* This was a PC-relative instruction that was completely resolved. */
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
++ + isym->st_value, sec);
++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++ irelscan->r_addend);
++ }
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
++ fprintf(stderr, "Unhandled NONE 64\n");
++ }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 42dd7ae..50dbfc7 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2183,6 +2183,7 @@ md_apply_fix (fixS * fixP,
+ else
+ fixP->fx_r_type = BFD_RELOC_NONE;
+ fixP->fx_addsy = section_symbol (absolute_section);
++ fixP->fx_done = 0;
+ }
+ return;
+ }
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
new file mode 100644
index 0000000..3817234
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
@@ -0,0 +1,242 @@
+From 5bf68bc39976903929f730b6eed18686c3563c05 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:56 -0700
+Subject: [PATCH] Fixup MicroBlaze debug_loc sections after linker relaxation
+
+Fixup debug_loc sections after linker relaxation Adds a new reloctype
+R_MICROBLAZE_32_NONE, used for passing reloc info from the assembler to
+the linker when the linker manages to fully resolve a local symbol
+reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+03/2018
+Rebased for binutils 2.30
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
+
+Upstream-Status: Pending
+
+---
+ bfd/bfd-in2.h | 9 +++++++--
+ bfd/elf32-microblaze.c | 45 ++++++++++++++++++++++++++++++++++++++-------
+ bfd/libbfd.h | 1 +
+ bfd/reloc.c | 6 ++++++
+ binutils/readelf.c | 4 ++++
+ gas/config/tc-microblaze.c | 5 ++++-
+ include/elf/microblaze.h | 1 +
+ 7 files changed, 61 insertions(+), 10 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 4228603..1906195 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5826,10 +5826,15 @@ value relative to the read-write small data area anchor */
+ expressions of the form "Symbol Op Symbol" */
+ BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 32 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing */
+- BFD_RELOC_MICROBLAZE_64_NONE,
++ BFD_RELOC_MICROBLAZE_32_NONE,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ * +value in two words (with an imm instruction). No relocation is
++ * +done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_64_NONE,
+
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). The relocation is
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a1d810c..fc0d3e1 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
+ FALSE), /* PC relative offset? */
+
++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_32_NONE",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
+ /* This reloc does nothing. Used for relaxation. */
+ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
+ 0, /* Rightshift. */
+@@ -532,6 +546,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_NONE:
+ microblaze_reloc = R_MICROBLAZE_NONE;
+ break;
++ case BFD_RELOC_MICROBLAZE_32_NONE:
++ microblaze_reloc = R_MICROBLAZE_32_NONE;
++ break;
+ case BFD_RELOC_MICROBLAZE_64_NONE:
+ microblaze_reloc = R_MICROBLAZE_64_NONE;
+ break;
+@@ -1832,14 +1849,23 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ break;
+ case R_MICROBLAZE_NONE:
++ case R_MICROBLAZE_32_NONE:
+ {
+ /* This was a PC-relative instruction that was
+ completely resolved. */
+ int sfix, efix;
++ unsigned int val;
+ bfd_vma target_address;
+ target_address = irel->r_addend + irel->r_offset;
+ sfix = calc_fixup (irel->r_offset, 0, sec);
+ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
++
+ irel->r_addend -= (efix - sfix);
+ /* Should use HOWTO. */
+ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -1887,12 +1913,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+ {
+ unsigned int val;
+
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
++ /* hax: We only do the following fixup for debug location lists. */
++ if (strcmp(".debug_loc", o->name))
++ continue;
++
+ /* This was a PC-relative instruction that was completely resolved. */
+ if (ocontents == NULL)
+ {
+@@ -1917,15 +1947,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ }
+
+- irelscan->r_addend -= calc_fixup (irelscan->r_addend
+- + isym->st_value, sec);
+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++
++ if (val != irelscan->r_addend) {
++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++ }
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+- fprintf(stderr, "Unhandled NONE 64\n");
+- }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+@@ -1985,7 +2016,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ elf_section_data (o)->this_hdr.contents = ocontents;
+ }
+ }
+- irelscan->r_addend -= calc_fixup (irel->r_addend
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ + isym->st_value,
+ 0,
+ sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 2f5f16e..854bb0c 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2853,6 +2853,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_MICROBLAZE_32_ROSDA",
+ "BFD_RELOC_MICROBLAZE_32_RWSDA",
+ "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++ "BFD_RELOC_MICROBLAZE_32_NONE",
+ "BFD_RELOC_MICROBLAZE_64_NONE",
+ "BFD_RELOC_MICROBLAZE_64_GOTPC",
+ "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index a1353a2..4b57de7 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6903,6 +6903,12 @@ ENUMDOC
+ This is a 32 bit reloc for the microblaze to handle
+ expressions of the form "Symbol Op Symbol"
+ ENUM
++ BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imm instruction). No relocation is
++ done here - only used for relaxing
++ENUM
+ BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index fed0387..92f655d 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -12774,6 +12774,10 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
+ || reloc_type == 32 /* R_AVR_DIFF32. */);
+ case EM_METAG:
+ return reloc_type == 3; /* R_METAG_NONE. */
++ case EM_MICROBLAZE:
++ return reloc_type == 30 /* R_MICROBLAZE_32_NONE. */
++ || reloc_type == 0 /* R_MICROBLAZE_NONE. */
++ || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */
+ case EM_NDS32:
+ return (reloc_type == 0 /* R_XTENSA_NONE. */
+ || reloc_type == 204 /* R_NDS32_DIFF8. */
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 50dbfc7..d66e949 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2179,7 +2179,9 @@ md_apply_fix (fixS * fixP,
+ /* This fixup has been resolved. Create a reloc in case the linker
+ moves code around due to relaxing. */
+ if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++ else if (fixP->fx_r_type == BFD_RELOC_32)
++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+ else
+ fixP->fx_r_type = BFD_RELOC_NONE;
+ fixP->fx_addsy = section_symbol (absolute_section);
+@@ -2401,6 +2403,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+ switch (fixp->fx_r_type)
+ {
+ case BFD_RELOC_NONE:
++ case BFD_RELOC_MICROBLAZE_32_NONE:
+ case BFD_RELOC_MICROBLAZE_64_NONE:
+ case BFD_RELOC_32:
+ case BFD_RELOC_MICROBLAZE_32_LO:
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index ae98099..c8cc57b 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+ RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27) /* TLS Offset Within TLS Block */
+ RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
+ RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29) /* TLS Offset From Thread Pointer */
++ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
+
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
new file mode 100644
index 0000000..a671cf8
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
@@ -0,0 +1,35 @@
+From 0cad227ce495a975b32c10a8b6b0970c45024dd6 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:58 -0700
+Subject: [PATCH] Fix bug in MicroBlaze TLSTPREL Relocation
+
+Fixed the problem related to the fixup/relocations TLSTPREL.
+When the fixup is applied the addend is not added at the correct offset
+of the instruction. The offset is hard coded considering its big endian
+and it fails for Little endian. This patch allows support for both
+big & little-endian compilers
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index fc0d3e1..a94799f 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1402,9 +1402,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ relocation += addend;
+ relocation -= dtprel_base(info);
+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
+- contents + offset + 2);
++ contents + offset + endian);
+ bfd_put_16 (input_bfd, relocation & 0xffff,
+- contents + offset + 2 + INST_WORD_SIZE);
++ contents + offset + endian + INST_WORD_SIZE);
+ break;
+ case (int) R_MICROBLAZE_64_PCREL :
+ case (int) R_MICROBLAZE_64:
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch
new file mode 100644
index 0000000..9672c51
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch
@@ -0,0 +1,104 @@
+From 3895968b5c55321d203cadb7630a2baee8699e17 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:59 -0700
+Subject: [PATCH] Add MicroBlaze address extension instructions
+
+This patch adds the support of new instructions which are required
+for supporting Address extension feature.
+
+2016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * microblaze-opc.h (op_code_struct): Added new instructions
+ * microblaze-opcm.h (microblaze_instr): Added new instructions
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 13 ++++++++++++-
+ opcodes/microblaze-opcm.h | 10 +++++-----
+ 2 files changed, 17 insertions(+), 6 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 773dc81..4e69f76 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -102,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 291
++#define MAX_OPCODES 299
+
+ struct op_code_struct
+ {
+@@ -178,8 +178,11 @@ struct op_code_struct
+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
++ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
++ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
++ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+ {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
+ {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
+@@ -229,18 +232,24 @@ struct op_code_struct
+ {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
+ {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+ {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
++ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
+ {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+ {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
++ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
+ {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+ {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
+ {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
++ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
+ {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+ {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
++ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
+ {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+ {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
++ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
+ {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+ {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
+ {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
++ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
+ {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
+ {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
+ {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
+@@ -405,6 +414,8 @@ struct op_code_struct
+ {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
+ {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
+ {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
++ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */
++ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
+ {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
+ {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
+ {"", 0, 0, 0, 0, 0, 0, 0, 0},
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 7338f6a..c75f10a 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,13 +33,13 @@ enum microblaze_instr
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+- brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
++ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
++ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+- shr, sw, swr, swx, lbui, lhui, lwi,
++ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+ sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
+ fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+ fint, fsqrt,
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch
new file mode 100644
index 0000000..0bc0117
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch
@@ -0,0 +1,232 @@
+From 5c4dacaae2ba93569c1d37cda9859c57d6649dc0 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:54:01 -0700
+Subject: [PATCH] Add new MicroBlaze bit-field instructions
+
+This patches adds new bsefi and bsifi instructions. BSEFI- The
+instruction shall extract a bit field from a register and place it
+right-adjusted in the destination register. The other bits in the
+destination register shall be set to zero BSIFI- The instruction shall
+insert a right-adjusted bit field from a register at another position in
+the destination register. The rest of the bits in the destination
+register shall be unchanged
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c | 16 +++++++++++
+ opcodes/microblaze-opc.h | 12 +++++++-
+ opcodes/microblaze-opcm.h | 6 +++-
+ 4 files changed, 102 insertions(+), 3 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index e135547e62..34cb80fac2 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -909,7 +909,7 @@ md_assemble (char * str)
+ unsigned reg2;
+ unsigned reg3;
+ unsigned isize;
+- unsigned int immed, temp;
++ unsigned int immed, immed2, temp;
+ expressionS exp;
+ char name[20];
+
+@@ -1164,7 +1164,76 @@ md_assemble (char * str)
+ inst |= (reg2 << RA_LOW) & RA_MASK;
+ inst |= (immed << IMM_LOW) & IMM5_MASK;
+ break;
++ case INST_TYPE_RD_R1_IMM5_IMM5:
++ if (strcmp (op_end, ""))
++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
++ else
++ {
++ as_fatal (_("Error in statement syntax"));
++ reg1 = 0;
++ }
++ if (strcmp (op_end, ""))
++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */
++ else
++ {
++ as_fatal (_("Error in statement syntax"));
++ reg2 = 0;
++ }
++
++ /* Check for spl registers. */
++ if (check_spl_reg (®1))
++ as_fatal (_("Cannot use special register with this instruction"));
++ if (check_spl_reg (®2))
++ as_fatal (_("Cannot use special register with this instruction"));
+
++ /* Width immediate value. */
++ if (strcmp (op_end, ""))
++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++ else
++ as_fatal (_("Error in statement syntax"));
++ if (exp.X_op != O_constant)
++ {
++ as_warn (_("Symbol used as immediate width value for bit field instruction"));
++ immed = 1;
++ }
++ else
++ immed = exp.X_add_number;
++ if (opcode->instr == bsefi && immed > 31)
++ as_fatal (_("Width value must be less than 32"));
++
++ /* Shift immediate value. */
++ if (strcmp (op_end, ""))
++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
++ else
++ as_fatal (_("Error in statement syntax"));
++ if (exp.X_op != O_constant)
++ {
++ as_warn (_("Symbol used as immediate shift value for bit field instruction"));
++ immed2 = 0;
++ }
++ else
++ {
++ output = frag_more (isize);
++ immed2 = exp.X_add_number;
++ }
++ if (immed2 != (immed2 % 32))
++ {
++ as_warn (_("Shift value greater than 32. using <value %% 32>"));
++ immed2 = immed2 % 32;
++ }
++
++ /* Check combined value. */
++ if (immed + immed2 > 32)
++ as_fatal (_("Width value + shift value must not be greater than 32"));
++
++ inst |= (reg1 << RD_LOW) & RD_MASK;
++ inst |= (reg2 << RA_LOW) & RA_MASK;
++ if (opcode->instr == bsefi)
++ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++ else
++ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
++ inst |= (immed2 << IMM_LOW) & IMM5_MASK;
++ break;
+ case INST_TYPE_R1_R2:
+ if (strcmp (op_end, ""))
+ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 6a174b0eb9..80a47ad2fc 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr)
+ return(strdup(tmpstr));
+ }
+
++static char *
++get_field_imm5width (long instr)
++{
++ char tmpstr[25];
++
++ if (instr & 0x00004000)
++ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++ return (strdup (tmpstr));
++}
++
+ static char *
+ get_field_rfsl (long instr)
+ {
+@@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ /* For mbar 16 or sleep insn. */
+ case INST_TYPE_NONE:
+ break;
++ /* For bit field insns. */
++ case INST_TYPE_RD_R1_IMM5_IMM5:
++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst));
++ break;
+ /* For tuqula instruction */
+ case INST_TYPE_RD:
+ print_func (stream, "\t%s", get_field_rd (inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index a64f8362da..afb34989d9 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -59,6 +59,9 @@
+ /* For mbar. */
+ #define INST_TYPE_IMM5 20
+
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMM5_IMM5 21
++
+ #define INST_TYPE_NONE 25
+
+
+@@ -89,7 +92,9 @@
+ #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
++#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
++#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+@@ -102,7 +107,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 299
++#define MAX_OPCODES 301
+
+ struct op_code_struct
+ {
+@@ -159,6 +164,8 @@ struct op_code_struct
+ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+ {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+ {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+ {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5 ((int) 0x00000000)
+ #define MAX_IMM5 ((int) 0x0000001f)
+
++#define MIN_IMM_WIDTH ((int) 0x00000001)
++#define MAX_IMM_WIDTH ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 21a3dc8d76..dd6be7f65c 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -29,7 +29,7 @@ enum microblaze_instr
+ addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+ mulh, mulhu, mulhsu,swapb,swaph,
+ idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -129,6 +129,7 @@ enum microblaze_instr_type
+ #define RB_LOW 11 /* Low bit for RB. */
+ #define IMM_LOW 0 /* Low bit for immediate. */
+ #define IMM_MBAR 21 /* low bit for mbar instruction. */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+@@ -141,6 +142,9 @@ enum microblaze_instr_type
+ /* Imm mask for mbar. */
+ #define IMM5_MBAR_MASK 0x03E00000
+
++/* Imm mask for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++
+ /* FSL imm mask for get, put instructions. */
+ #define RFSL_MASK 0x000000F
+
+--
+2.15.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch
new file mode 100644
index 0000000..bb7e91c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch
@@ -0,0 +1,29 @@
+From f649406ccaea992f3931e0d9ca9fbd6efb0c553b Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:54:02 -0700
+Subject: [PATCH] Fixing MicroBlaze IMM bug
+
+Fixing the imm bug. with relax option imm -1 is also getting removed this is corrected now.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a94799f..74b00d2 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1789,8 +1789,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ else
+ symval += irel->r_addend;
+
+- if ((symval & 0xffff8000) == 0
+- || (symval & 0xffff8000) == 0xffff8000)
++ if ((symval & 0xffff8000) == 0)
+ {
+ /* We can delete this instruction. */
+ sec->relax[sec->relax_count].addr = irel->r_offset;
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
new file mode 100644
index 0000000..077343e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
@@ -0,0 +1,34 @@
+From e1bacaa7c1aa387f167afff74876c5acdffc39d9 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 15 Nov 2017 17:45:35 -0800
+Subject: [PATCH] Fixed bug in GCC so that it will support .long 0U and .long
+ 0u
+
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/expr.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/expr.c b/gas/expr.c
+index 3e28af6..0b7cc76 100644
+--- a/gas/expr.c
++++ b/gas/expr.c
+@@ -810,6 +810,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
+ break;
+ }
+ }
++ if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
++ {
++ input_line_pointer--;
++
++ integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
++ ? 0 : 10,
++ expressionP);
++ break;
++ }
+ c = *input_line_pointer;
+ switch (c)
+ {
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
new file mode 100644
index 0000000..244a7ad
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
@@ -0,0 +1,28 @@
+From 9393a3e346d2ccbb86761117260c1dd89070a507 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Wed, 15 Nov 2017 17:45:34 -0800
+Subject: [PATCH] Fixing MicroBlaze constant range check issue
+
+Sample error: not in range ffffffff80000000..7fffffff, not ffffffff70000000
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/config/tc-microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 21a5a0c..c614556 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -749,7 +749,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
+ if ((e->X_add_number >> 31) == 1)
+ e->X_add_number |= -((addressT) (1U << 31));
+
+- if (e->X_add_number < min || e->X_add_number > max)
++ if ((int)e->X_add_number < min || (int)e->X_add_number > max)
+ {
+ as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
+ (long) min, (long) max, (long) e->X_add_number);
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
new file mode 100644
index 0000000..e340c50
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
@@ -0,0 +1,36 @@
+From 732b5a44a0a032da5ebb775b5df2ee2a36af988f Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan@nathanrossi.com>
+Date: Sun, 5 Nov 2017 22:17:39 +1000
+Subject: [PATCH] MicroBlaze fix mask for barrel shift instructions
+
+As of v10.0 the bsi (bslli/bsrai/bsrli/bsefi/bsifi) instructions have
+bits 16 and 17 defined as 'Insert' and 'Extract' respectively to support
+bit field insert/extract operations. For the bslli/bsrai/bsrli
+instructions these bits must be 0, as such update the opcode mask so
+that the bslli/bsrai/bsrli instructions do not also match the bsefi and
+bsifi instructions.
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 4bc400a..9482d81 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -161,9 +161,9 @@ struct op_code_struct
+ {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+ {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+ {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
+ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+ {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch
new file mode 100644
index 0000000..93af651
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch
@@ -0,0 +1,42 @@
+From 12cd383fbef719cc1a84cc80ff171073409a8557 Mon Sep 17 00:00:00 2001
+From: eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Sat, 27 May 2017 18:29:40 +0000
+Subject: [PATCH] Revert: 2016-01-21 Ajit Agarwal
+ <ajitkum@xilinx.com>
+
+ See https://gcc.gnu.org/ml/gcc/2017-05/msg00221.html.
+
+ * config/microblaze/microblaze.h
+ (FIXED_REGISTERS): Update in macro.
+ (CALL_USED_REGISTERS): Update in macro.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248540 138bc75d-0d04-0410-961f-82ee72b054a4
+Upstream-Status: Backport [from post gcc-7]
+---
+ gcc/config/microblaze/microblaze.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 66e4ef5c3d..2c9ece1d6c 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -269,14 +269,14 @@ extern enum pipeline_type microblaze_pipe;
+ #define FIXED_REGISTERS \
+ { \
+ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
+- 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
++ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 1, 1, 1, 1 \
+ }
+
+ #define CALL_USED_REGISTERS \
+ { \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+- 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
++ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 1, 1, 1, 1 \
+ }
+ #define GP_REG_FIRST 0
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
new file mode 100644
index 0000000..03ea8b1
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
@@ -0,0 +1,66 @@
+From 2d90c10cf4d95999f68f474305828c7dfc51af18 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan@nathanrossi.com>
+Date: Thu, 12 Nov 2015 16:09:31 +1000
+Subject: [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' insn definitions
+
+Change adddi3 to handle DI immediates as the second operand, this
+requires modification to the output template however reduces the need to
+specify seperate templates for 16-bit positive/negative immediate
+operands. The use of 32-bit immediates for the addi and addic
+instructions is handled by the assembler, which will emit the imm
+instructions when required. This conveniently handles the optimizable
+cases where the immediate constant value does not need the higher half
+words of the operands upper/lower words.
+
+Change the constraints of the subdi3 instruction definition such that it
+does not match the second operand as an immediate value. This is because
+there is no definition to handle this case nor is it possible to
+implement purely with instructions as microblaze does not provide an
+instruction to perform a forward arithmetic subtraction (it only
+provides reverse 'rD = IMM - rA').
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Unsubmitted
+---
+ gcc/config/microblaze/microblaze.md | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index b3a0011fd7..8a372d7ebb 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -483,17 +483,16 @@
+ ;; Adding 2 DI operands in register or reg/imm
+
+ (define_insn "adddi3"
+- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
+- (match_operand:DI 2 "arith_operand32" "d,P,N")))]
++ [(set (match_operand:DI 0 "register_operand" "=d,d")
++ (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
++ (match_operand:DI 2 "arith_operand" "d,i")))]
+ ""
+ "@
+ add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
+- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
+- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
++ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
+ [(set_attr "type" "darith")
+ (set_attr "mode" "DI")
+- (set_attr "length" "8,8,12")])
++ (set_attr "length" "8,8")])
+
+ ;;----------------------------------------------------------------
+ ;; Subtraction
+@@ -530,7 +529,7 @@
+ (define_insn "subdi3"
+ [(set (match_operand:DI 0 "register_operand" "=&d")
+ (minus:DI (match_operand:DI 1 "register_operand" "d")
+- (match_operand:DI 2 "arith_operand32" "d")))]
++ (match_operand:DI 2 "register_operand" "d")))]
+ ""
+ "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
+ [(set_attr "type" "darith")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch
new file mode 100644
index 0000000..42bfd3c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch
@@ -0,0 +1,32 @@
+From f17cdebf4e0defaefce927176ddeb9717de073d2 Mon Sep 17 00:00:00 2001
+From: law <law@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Mon, 15 Jan 2018 06:02:19 +0000
+Subject: [PATCH] PR target/83013
+
+ * config/microblaze/microblaze.c (microblaze_asm_output_ident):
+ Use .pushsection/.popsection.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@256681 138bc75d-0d04-0410-961f-82ee72b054a4
+Upstream-Status: Backport [backport from trunk pre-release v8]
+---
+ gcc/config/microblaze/microblaze.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index d0f86fd460..a98aca1235 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3371,7 +3371,9 @@ microblaze_asm_output_ident (const char *string)
+ else
+ section_asm_op = READONLY_DATA_SECTION_ASM_OP;
+
+- buf = ACONCAT ((section_asm_op, "\n\t.ascii \"", string, "\\0\"\n", NULL));
++ buf = ACONCAT (("\t.pushsection", section_asm_op,
++ "\n\t.ascii \"", string, "\\0\"\n",
++ "\t.popsection\n", NULL));
+ symtab->finalize_toplevel_asm (build_string (strlen (buf), buf));
+ }
+
+--
+2.15.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch
new file mode 100644
index 0000000..c0a427e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch
@@ -0,0 +1,36 @@
+From ab2cb6320138c173b20fee8ce6e8d4afa4696384 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:16 -0700
+Subject: [PATCH] dejagnu static testing on qemu, suppress warnings
+
+For dejagnu static testing on qemu, suppress warnings about multiple
+definitions from the test function and libc in line with method used by
+powerpc. Dynamic linking and using a qemu binary which understands
+sysroot resolves all test failures with builtins
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+index ba16b09c41..ada149912b 100644
+--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+@@ -48,6 +48,10 @@ if { [istarget *-*-eabi*]
+ lappend additional_flags "-Wl,--allow-multiple-definition"
+ }
+
++if [istarget "microblaze*-*-linux*"] {
++ lappend additional_flags "-Wl,-zmuldefs"
++}
++
+ foreach src [lsort [find $srcdir/$subdir *.c]] {
+ if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
+ c-torture-execute [list $src \
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
new file mode 100644
index 0000000..b428d12
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
@@ -0,0 +1,118 @@
+From 7f0a129701ce9809d79ea4618f3293062bd24bbf Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:18 -0700
+Subject: [PATCH] Testsuite - explicitly add -fivopts for tests that depend on
+ it
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +-
+ gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-2.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-4.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-5.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr19590.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
+ 8 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
+index 438db88204..ede883eb28 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
+-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
+
+ void test (int *b, int *e, int stride)
+ {
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
+index eb72581390..02f3ea4a7d 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
+@@ -1,5 +1,5 @@
+ // { dg-do compile }
+-// { dg-options "-O2 -fdump-tree-ivopts-details" }
++// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
+
+ class MinimalVec3
+ {
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
+index bda2516735..22c8a5dcff 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
+@@ -1,7 +1,7 @@
+ /* A test for strength reduction and induction variable elimination. */
+
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ /* { dg-require-effective-target size32plus } */
+
+ /* Size of this structure should be sufficiently weird so that no memory
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
+index f0770abdbb..65d74c8e62 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
+@@ -1,7 +1,7 @@
+ /* A test for strength reduction and induction variable elimination. */
+
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ /* { dg-require-effective-target size32plus } */
+
+ /* Size of this structure should be sufficiently weird so that no memory
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
+index 5f42857fe1..9bc86ee0d2 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
+@@ -1,7 +1,7 @@
+ /* A test for induction variable merging. */
+
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+
+ void foo(long);
+
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+index 3c8ee06016..db192a657f 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -Wunsafe-loop-optimizations" } */
++/* { dg-options "-O2 -fivopts -Wunsafe-loop-optimizations" } */
+ extern void g(void);
+
+ void
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
+index 2c6cfc6f83..648e6e67e8 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-ivopts" } */
++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
+
+ void vnum_test8(int *data)
+ {
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
+index e911bfcd52..5d3e7e0801 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-Os -fdump-tree-optimized" } */
++/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
+
+ /* Slightly changed testcase from PR middle-end/40815. */
+ void bar(char*, char*, int);
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch
new file mode 100644
index 0000000..6fad8bf
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch
@@ -0,0 +1,37 @@
+From 8bcdd551f7fe585126ea3173ece976fbc646c34a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:20 -0700
+Subject: [PATCH] Add MicroBlaze to target-supports for atomic builtin tests
+
+MicroBlaze added to supported targets for atomic builtin tests.
+
+Changelog/testsuite
+
+2014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/lib/target-supports.exp: Add microblaze to
+ check_effective_target_sync_int_long.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/lib/target-supports.exp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index 342af270ab..b0f510e596 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -6715,6 +6715,7 @@ proc check_effective_target_sync_int_long { } {
+ && [check_effective_target_arm_acq_rel])
+ || [istarget bfin*-*linux*]
+ || [istarget hppa*-*linux*]
++ || [istarget microblaze*-*linux*]
+ || [istarget s390*-*-*]
+ || [istarget powerpc*-*-*]
+ || [istarget crisv32-*-*] || [istarget cris-*-*]
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch
new file mode 100644
index 0000000..069329f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch
@@ -0,0 +1,46 @@
+From 4622988b62335af6ef17d58bf10940419fd0f99f Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:21 -0700
+Subject: [PATCH] Update MicroBlaze strings test for new scan-assembly output
+ resulting in use of $LC label
+
+ChangeLog/testsuite
+
+2014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
+ to include $LC label.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
+index 7a63faf79f..0403b7bdca 100644
+--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
++++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
+@@ -1,13 +1,15 @@
+ /* { dg-options "-O3" } */
+
++/* { dg-final { scan-assembler "\.rodata*" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
++/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
++
+ #include <string.h>
+
+-/* { dg-final { scan-assembler "\.rodata*" } } */
+ extern void somefunc (char *);
+ int testfunc ()
+ {
+ char string2[80];
+-/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */
+ strcpy (string2, "hello");
+ somefunc (string2);
+ }
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch
new file mode 100644
index 0000000..dbfeb52
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch
@@ -0,0 +1,68 @@
+From 037809e91bfed9c501ecd5272ff6d3ce96edf76c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:22 -0700
+Subject: [PATCH] Allow MicroBlaze .weakext pattern in testsuite
+
+Allow MicroBlaze .weakext pattern in regex match Extend regex pattern to
+include optional ext at the end of .weak to match the MicroBlaze weak
+label .weakext
+
+ChangeLog/testsuite
+
+2014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
+ pattern to take optional ext after .weak.
+ * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++--
+ gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
+ gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
+index 0316bcb5de..5a39a0811f 100644
+--- a/gcc/testsuite/g++.dg/abi/rtti3.C
++++ b/gcc/testsuite/g++.dg/abi/rtti3.C
+@@ -3,8 +3,8 @@
+
+ // { dg-require-weak "" }
+ // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } }
+-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
+-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
+ // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
+
+diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
+index f2347f79ec..dcec8a771a 100644
+--- a/gcc/testsuite/g++.dg/abi/thunk3.C
++++ b/gcc/testsuite/g++.dg/abi/thunk3.C
+@@ -1,5 +1,5 @@
+ // { dg-require-weak "" }
+-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
+
+ struct Base
+diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
+index fa5fbd4327..79cb311cab 100644
+--- a/gcc/testsuite/g++.dg/abi/thunk4.C
++++ b/gcc/testsuite/g++.dg/abi/thunk4.C
+@@ -1,6 +1,6 @@
+ // { dg-require-weak "" }
+ // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } }
+-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
+
+ struct Base
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch
new file mode 100644
index 0000000..6b9dd99
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch
@@ -0,0 +1,32 @@
+From 23a04c06c2a689fed151eeb94c45ea9b512036ae Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:23 -0700
+Subject: [PATCH] Add MicroBlaze to check_profiling_available Testsuite
+
+Add MicroBlaze to check_profiling_available Testsuite, add
+microblaze*-*-* target in check_profiling_available inline with other
+archs setting profiling_available_saved to 0
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/lib/target-supports.exp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index b0f510e596..fffb690e49 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -625,6 +625,7 @@ proc check_profiling_available { test_what } {
+ || [istarget m68k-*-elf]
+ || [istarget m68k-*-uclinux*]
+ || [istarget mips*-*-elf*]
++ || [istarget microblaze*-*-*]
+ || [istarget mmix-*-*]
+ || [istarget mn10300-*-elf*]
+ || [istarget moxie-*-elf*]
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch
new file mode 100644
index 0000000..c21ca81
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch
@@ -0,0 +1,69 @@
+From c1e8a1419e8f5d18e7135fb4fe3bf21941125008 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:24 -0700
+Subject: [PATCH] Fix atomic side effects.
+
+In atomic_compare_and_swapsi, add side effects to prevent incorrect
+assumptions during optimization. Previously, the outputs were considered
+unused; this generated assembly code with undefined side effects after
+invocation of the atomic.
+
+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 3 +++
+ gcc/config/microblaze/sync.md | 21 +++++++++++++--------
+ 2 files changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 8a372d7ebb..59d629b559 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -41,6 +41,9 @@
+ (UNSPEC_CMP 104) ;; signed compare
+ (UNSPEC_CMPU 105) ;; unsigned compare
+ (UNSPEC_TLS 106) ;; jump table
++ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool)
++ (UNSPECV_CAS_VAL 202) ;; compare and swap (val)
++ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem)
+ ])
+
+ (define_c_enum "unspec" [
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index 8125bd8d63..edf4bdd811 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -18,14 +18,19 @@
+ ;; <http://www.gnu.org/licenses/>.
+
+ (define_insn "atomic_compare_and_swapsi"
+- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
+- (match_operand:SI 1 "register_operand" "=&d") ;; val output
+- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
+- (match_operand:SI 3 "register_operand" "d") ;; expected value
+- (match_operand:SI 4 "register_operand" "d") ;; desired value
+- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
+- (match_operand:SI 6 "const_int_operand" "") ;; mod_s
+- (match_operand:SI 7 "const_int_operand" "") ;; mod_f
++ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
++ (unspec_volatile:SI
++ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
++ (match_operand:SI 3 "register_operand" "d") ;; expected value
++ (match_operand:SI 4 "register_operand" "d")] ;; desired value
++ UNSPECV_CAS_BOOL))
++ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
++ (set (match_dup 2)
++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
++ (match_operand:SI 5 "const_int_operand" "") ;; is_weak
++ (match_operand:SI 6 "const_int_operand" "") ;; mod_s
++ (match_operand:SI 7 "const_int_operand" "") ;; mod_f
+ (clobber (match_scratch:SI 8 "=&d"))]
+ ""
+ {
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch
new file mode 100644
index 0000000..f4bc16e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch
@@ -0,0 +1,44 @@
+From a5957bdf7acfde0a65eeba90bae11f5619bf96af Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:25 -0700
+Subject: [PATCH] Fix atomic boolean return value.
+
+In atomic_compare_and_swapsi, fix boolean return value. Previously, it
+contained zero if successful and non-zero if unsuccessful.
+
+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/sync.md | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index edf4bdd811..aadb414728 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -34,15 +34,16 @@
+ (clobber (match_scratch:SI 8 "=&d"))]
+ ""
+ {
+- output_asm_insn ("addc \tr0,r0,r0", operands);
++ output_asm_insn ("add \t%0,r0,r0", operands);
+ output_asm_insn ("lwx \t%1,%y2,r0", operands);
+ output_asm_insn ("addic\t%8,r0,0", operands);
+ output_asm_insn ("bnei \t%8,.-8", operands);
+- output_asm_insn ("cmp \t%0,%1,%3", operands);
+- output_asm_insn ("bnei \t%0,.+16", operands);
++ output_asm_insn ("cmp \t%8,%1,%3", operands);
++ output_asm_insn ("bnei \t%8,.+20", operands);
+ output_asm_insn ("swx \t%4,%y2,r0", operands);
+ output_asm_insn ("addic\t%8,r0,0", operands);
+ output_asm_insn ("bnei \t%8,.-28", operands);
++ output_asm_insn ("addi \t%0,r0,1", operands);
+ return "";
+ }
+ )
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch
new file mode 100644
index 0000000..464f59e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch
@@ -0,0 +1,37 @@
+From 1a9dcdb578452ecd53e0aec65fe6279233218778 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:26 -0700
+Subject: [PATCH] Fix the Microblaze crash with msmall-divides flag
+
+Fix the Microblaze crash with msmall-divides flag Compiler is crashing
+when we use msmall-divides and mxl-barrel-shift flag. This is because
+when use above flags microblaze_expand_divide function will be called
+for division operation. In microblaze_expand_divide function we are
+using sub_reg but MicroBlaze doesn't have subreg register due to this
+compiler was crashing. Changed the logic to avoid sub_reg call
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index bba6983b65..15080db539 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3527,8 +3527,7 @@ microblaze_expand_divide (rtx operands[])
+ mem_rtx = gen_rtx_MEM (QImode,
+ gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
+
+- insn = emit_insn (gen_movqi (regqi, mem_rtx));
+- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
++ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+ jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
+ JUMP_LABEL (jump) = div_end_label;
+ LABEL_NUSES (div_end_label) = 1;
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch
new file mode 100644
index 0000000..6005e21
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch
@@ -0,0 +1,53 @@
+From c32df2ec3d269d19b631a17cea2b6d19bbb98c27 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:27 -0700
+Subject: [PATCH] Add MicroBlaze ashrsi_3_with_size_opt
+
+Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt pattern to
+optimize the sra instructions when the -Os optimization is used.
+lshrsi3_with_size_opt is being removed as it has conflicts with unsigned
+int variables
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 59d629b559..8c0a97e032 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1505,6 +1505,27 @@
+ (set_attr "length" "4,4")]
+ )
+
++(define_insn "*ashrsi3_with_size_opt"
++ [(set (match_operand:SI 0 "register_operand" "=&d")
++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
++ (match_operand:SI 2 "immediate_operand" "I")))]
++ "(INTVAL (operands[2]) > 5 && optimize_size)"
++ {
++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++
++ output_asm_insn ("ori\t%3,r0,%2", operands);
++ if (REGNO (operands[0]) != REGNO (operands[1]))
++ output_asm_insn ("addk\t%0,%1,r0", operands);
++
++ output_asm_insn ("addik\t%3,%3,-1", operands);
++ output_asm_insn ("bneid\t%3,.-4", operands);
++ return "sra\t%0,%0";
++ }
++ [(set_attr "type" "arith")
++ (set_attr "mode" "SI")
++ (set_attr "length" "20")]
++)
++
+ (define_insn "*ashrsi_inline"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch
new file mode 100644
index 0000000..b019571
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch
@@ -0,0 +1,156 @@
+From a68e94fc57bcf60cb730894e49dde55d081397f5 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:28 -0700
+Subject: [PATCH] Removed MicroBlaze moddi3 routinue
+
+Removed moddi3 routinue Using the default moddi3 function as the
+existing implementation has many bugs
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ libgcc/config/microblaze/moddi3.S | 115 ----------------------------------
+ libgcc/config/microblaze/t-microblaze | 3 +-
+ 2 files changed, 1 insertion(+), 117 deletions(-)
+ delete mode 100644 libgcc/config/microblaze/moddi3.S
+
+diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
+deleted file mode 100644
+index bcea079476..0000000000
+--- a/libgcc/config/microblaze/moddi3.S
++++ /dev/null
+@@ -1,115 +0,0 @@
+-###################################
+-#
+-# Copyright (C) 2009-2017 Free Software Foundation, Inc.
+-#
+-# Contributed by Michael Eager <eager@eagercon.com>.
+-#
+-# This file is free software; you can redistribute it and/or modify it
+-# under the terms of the GNU General Public License as published by the
+-# Free Software Foundation; either version 3, or (at your option) any
+-# later version.
+-#
+-# GCC is distributed in the hope that it will be useful, but WITHOUT
+-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+-# License for more details.
+-#
+-# Under Section 7 of GPL version 3, you are granted additional
+-# permissions described in the GCC Runtime Library Exception, version
+-# 3.1, as published by the Free Software Foundation.
+-#
+-# You should have received a copy of the GNU General Public License and
+-# a copy of the GCC Runtime Library Exception along with this program;
+-# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+-# <http://www.gnu.org/licenses/>.
+-#
+-# modsi3.S
+-#
+-# modulo operation for 64 bit integers.
+-#
+-#######################################
+-
+-
+- .globl __moddi3
+- .ent __moddi3
+-__moddi3:
+- .frame r1,0,r15
+-
+-#Change the stack pointer value and Save callee saved regs
+- addik r1,r1,-24
+- swi r25,r1,0
+- swi r26,r1,4
+- swi r27,r1,8 # used for sign
+- swi r28,r1,12 # used for loop count
+- swi r29,r1,16 # Used for div value High
+- swi r30,r1,20 # Used for div value Low
+-
+-#Check for Zero Value in the divisor/dividend
+- OR r9,r5,r6 # Check for the op1 being zero
+- BEQID r9,$LaResult_Is_Zero # Result is zero
+- OR r9,r7,r8 # Check for the dividend being zero
+- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error
+- BGEId r5,$La1_Pos
+- XOR r27,r5,r7 # Get the sign of the result
+- RSUBI r6,r6,0 # Make dividend positive
+- RSUBIC r5,r5,0 # Make dividend positive
+-$La1_Pos:
+- BGEI r7,$La2_Pos
+- RSUBI r8,r8,0 # Make Divisor Positive
+- RSUBIC r9,r9,0 # Make Divisor Positive
+-$La2_Pos:
+- ADDIK r4,r0,0 # Clear mod low
+- ADDIK r3,r0,0 # Clear mod high
+- ADDIK r29,r0,0 # clear div high
+- ADDIK r30,r0,0 # clear div low
+- ADDIK r28,r0,64 # Initialize the loop count
+- # First part try to find the first '1' in the r5/r6
+-$LaDIV1:
+- ADD r6,r6,r6
+- ADDC r5,r5,r5 # left shift logical r5
+- BGEID r5,$LaDIV1
+- ADDIK r28,r28,-1
+-$LaDIV2:
+- ADD r6,r6,r6
+- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry
+- ADDC r4,r4,r4 # Move that bit into the Mod register
+- ADDC r3,r3,r3 # Move carry into high mod register
+- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor
+- bnei r18,$L_High_EQ
+- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h]
+-$L_High_EQ:
+- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L]
+- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H]
+- BLTi r25,$LaMOD_TOO_SMALL
+- OR r3,r0,r25 # move r25 to mod [h]
+- OR r4,r0,r26 # move r26 to mod [l]
+- ADDI r30,r30,1
+- ADDC r29,r29,r0
+-$LaMOD_TOO_SMALL:
+- ADDIK r28,r28,-1
+- BEQi r28,$LaLOOP_END
+- ADD r30,r30,r30 # Shift in the '1' into div [low]
+- ADDC r29,r29,r29 # Move the carry generated into high
+- BRI $LaDIV2 # Div2
+-$LaLOOP_END:
+- BGEI r27,$LaRETURN_HERE
+- rsubi r30,r30,0
+- rsubc r29,r29,r0
+- BRI $LaRETURN_HERE
+-$LaDiv_By_Zero:
+-$LaResult_Is_Zero:
+- or r29,r0,r0 # set result to 0 [High]
+- or r30,r0,r0 # set result to 0 [Low]
+-$LaRETURN_HERE:
+-# Restore values of CSRs and that of r29 and the divisor and the dividend
+-
+- lwi r25,r1,0
+- lwi r26,r1,4
+- lwi r27,r1,8
+- lwi r28,r1,12
+- lwi r29,r1,16
+- lwi r30,r1,20
+- rtsd r15,8
+- addik r1,r1,24
+- .end __moddi3
+-
+diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
+index 96959f0292..8d954a4957 100644
+--- a/libgcc/config/microblaze/t-microblaze
++++ b/libgcc/config/microblaze/t-microblaze
+@@ -1,8 +1,7 @@
+-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
+
+ LIB2ADD += \
+ $(srcdir)/config/microblaze/divsi3.S \
+- $(srcdir)/config/microblaze/moddi3.S \
+ $(srcdir)/config/microblaze/modsi3.S \
+ $(srcdir)/config/microblaze/muldi3_hard.S \
+ $(srcdir)/config/microblaze/mulsi3.S \
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch
new file mode 100644
index 0000000..e75bebe
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch
@@ -0,0 +1,46 @@
+From 79ea36649467aea6045a49c7d016f8f9245efb8c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:29 -0700
+Subject: [PATCH] MicroBlaze fixed missing save of r18 in fast_interrupt
+
+Fixed missing save of r18 in fast_interrupt. Register 18 is used as a
+clobber register, and must be stored when entering a fast_interrupt.
+Before this fix, register 18 was only saved if it was used directly in
+the interrupt function.
+
+However, if the fast_interrupt function called a function that used
+r18, the register would not be saved, and thus be mangled
+upon returning from the interrupt.
+
+Changelog
+
+2014-02-27 Klaus Petersen <klauspetersen@gmail.com>
+
+ * gcc/config/microblaze/microblaze.c: Check for fast_interrupt in
+ microblaze_must_save_register.
+
+Signed-off-by: Klaus Petersen <klauspetersen@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 15080db539..558796cad9 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -1943,7 +1943,7 @@ microblaze_must_save_register (int regno)
+ {
+ if (df_regs_ever_live_p (regno)
+ || regno == MB_ABI_MSR_SAVE_REG
+- || (interrupt_handler
++ || ((interrupt_handler || fast_interrupt)
+ && (regno == MB_ABI_ASM_TEMP_REGNUM
+ || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM)))
+ return 1;
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch
new file mode 100644
index 0000000..f5de718
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch
@@ -0,0 +1,29 @@
+From 6ed57ee8219e5d09a294b329dd7c531a1868dc8a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:31 -0700
+Subject: [PATCH] MicroBlaze use bralid for profiler calls
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index ccd77e8b4d..0dd8b853e2 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -519,7 +519,7 @@ typedef struct microblaze_args
+
+ #define FUNCTION_PROFILER(FILE, LABELNO) { \
+ { \
+- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
++ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \
+ } \
+ }
+
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch
new file mode 100644
index 0000000..4041e11
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch
@@ -0,0 +1,38 @@
+From 25b161dd222311cca0e6ab46b7f3be444bd4bbe8 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:32 -0700
+Subject: [PATCH] Disable fivopts by default Turn off ivopts by default.
+ Interferes with cse.
+
+Changelog
+
+2013-03-18 Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+ * gcc/common/config/microblaze/microblaze-common.c
+ (microblaze_option_optimization_table): Disable fivopts by default.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/common/config/microblaze/microblaze-common.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
+index 4975663305..8ddc4c3cbe 100644
+--- a/gcc/common/config/microblaze/microblaze-common.c
++++ b/gcc/common/config/microblaze/microblaze-common.c
+@@ -27,6 +27,8 @@
+ /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
+ static const struct default_options microblaze_option_optimization_table[] =
+ {
++ /* Turn off ivopts by default. It messes up cse. */
++ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+ { OPT_LEVELS_NONE, 0, NULL, 0 }
+ };
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch
new file mode 100644
index 0000000..5239d2b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch
@@ -0,0 +1,104 @@
+From 02d8afd50a868e827ac8b6b6243c69922cd694ed Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:34 -0700
+Subject: [PATCH] Add INIT_PRIORITY support Added TARGET_ASM_CONSTRUCTOR and
+ TARGET_ASM_DESTRUCTOR macros.
+
+These macros allows users to control the order of initialization
+of objects defined at namespace scope with the init_priority
+attribute by specifying a relative priority, a constant integral
+expression currently bounded between 101 and 65535 inclusive.
+
+Lower numbers indicate a higher priority.
+
+Changelog
+
+2013-11-26 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
+ microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
+ TARGET_ASM_DESTRUCTOR.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 558796cad9..c1b0172bcf 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2530,6 +2530,53 @@ print_operand_address (FILE * file, rtx addr)
+ }
+ }
+
++/* Output an element in the table of global constructors. */
++void
++microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
++{
++ const char *section = ".ctors";
++ char buf[16];
++
++ if (priority != DEFAULT_INIT_PRIORITY)
++ {
++ sprintf (buf, ".ctors.%.5u",
++ /* Invert the numbering so the linker puts us in the proper
++ order; constructors are run from right to left, and the
++ linker sorts in increasing order. */
++ MAX_INIT_PRIORITY - priority);
++ section = buf;
++ }
++
++ switch_to_section (get_section (section, 0, NULL));
++ assemble_align (POINTER_SIZE);
++ fputs ("\t.word\t", asm_out_file);
++ output_addr_const (asm_out_file, symbol);
++ fputs ("\n", asm_out_file);
++}
++
++/* Output an element in the table of global destructors. */
++void
++microblaze_asm_destructor (rtx symbol, int priority)
++{
++ const char *section = ".dtors";
++ char buf[16];
++ if (priority != DEFAULT_INIT_PRIORITY)
++ {
++ sprintf (buf, ".dtors.%.5u",
++ /* Invert the numbering so the linker puts us in the proper
++ order; constructors are run from right to left, and the
++ linker sorts in increasing order. */
++ MAX_INIT_PRIORITY - priority);
++ section = buf;
++ }
++
++ switch_to_section (get_section (section, 0, NULL));
++ assemble_align (POINTER_SIZE);
++ fputs ("\t.word\t", asm_out_file);
++ output_addr_const (asm_out_file, symbol);
++ fputs ("\n", asm_out_file);
++}
++
+ /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
+ is used, so that we don't emit an .extern for it in
+ microblaze_asm_file_end. */
+@@ -3775,6 +3822,12 @@ microblaze_machine_dependent_reorg (void)
+ #undef TARGET_ATTRIBUTE_TABLE
+ #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table
+
++#undef TARGET_ASM_CONSTRUCTOR
++#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor
++
++#undef TARGET_ASM_DESTRUCTOR
++#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor
++
+ #undef TARGET_IN_SMALL_DATA_P
+ #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p
+
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch
new file mode 100644
index 0000000..049ce3f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch
@@ -0,0 +1,87 @@
+From 0b2061ac7706df97da3e8b3c01c6a5cfc504c16e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:35 -0700
+Subject: [PATCH] MicroBlaze add optimized lshrsi3 When barrel shifter is not
+ present
+
+Add optimized lshrsi3 When barrel shifter is not present, the immediate
+value is greater than #5 and optimization is -OS, the compiler will
+generate shift operation using loop.
+
+Changelog
+
+2013-11-26 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
+
+ChangeLog/testsuite
+
+2014-02-12 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
+ .../gcc.target/microblaze/others/lshrsi_Os_1.c | 13 +++++++++++++
+ 2 files changed, 34 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 8c0a97e032..abbe97c15f 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1615,6 +1615,27 @@
+ (set_attr "length" "4,4")]
+ )
+
++(define_insn "*lshrsi3_with_size_opt"
++ [(set (match_operand:SI 0 "register_operand" "=&d")
++ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
++ (match_operand:SI 2 "immediate_operand" "I")))]
++ "(INTVAL (operands[2]) > 5 && optimize_size)"
++ {
++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++
++ output_asm_insn ("ori\t%3,r0,%2", operands);
++ if (REGNO (operands[0]) != REGNO (operands[1]))
++ output_asm_insn ("addk\t%0,%1,r0", operands);
++
++ output_asm_insn ("addik\t%3,%3,-1", operands);
++ output_asm_insn ("bneid\t%3,.-4", operands);
++ return "srl\t%0,%0";
++ }
++ [(set_attr "type" "multi")
++ (set_attr "mode" "SI")
++ (set_attr "length" "20")]
++)
++
+ (define_insn "*lshrsi_inline"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+new file mode 100644
+index 0000000000..32a3be7c76
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-Os -mno-xl-barrel-shift" } */
++
++void testfunc(void)
++{
++ unsigned volatile int z = 8192;
++ z >>= 8;
++}
++/* { dg-final { scan-assembler-not "\bsrli" } } */
++/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
++/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
++/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
++/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
++/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch
new file mode 100644
index 0000000..00e79b9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch
@@ -0,0 +1,33 @@
+From 1b9bd76840fc1e67770a23c58bf18a24a25eb2b9 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:36 -0700
+Subject: [PATCH] Modified MicroBlaze trap instruction
+
+Modified trap instruction The instruction was wrongly written to brki
+r0,-1 it should be bri r0. Modified with the correct instruction
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index abbe97c15f..a3954a24b6 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2343,7 +2343,7 @@
+ (define_insn "trap"
+ [(trap_if (const_int 1) (const_int 0))]
+ ""
+- "brki\tr0,-1"
++ "bri\t0"
+ [(set_attr "type" "trap")]
+ )
+
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch
new file mode 100644
index 0000000..ead929a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch
@@ -0,0 +1,212 @@
+From f5416ee7ddc6e4853e57ed15fb2bf630de2c3b12 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:37 -0700
+Subject: [PATCH] Reducing Stack space for arguments Currently in Microblaze
+ target stack space
+
+Reducing Stack space for arguments Currently in Microblaze target stack
+space for arguments in register is being allocated even if there are no
+arguments in the function. This patch will optimize the extra 24 bytes
+that are being allocated.
+
+ChangeLog:
+2015-04-17 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New
+ * microblaze.c (REG_PARM_STACK_SPACE): Modify
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze-protos.h | 1 +
+ gcc/config/microblaze/microblaze.c | 134 +++++++++++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.h | 4 +-
+ 3 files changed, 136 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index b56e052ae4..a1408629cc 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
++++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -57,6 +57,7 @@ extern int symbol_mentioned_p (rtx);
+ extern int label_mentioned_p (rtx);
+ extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
+ extern void microblaze_eh_return (rtx op0);
++int microblaze_reg_parm_stack_space(tree fun);
+ #endif /* RTX_CODE */
+
+ /* Declare functions in microblaze-c.c. */
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index c1b0172bcf..f46dffff0d 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -1965,6 +1965,138 @@ microblaze_must_save_register (int regno)
+ return 0;
+ }
+
++static bool
++microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
++{
++ enum machine_mode mode;
++ int unsignedp;
++ rtx entry_parm;
++
++ /* Catch errors. */
++ if (type == NULL || type == error_mark_node)
++ return true;
++
++ if (TREE_CODE (type) == POINTER_TYPE)
++ return true;
++
++ /* Handle types with no storage requirement. */
++ if (TYPE_MODE (type) == VOIDmode)
++ return false;
++
++ /* Handle complex types. */
++ if (TREE_CODE (type) == COMPLEX_TYPE)
++ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
++ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
++
++ /* Handle transparent aggregates. */
++ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
++ && TYPE_TRANSPARENT_AGGR (type))
++ type = TREE_TYPE (first_field (type));
++
++ /* See if this arg was passed by invisible reference. */
++ if (pass_by_reference (get_cumulative_args (args_so_far),
++ TYPE_MODE (type), type, true))
++ type = build_pointer_type (type);
++
++ /* Find mode as it is passed by the ABI. */
++ unsignedp = TYPE_UNSIGNED (type);
++ mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
++
++/* If there is no incoming register, we need a stack. */
++ entry_parm = microblaze_function_arg (args_so_far, mode, type, true);
++ if (entry_parm == NULL)
++ return true;
++
++ /* Likewise if we need to pass both in registers and on the stack. */
++ if (GET_CODE (entry_parm) == PARALLEL
++ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
++ return true;
++
++ /* Also true if we're partially in registers and partially not. */
++ if (function_arg_partial_bytes (args_so_far, mode, type, true) != 0)
++ return true;
++
++ /* Update info on where next arg arrives in registers. */
++ microblaze_function_arg_advance (args_so_far, mode, type, true);
++ return false;
++ }
++
++static bool
++microblaze_function_parms_need_stack (tree fun, bool incoming)
++{
++ tree fntype, result;
++ CUMULATIVE_ARGS args_so_far_v;
++ cumulative_args_t args_so_far;
++ int num_of_args = 0;
++
++ /* Must be a libcall, all of which only use reg parms. */
++ if (!fun)
++ return true;
++
++ fntype = fun;
++ if (!TYPE_P (fun))
++ fntype = TREE_TYPE (fun);
++
++ /* Varargs functions need the parameter save area. */
++ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
++ return true;
++
++ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
++ args_so_far = pack_cumulative_args (&args_so_far_v);
++
++ /* When incoming, we will have been passed the function decl.
++ * It is necessary to use the decl to handle K&R style functions,
++ * where TYPE_ARG_TYPES may not be available. */
++ if (incoming)
++ {
++ gcc_assert (DECL_P (fun));
++ result = DECL_RESULT (fun);
++ }
++ else
++ result = TREE_TYPE (fntype);
++
++ if (result && aggregate_value_p (result, fntype))
++ {
++ if (!TYPE_P (result))
++ result = build_pointer_type (result);
++ microblaze_parm_needs_stack (args_so_far, result);
++ }
++
++ if (incoming)
++ {
++ tree parm;
++ for (parm = DECL_ARGUMENTS (fun);
++ parm && parm != void_list_node;
++ parm = TREE_CHAIN (parm))
++ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
++ return true;
++ }
++ else
++ {
++ function_args_iterator args_iter;
++ tree arg_type;
++
++ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
++ {
++ num_of_args++;
++ if (microblaze_parm_needs_stack (args_so_far, arg_type))
++ return true;
++ }
++ }
++
++ if (num_of_args > 3) return true;
++
++ return false;
++}
++
++int microblaze_reg_parm_stack_space(tree fun)
++{
++ if (microblaze_function_parms_need_stack (fun,false))
++ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
++ else
++ return 0;
++}
++
+ /* Return the bytes needed to compute the frame pointer from the current
+ stack pointer.
+
+@@ -3275,7 +3407,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ emit_insn (gen_indirect_jump (temp2));
+
+ /* Run just enough of rest_of_compilation. This sequence was
+- "borrowed" from rs6000.c. */
++ "borrowed" from microblaze.c. */
+ insn = get_insns ();
+ shorten_branches (insn);
+ final_start_function (insn, file, 1);
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 0dd8b853e2..82e7e890be 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -467,9 +467,9 @@ extern struct microblaze_frame_info current_frame_info;
+
+ #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
+
+-#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
++#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL)
+
+-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
++#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
+
+ #define STACK_BOUNDARY 32
+
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch
new file mode 100644
index 0000000..6de1702
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch
@@ -0,0 +1,64 @@
+From cf85f09a0fade1e7827828a3dc9a526c212f3be7 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:39 -0700
+Subject: [PATCH] Inline Expansion of fsqrt builtin
+
+Inline Expansion of fsqrt builtin. The changes are made in the patch for
+the inline expansion of the fsqrt builtin with fqrt instruction. The
+sqrt math function takes double as argument and return double as
+argument. The pattern is selected while expanding the unary op through
+expand_unop which passes DFmode and the DFmode pattern was not there
+returning zero. Thus the sqrt math function is not inlined and expanded.
+The pattern with DFmode argument is added. Also the source and
+destination argument is not same the DF through two different
+consecutive registers with lower 32 bit is the argument passed to sqrt
+and the higher 32 bit is zero. If the source and destinations are
+different the DFmode 64 bits registers is not set properly giving the
+problem in runtime. Such changes are taken care in the implementation of
+the pattern for DFmode for inline expansion of the sqrt.
+
+ChangeLog:
+
+2015-06-16 Ajit Agarwal <ajitkum@xilinx.com>
+ Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * config/microblaze/microblaze.md (sqrtdf2): New
+ pattern.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index a3954a24b6..13f8803428 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -449,6 +449,20 @@
+ (set_attr "mode" "SF")
+ (set_attr "length" "4")])
+
++(define_insn "sqrtdf2"
++ [(set (match_operand:DF 0 "register_operand" "=d")
++ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
++ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
++ {
++ if (REGNO (operands[0]) == REGNO (operands[1]))
++ return "fsqrt\t%0,%1";
++ else
++ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
++ }
++ [(set_attr "type" "fsqrt")
++ (set_attr "mode" "SF")
++ (set_attr "length" "4")])
++
+ (define_insn "fix_truncsfsi2"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch
new file mode 100644
index 0000000..d8eb769
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch
@@ -0,0 +1,78 @@
+From f269f552e1abf182dc3749e0f29b1529fc82644a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:42 -0700
+Subject: [PATCH] Update MicroBlaze ashlsi3 & movsf patterns
+
+This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in
+print_operand of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and
+movsf_internal patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating
+64-bit value which our instruction doesn't support so using gen_int_mode
+function
+
+ChangeLog:
+
+2016-01-07 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * microblaze.md (ashlsi3_with_mul_nodelay,
+ ashlsi3_with_mul_delay,
+ movsf_internal):
+ Updated the patterns to use gen_int_mode function
+ * microblaze.c (print_operand):
+ updated the 'F' case to use "unsinged int" instead
+ of HOST_WIDE_INT_PRINT_HEX
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ gcc/config/microblaze/microblaze.md | 10 ++++++++--
+ 2 files changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index f46dffff0d..663b20a022 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2507,7 +2507,7 @@ print_operand (FILE * file, rtx op, int letter)
+ unsigned long value_long;
+ REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
+ value_long);
+- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long);
++ fprintf (file, "0x%08x", (unsigned int) value_long);
+ }
+ else
+ {
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 13f8803428..b9c62b6d0f 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1366,7 +1366,10 @@
+ (match_operand:SI 2 "immediate_operand" "I")))]
+ "!TARGET_SOFT_MUL
+ && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
+- "muli\t%0,%1,%m2"
++ {
++ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
++ return "muli\t%0,%1,%2";
++ }
+ ;; This MUL will not generate an imm. Can go into a delay slot.
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+@@ -1378,7 +1381,10 @@
+ (ashift:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "immediate_operand" "I")))]
+ "!TARGET_SOFT_MUL"
+- "muli\t%0,%1,%m2"
++ {
++ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
++ return "muli\t%0,%1,%2";
++ }
+ ;; This MUL will generate an IMM. Cannot go into a delay slot
+ [(set_attr "type" "no_delay_arith")
+ (set_attr "mode" "SI")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch
new file mode 100644
index 0000000..6faa625
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch
@@ -0,0 +1,195 @@
+From 17353cc4ba521f5ad928a1ede61cf03110e366ae Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:43 -0700
+Subject: [PATCH] 8-stage pipeline for microblaze
+
+This patch adds the support for the 8-stage pipeline. The new 8-stage
+pipeline reduces the latencies of float & integer division drastically
+
+ChangeLog:
+
+2016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * microblaze.md (define_automaton mbpipe_8): New
+ * microblaze.c (microblaze_option_override): Update
+ Updated the logic to generate only when MB version is 10.0
+ * microblaze.h (pipeline_type): Update
+ Update the enum with MICROBLAZE_PIPE_8
+ * microblaze.opt (mxl-frequency): New
+ New flag added for 8-stage pipeline
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 13 ++++++
+ gcc/config/microblaze/microblaze.h | 3 +-
+ gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.opt | 4 ++
+ 4 files changed, 96 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 663b20a022..e7697bf30d 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -1773,6 +1773,19 @@ microblaze_option_override (void)
+ warning (0, "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a");
+ TARGET_REORDER = 0;
+ }
++ ver = ver_int - microblaze_version_to_int("v10.0");
++ if (ver < 0)
++ {
++ if (TARGET_AREA_OPTIMIZED_2)
++ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
++ }
++ else
++ {
++ if (TARGET_AREA_OPTIMIZED_2)
++ microblaze_pipe = MICROBLAZE_PIPE_8;
++ if (TARGET_BARREL_SHIFT)
++ microblaze_has_bitfield = 1;
++ }
+
+ if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
+ error ("-mxl-multiply-high requires -mno-xl-soft-mul");
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 82e7e890be..3f48e48f10 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -27,7 +27,8 @@
+ enum pipeline_type
+ {
+ MICROBLAZE_PIPE_3 = 0,
+- MICROBLAZE_PIPE_5 = 1
++ MICROBLAZE_PIPE_5 = 1,
++ MICROBLAZE_PIPE_8 = 2
+ };
+
+ #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index b9c62b6d0f..61d6412dac 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -35,6 +35,7 @@
+ (R_GOT 20) ;; GOT ptr reg
+ (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline
+ (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline
++ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline
+ (UNSPEC_SET_GOT 101) ;;
+ (UNSPEC_GOTOFF 102) ;; GOT offset
+ (UNSPEC_PLT 103) ;; jump table
+@@ -80,7 +81,7 @@
+ ;; bshift Shift operations
+
+ (define_attr "type"
+- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
++ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
+ (const_string "unknown"))
+
+ ;; Main data type used by the insn
+@@ -222,6 +223,80 @@
+ ;;-----------------------------------------------------------------
+
+
++
++;;----------------------------------------------------------------
++;; Microblaze 8-stage pipeline description (v10.0 and later)
++;;----------------------------------------------------------------
++
++(define_automaton "mbpipe_8")
++(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
++
++(define_insn_reservation "mb8-integer" 1
++ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-special-move" 2
++ (and (eq_attr "type" "move")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_iu*2,mb8_wb")
++
++(define_insn_reservation "mb8-mem-load" 3
++ (and (eq_attr "type" "load,no_delay_load")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-mem-store" 1
++ (and (eq_attr "type" "store,no_delay_store")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-mul" 3
++ (and (eq_attr "type" "imul,no_delay_imul")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
++
++(define_insn_reservation "mb8-div" 30
++ (and (eq_attr "type" "idiv")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
++
++(define_insn_reservation "mb8-bs" 2
++ (and (eq_attr "type" "bshift")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-add-sub-mul" 1
++ (and (eq_attr "type" "fadd,frsub,fmul")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fcmp" 3
++ (and (eq_attr "type" "fcmp")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-div" 24
++ (and (eq_attr "type" "fdiv")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-sqrt" 23
++ (and (eq_attr "type" "fsqrt")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fcvt" 1
++ (and (eq_attr "type" "fcvt")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fint" 2
++ (and (eq_attr "type" "fint")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_wb")
++
++
+ ;;----------------------------------------------------------------
+ ;; Microblaze 5-stage pipeline description (v5.00.a and later)
+ ;;----------------------------------------------------------------
+@@ -468,7 +543,7 @@
+ (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+ "fint\t%0,%1"
+- [(set_attr "type" "fcvt")
++ [(set_attr "type" "fint")
+ (set_attr "mode" "SF")
+ (set_attr "length" "4")])
+
+diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
+index 8847c3daf8..85a9929d74 100644
+--- a/gcc/config/microblaze/microblaze.opt
++++ b/gcc/config/microblaze/microblaze.opt
+@@ -129,3 +129,7 @@ Use hardware prefetch instruction
+
+ mxl-mode-xilkernel
+ Target
++
++mxl-frequency
++Target Mask(AREA_OPTIMIZED_2)
++Use 8 stage pipeline (frequency optimization)
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch
new file mode 100644
index 0000000..ff8e610
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch
@@ -0,0 +1,72 @@
+From fabd23a354496701b4a9ebf6931485b0d61c7bbe Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:45 -0700
+Subject: [PATCH] MicroBlaze correct the const high double immediate value
+
+With this patch the loading of the DI mode immediate values will be
+using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
+functions, as CONST_DOUBLE_HIGH was returning the sign extension value
+even of the unsigned long long constants also
+
+ChangeLog:
+
+2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE &
+ REAL_VALUE_TO_TARGET_DOUBLE
+ * long.c (new): Added new testcase
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 6 ++++--
+ gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++
+ 2 files changed, 14 insertions(+), 2 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index e7697bf30d..96bf6e1cab 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2493,14 +2493,16 @@ print_operand (FILE * file, rtx op, int letter)
+ else if (letter == 'h' || letter == 'j')
+ {
+ long val[2];
++ long l[2];
+ if (code == CONST_DOUBLE)
+ {
+ if (GET_MODE (op) == DFmode)
+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
+ else
+ {
+- val[0] = CONST_DOUBLE_HIGH (op);
+- val[1] = CONST_DOUBLE_LOW (op);
++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
++ val[1] = l[WORDS_BIG_ENDIAN == 0];
++ val[0] = l[WORDS_BIG_ENDIAN != 0];
+ }
+ }
+ else if (code == CONST_INT)
+diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c
+new file mode 100644
+index 0000000000..4d4518619d
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/long.c
+@@ -0,0 +1,10 @@
++/* { dg-options "-O0" } */
++#define BASEADDR 0xF0000000ULL
++int main ()
++{
++ unsigned long long start;
++ start = (unsigned long long) BASEADDR;
++ return 0;
++}
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch
new file mode 100644
index 0000000..7ea28ee
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch
@@ -0,0 +1,42 @@
+From 2149d85f1f7375dd97bf961b2bdb693d6d931c13 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:46 -0700
+Subject: [PATCH] Fix internal compiler error with msmall-divides
+
+This patch will fix the internal error microblaze_expand_divide function
+which comes because of rtx PLUS where the mem_rtx is of type SI and the
+operand is of type QImode. This patch modifies the mem_rtx as QImode and
+Plus as QImode to fix the error.
+
+ChangeLog:
+
+2016-02-23 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * microblaze.c (microblaze_expand_divide): Update
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 96bf6e1cab..a41121264e 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3719,7 +3719,7 @@ microblaze_expand_divide (rtx operands[])
+ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
+ emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
+ mem_rtx = gen_rtx_MEM (QImode,
+- gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
++ gen_rtx_PLUS (QImode, regt1, div_table_rtx));
+
+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+ jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch
new file mode 100644
index 0000000..97422ae
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch
@@ -0,0 +1,48 @@
+From 34049c9fcaa256befad032cbcd8aa74beecf13dc Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:47 -0700
+Subject: [PATCH] Fix the calculation of high word in a long long 64-bit
+
+This patch will change the calculation of high word in a long long 64-bit.
+Earlier to this patch the high word of long long word (0xF0000000ULL) is
+coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
+should be 0x00000000 and the low word should be 0xF0000000. This patch
+removes the condition of checking high word = 0 & low word < 0.
+This check is not required for the correctness of calculating 32-bit high
+and low words in a 64-bit long long.
+
+ChangeLog:
+
+2016-03-01 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * config/microblaze/microblaze.c (print_operand): Remove the
+ condition of checking high word = 0 & low word < 0.
+ * testsuite/gcc.target/microblaze/others/long.c: Add -O0 option.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index a41121264e..2ed64971fb 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2509,9 +2509,6 @@ print_operand (FILE * file, rtx op, int letter)
+ {
+ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
+ val[1] = INTVAL (op) & 0x00000000ffffffffLL;
+- if (val[0] == 0 && val[1] < 0)
+- val[0] = -1;
+-
+ }
+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
+ }
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch
new file mode 100644
index 0000000..02940e2
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch
@@ -0,0 +1,126 @@
+From 90b6f833bd59f89d4192a3dc787fc2c9115b9c00 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:48 -0700
+Subject: [PATCH] Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions. BSEFI- The
+instruction shall extract a bit field from a register and place it
+right-adjusted in the destination register. The other bits in the
+destination register shall be set to zero BSIFI- The instruction shall
+insert a right-adjusted bit field from a register at another position in
+the destination register. The rest of the bits in the destination
+register shall be unchanged
+
+ChangeLog:
+
+2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * microblaze.md (Update): Added new patterns
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 61d6412dac..7a00629922 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -980,6 +980,8 @@
+ (set_attr "mode" "DI")
+ (set_attr "length" "20,20,20")])
+
++
++
+ ;;----------------------------------------------------------------
+ ;; Data movement
+ ;;----------------------------------------------------------------
+@@ -1774,6 +1776,7 @@
+ (set_attr "length" "28")]
+ )
+
++
+ ;;----------------------------------------------------------------
+ ;; Setting a register from an integer comparison.
+ ;;----------------------------------------------------------------
+@@ -2473,4 +2476,74 @@
+ DONE;
+ }")
+
++(define_expand "extvsi"
++ [(set (match_operand:SI 0 "register_operand" "r")
++ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++ (match_operand:SI 2 "immediate_operand" "I")
++ (match_operand:SI 3 "immediate_operand" "I")))]
++"TARGET_HAS_BITFIELD"
++"
++{
++ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
++
++ if ((len == 0) || (pos + len > 32) )
++ FAIL;
++
++ ;;if (!register_operand (operands[1], VOIDmode))
++ ;; FAIL;
++ if (operands[0] == operands[1])
++ FAIL;
++ if (GET_CODE (operands[1]) == ASHIFT)
++ FAIL;
++;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
++ emit_insn (gen_extv_32 (operands[0], operands[1],
++ operands[2], operands[3]));
++ DONE;
++}")
++
++(define_insn "extv_32"
++ [(set (match_operand:SI 0 "register_operand" "=r")
++ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++ (match_operand:SI 2 "immediate_operand" "I")
++ (match_operand:SI 3 "immediate_operand" "I")))]
++ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
++ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
++ "bsefi %0,%1,%2,%3"
++ [(set_attr "type" "bshift")
++ (set_attr "length" "4")])
++
++(define_expand "insvsi"
++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++ (match_operand:SI 1 "immediate_operand" "I")
++ (match_operand:SI 2 "immediate_operand" "I"))
++ (match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_HAS_BITFIELD"
++ "
++{
++ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
++
++ if (len <= 0 || pos + len > 32)
++ FAIL;
++
++ ;;if (!register_operand (operands[0], VOIDmode))
++ ;; FAIL;
++
++ emit_insn (gen_insv_32 (operands[0], operands[1],
++ operands[2], operands[3]));
++ DONE;
++}")
++
++(define_insn "insv_32"
++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++ (match_operand:SI 1 "immediate_operand" "I")
++ (match_operand:SI 2 "immediate_operand" "I"))
++ (match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
++ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
++ "bsifi %0, %3, %1, %2"
++ [(set_attr "type" "bshift")
++ (set_attr "length" "4")])
++
+ (include "sync.md")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch
new file mode 100644
index 0000000..c3e4bc9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch
@@ -0,0 +1,250 @@
+From 3eada9d81437d378ef24f11a8bd046fee5b3505a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:49 -0700
+Subject: [PATCH] Fix bug in MB version calculation
+
+This patch fixes the bug in microblaze_version_to_int function. Earlier
+the conversion of vXX.YY.Z to int has a bug which is fixed now.
+
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 147 ++++++++++++++++++-------------------
+ 1 file changed, 70 insertions(+), 77 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 2ed64971fb..55dba83882 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -239,6 +239,63 @@ section *sdata2_section;
+ #define TARGET_HAVE_TLS true
+ #endif
+
++/* Convert a version number of the form "vX.YY.Z" to an integer encoding
++ for easier range comparison. */
++static int
++microblaze_version_to_int (const char *version)
++{
++ const char *p, *v;
++ const char *tmpl = "vXX.YY.Z";
++ int iver1 =0, iver2 =0, iver3 =0;
++
++ p = version;
++ v = tmpl;
++
++ while (*p)
++ {
++ if (*v == 'X')
++ { /* Looking for major */
++ if (*p == '.')
++ {
++ *v++;
++ }
++ else
++ {
++ if (!(*p >= '0' && *p <= '9'))
++ return -1;
++ iver1 += (int) (*p - '0');
++ iver1 *= 1000;
++ }
++ }
++ else if (*v == 'Y')
++ { /* Looking for minor */
++ if (!(*p >= '0' && *p <= '9'))
++ return -1;
++ iver2 += (int) (*p - '0');
++ iver2 *= 10;
++ }
++ else if (*v == 'Z')
++ { /* Looking for compat */
++ if (!(*p >= 'a' && *p <= 'z'))
++ return -1;
++ iver3 = ((int) (*p)) - 96;
++ }
++ else
++ {
++ if (*p != *v)
++ return -1;
++ }
++
++ v++;
++ p++;
++ }
++
++ if (*p)
++ return -1;
++
++ return iver1 + iver2 + iver3;
++}
++
+ /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
+ static bool
+ microblaze_const_double_ok (rtx op, machine_mode mode)
+@@ -1267,8 +1324,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+ {
+ if (TARGET_BARREL_SHIFT)
+ {
+- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
+- >= 0)
++ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (2);
+@@ -1329,8 +1385,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+ }
+ else if (!TARGET_SOFT_MUL)
+ {
+- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
+- >= 0)
++ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (3);
+@@ -1610,72 +1665,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
+ return 0;
+ }
+
+-/* Convert a version number of the form "vX.YY.Z" to an integer encoding
+- for easier range comparison. */
+-static int
+-microblaze_version_to_int (const char *version)
+-{
+- const char *p, *v;
+- const char *tmpl = "vXX.YY.Z";
+- int iver = 0;
+-
+- p = version;
+- v = tmpl;
+-
+- while (*p)
+- {
+- if (*v == 'X')
+- { /* Looking for major */
+- if (*p == '.')
+- {
+- v++;
+- }
+- else
+- {
+- if (!(*p >= '0' && *p <= '9'))
+- return -1;
+- iver += (int) (*p - '0');
+- iver *= 10;
+- }
+- }
+- else if (*v == 'Y')
+- { /* Looking for minor */
+- if (!(*p >= '0' && *p <= '9'))
+- return -1;
+- iver += (int) (*p - '0');
+- iver *= 10;
+- }
+- else if (*v == 'Z')
+- { /* Looking for compat */
+- if (!(*p >= 'a' && *p <= 'z'))
+- return -1;
+- iver *= 10;
+- iver += (int) (*p - 'a');
+- }
+- else
+- {
+- if (*p != *v)
+- return -1;
+- }
+-
+- v++;
+- p++;
+- }
+-
+- if (*p)
+- return -1;
+-
+- return iver;
+-}
+-
+-
+ static void
+ microblaze_option_override (void)
+ {
+ register int i, start;
+ register int regno;
+ register machine_mode mode;
+- int ver;
++ int ver,ver_int;
+
+ microblaze_section_threshold = (global_options_set.x_g_switch_value
+ ? g_switch_value
+@@ -1696,13 +1692,13 @@ microblaze_option_override (void)
+ /* Check the MicroBlaze CPU version for any special action to be done. */
+ if (microblaze_select_cpu == NULL)
+ microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
+- ver = microblaze_version_to_int (microblaze_select_cpu);
+- if (ver == -1)
++ ver_int = microblaze_version_to_int (microblaze_select_cpu);
++ if (ver_int == -1)
+ {
+ error ("%qs is an invalid argument to -mcpu=", microblaze_select_cpu);
+ }
+
+- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
++ ver = ver_int - microblaze_version_to_int("v3.00.a");
+ if (ver < 0)
+ {
+ /* No hardware exceptions in earlier versions. So no worries. */
+@@ -1713,8 +1709,7 @@ microblaze_option_override (void)
+ microblaze_pipe = MICROBLAZE_PIPE_3;
+ }
+ else if (ver == 0
+- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
+- == 0))
++ || (ver_int == microblaze_version_to_int("v4.00.b")))
+ {
+ #if 0
+ microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
+@@ -1731,11 +1726,9 @@ microblaze_option_override (void)
+ #endif
+ microblaze_no_unsafe_delay = 0;
+ microblaze_pipe = MICROBLAZE_PIPE_5;
+- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
+- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
+- "v5.00.b") == 0
+- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
+- "v5.00.c") == 0)
++ if ((ver_int == microblaze_version_to_int("v5.00.a"))
++ || (ver_int == microblaze_version_to_int("v5.00.b"))
++ || (ver_int == microblaze_version_to_int("v5.00.c")))
+ {
+ /* Pattern compares are to be turned on by default only when
+ compiling for MB v5.00.'z'. */
+@@ -1743,7 +1736,7 @@ microblaze_option_override (void)
+ }
+ }
+
+- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
++ ver = ver_int - microblaze_version_to_int("v6.00.a");
+ if (ver < 0)
+ {
+ if (TARGET_MULTIPLY_HIGH)
+@@ -1751,7 +1744,7 @@ microblaze_option_override (void)
+ "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater");
+ }
+
+- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
++ ver = ver_int - microblaze_version_to_int("v8.10.a");
+ microblaze_has_clz = 1;
+ if (ver < 0)
+ {
+@@ -1760,7 +1753,7 @@ microblaze_option_override (void)
+ }
+
+ /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */
+- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
++ ver = ver_int - microblaze_version_to_int("v8.30.a");
+ if (ver < 0)
+ {
+ if (TARGET_REORDER == 1)
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch
new file mode 100644
index 0000000..1d877be
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch
@@ -0,0 +1,52 @@
+From 0c740ddd203433ef8d979348c085269f8b97cbfc Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:50 -0700
+Subject: [PATCH] MicroBlaze fixing the bug in the bit-field instruction.
+
+Bit field instruction should be generated only if mcpu >10.0
+
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 3 +++
+ gcc/config/microblaze/microblaze.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 55dba83882..4f6d399bba 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -159,6 +159,9 @@ int microblaze_no_unsafe_delay;
+ /* Set to one if the targeted core has the CLZ insn. */
+ int microblaze_has_clz = 0;
+
++/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
++int microblaze_has_bitfield = 0;
++
+ /* Which CPU pipeline do we use. We haven't really standardized on a CPU
+ version having only a particular type of pipeline. There can still be
+ options on the CPU to scale pipeline features up or down. :(
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 3f48e48f10..712525f856 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
+
+ extern int microblaze_no_unsafe_delay;
+ extern int microblaze_has_clz;
++extern int microblaze_has_bitfield;
+ extern enum pipeline_type microblaze_pipe;
+
+ #define OBJECT_FORMAT_ELF
+@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
+
+ /* Do we have CLZ? */
+ #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
++#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
+
+ /* The default is to support PIC. */
+ #define TARGET_SUPPORTS_PIC 1
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch
new file mode 100644
index 0000000..3786a71
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch
@@ -0,0 +1,48 @@
+From fdb99f97b41f7cd06b81e668b88463d0fc2cbe87 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:54 -0700
+Subject: [PATCH] Fixing the issue with MicroBlaze builtin_alloc
+
+Fixing the issue with the builtin_alloc. Register r18 was not properly
+handling the stack pattern which was resolved by using free available
+register
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 7a00629922..68c3b22bd4 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2076,10 +2076,10 @@
+ ""
+ {
+ rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
+- rtx rtmp = gen_rtx_REG (SImode, R_TMP);
++ rtx reg = gen_reg_rtx (Pmode);
+ rtx neg_op0;
+
+- emit_move_insn (rtmp, retaddr);
++ emit_move_insn (reg, retaddr);
+ if (GET_CODE (operands[1]) != CONST_INT)
+ {
+ neg_op0 = gen_reg_rtx (Pmode);
+@@ -2088,9 +2088,9 @@
+ neg_op0 = GEN_INT (- INTVAL (operands[1]));
+
+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
+- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
++ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
+ emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
+- emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
++ emit_insn (gen_rtx_CLOBBER (SImode, reg));
+ DONE;
+ }
+ )
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch
new file mode 100644
index 0000000..29bc752
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch
@@ -0,0 +1,83 @@
+From 646fe1dbaca06f2fe2df4c0da3fa20e0aff0a4ec Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:56 -0700
+Subject: [PATCH] MicroBlaze remove bitfield instructions macros
+
+Remove the conditions in the bit field expand macros to generate the
+instructions in structure bit-field usecases
+
+ChangeLog:
+
+2018-08-16 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.md:
+ remove the expand constraints
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 40 +++++--------------------------------
+ 1 file changed, 5 insertions(+), 35 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 68c3b22bd4..ef53c3069e 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2482,25 +2482,8 @@
+ (match_operand:SI 2 "immediate_operand" "I")
+ (match_operand:SI 3 "immediate_operand" "I")))]
+ "TARGET_HAS_BITFIELD"
+-"
+-{
+- unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
+- unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
+-
+- if ((len == 0) || (pos + len > 32) )
+- FAIL;
+-
+- ;;if (!register_operand (operands[1], VOIDmode))
+- ;; FAIL;
+- if (operands[0] == operands[1])
+- FAIL;
+- if (GET_CODE (operands[1]) == ASHIFT)
+- FAIL;
+-;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
+- emit_insn (gen_extv_32 (operands[0], operands[1],
+- operands[2], operands[3]));
+- DONE;
+-}")
++""
++)
+
+ (define_insn "extv_32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -2518,22 +2501,9 @@
+ (match_operand:SI 1 "immediate_operand" "I")
+ (match_operand:SI 2 "immediate_operand" "I"))
+ (match_operand:SI 3 "register_operand" "r"))]
+- "TARGET_HAS_BITFIELD"
+- "
+-{
+- unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
+- unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
+-
+- if (len <= 0 || pos + len > 32)
+- FAIL;
+-
+- ;;if (!register_operand (operands[0], VOIDmode))
+- ;; FAIL;
+-
+- emit_insn (gen_insv_32 (operands[0], operands[1],
+- operands[2], operands[3]));
+- DONE;
+-}")
++"TARGET_HAS_BITFIELD"
++""
++)
+
+ (define_insn "insv_32"
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch
new file mode 100644
index 0000000..eaae566
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch
@@ -0,0 +1,51 @@
+From e2a7a582945d24ede55393462a3360f377f45478 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan@nathanrossi.com>
+Date: Sun, 5 Nov 2017 23:03:54 +1000
+Subject: [PATCH] MicroBlaze fix signed bit fields with bit field instructions
+
+The 'extv' definition is expected to sign extended the result based on
+the width of the bit field.
+
+ https://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html#index-extvm-instruction-pattern
+
+The MicroBlaze 'bsefi' instruction does not sign extended, it zero
+extends. There is no option for the instruction to sign extended the
+result and no simple instruction or expression to implement a variant
+length sign extend (only sext8/sext16 instructions exist).
+
+As such these definitions needs to be changed to the zero extended
+variant of 'extv' which is 'extzv'. This change updates the existing
+definitions to allow for signed bit fields to function correctly and be
+sign extended.
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index ef53c3069e..b52be42d6e 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2476,7 +2476,7 @@
+ DONE;
+ }")
+
+-(define_expand "extvsi"
++(define_expand "extzvsi"
+ [(set (match_operand:SI 0 "register_operand" "r")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "immediate_operand" "I")
+@@ -2485,7 +2485,7 @@
+ ""
+ )
+
+-(define_insn "extv_32"
++(define_insn "extzv_32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "immediate_operand" "I")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend
new file mode 100644
index 0000000..9770af6
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend
@@ -0,0 +1,38 @@
+# Add MicroBlaze Patches (only when using MicroBlaze)
+FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-7:"
+SRC_URI_append_microblaze = " \
+ file://0001-Revert.patch \
+ file://0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch \
+ file://0003-PR-target-83013.patch \
+ file://0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch \
+ file://0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch \
+ file://0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch \
+ file://0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch \
+ file://0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch \
+ file://0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch \
+ file://0010-Fix-atomic-side-effects.patch \
+ file://0011-Fix-atomic-boolean-return-value.patch \
+ file://0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch \
+ file://0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch \
+ file://0014-Removed-MicroBlaze-moddi3-routinue.patch \
+ file://0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch \
+ file://0016-MicroBlaze-use-bralid-for-profiler-calls.patch \
+ file://0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch \
+ file://0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch \
+ file://0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch \
+ file://0020-Modified-MicroBlaze-trap-instruction.patch \
+ file://0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch \
+ file://0022-Inline-Expansion-of-fsqrt-builtin.patch \
+ file://0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch \
+ file://0024-8-stage-pipeline-for-microblaze.patch \
+ file://0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch \
+ file://0026-Fix-internal-compiler-error-with-msmall-divides.patch \
+ file://0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch \
+ file://0028-Add-new-bit-field-instructions.patch \
+ file://0029-Fix-bug-in-MB-version-calculation.patch \
+ file://0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch \
+ file://0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch \
+ file://0032-MicroBlaze-remove-bitfield-instructions-macros.patch \
+ file://0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch
new file mode 100644
index 0000000..3575cd7
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch
@@ -0,0 +1,69 @@
+From 8ab9a20c73acedbb636a41842a681872af8ae1d6 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 8 May 2013 11:03:36 +1000
+Subject: [PATCH 01/16] [Patch, microblaze]: Add wdc.ext.clear and
+ wdc.ext.flush insns
+
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ opcodes/microblaze-opc.h | 5 ++++-
+ opcodes/microblaze-opcm.h | 6 +++---
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index e3cc1d9..f453097 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+
+ /* New Mask for msrset, msrclr insns. */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+ {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+ {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 6868389..8f5c1cb 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -31,9 +31,9 @@ enum microblaze_instr
+ idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+ ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar,
++ br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned,
++ blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+ bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0003-Patch-microblaze-Initial-port-of-microblaze-core-rea.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0003-Patch-microblaze-Initial-port-of-microblaze-core-rea.patch
new file mode 100644
index 0000000..5d85640
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0003-Patch-microblaze-Initial-port-of-microblaze-core-rea.patch
@@ -0,0 +1,384 @@
+From da27c7161c676550f5fe8a4e0f7f395e5e0d4770 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 18 May 2012 11:49:50 +1000
+Subject: [PATCH 03/16] [Patch, microblaze]: Initial port of microblaze core
+ reading support
+
+Added support for reading notes in linux core dumps
+Support for reading of PRSTATUS and PSINFO information for rebuilding
+".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
+Upstream-Status: Pending
+---
+ bfd/elf32-microblaze.c | 64 ++++++++++++++++++++++++++++++++
+ gdb/configure.tgt | 2 +-
+ gdb/microblaze-linux-tdep.c | 61 +++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.c | 89 +++++++++++++++++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.h | 28 ++++++++++++++
+ 5 files changed, 243 insertions(+), 1 deletion(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 9837b18..cbd18f0 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -668,6 +668,67 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+ return _bfd_elf_is_local_label_name (abfd, name);
+ }
+
++/* Support for core dump NOTE sections. */
++static bfd_boolean
++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
++{
++ int offset;
++ unsigned int size;
++
++ switch (note->descsz)
++ {
++ default:
++ return FALSE;
++
++ case 228: /* Linux/MicroBlaze */
++ /* pr_cursig */
++ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
++
++ /* pr_pid */
++ elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
++
++ /* pr_reg */
++ offset = 72;
++ size = 50 * 4;
++
++ break;
++ }
++
++ /* Make a ".reg/999" section. */
++ return _bfd_elfcore_make_pseudosection (abfd, ".reg",
++ size, note->descpos + offset);
++}
++
++static bfd_boolean
++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
++{
++ switch (note->descsz)
++ {
++ default:
++ return FALSE;
++
++ case 128: /* Linux/MicroBlaze elf_prpsinfo */
++ elf_tdata (abfd)->core->program
++ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
++ elf_tdata (abfd)->core->command
++ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
++ }
++
++ /* Note that for some reason, a spurious space is tacked
++ onto the end of the args in some (at least one anyway)
++ implementations, so strip it off if it exists. */
++
++ {
++ char *command = elf_tdata (abfd)->core->command;
++ int n = strlen (command);
++
++ if (0 < n && command[n - 1] == ' ')
++ command[n - 1] = '\0';
++ }
++
++ return TRUE;
++}
++
+ /* The microblaze linker (like many others) needs to keep track of
+ the number of relocs that it decides to copy as dynamic relocs in
+ check_relocs for each symbol. This is so that it can later discard
+@@ -3506,4 +3567,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook
+
++#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus
++#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo
++
+ #include "elf32-target.h"
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 01311b2..9297c56 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -340,7 +340,7 @@ mep-*-*)
+
+ microblaze*-linux-*|microblaze*-*-linux*)
+ # Target: Xilinx MicroBlaze running Linux
+- gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o \
++ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o glibc-tdep.o \
+ monitor.o dsrec.o solib-svr4.o symfile-mem.o linux-tdep.o"
+ gdb_sim=../sim/microblaze/libsim.a
+ ;;
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 8d360eb..7e6b61b 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -32,6 +32,7 @@
+ #include "regset.h"
+ #include "solib-svr4.h"
+ #include "microblaze-tdep.h"
++#include "glibc-tdep.h"
+ #include "trad-frame.h"
+ #include "frame-unwind.h"
+ #include "tramp-frame.h"
+@@ -116,6 +117,43 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
+ microblaze_linux_sighandler_cache_init
+ };
+
++const struct microblaze_gregset microblaze_linux_core_gregset;
++
++static void
++microblaze_linux_supply_core_gregset (const struct regset *regset,
++ struct regcache *regcache,
++ int regnum, const void *gregs, size_t len)
++{
++ microblaze_supply_gregset (µblaze_linux_core_gregset, regcache,
++ regnum, gregs);
++}
++
++static void
++microblaze_linux_collect_core_gregset (const struct regset *regset,
++ const struct regcache *regcache,
++ int regnum, void *gregs, size_t len)
++{
++ microblaze_collect_gregset (µblaze_linux_core_gregset, regcache,
++ regnum, gregs);
++}
++
++static void
++microblaze_linux_supply_core_fpregset (const struct regset *regset,
++ struct regcache *regcache,
++ int regnum, const void *fpregs, size_t len)
++{
++ /* FIXME. */
++ microblaze_supply_fpregset (regcache, regnum, fpregs);
++}
++
++static void
++microblaze_linux_collect_core_fpregset (const struct regset *regset,
++ const struct regcache *regcache,
++ int regnum, void *fpregs, size_t len)
++{
++ /* FIXME. */
++ microblaze_collect_fpregset (regcache, regnum, fpregs);
++}
+
+ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+@@ -123,6 +161,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ {
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
++ tdep->gregset = regset_alloc (gdbarch, microblaze_linux_supply_core_gregset,
++ microblaze_linux_collect_core_gregset);
++ tdep->sizeof_gregset = 200;
++
+ linux_init_abi (info, gdbarch);
+
+ set_gdbarch_memory_remove_breakpoint (gdbarch,
+@@ -135,6 +177,25 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ /* Trampolines. */
+ tramp_frame_prepend_unwinder (gdbarch,
+ µblaze_linux_sighandler_tramp_frame);
++
++ /* BFD target for core files. */
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++ else
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++ /* Shared library handling. */
++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
++ set_gdbarch_regset_from_core_section (gdbarch,
++ microblaze_regset_from_core_section);
++
++ /* Enable TLS support. */
++ set_gdbarch_fetch_tls_load_module_address (gdbarch,
++ svr4_fetch_objfile_link_map);
++
+ }
+
+ /* -Wmissing-prototypes */
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 14c1b52..36cf1ca 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -145,6 +145,14 @@ microblaze_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
+ return sp;
+ }
+
++static CORE_ADDR
++microblaze_store_arguments (struct regcache *regcache, int nargs,
++ struct value **args, CORE_ADDR sp,
++ int struct_return, CORE_ADDR struct_addr)
++{
++ error (_("store_arguments not implemented"));
++ return sp;
++}
+
+ static CORE_ADDR
+ microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+@@ -536,6 +544,12 @@ microblaze_frame_base_address (struct frame_info *next_frame,
+ return cache->base;
+ }
+
++static const struct frame_unwind *
++microblaze_frame_sniffer (struct frame_info *next_frame)
++{
++ return µblaze_frame_unwind;
++}
++
+ static const struct frame_base microblaze_frame_base =
+ {
+ µblaze_frame_unwind,
+@@ -664,6 +678,70 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ return dwarf2_to_reg_map[reg];
+ }
+
++
++void
++microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++ struct regcache *regcache,
++ int regnum, const void *gregs)
++{
++ unsigned int *regs = gregs;
++ if (regnum >= 0)
++ regcache_raw_supply (regcache, regnum, regs + regnum);
++
++ if (regnum == -1) {
++ int i;
++
++ for (i = 0; i < 50; i++) {
++ regcache_raw_supply (regcache, i, regs + i);
++ }
++ }
++}
++
++
++void
++microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++ const struct regcache *regcache,
++ int regnum, void *gregs)
++{
++ /* FIXME. */
++}
++
++void
++microblaze_supply_fpregset (struct regcache *regcache,
++ int regnum, const void *fpregs)
++{
++ /* FIXME. */
++}
++
++void
++microblaze_collect_fpregset (const struct regcache *regcache,
++ int regnum, void *fpregs)
++{
++ /* FIXME. */
++}
++
++
++/* Return the appropriate register set for the core section identified
++ by SECT_NAME and SECT_SIZE. */
++
++const struct regset *
++microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++ const char *sect_name, size_t sect_size)
++{
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++ microblaze_debug ("microblaze_regset_from_core_section, sect_name = %s\n", sect_name);
++
++ if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
++ return tdep->gregset;
++
++ if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
++ return tdep->fpregset;
++
++ microblaze_debug ("microblaze_regset_from_core_section returning null :-( \n");
++ return NULL;
++}
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -679,6 +757,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ tdep = XNEW (struct gdbarch_tdep);
+ gdbarch = gdbarch_alloc (&info, tdep);
+
++ tdep->gregset = NULL;
++ tdep->sizeof_gregset = 0;
++ tdep->fpregset = NULL;
++ tdep->sizeof_fpregset = 0;
++
+ set_gdbarch_long_double_bit (gdbarch, 128);
+
+ set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
+@@ -726,6 +809,12 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ frame_unwind_append_unwinder (gdbarch, µblaze_frame_unwind);
+ frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
+
++ /* If we have register sets, enable the generic core file support. */
++ if (tdep->gregset) {
++ set_gdbarch_regset_from_core_section (gdbarch,
++ microblaze_regset_from_core_section);
++ }
++
+ return gdbarch;
+ }
+
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index a532092..fec24b9 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -22,8 +22,22 @@
+
+
+ /* Microblaze architecture-specific information. */
++struct microblaze_gregset
++{
++ unsigned int gregs[32];
++ unsigned int fpregs[32];
++ unsigned int pregs[16];
++};
++
+ struct gdbarch_tdep
+ {
++ int dummy; // declare something.
++
++ /* Register sets. */
++ struct regset *gregset;
++ size_t sizeof_gregset;
++ struct regset *fpregset;
++ size_t sizeof_fpregset;
+ };
+
+ struct microblaze_frame_cache
+@@ -117,4 +131,18 @@ enum microblaze_regnum
+ Only used for native debugging. */
+ #define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
+
++extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++ struct regcache *regcache,
++ int regnum, const void *gregs);
++extern void microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++ const struct regcache *regcache,
++ int regnum, void *gregs);
++extern void microblaze_supply_fpregset (struct regcache *regcache,
++ int regnum, const void *fpregs);
++extern void microblaze_collect_fpregset (const struct regcache *regcache,
++ int regnum, void *fpregs);
++
++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++ const char *sect_name, size_t sect_size);
++
+ #endif /* microblaze-tdep.h */
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0004-Patch-microblaze-Communicate-in-larger-blocks-with-t.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0004-Patch-microblaze-Communicate-in-larger-blocks-with-t.patch
new file mode 100644
index 0000000..b14e409
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0004-Patch-microblaze-Communicate-in-larger-blocks-with-t.patch
@@ -0,0 +1,67 @@
+From 26e124f0d78233b1d976bd4b787f6a7866bcb7e7 Mon Sep 17 00:00:00 2001
+From: nagaraju <nmekala@xilix.com>
+Date: Wed, 4 Jan 2012 16:59:33 +0530
+Subject: [PATCH 04/16] [Patch, microblaze]: Communicate in larger blocks with
+ the target
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c | 25 ++++++++++++++++++++++---
+ 1 file changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 36cf1ca..76e87b3 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -242,6 +242,10 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ int flags = 0;
+ int save_hidden_pointer_found = 0;
+ int non_stack_instruction_found = 0;
++ int n_insns;
++ unsigned long *insn_block;
++ gdb_byte *buf_block;
++ int ti, tj;
+
+ /* Find the start of this function. */
+ find_pc_partial_function (pc, &name, &func_addr, &func_end);
+@@ -281,9 +285,23 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ name, paddress (gdbarch, func_addr),
+ paddress (gdbarch, stop));
+
++/* Do a block read to minimize the transaction with the Debug Agent */
++ n_insns = (stop == func_addr) ? 1 : ((stop - func_addr) / INST_WORD_SIZE);
++ insn_block = (unsigned long *)calloc(n_insns, sizeof(unsigned long));
++ buf_block = (gdb_byte *)calloc(n_insns * INST_WORD_SIZE, sizeof(gdb_byte));
++
++ target_read_memory (func_addr, buf_block, n_insns * INST_WORD_SIZE );
++
++ for(ti = 0; ti < n_insns; ti++){
++ insn_block[ti] = 0;
++ for( tj = ti * INST_WORD_SIZE; tj < (ti + 1) * INST_WORD_SIZE; tj++ )
++ insn_block[ti] = (insn_block[ti] << 8) | buf_block[tj];
++ }
++
+ for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
+ {
+- insn = microblaze_fetch_instruction (addr);
++ //insn = microblaze_fetch_instruction (addr);
++ insn = insn_block[(addr - func_addr) / INST_WORD_SIZE];
+ op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
+ microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn);
+
+@@ -409,8 +427,9 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ part of the prologue. */
+ if (save_hidden_pointer_found)
+ prologue_end_addr -= INST_WORD_SIZE;
+-
+- return prologue_end_addr;
++ free(insn_block);
++ free(buf_block);
++ return prologue_end_addr;
+ }
+
+ static CORE_ADDR
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0005-Patch-microblaze-Add-mb-singlestepping.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0005-Patch-microblaze-Add-mb-singlestepping.patch
new file mode 100644
index 0000000..e490f02
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0005-Patch-microblaze-Add-mb-singlestepping.patch
@@ -0,0 +1,200 @@
+From 5c3a08f407e1cbee5b0a4ca6092165b97acddda5 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar@axis.com>
+Date: Fri, 24 Feb 2012 11:52:30 +0100
+Subject: [PATCH 05/16] [Patch, microblaze]: Add mb singlestepping.
+
+Fix prologue analysis for little-endian.
+Always provide a frame base.
+
+Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c | 123 ++++++++++++++++++++++++++++++++++++++++++++------
+ 1 file changed, 108 insertions(+), 15 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 76e87b3..50b68d2 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -243,9 +243,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ int save_hidden_pointer_found = 0;
+ int non_stack_instruction_found = 0;
+ int n_insns;
+- unsigned long *insn_block;
+- gdb_byte *buf_block;
+- int ti, tj;
++ unsigned int *insn_block;
+
+ /* Find the start of this function. */
+ find_pc_partial_function (pc, &name, &func_addr, &func_end);
+@@ -287,23 +285,16 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+
+ /* Do a block read to minimize the transaction with the Debug Agent */
+ n_insns = (stop == func_addr) ? 1 : ((stop - func_addr) / INST_WORD_SIZE);
+- insn_block = (unsigned long *)calloc(n_insns, sizeof(unsigned long));
+- buf_block = (gdb_byte *)calloc(n_insns * INST_WORD_SIZE, sizeof(gdb_byte));
++ insn_block = calloc(n_insns, sizeof(unsigned long));
+
+- target_read_memory (func_addr, buf_block, n_insns * INST_WORD_SIZE );
+-
+- for(ti = 0; ti < n_insns; ti++){
+- insn_block[ti] = 0;
+- for( tj = ti * INST_WORD_SIZE; tj < (ti + 1) * INST_WORD_SIZE; tj++ )
+- insn_block[ti] = (insn_block[ti] << 8) | buf_block[tj];
+- }
++ target_read_memory (func_addr, (void*) insn_block, n_insns * INST_WORD_SIZE );
+
+ for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
+ {
+ //insn = microblaze_fetch_instruction (addr);
+ insn = insn_block[(addr - func_addr) / INST_WORD_SIZE];
+ op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
+- microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn);
++ microblaze_debug ("%s %08lx op=%x r%d r%d imm=%d\n", paddress (gdbarch, addr), insn, op, rd, ra, imm);
+
+ /* This code is very sensitive to what functions are present in the
+ prologue. It assumes that the (addi, addik, swi, sw) can be the
+@@ -428,7 +419,6 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ if (save_hidden_pointer_found)
+ prologue_end_addr -= INST_WORD_SIZE;
+ free(insn_block);
+- free(buf_block);
+ return prologue_end_addr;
+ }
+
+@@ -502,6 +492,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+
+ func = get_frame_func (next_frame);
+
++ cache->base = get_frame_register_unsigned (next_frame, gdbarch_sp_regnum (gdbarch));
+ cache->pc = get_frame_address_in_block (next_frame);
+
+ return cache;
+@@ -518,7 +509,7 @@ microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache,
+ if (cache->base == 0)
+ return;
+
+- (*this_id) = frame_id_build (cache->base, cache->pc);
++ (*this_id) = frame_id_build (cache->base, get_frame_pc (next_frame));
+ }
+
+ static struct value *
+@@ -661,6 +652,107 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
+ return (TYPE_LENGTH (type) == 16);
+ }
+
++int
++microblaze_software_single_step (struct frame_info *frame)
++{
++ struct gdbarch *arch = get_frame_arch (frame);
++ struct address_space *aspace = get_frame_address_space (frame);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++ static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
++ static char be_breakp[] = MICROBLAZE_BREAKPOINT;
++ enum bfd_endian byte_order = gdbarch_byte_order (arch);
++ char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
++ int ret = 0;
++
++ /* Save the address and the values of the next_pc and the target */
++ static struct sstep_breaks
++ {
++ CORE_ADDR address;
++ bfd_boolean valid;
++ /* Shadow contents. */
++ char data[INST_WORD_SIZE];
++ } stepbreaks[2];
++ int ii;
++
++ if (1)
++ {
++ CORE_ADDR pc;
++ long insn;
++ enum microblaze_instr minstr;
++ bfd_boolean isunsignednum;
++ enum microblaze_instr_type insn_type;
++ short delay_slots;
++ int imm;
++ bfd_boolean immfound = FALSE;
++
++ /* Set a breakpoint at the next instruction */
++ /* If the current instruction is an imm, set it at the inst after */
++ /* If the instruction has a delay slot, skip the delay slot */
++ pc = get_frame_pc (frame);
++ insn = microblaze_fetch_instruction (pc);
++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++ if (insn_type == immediate_inst)
++ {
++ int rd, ra, rb;
++ immfound = TRUE;
++ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
++ pc = pc + INST_WORD_SIZE;
++ insn = microblaze_fetch_instruction (pc);
++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++ }
++ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
++ if (insn_type != return_inst) {
++ stepbreaks[0].valid = TRUE;
++ } else {
++ stepbreaks[0].valid = FALSE;
++ }
++
++ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
++ /* Now check for branch or return instructions */
++ if (insn_type == branch_inst || insn_type == return_inst) {
++ int limm;
++ int lrd, lra, lrb;
++ int ra, rb;
++ bfd_boolean targetvalid;
++ bfd_boolean unconditionalbranch;
++ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
++ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
++ ra = get_frame_register_unsigned (frame, lra);
++ else
++ ra = 0;
++ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
++ rb = get_frame_register_unsigned (frame, lrb);
++ else
++ rb = 0;
++ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++ if (unconditionalbranch)
++ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
++ if (targetvalid && (stepbreaks[0].valid == FALSE ||
++ (stepbreaks[0].address != stepbreaks[1].address))
++ && (stepbreaks[1].address != pc)) {
++ stepbreaks[1].valid = TRUE;
++ } else {
++ stepbreaks[1].valid = FALSE;
++ }
++ } else {
++ stepbreaks[1].valid = FALSE;
++ }
++
++ /* Insert the breakpoints */
++ for (ii = 0; ii < 2; ++ii)
++ {
++
++ /* ignore invalid breakpoint. */
++ if (stepbreaks[ii].valid) {
++ insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
++ ret = 1;
++ }
++ }
++ }
++ return ret;
++}
++
+ static void
+ microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
+ {
+@@ -809,6 +901,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+
+ set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc);
++ set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+
+ set_gdbarch_frame_args_skip (gdbarch, 8);
+
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0006-Patch-microblaze-Add-initial-port-of-linux-gdbserver.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0006-Patch-microblaze-Add-initial-port-of-linux-gdbserver.patch
new file mode 100644
index 0000000..cb2eec1
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0006-Patch-microblaze-Add-initial-port-of-linux-gdbserver.patch
@@ -0,0 +1,553 @@
+From 2112c9ded01ddd08f0e31e5ce23eecac6c04e8c4 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Mon, 6 Feb 2012 10:28:29 +1000
+Subject: [PATCH 06/16] [Patch, microblaze]: Add initial port of linux
+ gdbserver
+
+add gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * gdb/configure.tgt: Set build_gdbserver=yes
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Upstream-Status: Pending
+---
+ gdb/configure.host | 3 +
+ gdb/configure.tgt | 1 +
+ gdb/gdbserver/Makefile.in | 4 +
+ gdb/gdbserver/configure.srv | 6 +
+ gdb/gdbserver/linux-microblaze-low.c | 228 +++++++++++++++++++++++++++++++++++
+ gdb/microblaze-linux-tdep.c | 25 +++-
+ gdb/microblaze-tdep.c | 45 ++++++-
+ gdb/microblaze-tdep.h | 3 +-
+ gdb/regformats/reg-microblaze.dat | 39 ++++++
+ 9 files changed, 348 insertions(+), 6 deletions(-)
+ create mode 100644 gdb/gdbserver/linux-microblaze-low.c
+ create mode 100644 gdb/regformats/reg-microblaze.dat
+
+diff --git a/gdb/configure.host b/gdb/configure.host
+index 15a8288..76cc5fe 100644
+--- a/gdb/configure.host
++++ b/gdb/configure.host
+@@ -59,6 +59,7 @@ i[34567]86*) gdb_host_cpu=i386 ;;
+ m68*) gdb_host_cpu=m68k ;;
+ m88*) gdb_host_cpu=m88k ;;
+ mips*) gdb_host_cpu=mips ;;
++microblaze*) gdb_host_cpu=microblaze ;;
+ powerpc* | rs6000) gdb_host_cpu=powerpc ;;
+ sparcv9 | sparc64) gdb_host_cpu=sparc ;;
+ s390*) gdb_host_cpu=s390 ;;
+@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
+ gdb_host=nbsd ;;
+ mips64*-*-openbsd*) gdb_host=obsd64 ;;
+
++microblaze*-*linux*) gdb_host=linux ;;
++
+ powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*)
+ gdb_host=aix ;;
+ powerpc*-*-freebsd*) gdb_host=fbsd ;;
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 9297c56..3a7951a 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -343,6 +343,7 @@ microblaze*-linux-*|microblaze*-*-linux*)
+ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o glibc-tdep.o \
+ monitor.o dsrec.o solib-svr4.o symfile-mem.o linux-tdep.o"
+ gdb_sim=../sim/microblaze/libsim.a
++ build_gdbserver=yes
+ ;;
+ microblaze*-*-*)
+ # Target: Xilinx MicroBlaze running standalone
+diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
+index f773fa2..a11ace1 100644
+--- a/gdb/gdbserver/Makefile.in
++++ b/gdb/gdbserver/Makefile.in
+@@ -148,6 +148,7 @@ SFILES= $(srcdir)/gdbreplay.c $(srcdir)/inferiors.c $(srcdir)/dll.c \
+ $(srcdir)/linux-ia64-low.c $(srcdir)/linux-low.c \
+ $(srcdir)/linux-m32r-low.c \
+ $(srcdir)/linux-m68k-low.c $(srcdir)/linux-mips-low.c \
++ $(srcdir)/linux-microblaze-low.c \
+ $(srcdir)/linux-nios2-low.c \
+ $(srcdir)/linux-ppc-low.c \
+ $(srcdir)/linux-s390-low.c \
+@@ -329,6 +330,7 @@ clean:
+ rm -f arm-with-iwmmxt.c
+ rm -f arm-with-vfpv2.c arm-with-vfpv3.c arm-with-neon.c
+ rm -f mips-linux.c mips64-linux.c
++ rm -f microblaze-linux.c
+ rm -f nios2-linux.c
+ rm -f powerpc-32.c powerpc-32l.c powerpc-64l.c powerpc-e500l.c
+ rm -f powerpc-altivec32l.c powerpc-cell32l.c powerpc-vsx32l.c
+@@ -612,6 +614,8 @@ reg-m68k.c : $(srcdir)/../regformats/reg-m68k.dat $(regdat_sh)
+ $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-m68k.dat reg-m68k.c
+ reg-cf.c : $(srcdir)/../regformats/reg-cf.dat $(regdat_sh)
+ $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-cf.dat reg-cf.c
++microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
++ $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
+ mips-linux.c : $(srcdir)/../regformats/mips-linux.dat $(regdat_sh)
+ $(SHELL) $(regdat_sh) $(srcdir)/../regformats/mips-linux.dat mips-linux.c
+ mips-dsp-linux.c : $(srcdir)/../regformats/mips-dsp-linux.dat $(regdat_sh)
+diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
+index cc4f53d..359c756 100644
+--- a/gdb/gdbserver/configure.srv
++++ b/gdb/gdbserver/configure.srv
+@@ -198,6 +198,12 @@ case "${target}" in
+ srv_linux_usrregs=yes
+ srv_linux_thread_db=yes
+ ;;
++ microblaze*-*-linux*) srv_regobj=microblaze-linux.o
++ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o"
++ srv_linux_usrregs=yes
++ srv_linux_regsets=yes
++ srv_linux_thread_db=yes
++ ;;
+ nios2*-*-linux*) srv_regobj="nios2-linux.o"
+ srv_tgtobj="$srv_linux_obj linux-nios2-low.o"
+ srv_xmlfiles="nios2-linux.xml"
+diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
+new file mode 100644
+index 0000000..279df9f
+--- /dev/null
++++ b/gdb/gdbserver/linux-microblaze-low.c
+@@ -0,0 +1,228 @@
++/* GNU/Linux/Microblaze specific low level interface, for the remote server for
++ GDB.
++ Copyright (C) 1995-2013 Free Software Foundation, Inc.
++
++ This file is part of GDB.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include "server.h"
++#include "linux-low.h"
++
++#include <asm/ptrace.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++#include "gdb_proc_service.h"
++
++static int microblaze_regmap[] =
++ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3),
++ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7),
++ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11),
++ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15),
++ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19),
++ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23),
++ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27),
++ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31),
++ PT_PC, PT_MSR, PT_EAR, PT_ESR,
++ PT_FSR
++ };
++
++#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++
++/* Defined in auto-generated file microblaze-linux.c. */
++void init_registers_microblaze (void);
++extern const struct target_desc *tdesc_microblaze;
++
++static int
++microblaze_cannot_store_register (int regno)
++{
++ if (microblaze_regmap[regno] == -1 || regno == 0)
++ return 1;
++
++ return 0;
++}
++
++static int
++microblaze_cannot_fetch_register (int regno)
++{
++ return 0;
++}
++
++static CORE_ADDR
++microblaze_get_pc (struct regcache *regcache)
++{
++ unsigned long pc;
++
++ collect_register_by_name (regcache, "pc", &pc);
++ return (CORE_ADDR) pc;
++}
++
++static void
++microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++ unsigned long newpc = pc;
++
++ supply_register_by_name (regcache, "pc", &newpc);
++}
++
++/* dbtrap insn */
++/* brki r16, 0x18; */
++static const unsigned long microblaze_breakpoint = 0xba0c0018;
++#define microblaze_breakpoint_len 4
++
++static int
++microblaze_breakpoint_at (CORE_ADDR where)
++{
++ unsigned long insn;
++
++ (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
++ if (insn == microblaze_breakpoint)
++ return 1;
++ /* If necessary, recognize more trap instructions here. GDB only uses the
++ one. */
++ return 0;
++}
++
++static CORE_ADDR
++microblaze_reinsert_addr (struct regcache *regcache)
++{
++ unsigned long pc;
++ collect_register_by_name (regcache, "r15", &pc);
++ return pc;
++}
++
++#ifdef HAVE_PTRACE_GETREGS
++
++static void
++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
++{
++ int size = register_size (regcache->tdesc, regno);
++
++ memset (buf, 0, sizeof (long));
++
++ if (size < sizeof (long))
++ collect_register (regcache, regno, buf + sizeof (long) - size);
++ else
++ collect_register (regcache, regno, buf);
++}
++
++static void
++microblaze_supply_ptrace_register (struct regcache *regcache,
++ int regno, const char *buf)
++{
++ int size = register_size (regcache->tdesc, regno);
++
++ if (regno == 0) {
++ unsigned long regbuf_0 = 0;
++ /* clobbering r0 so that it is always 0 as enforced by hardware */
++ supply_register (regcache, regno, (const char*)®buf_0);
++ } else {
++ if (size < sizeof (long))
++ supply_register (regcache, regno, buf + sizeof (long) - size);
++ else
++ supply_register (regcache, regno, buf);
++ }
++}
++
++/* Provide only a fill function for the general register set. ps_lgetregs
++ will use this for NPTL support. */
++
++static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
++{
++ int i;
++
++ for (i = 0; i < 32; i++)
++ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++static void
++microblaze_store_gregset (struct regcache *regcache, const void *buf)
++{
++ int i;
++
++ for (i = 0; i < 32; i++)
++ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++#endif /* HAVE_PTRACE_GETREGS */
++
++static struct regset_info microblaze_regsets[] = {
++#ifdef HAVE_PTRACE_GETREGS
++ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
++ { 0, 0, 0, -1, -1, NULL, NULL },
++#endif /* HAVE_PTRACE_GETREGS */
++ { 0, 0, 0, -1, -1, NULL, NULL }
++};
++
++static struct regsets_info microblaze_regsets_info =
++ {
++ microblaze_regsets, /* regsets */
++ 0, /* num_regsets */
++ NULL, /* disabled_regsets */
++ };
++
++static struct usrregs_info microblaze_usrregs_info =
++ {
++ microblaze_num_regs,
++ microblaze_regmap,
++ };
++
++static struct regs_info regs_info =
++ {
++ NULL, /* regset_bitmap */
++ µblaze_usrregs_info,
++ µblaze_regsets_info
++ };
++
++static const struct regs_info *
++microblaze_regs_info (void)
++{
++ return ®s_info;
++}
++
++static void
++microblaze_arch_setup (void)
++{
++ current_process ()->tdesc = tdesc_microblaze;
++}
++
++struct linux_target_ops the_low_target = {
++ microblaze_arch_setup,
++ microblaze_regs_info,
++ microblaze_cannot_fetch_register,
++ microblaze_cannot_store_register,
++ NULL, /* fetch_register */
++ microblaze_get_pc,
++ microblaze_set_pc,
++ (const unsigned char *) µblaze_breakpoint,
++ microblaze_breakpoint_len,
++ microblaze_reinsert_addr,
++ 0,
++ microblaze_breakpoint_at,
++ NULL,
++ NULL,
++ NULL,
++ NULL,
++ microblaze_collect_ptrace_register,
++ microblaze_supply_ptrace_register,
++};
++
++void
++initialize_low_arch (void)
++{
++ init_registers_microblaze ();
++
++ initialize_regsets_info (µblaze_regsets_info);
++}
+\ No newline at end of file
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 7e6b61b..cf58e21 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -38,6 +38,22 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+
++static int microblaze_debug_flag = 0;
++
++static void
++microblaze_debug (const char *fmt, ...)
++{
++ if (microblaze_debug_flag)
++ {
++ va_list args;
++
++ va_start (args, fmt);
++ printf_unfiltered ("MICROBLAZE LINUX: ");
++ vprintf_unfiltered (fmt, args);
++ va_end (args);
++ }
++}
++
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+@@ -47,20 +63,27 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ int val;
+ int bplen;
+ gdb_byte old_contents[BREAKPOINT_MAX];
++ struct cleanup *cleanup;
+
+ /* Determine appropriate breakpoint contents and size for this address. */
+ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+ if (bp == NULL)
+ error (_("Software breakpoints not implemented for this target."));
+
++ /* Make sure we see the memory breakpoints. */
++ cleanup = make_show_memory_breakpoints_cleanup (1);
+ val = target_read_memory (addr, old_contents, bplen);
+
+ /* If our breakpoint is no longer at the address, this means that the
+ program modified the code on us, so it is wrong to put back the
+ old value. */
+ if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ {
++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++ }
+
++ do_cleanups (cleanup);
+ return val;
+ }
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 50b68d2..1c6dbfe 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -164,6 +164,39 @@ microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+ return sp;
+ }
+
++static int
++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
++ struct bp_target_info *bp_tgt)
++{
++ CORE_ADDR addr = bp_tgt->placed_address;
++ const unsigned char *bp;
++ int val;
++ int bplen;
++ gdb_byte old_contents[BREAKPOINT_MAX];
++ struct cleanup *cleanup;
++
++ /* Determine appropriate breakpoint contents and size for this address. */
++ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
++ if (bp == NULL)
++ error (_("Software breakpoints not implemented for this target."));
++
++ /* Make sure we see the memory breakpoints. */
++ cleanup = make_show_memory_breakpoints_cleanup (1);
++ val = target_read_memory (addr, old_contents, bplen);
++
++ /* If our breakpoint is no longer at the address, this means that the
++ program modified the code on us, so it is wrong to put back the
++ old value. */
++ if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
++ {
++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++ }
++
++ do_cleanups (cleanup);
++ return val;
++}
++
+ static const gdb_byte *
+ microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc,
+ int *len)
+@@ -291,8 +324,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+
+ for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
+ {
+- //insn = microblaze_fetch_instruction (addr);
+- insn = insn_block[(addr - func_addr) / INST_WORD_SIZE];
++ insn = microblaze_fetch_instruction (addr);
++ //insn = insn_block[(addr - func_addr) / INST_WORD_SIZE];
+ op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
+ microblaze_debug ("%s %08lx op=%x r%d r%d imm=%d\n", paddress (gdbarch, addr), insn, op, rd, ra, imm);
+
+@@ -724,13 +757,15 @@ microblaze_software_single_step (struct frame_info *frame)
+ rb = get_frame_register_unsigned (frame, lrb);
+ else
+ rb = 0;
++
+ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
+- microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++
+ if (unconditionalbranch)
+ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
+ if (targetvalid && (stepbreaks[0].valid == FALSE ||
+ (stepbreaks[0].address != stepbreaks[1].address))
+- && (stepbreaks[1].address != pc)) {
++ && (stepbreaks[1].address != pc)) {
+ stepbreaks[1].valid = TRUE;
+ } else {
+ stepbreaks[1].valid = FALSE;
+@@ -900,6 +935,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ /* Stack grows downward. */
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+
++ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++
+ set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc);
+ set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index fec24b9..98aa0f5 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -129,7 +129,8 @@ enum microblaze_regnum
+
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+ Only used for native debugging. */
+-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+
+ extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset,
+ struct regcache *regcache,
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+new file mode 100644
+index 0000000..a5dd0a0
+--- /dev/null
++++ b/gdb/regformats/reg-microblaze.dat
+@@ -0,0 +1,39 @@
++name:microblaze
++expedite:r1,pc
++32:r0
++32:r1
++32:r2
++32:r3
++32:r4
++32:r5
++32:r6
++32:r7
++32:r8
++32:r9
++32:r10
++32:r11
++32:r12
++32:r13
++32:r14
++32:r15
++32:r16
++32:r17
++32:r18
++32:r19
++32:r20
++32:r21
++32:r22
++32:r23
++32:r24
++32:r25
++32:r26
++32:r27
++32:r28
++32:r29
++32:r30
++32:r31
++32:pc
++32:msr
++32:ear
++32:esr
++32:fsr
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0007-Patch-microblaze-Add-slr-and-shr-regs-and-little-end.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0007-Patch-microblaze-Add-slr-and-shr-regs-and-little-end.patch
new file mode 100644
index 0000000..7cd1190
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0007-Patch-microblaze-Add-slr-and-shr-regs-and-little-end.patch
@@ -0,0 +1,82 @@
+From fb2af2fffb673dbb14d743c8da94c4a83b71c792 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 26 Nov 2012 17:39:17 +1000
+Subject: [PATCH 07/16] [Patch, microblaze]: Add slr and shr regs and
+ little-endian breakpoint
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c | 10 ++++++++--
+ gdb/microblaze-tdep.h | 6 ++++--
+ gdb/regformats/reg-microblaze.dat | 2 ++
+ 3 files changed, 14 insertions(+), 4 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 1c6dbfe..0ce4947 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -73,7 +73,8 @@ static const char *microblaze_register_names[] =
+ "rpc", "rmsr", "rear", "resr", "rfsr", "rbtr",
+ "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+ "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+- "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi"
++ "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
++ "rslr", "rshr"
+ };
+
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+@@ -201,10 +202,15 @@ static const gdb_byte *
+ microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc,
+ int *len)
+ {
++ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ static gdb_byte break_insn[] = MICROBLAZE_BREAKPOINT;
++ static gdb_byte break_insn_le[] = MICROBLAZE_BREAKPOINT_LE;
+
+ *len = sizeof (break_insn);
+- return break_insn;
++ if (byte_order == BFD_ENDIAN_BIG)
++ return break_insn;
++ else
++ return break_insn_le;
+ }
+
+ /* Allocate and initialize a frame cache. */
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 98aa0f5..cd32e9f 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -56,7 +56,7 @@ struct microblaze_frame_cache
+ int fp_regnum;
+
+ /* Offsets to saved registers. */
+- int register_offsets[57]; /* Must match MICROBLAZE_NUM_REGS. */
++ int register_offsets[59]; /* Must match MICROBLAZE_NUM_REGS. */
+
+ /* Table of saved registers. */
+ struct trad_frame_saved_reg *saved_regs;
+@@ -121,7 +121,9 @@ enum microblaze_regnum
+ MICROBLAZE_RTLBX_REGNUM,
+ MICROBLAZE_RTLBSX_REGNUM,
+ MICROBLAZE_RTLBLO_REGNUM,
+- MICROBLAZE_RTLBHI_REGNUM
++ MICROBLAZE_RTLBHI_REGNUM,
++ MICROBLAZE_SLR_REGNUM,
++ MICROBLAZE_SHR_REGNUM
+ };
+
+ /* All registers are 32 bits. */
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+index a5dd0a0..bd8a438 100644
+--- a/gdb/regformats/reg-microblaze.dat
++++ b/gdb/regformats/reg-microblaze.dat
+@@ -37,3 +37,5 @@ expedite:r1,pc
+ 32:ear
+ 32:esr
+ 32:fsr
++32:slr
++32:shr
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0008-Patch-microblaze-Added-Backtrace-support-to-GDB.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0008-Patch-microblaze-Added-Backtrace-support-to-GDB.patch
new file mode 100644
index 0000000..7f075d5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0008-Patch-microblaze-Added-Backtrace-support-to-GDB.patch
@@ -0,0 +1,156 @@
+From 7944750e435100e72913f01aa0a43b7d7cffd421 Mon Sep 17 00:00:00 2001
+From: nagaraju <nmekala@xilix.com>
+Date: Tue, 3 Sep 2013 12:09:47 +0530
+Subject: [PATCH 08/16] [Patch, microblaze]: Added Backtrace support to GDB
+
+Added backtrace support without debugging information.
+
+Earlier backtrace used to work only when debug information is available.
+Previous pc & sp values are calculated incorrectly due to which backtrace
+was failing.
+
+In this patch, previous frame sp & pc values are calculated correctly
+in microblaze_frame_cache function and supplied them to
+microblaze_frame_prev_register function
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c | 42 ++++++++++++++++++++++++++++++++++--------
+ gdb/microblaze-tdep.h | 5 +++--
+ 2 files changed, 37 insertions(+), 10 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 0ce4947..247740e 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -225,6 +225,7 @@ microblaze_alloc_frame_cache (void)
+ /* Base address. */
+ cache->base = 0;
+ cache->pc = 0;
++ cache->saved_sp = 0;
+
+ /* Frameless until proven otherwise. */
+ cache->frameless_p = 1;
+@@ -347,6 +348,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ cache->frameless_p = 0; /* Frame found. */
+ save_hidden_pointer_found = 0;
+ non_stack_instruction_found = 0;
++ cache->register_offsets[rd] = -imm;
+ continue;
+ }
+ else if (IS_SPILL_SP(op, rd, ra))
+@@ -508,6 +510,7 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
+ return start_pc;
+ }
+
++enum { REG_UNAVAIL = (CORE_ADDR) -1 };
+ /* Normal frames. */
+
+ static struct microblaze_frame_cache *
+@@ -515,7 +518,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+ {
+ struct microblaze_frame_cache *cache;
+ struct gdbarch *gdbarch = get_frame_arch (next_frame);
+- CORE_ADDR func;
++ CORE_ADDR current_pc;
+ int rn;
+
+ if (*this_cache)
+@@ -529,10 +532,18 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+ for (rn = 0; rn < gdbarch_num_regs (gdbarch); rn++)
+ cache->register_offsets[rn] = -1;
+
+- func = get_frame_func (next_frame);
++ cache->pc = get_frame_func (next_frame);
++ current_pc = get_frame_pc (next_frame);
++
++ if (cache->pc)
++ microblaze_analyze_prologue (gdbarch, cache->pc, current_pc,
++ cache);
+
+ cache->base = get_frame_register_unsigned (next_frame, gdbarch_sp_regnum (gdbarch));
+- cache->pc = get_frame_address_in_block (next_frame);
++ cache->saved_sp = cache->base + cache->framesize;
++
++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM] = cache->base;
++ cache->register_offsets[MICROBLAZE_SP_REGNUM] = cache->saved_sp;
+
+ return cache;
+ }
+@@ -548,7 +559,7 @@ microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache,
+ if (cache->base == 0)
+ return;
+
+- (*this_id) = frame_id_build (cache->base, get_frame_pc (next_frame));
++ (*this_id) = frame_id_build (cache->base, cache->pc);
+ }
+
+ static struct value *
+@@ -558,6 +569,14 @@ microblaze_frame_prev_register (struct frame_info *this_frame,
+ struct microblaze_frame_cache *cache =
+ microblaze_frame_cache (this_frame, this_cache);
+
++ if ((regnum == MICROBLAZE_SP_REGNUM &&
++ cache->register_offsets[MICROBLAZE_SP_REGNUM])
++ || (regnum == MICROBLAZE_FP_REGNUM &&
++ cache->register_offsets[MICROBLAZE_SP_REGNUM]))
++
++ return frame_unwind_got_constant (this_frame, regnum,
++ cache->register_offsets[MICROBLAZE_SP_REGNUM]);
++
+ if (cache->frameless_p)
+ {
+ if (regnum == MICROBLAZE_PC_REGNUM)
+@@ -565,11 +584,18 @@ microblaze_frame_prev_register (struct frame_info *this_frame,
+ if (regnum == MICROBLAZE_SP_REGNUM)
+ regnum = 1;
+ return trad_frame_get_prev_register (this_frame,
+- cache->saved_regs, regnum);
++ cache->saved_regs, regnum);
+ }
+- else
+- return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+- regnum);
++
++ if (regnum == MICROBLAZE_PC_REGNUM)
++ {
++ regnum = 15;
++ return frame_unwind_got_memory (this_frame, regnum,
++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]);
++ }
++
++ return trad_frame_get_prev_register (this_frame, cache->saved_regs,
++ regnum);
+
+ }
+
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index cd32e9f..14eb3ab 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -57,6 +57,7 @@ struct microblaze_frame_cache
+
+ /* Offsets to saved registers. */
+ int register_offsets[59]; /* Must match MICROBLAZE_NUM_REGS. */
++ CORE_ADDR saved_sp;
+
+ /* Table of saved registers. */
+ struct trad_frame_saved_reg *saved_regs;
+@@ -80,11 +81,11 @@ enum microblaze_regnum
+ MICROBLAZE_R12_REGNUM,
+ MICROBLAZE_R13_REGNUM,
+ MICROBLAZE_R14_REGNUM,
+- MICROBLAZE_R15_REGNUM,
++ MICROBLAZE_R15_REGNUM, MICROBLAZE_PREV_PC_REGNUM = MICROBLAZE_R15_REGNUM,
+ MICROBLAZE_R16_REGNUM,
+ MICROBLAZE_R17_REGNUM,
+ MICROBLAZE_R18_REGNUM,
+- MICROBLAZE_R19_REGNUM,
++ MICROBLAZE_R19_REGNUM, MICROBLAZE_FP_REGNUM = MICROBLAZE_R19_REGNUM,
+ MICROBLAZE_R20_REGNUM,
+ MICROBLAZE_R21_REGNUM,
+ MICROBLAZE_R22_REGNUM,
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0009-Patch-microblaze-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0009-Patch-microblaze-Initial-support-for-native-gdb.patch
new file mode 100644
index 0000000..1ad6b89
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0009-Patch-microblaze-Initial-support-for-native-gdb.patch
@@ -0,0 +1,495 @@
+From c7b918283f2e438deef78aae84f6b748a7a1bb54 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 20 Jul 2012 15:18:35 +1000
+Subject: [PATCH 09/16] [Patch, microblaze]: Initial support for native gdb
+
+microblaze: Follow PPC method of getting setting registers
+using PTRACE PEEK/POKE
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Upstream-Status: Pending
+---
+ gdb/Makefile.in | 4 +-
+ gdb/config/microblaze/linux.mh | 10 +
+ gdb/microblaze-linux-nat.c | 431 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 443 insertions(+), 2 deletions(-)
+ create mode 100644 gdb/config/microblaze/linux.mh
+ create mode 100644 gdb/microblaze-linux-nat.c
+
+diff --git a/gdb/Makefile.in b/gdb/Makefile.in
+index f2c16ec..12870a4 100644
+--- a/gdb/Makefile.in
++++ b/gdb/Makefile.in
+@@ -904,7 +904,7 @@ top.h bsd-kvm.h gdb-stabs.h reggroups.h \
+ annotate.h sim-regno.h dictionary.h dfp.h main.h frame-unwind.h \
+ remote-fileio.h i386-linux-tdep.h vax-tdep.h objc-lang.h \
+ sentinel-frame.h bcache.h symfile.h windows-tdep.h linux-tdep.h \
+-gdb_usleep.h jit.h xml-syscall.h microblaze-tdep.h \
++gdb_usleep.h jit.h xml-syscall.h microblaze-tdep.h microblaze-linux-tdep.h \
+ psymtab.h psympriv.h progspace.h bfin-tdep.h ia64-hpux-tdep.h \
+ amd64-darwin-tdep.h charset-list.h \
+ config/djgpp/langinfo.h config/djgpp/nl_types.h darwin-nat.h \
+@@ -1631,7 +1631,7 @@ ALLDEPFILES = \
+ m68kbsd-nat.c m68kbsd-tdep.c \
+ m68klinux-nat.c m68klinux-tdep.c \
+ m88k-tdep.c m88kbsd-nat.c \
+- microblaze-tdep.c microblaze-linux-tdep.c \
++ microblaze-tdep.c microblaze-linux-nat.c microblaze-linux-tdep.c \
+ mingw-hdep.c \
+ mips-linux-nat.c mips-linux-tdep.c \
+ mips-irix-tdep.c \
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+new file mode 100644
+index 0000000..547d103
+--- /dev/null
++++ b/gdb/config/microblaze/linux.mh
+@@ -0,0 +1,10 @@
++# Host: Microblaze, running Linux
++
++NAT_FILE= config/nm-linux.h
++NATDEPFILES= inf-ptrace.o fork-child.o \
++ microblaze-linux-nat.o proc-service.o linux-thread-db.o \
++ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \
++ linux-waitpid.o
++NAT_CDEPS = $(srcdir)/proc-service.list
++
++LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+new file mode 100644
+index 0000000..81f8346
+--- /dev/null
++++ b/gdb/microblaze-linux-nat.c
+@@ -0,0 +1,431 @@
++/* Microblaze GNU/Linux native support.
++
++ Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
++ Software Foundation, Inc.
++
++ This file is part of GDB.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include "defs.h"
++#include "arch-utils.h"
++#include "dis-asm.h"
++#include "frame.h"
++#include "trad-frame.h"
++#include "symtab.h"
++#include "value.h"
++#include "gdbcmd.h"
++#include "breakpoint.h"
++#include "inferior.h"
++#include "regcache.h"
++#include "target.h"
++#include "frame.h"
++#include "frame-base.h"
++#include "frame-unwind.h"
++#include "dwarf2-frame.h"
++#include "osabi.h"
++
++#include "gdb_assert.h"
++#include <string.h>
++#include "target-descriptions.h"
++#include "opcodes/microblaze-opcm.h"
++#include "opcodes/microblaze-dis.h"
++
++#include "linux-nat.h"
++#include "target-descriptions.h"
++
++#include <sys/user.h>
++#include <sys/utsname.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++/* Prototypes for supply_gregset etc. */
++#include "gregset.h"
++
++#include "microblaze-tdep.h"
++
++#include <elf/common.h>
++#include "auxv.h"
++
++/* Defines ps_err_e, struct ps_prochandle. */
++#include "gdb_proc_service.h"
++
++/* On GNU/Linux, threads are implemented as pseudo-processes, in which
++ case we may be tracing more than one process at a time. In that
++ case, inferior_ptid will contain the main process ID and the
++ individual thread (process) ID. get_thread_id () is used to get
++ the thread id if it's available, and the process id otherwise. */
++
++int
++get_thread_id (ptid_t ptid)
++{
++ int tid = ptid_get_lwp (ptid);
++ if (0 == tid)
++ tid = ptid_get_pid (ptid);
++ return tid;
++}
++
++#define GET_THREAD_ID(PTID) get_thread_id (PTID)
++
++/* Non-zero if our kernel may support the PTRACE_GETREGS and
++ PTRACE_SETREGS requests, for reading and writing the
++ general-purpose registers. Zero if we've tried one of
++ them and gotten an error. */
++int have_ptrace_getsetregs = 1;
++
++static int
++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
++{
++ int u_addr = -1;
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
++ interface, and not the wordsize of the program's ABI. */
++ int wordsize = sizeof (long);
++
++ /* General purpose registers occupy 1 slot each in the buffer. */
++ if (regno >= MICROBLAZE_R0_REGNUM
++ && regno <= MICROBLAZE_FSR_REGNUM)
++ u_addr = (regno * wordsize);
++
++ return u_addr;
++}
++
++
++static void
++fetch_register (struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* This isn't really an address. But ptrace thinks of it as one. */
++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++ int bytes_transferred;
++ unsigned int offset; /* Offset of registers within the u area. */
++ char buf[MAX_REGISTER_SIZE];
++
++ if (regaddr == -1)
++ {
++ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
++ regcache_raw_supply (regcache, regno, buf);
++ return;
++ }
++
++ /* Read the raw register using sizeof(long) sized chunks. On a
++ 32-bit platform, 64-bit floating-point registers will require two
++ transfers. */
++ for (bytes_transferred = 0;
++ bytes_transferred < register_size (gdbarch, regno);
++ bytes_transferred += sizeof (long))
++ {
++ long l;
++
++ errno = 0;
++ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
++ regaddr += sizeof (long);
++ if (errno != 0)
++ {
++ char message[128];
++ sprintf (message, "reading register %s (#%d)",
++ gdbarch_register_name (gdbarch, regno), regno);
++ perror_with_name (message);
++ }
++ memcpy (&buf[bytes_transferred], &l, sizeof (l));
++ }
++
++ /* Now supply the register. Keep in mind that the regcache's idea
++ of the register's size may not be a multiple of sizeof
++ (long). */
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++ {
++ /* Little-endian values are always found at the left end of the
++ bytes transferred. */
++ regcache_raw_supply (regcache, regno, buf);
++ }
++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ {
++ /* Big-endian values are found at the right end of the bytes
++ transferred. */
++ size_t padding = (bytes_transferred - register_size (gdbarch, regno));
++ regcache_raw_supply (regcache, regno, buf + padding);
++ }
++ else
++ internal_error (__FILE__, __LINE__,
++ _("fetch_register: unexpected byte order: %d"),
++ gdbarch_byte_order (gdbarch));
++}
++
++/* This function actually issues the request to ptrace, telling
++ it to get all general-purpose registers and put them into the
++ specified regset.
++
++ If the ptrace request does not exist, this function returns 0
++ and properly sets the have_ptrace_* flag. If the request fails,
++ this function calls perror_with_name. Otherwise, if the request
++ succeeds, then the regcache gets filled and 1 is returned. */
++static int
++fetch_all_gp_regs (struct regcache *regcache, int tid)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ gdb_gregset_t gregset;
++
++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't get general-purpose registers."));
++ }
++
++ supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
++
++ return 1;
++}
++
++
++/* This is a wrapper for the fetch_all_gp_regs function. It is
++ responsible for verifying if this target has the ptrace request
++ that can be used to fetch all general-purpose registers at one
++ shot. If it doesn't, then we should fetch them using the
++ old-fashioned way, which is to iterate over the registers and
++ request them one by one. */
++static void
++fetch_gp_regs (struct regcache *regcache, int tid)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ int i;
++
++ if (have_ptrace_getsetregs)
++ if (fetch_all_gp_regs (regcache, tid))
++ return;
++
++ /* If we've hit this point, it doesn't really matter which
++ architecture we are using. We just need to read the
++ registers in the "old-fashioned way". */
++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++ fetch_register (regcache, tid, i);
++}
++
++
++static void
++store_register (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* This isn't really an address. But ptrace thinks of it as one. */
++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++ int i;
++ size_t bytes_to_transfer;
++ char buf[MAX_REGISTER_SIZE];
++
++ if (regaddr == -1)
++ return;
++
++ /* First collect the register. Keep in mind that the regcache's
++ idea of the register's size may not be a multiple of sizeof
++ (long). */
++ memset (buf, 0, sizeof buf);
++ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++ {
++ /* Little-endian values always sit at the left end of the buffer. */
++ regcache_raw_collect (regcache, regno, buf);
++ }
++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ {
++ /* Big-endian values sit at the right end of the buffer. */
++ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
++ regcache_raw_collect (regcache, regno, buf + padding);
++ }
++
++ for (i = 0; i < bytes_to_transfer; i += sizeof (long))
++ {
++ long l;
++
++ memcpy (&l, &buf[i], sizeof (l));
++ errno = 0;
++ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
++ regaddr += sizeof (long);
++
++ if (errno != 0)
++ {
++ char message[128];
++ sprintf (message, "writing register %s (#%d)",
++ gdbarch_register_name (gdbarch, regno), regno);
++ perror_with_name (message);
++ }
++ }
++}
++
++/* This function actually issues the request to ptrace, telling
++ it to store all general-purpose registers present in the specified
++ regset.
++
++ If the ptrace request does not exist, this function returns 0
++ and properly sets the have_ptrace_* flag. If the request fails,
++ this function calls perror_with_name. Otherwise, if the request
++ succeeds, then the regcache is stored and 1 is returned. */
++static int
++store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ gdb_gregset_t gregset;
++
++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't get general-purpose registers."));
++ }
++
++ fill_gregset (regcache, &gregset, regno);
++
++ if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't set general-purpose registers."));
++ }
++
++ return 1;
++}
++
++/* This is a wrapper for the store_all_gp_regs function. It is
++ responsible for verifying if this target has the ptrace request
++ that can be used to store all general-purpose registers at one
++ shot. If it doesn't, then we should store them using the
++ old-fashioned way, which is to iterate over the registers and
++ store them one by one. */
++static void
++store_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ int i;
++
++ if (have_ptrace_getsetregs)
++ if (store_all_gp_regs (regcache, tid, regno))
++ return;
++
++ /* If we hit this point, it doesn't really matter which
++ architecture we are using. We just need to store the
++ registers in the "old-fashioned way". */
++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++ store_register (regcache, tid, i);
++}
++
++
++/* Fetch registers from the child process. Fetch all registers if
++ regno == -1, otherwise fetch all general registers or all floating
++ point registers depending upon the value of regno. */
++
++static void
++microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
++ struct regcache *regcache, int regno)
++{
++ /* Get the thread id for the ptrace call. */
++ int tid = GET_THREAD_ID (inferior_ptid);
++
++ if (regno == -1)
++ fetch_gp_regs (regcache, tid);
++ else
++ fetch_register (regcache, tid, regno);
++}
++
++/* Store registers back into the inferior. Store all registers if
++ regno == -1, otherwise store all general registers or all floating
++ point registers depending upon the value of regno. */
++
++static void
++microblaze_linux_store_inferior_registers (struct target_ops *ops,
++ struct regcache *regcache, int regno)
++{
++ /* Get the thread id for the ptrace call. */
++ int tid = GET_THREAD_ID (inferior_ptid);
++
++ if (regno >= 0)
++ store_register (regcache, tid, regno);
++ else
++ store_gp_regs (regcache, tid, -1);
++}
++
++/* Wrapper functions for the standard regset handling, used by
++ thread debugging. */
++
++void
++fill_gregset (const struct regcache *regcache,
++ gdb_gregset_t *gregsetp, int regno)
++{
++ microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
++}
++
++void
++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
++{
++ microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
++}
++
++void
++fill_fpregset (const struct regcache *regcache,
++ gdb_fpregset_t *fpregsetp, int regno)
++{
++ /* FIXME. */
++}
++
++void
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
++{
++ /* FIXME. */
++}
++
++static const struct target_desc *
++microblaze_linux_read_description (struct target_ops *ops)
++{
++ CORE_ADDR microblaze_hwcap = 0;
++
++ if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1)
++ return NULL;
++
++ return NULL;
++}
++
++
++void _initialize_microblaze_linux_nat (void);
++
++void
++_initialize_microblaze_linux_nat (void)
++{
++ struct target_ops *t;
++
++ /* Fill in the generic GNU/Linux methods. */
++ t = linux_target ();
++
++ /* Add our register access methods. */
++ t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
++ t->to_store_registers = microblaze_linux_store_inferior_registers;
++
++ t->to_read_description = microblaze_linux_read_description;
++
++ /* Register the target. */
++ linux_nat_add_target (t);
++}
+--
+1.9.0
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0010-Patch-gdb-Robustify-inline-function-support.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0010-Patch-gdb-Robustify-inline-function-support.patch
new file mode 100644
index 0000000..3912ca5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0010-Patch-gdb-Robustify-inline-function-support.patch
@@ -0,0 +1,43 @@
+From a02963a97d7ce38b0af205f9e3e6dd7e0e06d9be Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar@axis.com>
+Date: Mon, 27 Feb 2012 06:28:00 +0100
+Subject: [PATCH 10/16] [Patch, gdb]: Robustify inline function support
+
+Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
+Upstream-Status: Pending
+---
+ gdb/blockframe.c | 3 ++-
+ gdb/inline-frame.c | 3 +++
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/gdb/blockframe.c b/gdb/blockframe.c
+index 0a9381e..ba41d85 100644
+--- a/gdb/blockframe.c
++++ b/gdb/blockframe.c
+@@ -77,7 +77,8 @@ get_frame_block (struct frame_info *frame, CORE_ADDR *addr_in_block)
+ inline_count--;
+
+ bl = BLOCK_SUPERBLOCK (bl);
+- gdb_assert (bl != NULL);
++ if (!bl)
++ return NULL;
+ }
+
+ return bl;
+diff --git a/gdb/inline-frame.c b/gdb/inline-frame.c
+index eb82143..a793390 100644
+--- a/gdb/inline-frame.c
++++ b/gdb/inline-frame.c
+@@ -231,6 +231,9 @@ inline_frame_sniffer (const struct frame_unwind *self,
+ cur_block = BLOCK_SUPERBLOCK (cur_block);
+ }
+
++ if (depth == 0)
++ return 0;
++
+ /* Check how many inlined functions already have frames. */
+ for (next_frame = get_next_frame (this_frame);
+ next_frame && get_frame_type (next_frame) == INLINE_FRAME;
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0011-Patch-gdb-Fix-debug-message-when-register-is-unavail.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0011-Patch-gdb-Fix-debug-message-when-register-is-unavail.patch
new file mode 100644
index 0000000..bdec77c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0011-Patch-gdb-Fix-debug-message-when-register-is-unavail.patch
@@ -0,0 +1,43 @@
+From a05fb34192727fc1b63c827ed006ddde846ce6b8 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: [PATCH 11/16] [Patch, gdb]: Fix debug message when register is
+ unavailable
+
+Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/frame.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/frame.c b/gdb/frame.c
+index 013d602..4d0766f 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1134,12 +1134,19 @@ frame_unwind_register_value (struct frame_info *frame, int regnum)
+ else
+ {
+ int i;
+- const gdb_byte *buf = value_contents (value);
++ const gdb_byte *buf = NULL;
++ if (value_entirely_available(value)) {
++ buf = value_contents (value);
++ }
+
+ fprintf_unfiltered (gdb_stdlog, " bytes=");
+ fprintf_unfiltered (gdb_stdlog, "[");
+- for (i = 0; i < register_size (gdbarch, regnum); i++)
+- fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++ if (buf != NULL) {
++ for (i = 0; i < register_size (gdbarch, regnum); i++)
++ fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++ } else {
++ fprintf_unfiltered (gdb_stdlog, "unavailable");
++ }
+ fprintf_unfiltered (gdb_stdlog, "]");
+ }
+ }
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0012-LOCAL-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0012-LOCAL-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 0000000..819cd17
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0012-LOCAL-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,34 @@
+From f54d5334afe799e15ca21c5d83097a4c81bbab7e Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Fri, 22 Jun 2012 01:20:20 +0200
+Subject: [PATCH 12/16] [LOCAL]: Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Upstream-Status: Pending
+---
+ bfd/elf-eh-frame.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index 0f0a563..7d8e047 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -919,9 +919,12 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+ goto success;
+
+ free_no_table:
+- (*info->callbacks->einfo)
+- (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
+- abfd, sec);
++ /* FIXME: Remove the microblaze specifics when relaxing gets fixed. */
++ if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
++ (*info->callbacks->einfo)
++ (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
++ abfd, sec);
++ }
+ hdr_info->table = FALSE;
+ if (sec_info)
+ free (sec_info);
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0013-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0013-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
new file mode 100644
index 0000000..3a0eae8
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0013-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
@@ -0,0 +1,64 @@
+From c9f1f07e5b0756069e3d4b04eb9505027f09677f Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Tue, 14 Feb 2012 01:00:22 +0100
+Subject: [PATCH 13/16] [LOCAL]: Fix relaxation of assembler resolved
+ references
+
+Upstream-Status: Pending
+---
+ bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index cbd18f0..f90df47 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1968,6 +1968,45 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ {
++ unsigned int val;
++
++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++ /* This was a PC-relative instruction that was completely resolved. */
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
++ + isym->st_value, sec);
++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++ irelscan->r_addend);
++ }
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
++ fprintf(stderr, "Unhandled NONE 64\n");
++ }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0014-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0014-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
new file mode 100644
index 0000000..85cee9d
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0014-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
@@ -0,0 +1,192 @@
+From aca2758cff1f8fdc5ad7b6076ef985ba9ec5f857 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 4 Feb 2013 12:15:22 +1000
+Subject: [PATCH 14/16] [LOCAL]: Fixup debug_loc sections after linker
+ relaxation
+
+Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing
+reloc info from the assembler to the linker when the linker
+manages to fully resolve a local symbol reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ bfd/bfd-in2.h | 5 +++++
+ bfd/elf32-microblaze.c | 45 +++++++++++++++++++++++++++++++++++++--------
+ bfd/libbfd.h | 1 +
+ bfd/reloc.c | 6 ++++++
+ include/elf/microblaze.h | 1 +
+ 5 files changed, 50 insertions(+), 8 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 8b7f2ee..de38907 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5449,6 +5449,11 @@ value relative to the read-write small data area anchor */
+ expressions of the form "Symbol Op Symbol" */
+ BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction). No relocation is
++done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_32_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index f90df47..a3f89b9 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -177,6 +177,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ FALSE), /* PC relative offset? */
+
+ /* This reloc does nothing. Used for relaxation. */
++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_32_NONE",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
+ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
+ 0, /* Rightshift. */
+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
+@@ -532,7 +546,10 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_NONE:
+ microblaze_reloc = R_MICROBLAZE_NONE;
+ break;
+- case BFD_RELOC_MICROBLAZE_64_NONE:
++ case BFD_RELOC_MICROBLAZE_32_NONE:
++ microblaze_reloc = R_MICROBLAZE_32_NONE;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_NONE:
+ microblaze_reloc = R_MICROBLAZE_64_NONE;
+ break;
+ case BFD_RELOC_32:
+@@ -1913,14 +1930,22 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ break;
+ case R_MICROBLAZE_NONE:
++ case R_MICROBLAZE_32_NONE:
+ {
+ /* This was a PC-relative instruction that was
+ completely resolved. */
+ int sfix, efix;
++ unsigned int val;
+ bfd_vma target_address;
+ target_address = irel->r_addend + irel->r_offset;
+ sfix = calc_fixup (irel->r_offset, 0, sec);
+ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
+ irel->r_addend -= (efix - sfix);
+ /* Should use HOWTO. */
+ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -1968,12 +1993,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+ {
+ unsigned int val;
+
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
++ /* hax: We only do the following fixup for debug location lists. */
++ if (strcmp(".debug_loc", o->name))
++ continue;
++
+ /* This was a PC-relative instruction that was completely resolved. */
+ if (ocontents == NULL)
+ {
+@@ -1998,15 +2027,15 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ }
+
+- irelscan->r_addend -= calc_fixup (irelscan->r_addend
+- + isym->st_value, sec);
+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ if (val != irelscan->r_addend) {
++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++ }
++
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+- fprintf(stderr, "Unhandled NONE 64\n");
+- }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+@@ -2066,7 +2095,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ elf_section_data (o)->this_hdr.contents = ocontents;
+ }
+ }
+- irelscan->r_addend -= calc_fixup (irel->r_addend
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ + isym->st_value,
+ 0,
+ sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 09f307f..840c662 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2644,6 +2644,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_MICROBLAZE_32_ROSDA",
+ "BFD_RELOC_MICROBLAZE_32_RWSDA",
+ "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++ "BFD_RELOC_MICROBLAZE_32_NONE",
+ "BFD_RELOC_MICROBLAZE_64_NONE",
+ "BFD_RELOC_MICROBLAZE_64_GOTPC",
+ "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 7f46c58..5bcd52d 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6396,6 +6396,12 @@ ENUMDOC
+ This is a 32 bit reloc for the microblaze to handle
+ expressions of the form "Symbol Op Symbol"
+ ENUM
++ BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imm instruction). No relocation is
++ done here - only used for relaxing
++ENUM
+ BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index effca20..f8420dc 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+ RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27) /* TLS Offset Within TLS Block */
+ RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
+ RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29) /* TLS Offset From Thread Pointer */
++ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
+
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0015-LOCAL-upstream-change-to-garbage-collection-sweep-ca.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0015-LOCAL-upstream-change-to-garbage-collection-sweep-ca.patch
new file mode 100644
index 0000000..0bb66a9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0015-LOCAL-upstream-change-to-garbage-collection-sweep-ca.patch
@@ -0,0 +1,40 @@
+From 22c63d4d79ac488403340470c14c73bad4984fa3 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 27 Feb 2013 13:56:11 +1000
+Subject: [PATCH 15/16] [LOCAL]: upstream change to garbage collection sweep
+ causes mb regression
+
+Upstream change for PR13177 now clears the def_regular during gc_sweep of a
+section. (All other archs in binutils/bfd/elf32-*.c received an update
+to a warning about unresolvable relocations - this warning is not present
+in binutils/bfd/elf32-microblaze.c, but this warning check would not
+prevent the error being seen)
+
+The visible issue with this change is when running a c++ application
+in Petalinux which links libstdc++.so for exception handling it segfaults
+on execution.
+
+This does not occur if static linking libstdc++.a, so its during the
+relocations for a shared lib with garbage collection this occurs
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ bfd/elflink.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index 6756fb1..f21dc06 100644
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -11932,7 +11932,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
+
+ inf = (struct elf_gc_sweep_symbol_info *) data;
+ (*inf->hide_symbol) (inf->info, h, TRUE);
+- h->def_regular = 0;
+ h->ref_regular = 0;
+ h->ref_regular_nonweak = 0;
+ }
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-7.7.1.inc b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-7.7.1.inc
new file mode 100644
index 0000000..396f0fc
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-7.7.1.inc
@@ -0,0 +1,12 @@
+LICENSE = "GPLv2 & GPLv3 & LGPLv2 & LGPLv3"
+LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
+ file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \
+ file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \
+ file://COPYING.LIB;md5=9f604d8a4f8e74f4f5140845a21b6674"
+
+S = "${WORKDIR}/${BPN}-${PV}"
+
+SRC_URI = "${GNU_MIRROR}/gdb/gdb-${PV}.tar.gz"
+SRC_URI[md5sum] = "45b07b53d81832d32ccd4829465d4886"
+SRC_URI[sha256sum] = "eefadb9831e3695d1eaef34e98b8f1fb441df6fe5071317ea49c6bd6ba213eff"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross-canadian_7.7.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross-canadian_7.7.1.bb
new file mode 100644
index 0000000..c349ebb
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross-canadian_7.7.1.bb
@@ -0,0 +1,4 @@
+require recipes-devtools/gdb/gdb-common.inc
+require recipes-devtools/gdb/gdb-cross-canadian.inc
+require gdb-${PV}.inc
+require gdb-microblaze-7.7.inc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross_7.7.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross_7.7.1.bb
new file mode 100644
index 0000000..98b3359
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross_7.7.1.bb
@@ -0,0 +1,3 @@
+require recipes-devtools/gdb/gdb-cross.inc
+require gdb-${PV}.inc
+require gdb-microblaze-7.7.inc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-microblaze-7.7.inc b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-microblaze-7.7.inc
new file mode 100644
index 0000000..d1aba82
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-microblaze-7.7.inc
@@ -0,0 +1,22 @@
+
+# MicroBlaze does not support LTTng UST
+LTTNGUST_microblaze = ""
+
+# Add MicroBlaze Patches
+FILESEXTRAPATHS_append := "${THISDIR}/files:"
+SRC_URI_append = " \
+ file://0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch \
+ file://0003-Patch-microblaze-Initial-port-of-microblaze-core-rea.patch \
+ file://0004-Patch-microblaze-Communicate-in-larger-blocks-with-t.patch \
+ file://0005-Patch-microblaze-Add-mb-singlestepping.patch \
+ file://0006-Patch-microblaze-Add-initial-port-of-linux-gdbserver.patch \
+ file://0007-Patch-microblaze-Add-slr-and-shr-regs-and-little-end.patch \
+ file://0008-Patch-microblaze-Added-Backtrace-support-to-GDB.patch \
+ file://0009-Patch-microblaze-Initial-support-for-native-gdb.patch \
+ file://0010-Patch-gdb-Robustify-inline-function-support.patch \
+ file://0011-Patch-gdb-Fix-debug-message-when-register-is-unavail.patch \
+ file://0012-LOCAL-Disable-the-warning-message-for-eh_frame_hdr.patch \
+ file://0013-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch \
+ file://0014-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch \
+ file://0015-LOCAL-upstream-change-to-garbage-collection-sweep-ca.patch \
+ "
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb_7.7.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb_7.7.1.bb
new file mode 100644
index 0000000..80b589a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb_7.7.1.bb
@@ -0,0 +1,29 @@
+require recipes-devtools/gdb/gdb-common.inc
+require gdb-${PV}.inc
+require gdb-microblaze-7.7.inc
+
+inherit gettext
+inherit python-dir
+
+PACKAGECONFIG ??= ""
+PACKAGECONFIG[python] = "--with-python=${WORKDIR}/python,--without-python,python"
+PACKAGECONFIG[babeltrace] = "--with-babeltrace,--without-babeltrace,babeltrace"
+
+do_configure_prepend() {
+ if [ -n "${@bb.utils.contains('PACKAGECONFIG', 'python', 'python', '', d)}" ]; then
+ cat > ${WORKDIR}/python << EOF
+#!/bin/sh
+case "\$2" in
+ --includes) echo "-I${STAGING_INCDIR}/${PYTHON_DIR}/" ;;
+ --ldflags) echo "-Wl,-rpath-link,${STAGING_LIBDIR}/.. -Wl,-rpath,${libdir}/.. -lpthread -ldl -lutil -lm -lpython${PYTHON_BASEVERSION}" ;;
+ --exec-prefix) echo "${exec_prefix}" ;;
+ *) exit 1 ;;
+esac
+exit 0
+EOF
+ chmod +x ${WORKDIR}/python
+ fi
+}
+
+PACKAGES =+ "gdbserver"
+FILES_gdbserver = "${bindir}/gdbserver"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/qemu/qemu_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/qemu/qemu_%.bbappend
new file mode 100644
index 0000000..3d3a54f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/qemu/qemu_%.bbappend
@@ -0,0 +1,2 @@
+QEMU_TARGETS += "microblazeel microblaze"
+