meta-xilinx: subtree update:757bac706c..bef2bf9b15
Alejandro Enedino Hernandez Samaniego (76):
libmali-xlnx: Use update-alternatives to switch between GL backends
libmali-xlnx: modify REQUIRED_DISTRO_FEATURES
libmali-xlnx: only use and install dependencies that the DISTRO supports
libmali-xlnx: fix x11 headers
libmali-xlnx: Dont provide KHR headers
libmali-xlnx: Change version on gbm.pc to be compatible with mesa
libmali-xlnx: modify version on egl.pc for compatibility
run-postinsts: Pass the output of the scripts run to kmsg
zynqmp-pmu.conf: Upgrade tune to use Microblaze v10.0
zynqmp-pmu.conf: Update to Microblaze v11.0
newlib: export CC_FOR_TARGET as CC
gcc-cross: Dont override EXTRA_OECONF unless DISTRO is xilinx-standalone
Adds MACHINE.conf containing default tune for Cortex R5
Adds MACHINE.conf containing default tune for Cortex A53
toolchain: Provide specific configuration for cross(-canadian) gcc and binutils
Adds MACHINE.conf containing default tune for Cortex A72
xilinx-standalone: switch override and append
xilinx-standalone: Add staticdev packages for newlib and libgloss to dependencies
xilinx-standalone: Reorganize toolchain configure options
toolchain: add cortex-A9 options for gcc and binutils
gcc-cross-microblazeel: disable multilib
gcc: Separate binutils options
gcc: Add multilib-list=aprofile configure option for cortex A9
gcc-runtime: Enable bulding libsdtc++ for baremetal applications
gcc-runtime: Set correct overrides now that the build has been fixed in oe-core
gcc-xilinx-standalone: Enable multilib builds for baremetal microblaze
gcc-microblaze: Remove multilib builds that arent working (m64)
meta-xilinx-standalone: Restructure layer properly, gcc and binutils belong on recipes-devtools
newlib: Keep version numbers on bbappends
meta-xilinx-standalone: Restructure layer properly, newlib belongs to recipes-bsp
gcc-runtime: Move gcc-runtime to GCCs directory
layer.conf: Include recipe files from a pattern with no directory required
Create machines that use SOC_FAMILY
Microblaze-pmu: Change overrides to reflect machine name changes from zynqmp-pmu to microblaze-pmu
cortexr5: Change overrides to reflect machine name changes from cortexr5 to zynqmp and versal variants
cortexa72: To keep up with a standard rename cortexa72 to add its SOC_FAMILY to its name
meta-xilinx-bsp: Unify machine confs
cortexr5-versal.conf: Include the tune inc file from the correct path
cortexr5-zynqmp.conf: Include the tune inc file from the correct path
tune-cortexrm: Include PACKAGE_EXTRA_ARCHS to avoid parsing errors
esw: first step to move everything into an embeddedsw class
pmufw: Install and hence package and strip the pmufw elf file
fix license and compatible host for now
pmufw: fix filename on elf file and fix task order to get stripped elf file deployed
libxil: add flow for a53 using dtg
device-tree.bbappend: add appent to support cortexa53 MACHINE
device-tree: switch to AUTOREV to keep up with the repo changes for now
zynqmp-fsbl: Sync flow with pmufw
libxil: fix device tree flags for a53
libxil: Fix DTB and DTG flow to make it more transparent for the user
Fix XILINX_RELEASE_VERSION
Increase layer priority
device-tree: the Flags used from device tree have to be set on the device tree recipe, not in the libxil one
esw.bbclass: Fix devtool and externalsrc flow
esw.bbclass: Install artifacts from the build directory vs WORKDIR
pmufw: Install artifacts from the build directory vs WORKDIR
esw.bbclass: Make it possible for packages to use the cmake ncurses gui
libxil: Unify flow and get DTB using the device-tree recipe instead of creating it manually
SOC_FAMILY: Change overrides
Microblaze-pmu: Change overrides to reflect machine name chanches from zynqmp-pmu to microblaze-pmu
device-tree: Install psu_init files as well
fsbl: avoid using underscore in the directory filename
meta-xilinx-standalone: Restructure layer properly, pmufw and fsbl belong on recipes-applications
meta-xilinx-standalone: device-tree belongs on recipes-bsp
meta-xilinx-standalone: Restructure layer properly, move existing libraries from decoupling to recipes-libraries
zynqmp-fsbl: Fix race condition on copy_psu_init
device-tree: Fix install directory
meta-xilinx-standalone: clean up layer
libraries: Add inherit on python3native on libraries that were invoking nativepython3
meta-xilinx: Include templates for local.conf and bblayers.conf
esw: fix machines that have been renamed
libgloss: Dont install libgloss as libxil since we actually have libxil
esw: Switch release version to 2020.1
xilinx-standalone: Add buildhistory to the DISTRO to avoid cooker errors
device-tree: Override repo for supported machines
system-zcu102: Create heterogeneous machine configuration for ZCU102 evaluation board.
Anirudha Sarangi (4):
meta-xilinx-standalone: conf: distro: Add new distro for freertos
meta-xilinx-standalone: classes: Update CMAKE_SYSTEM_NAME for Freertos
meta-xilinx-standalone: recipes-libraries: Add recipe for freertos
meta-xilinx-standalone: recipes-applications: freertos-hello-world: Add recipe for freertos hello world
Appana Durga Kedareswara rao (82):
libxil: Add recipes for libxil and xilstandalone
pmufw: recipes for pmufw app generation in decoupled flow
Add recipes for xilffs and xilpm libraries
Add recipes for building zynqmp fsbl application
meta-xilinx-standalone: Add support for PLM and dependent library recipes
zynqmp-fsbl: Copy psu_init files to source code
meta-xilinx: meta-xilinx-standalone: Update source url path
meta-xilinx: meta-xilinx-standalone: comment flto flags by default
meta-xilinx-standalone: Using S instead of WORKDIR
meta-xilinx-standalone: classes: Add bbclass for building esw examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling csudma driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling emacps driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling axiethernet driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling axicdma driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling axidma driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling llfifo driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling mcdma driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling zdma driver examples
meta-xilinx-standalone: recipes-applications: Add recipe for compiling hello world application
meta-xilinx-standalone: classes: Update md5 checksum as per latest license
meta-xilinx-standalone: Add support for cortexa72 processor
meta-xilinx-standalone: recipes-libraries: xilstandalone: Cleanup the recipe
meta-xilinx-standalone: recipes-libraries: libxil: Cleanup the recipe
meta-xilinx-standalone: classes: cleanup the class
meta-xilinx-standalone: recipes-applications: hello-world: Remove dependency on esw_examples class
meta-xilinx-standalone: recipes-libraries: Add recipe for xilmailbox
cortexa72: Update cortexa72 machine variable naming
meta-xilinx: Add support for cortexr5 processor
meta-xilinx-standalone: Add dependencies on python3-dtc-native
meta-xilinx-standalone: recipes-libraries: xiltimer: Add task for generating cmake meta-data
meta-xilinx-standalone: recipes-libraries: lwip: Add recipe for lwip
meta-xilinx-standalone: recipes-applications: lwip-echo-server: Add recipe for compiling lwip echo server application
meta-xilinx-standalone: Add support for versal cortexr5 processor
meta-xilinx-standalone: recipes-applications: lwip-tcp-perf-client: Add recipe for compiling lwip tcp perf client application
meta-xilinx-standalone: recipes-applications: lwip-tcp-perf-server: Add recipe for compiling lwip tcp perf server application
meta-xilinx-standalone: recipes-applications: lwip-udp-perf-server: Add recipe for compiling lwip udp perf server application
meta-xilinx-standalone: recipes-applications: lwip-udp-perf-client: Add recipe for compiling lwip udp perf client application
meta-xilinx-standalone: recipes-applications: freertos-lwip-echo-server: Add recipe for compiling freertos lwip echo server application
meta-xilinx-standalone: recipes-applications: freertos-lwip-tcp-perf-client: Add recipe for compiling freertos lwip tcp perf client application
meta-xilinx-standalone: recipes-applications: freertos-lwip-tcp-perf-server: Add recipe for compiling freertos lwip tcp perf server application
meta-xilinx-standalone: recipes-applications: freertos-lwip-udp-perf-client: Add recipe for compiling freertos lwip udp perf client application
meta-xilinx-standalone: recipes-applications: freertos-lwip-udp-perf-server: Add recipe for compiling freertos lwip udp perf server application
meta-xilinx-standalone: recipes-libraries: Update depends list for socket mode
meta-xilinx-standalone: recipes-libraries: Add recipe for xilpuf
meta-xilinx-standalone: recipes-libraries: Fix workarounds
meta-xilinx-standalone: recipes-libraries: xilloader: Update depends list
meta-xilinx-standalone: recipes-applications: freertos-hello-world: Fix do_deploy elf variable name
meta-xilinx-standalone: classes: esw: Remove unneeded DISTRO check
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling dmaps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling usbpsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling axivdma driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling emaclite driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling xxvethernet driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling scugic driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling ttcps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling tmrctr driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling qspipsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling ospipsv driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling resetps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling clockps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling canfd driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling canps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling can driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling wdtps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling rtcpsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling gpiops driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling sdps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling ipipsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling nandpsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling devcfg driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling mbox driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling mutex driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling uartlite driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling uartps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling gpio driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling spips driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling qspips driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling xadcps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling sysmon driver examples
device-tree: Install psu_init files as well for zynqmp machines
meta-xilinx-standalone: recipes-applications: zynqmp-fsbl: Correct cflags based on the machine type
meta-xilinx-standalone: recipes-bsp: device-tree: Install psu_init* files only for standalone configuration
Bruce Ashfield (1):
linux-xlnx: cleanup and make yocto-kernel-cache available
Himanshu Choudhary (8):
xrt_git:zocl_git: added package_class for generating rpm
zocl_git: added post install script
xrt_git: added veral flags and dependencies
xrt_git:zocl_git: license and PV update from meta-xilinx-internal
xrt,zocl:Update commit id for 2020.1 release
xrt_git:zocl_git: updated commitid > CR-1063204
xrt_git:zocl_git: update commitid for 2020.1 release
xrt_git:zocl_git: update commitid for 2020.1 release
Jaewon Lee (28):
Update recipes for 2019.2 release
u-boot-zynq-scr: reworking boot.scr recipe to work for zynq and zynqmp
u-boot-zynq-scr: Setting sd as default bootmode for versal
zynq/zynqmp confs: Adding boot.scr to IMAGE_BOOT_FILES
bootgen_1.0.bb: Adding initial bootgen recipe to build bootgen
flashstrip utility: Build and ship flash strip utility needed for qemu
machine-xilinx-default.inc: Adding required dependencies to image_wic
**TEMPORARY**: Removing preferred provider overrides for mali backend
meson: Adding patch to add microblaze as supported CPU
glibc-locale_%.bbappend: Fix directory installed but not shipped issue
Revert "**TEMPORARY**: Removing preferred provider overrides for mali backend"
arm-trusted-firmware.inc: Changing generic DEBUG to DEBUG_ATF
gcc-cross-canadian_%.bbappend:temporary hack to build gcc cross canadian
gcc-source: Adding microblaze patch to fix compiler crash with -freg-struct-return
newlib: Adding xilinx specific patches on top of newlib/libgloss 3.1.0
cortexa*.conf: Change arch-armv8.inc to arch-armv8a.inc
gdb: Switching microblaze to use upstream gdb version 8.3.1
microblaze gdb/binutils: Adding necessary patches for microblaze
Using tune-cortexa72-cortexa53.inc for versal and zynqmp tunes
qemu-system-aarch64-multiarch: Adding comment for future fix
xilinx-standalone.conf: Adding qemu to TOOLCHAIN_HOST_TASK
arm-trusted-firmware.inc: installing elf with standard name
u-boot-xlnx:Updating defconfig for all zynq machines
Correcting ':' placement for appending file paths
Add older version of OpenCV 3.4.3
opencv_3.4.3.bb: Removing tiny-dnn from SRC_URI
versal confs: Upping RAM in runqemu command to 8G for versal boards
versal confs: cleaning up unnecessary file loading in runqemu command
Jean-Francois Dagenais (3):
libmali-xlnx: clean and fix FILESXTRAPATHS
libmali-xlnx: make version recognizable
kernel-module-mali: add patch to check dma_map_page error
Jeegar Patel (1):
kernel-module-vcu.bb : Autoload dmaproxy module on boot
Madhurkiran Harikrishnan (14):
libmali-xlnx: MALI will not provide wayland-egl
libmali-xlnx.bb: ABIs are made consistent for all backends
libmali-xlnx: Squash all monolithic library name into a variable
libmali-xlnx: Upgrade the userspace driver to r9p0
kernel-module-mali: Upgrade the kernel space driver to r9p0
weston: Migrate ZynqMP specific patches for weston to meta-xilinx
weston: Remove opaque substitute for ARGB8888 as ZynqMP DP does not support
kernel-module-mali: Make the driver compatible with kernel 5.4
Revert "libmali-xlnx: Dont provide KHR headers"
mesa: Do not provide KHR headers
cairo: For ZynqMP enable glesv2 packageconfig
libglu: Add build time dependency on glesv2 for zynqmp
xf86-video-armsoc: Bypass the exa layer to free the root pixmap
libmali: Fetch mali binaries from rel-v2020.1 branch
Manjukumar Matha (17):
libmali-xlnx: upgrade MALI recipe for 2019.2
xrt_git.bb: Fix xrt recipe for externalsrc
zocl_git.bb: Update the S path for zocl
kernel-module-hdmi_git.bb: New Yocto recipe for Xilinx HDMI drivers
machine-xilinx-default.inc: Add qemu-xilinx-helper-native as preferred provider
zynq-generic.conf: Add qemu wiring to generic conf
meta-xilinx-pynq: Add layer to support PYNQ
image-types-xilinx-qemu.bbclass: Add sector size as 512K
ultra96-zynqmp.conf: Add support for Ultra96 evaluation board
linux-firmware_git.bbappend: Add hook for wl18xx and bts file
vc-p-a2197-00-versal.conf:Add versal Tenzing +SE1 board configuration
kc705-microblaze: Update u-boot patch for kc705
layer.conf: Update XILINX_RELEASE_VERSION to v2020.1
libgpg-error: Add microblaze platform specific gpg-error.h file
qemu-xilinx-native: Enable packageconfig option for libgcrypt
qemu-xilinx.inc: Remove stale packageconfig options
qemu-xilinx.inc: Configure qemu-xilinx with gcrypt
Mark Hatle (82):
binutils/gcc: Refactor the oeconf
Revert "binutils/gcc: Refactor the oeconf"
gcc-runtime: Make the baremetal changes specific to class-target
binutils/gcc: Refactor the oeconf
gcc: Remove cortexa53 errata fixes
binutils: Merge latest binutils work
Revert "gcc-microblaze: Remove multilib builds that arent working (m64)"
gcc-cross-canadian: Fix issue being unable to find stdio.h
Enable multilib baremetal toolchains
gcc-runtime: Fix C++ multilib headers
Limit multilib toolchains to symlinks to the main toolchain
Create new baremetal toolchain machines
Fix arm cortex r/m profiles
microblaze-tc: Minor update and corrections
Adjust the microblaze standalone toolchain to match vitis expectations.
newlib: Adjust configuration for standalone to allow BSP library
qemu-xilinx: Point to master branch by default
distro/xilinx-standalone: Make LTO optional
distr/xilinx-standalone: Switch default optimization from ESW to Distro
cortex-r5: Add cortexr5f configuration
xilinx-standalone: When building for cortexr5, add -DARMR5 for CCARGS
newlib: Move microblaze support
newlib: Cleanup and merge the two newlib bbappends into a single append
python3-dtc: Add python3 dtc module
Ensure that bbappends do not affect task hashes
xlnx-compatible-os.bbclass: Class to allow recipes to list OS compatibility
Remove hardcoded XILINX_RELEASE_VERSION in recipes
meta-xilinx-standalone: Add dependencies on python3-dtc
meta-xilinx-standalone/device-tree: remove duplicate internal references
lopper: Add lopper utility
xilinx-standalone: sync distros
xilinx-standalone.inc: Replace qemu dependency with mingw32 specific recipe
lopper: Add runtime dependency of python3-dtc
cortexa53-zynqmp/cortexa72-versal: Fix cortex based BSPs
README.md: revise README.md based
README.md: Add information about the new embeddedsw support
microblaze_dtb.py: Convert a dtb to one or more microblaze TUNE_FEATURES
linux-xlnx: Use new default defconfigs
meta-xilinx-bsp: Rename soc configuration masquerading as a tune file
meta-xilinx-bsp: Remove default values
machine-xilinx-overrides: Make this generic
meta-xilinx-bsp: Update recipes to use SOC_FAMILY_ARCH and SOC_VARIANT_ARCH
meta-xilinx-bsp: rename machine-xilinx-override to xilinx-soc-family.inc
meta-xilinx-standalone: Move soc overrides from meta-xilinx-default
meta-xilinx-bsp: Adjust soc to permit multiple CPU/TUNES
libmali-xlnx: Remove virtual provides
meta-xilinx-bsp: remove redundant PREFERRED_PROVIDER
Revert "libmali-xlnx: Remove virtual provides"
meta-xilinx-bsp: machine-xilinx-default.inc allow empty WIC_DEPENDS
microblaze_dtb.py: Move to scripts subdir
zc706-zynq7: Add qemu wiring for zc706 machine
qemu-zynq7: Add qemu wiring for zc706 machine
meta-xilinx-bsp: cleanup qemu references
xilinx-qemu: Move -multiarch extension to the machine-xilinx-qemu
*-generic.conf: Add QEMU support to each of the generic BSPs
versal-generic: Move from vck190 to vc-p-a2197-00-versal
esw.bbclass: Adjust get_xlnx_cmake_process to use both tune and machine
Revise COMPATIBLE_MACHINE settings
esw.bbclass: Move DTBFILE to a single definition
xilinx-standalone.conf: Add workaround for microblaze -Os bug
Revert "linux-xlnx: Use new default defconfigs"
qemu-xilinx.inc: Move the URL to 'gitsm' and disable compile time submodules
esw.bbclass: Only work with xilinx-standalone distro
Rename plm_git.bb to plm-standalong_git.bb
meta-xilinx-standalone esw.bbclass: Allow SRCREV and SRC_URI to be overwritten
esw.bbclass: Change 'or' to 'and' to verify EXTERNALSRC is defined
Revert "xlnx-compatible-os.bbclass: Class to allow recipes to list OS compatibility"
Define COMPATIBLE_HOST to prevent mix of Linux and Baremetal recipes
device-tree.bbappend: Move to COMPATIBLE_HOST
machines: Move from SERIAL_CONSOLE (deprecated) to SERIAL_CONSOLES
machines: Move from SERIAL_CONSOLE (deprecated) to SERIAL_CONSOLES
machines: Allow the user to override SERIAL_CONSOLES
machines: Remove default SERIAL_CONSOLES_CHECK
machines: Allow user to override SERIAL_CONSOLE
microblaze machines: Set LINKER_HASH_STYLE defaults
kernel-module-mali: WIP
libcma: Fix SRC_URI definition
binutils: Microblaze integrate fix from upstream
init-ifupdown: Fix BSPs that were setting partial overrides
zynq-generic.conf: Remove the qemu overrides, not needed
meta-xilinx-standalone gcc: Fix microblaze crtend.o
lopper: Fix python3 reference in lopper_sanity.py
Min Ma (1):
xrt_git.bb: update XRT dependency
Mubin Usman Sayyed (3):
meta-xilinx-bsp: conf: machine: Add standalone based machine for zynq
meta-xilinx-standalone: Add support for zynq
meta-xilinx-standalone: classes: esw: Update ESW_CFLAGS with spec file
Mukund PVVN (3):
zcu1275-zynqmp.conf: Rename zc1275 to zcu1275
zcu1285-zynqmp.conf: Update UBOOT_MACHINE
v350-versal.conf:Add versal board configuration
Peter Ogden (1):
python3-pynq.bb: Update PYNQ to 2.5.1
Sai Hari Chandana Kalluri (54):
u-boot-xlnx_2019.2.bb: Rename zc1275 to zcu1275 board name
ultra96-zynqmp.conf: Include mipi as MACHINE_FEATURE
linux-xlnx.inc: Add MIPI kernel configuration for Ultra96
pynq-ultra96-*: Add Ultra96 specific pynq example demo:
vck-sc-zynqmp: Machine configuration for vck190 system controller
v350-versal.conf: Enforce system.dtb name when using virtual/dtb
vmk180-versal.conf: Add machine configuration for vmk180-versal
tune-versal.inc: Set default SOC_VARIANT = s80
arm-trusted-firmware_2019.2.bbappend: Update compilation flag
u-boot-xlnx: Add the platform init file for zcu216-zynqmp
plm_2019.2.bb: recipe to build plm standalone
psm-firmware_2019.2.bb: Create psm-firmware recipe for standalone build
versal-mb.conf: Add machine configuration to support standalone build for versal components like plm, psm-firmware
vck190-versal.conf: Add deploy dir for psm and plm firmware
tune-versal.inc: Rename include file from arch-armv8 to arch-armv8a
Move recipes to use _%.bb instead of version
qemu-*: Upgrade QEMU version 2.11 -> 4.1.5
Upgrade recipes to 2020.1
libmali-xlnx: Provide single shlib provider for libMali.so.9
"**TEMPORARY**" linux-xlnx.inc: Trim PV variable expansion
Revert "Revert "**TEMPORARY**: Removing preferred provider overrides for mali backend""
versal-generic: Add versal-generic machine configuration
Revert "**TEMPORARY**: Removing preferred provider overrides for mali backend"""
qemu-xilinx*: Enable qemu-xilinx-native as PROVIDER for qemu-native
u-boot-zyqn-scr.bb: Update DEVICETREE and KERNEL LOAD ADDRESS for zynqmp machines
u-boot-xlnx:Update UBOOT-MACHINE to xilinx_zynqmp_virt_defconfig for all zynqmp machines
qemu-xilinx: Enable qemu-xilinx to provide nativesdk-qemu
zedboard-zynq7.conf:update u-boot binary name
qemu-system-aarch64-multiarch: Update the binpath for qemu targets
zcu102-zynqmp.conf: Modify PMU_FIRMWARE_DEPLOY_DIR and PMU_FIRMWARE_IMAGE_NAME
Update KERNEL_VERSION to 5.4
zcu102-zynqmp.conf: Pass dtb and dtb load address as QB_OPT args for qemuboot
Enable kernel configurations for viruatlization distro feature
zc702-zynq7: Add qemu wiring for zc702 machine
qemu-xilinx-multiarch-helper-native_1.0.bb: Move multiarch wrapper script to bindir
qemuboot-xilinx.bbclass: Remove the subdir added to the qemu target path
external-hdf.bbappend: move to meta-xilinx-tools layer
xrt: Remove references to PACKAGE_CLASSES from xrt recipes
kernel-module-hdmi: Update LICENSE_CHECKSUM for kenrel-module-hdmi
xilinx-kmeta: Upstream xen and ocicontainer configs to YP kernel-cache
Update commit ids for 2020.1 release
arm-trusted-firmware.inc: Update package version
Update commit ids for 2020.1 release
lopper: Update commit id for 2020.1 release
layer.conf: Set layer compat to dunfell & gatesgarth
qemu-xilinx-native.inc: Fix the patch file names for dunfell Fix patch file names for dunfell
libmali-xlnx: Inherit features_check instead of distro_features_check
gcc-9*: Upgrade gcc from 9.2->10.1
libgloss, newlib: Upgrade version from 3.1 -> 3.3
meson_%.bbappend: Remove bbappend from layer
qemu-xilinx.inc: Add patch to enable/disbable libudev in qemu configure
python3-dtc_1.5.1.bb: Explicitly set the path to run make during configure
qemu-devicetrees: Use python3 instead of python
u-boot-xlnx.inc: Explicitly set builddir path
Sandeep Gundlupet Raju (2):
conf/machine/kc705-microbalzeel.conf: Fix U-boot defconfig
local.conf.sample: Updating XILINX_VER_MAIN
Swagath Gadde (4):
u-boot-zynq-scr: Add pxeboot support in u-boot-scr
zcu216-zynqmp: Add support for zcu216 board
u-boot-zynq-scr:Add initrd label to pxe config
zcu208-zynqmp: Add support for zcu208 board
Varalaxmi Bingi (4):
Update XILINX_RELEASE_VERSION to v2020.1
zcu1285-zynqmp.conf:using common u-boot defconfig
u-boot-xlnx.inc:u-boot-xlnx_2020.1.bb: kc705 patch
removing kc705 patch
Vishal Sagar (3):
kernel-module-hdmi_git.bb: Add versal support
kernel-module-hdmi: Update for 2020.1 release
kernel-module-hdmi: Update commit id and license md5sum for 2020.1
ch vamshi krishna (1):
xrt_git.bb: Add icd support for edge platforms
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Change-Id: I71ace4a7992c023b84c864abd45e634b5e48f751
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch
new file mode 100644
index 0000000..8141095
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch
@@ -0,0 +1,359 @@
+From 7b332d61cb3dbcae69021ce706f2c408c85af193 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:18:43 +0530
+Subject: [PATCH 30/43] Added support to new arithmetic single register
+ instructions
+
+---
+ gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c | 12 +++
+ opcodes/microblaze-opc.h | 43 ++++++++++-
+ opcodes/microblaze-opcm.h | 5 +-
+ 4 files changed, 201 insertions(+), 6 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 5b506d3348..12eef24a29 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -423,12 +423,33 @@ void
+ md_begin (void)
+ {
+ struct op_code_struct * opcode;
++ const char *prev_name = "";
+
+ opcode_hash_control = hash_new ();
+
+ /* Insert unique names into hash table. */
+- for (opcode = opcodes; opcode->name; opcode ++)
+- hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
++ for (opcode = (struct opcodes *)opcodes; opcode->name; opcode ++)
++ {
++ if (strcmp (prev_name, opcode->name))
++ {
++ prev_name = (char *) opcode->name;
++ hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
++ }
++ }
++}
++
++static int
++is_reg (char * s)
++{
++ int is_reg = 0;
++ /* Strip leading whitespace. */
++ while (ISSPACE (* s))
++ ++ s;
++ if (TOLOWER (s[0]) == 'r')
++ {
++ is_reg =1;
++ }
++ return is_reg;
+ }
+
+ /* Try to parse a reg name. */
+@@ -986,6 +1007,7 @@ md_assemble (char * str)
+ {
+ char * op_start;
+ char * op_end;
++ char * temp_op_end;
+ struct op_code_struct * opcode, *opcode1;
+ char * output = NULL;
+ int nlen = 0;
+@@ -996,9 +1018,10 @@ md_assemble (char * str)
+ unsigned reg3;
+ unsigned isize;
+ unsigned long immed, immed2, temp;
+- expressionS exp;
++ expressionS exp,exp1;
+ char name[20];
+ long immedl;
++ int reg=0;
+
+ /* Drop leading whitespace. */
+ while (ISSPACE (* str))
+@@ -1029,7 +1052,78 @@ md_assemble (char * str)
+ as_bad (_("unknown opcode \"%s\""), name);
+ return;
+ }
+-
++
++ if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") ||
++ streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli")
++ || streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc")
++ || streq (name, "andli") || streq (name, "andnli") || streq (name, "orli")
++ || streq (name, "xorli")))
++ {
++ temp_op_end = op_end;
++ if (strcmp (temp_op_end, ""))
++ temp_op_end = parse_reg (temp_op_end + 1, ®1); /* Get rd. */
++ if (strcmp (temp_op_end, ""))
++ reg = is_reg (temp_op_end + 1);
++ if (reg)
++ {
++
++ opcode->inst_type=INST_TYPE_RD_R1_IMML;
++ opcode->inst_offset_type = OPCODE_MASK_H;
++ if (streq (name, "addli"))
++ opcode->bit_sequence = ADDLI_MASK;
++ else if (streq (name, "addlic"))
++ opcode->bit_sequence = ADDLIC_MASK;
++ else if (streq (name, "addlik"))
++ opcode->bit_sequence = ADDLIK_MASK;
++ else if (streq (name, "addlikc"))
++ opcode->bit_sequence = ADDLIKC_MASK;
++ else if (streq (name, "rsubli"))
++ opcode->bit_sequence = RSUBLI_MASK;
++ else if (streq (name, "rsublic"))
++ opcode->bit_sequence = RSUBLIC_MASK;
++ else if (streq (name, "rsublik"))
++ opcode->bit_sequence = RSUBLIK_MASK;
++ else if (streq (name, "rsublikc"))
++ opcode->bit_sequence = RSUBLIKC_MASK;
++ else if (streq (name, "andli"))
++ opcode->bit_sequence = ANDLI_MASK;
++ else if (streq (name, "andnli"))
++ opcode->bit_sequence = ANDLNI_MASK;
++ else if (streq (name, "orli"))
++ opcode->bit_sequence = ORLI_MASK;
++ else if (streq (name, "xorli"))
++ opcode->bit_sequence = XORLI_MASK;
++ }
++ else
++ {
++ opcode->inst_type=INST_TYPE_RD_IMML;
++ opcode->inst_offset_type = OPCODE_MASK_LIMM;
++ if (streq (name, "addli"))
++ opcode->bit_sequence = ADDLI_ONE_REG_MASK;
++ else if (streq (name, "addlic"))
++ opcode->bit_sequence = ADDLIC_ONE_REG_MASK;
++ else if (streq (name, "addlik"))
++ opcode->bit_sequence = ADDLIK_ONE_REG_MASK;
++ else if (streq (name, "addlikc"))
++ opcode->bit_sequence = ADDLIKC_ONE_REG_MASK;
++ else if (streq (name, "rsubli"))
++ opcode->bit_sequence = RSUBLI_ONE_REG_MASK;
++ else if (streq (name, "rsublic"))
++ opcode->bit_sequence = RSUBLIC_ONE_REG_MASK;
++ else if (streq (name, "rsublik"))
++ opcode->bit_sequence = RSUBLIK_ONE_REG_MASK;
++ else if (streq (name, "rsublikc"))
++ opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK;
++ else if (streq (name, "andli"))
++ opcode->bit_sequence = ANDLI_ONE_REG_MASK;
++ else if (streq (name, "andnli"))
++ opcode->bit_sequence = ANDLNI_ONE_REG_MASK;
++ else if (streq (name, "orli"))
++ opcode->bit_sequence = ORLI_ONE_REG_MASK;
++ else if (streq (name, "xorli"))
++ opcode->bit_sequence = XORLI_ONE_REG_MASK;
++ }
++ }
+ inst = opcode->bit_sequence;
+ isize = 4;
+
+@@ -1480,6 +1574,51 @@ md_assemble (char * str)
+ inst |= (immed << IMM_LOW) & IMM15_MASK;
+ break;
+
++ case INST_TYPE_RD_IMML:
++ if (strcmp (op_end, ""))
++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
++ else
++ {
++ as_fatal (_("Error in statement syntax"));
++ reg1 = 0;
++ }
++
++ if (strcmp (op_end, ""))
++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++ else
++ as_fatal (_("Error in statement syntax"));
++
++ /* Check for spl registers. */
++ if (check_spl_reg (®1))
++ as_fatal (_("Cannot use special register with this instruction"));
++ if (exp.X_op != O_constant)
++ {
++ char *opc = NULL;
++ relax_substateT subtype;
++
++ if (exp.X_md != 0)
++ subtype = get_imm_otype(exp.X_md);
++ else
++ subtype = opcode->inst_offset_type;
++
++ output = frag_var (rs_machine_dependent,
++ isize * 2,
++ isize * 2,
++ subtype,
++ exp.X_add_symbol,
++ exp.X_add_number,
++ (char *) opc);
++ immedl = 0L;
++ }
++ else
++ {
++ output = frag_more (isize);
++ immed = exp.X_add_number;
++ }
++ inst |= (reg1 << RD_LOW) & RD_MASK;
++ inst |= (immed << IMM_LOW) & IMM16_MASK;
++ break;
++
+ case INST_TYPE_R1_RFSL:
+ if (strcmp (op_end, ""))
+ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index f679a43606..e5e880cb1c 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -114,6 +114,15 @@ get_field_imm15 (long instr)
+ return (strdup (tmpstr));
+ }
+
++static char *
++get_field_imm16 (long instr)
++{
++ char tmpstr[25];
++
++ sprintf (tmpstr, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
++ return (strdup (tmpstr));
++}
++
+ static char *
+ get_field_special (long instr, struct op_code_struct * op)
+ {
+@@ -419,6 +428,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ case INST_TYPE_RD_IMM15:
+ print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
+ break;
++ case INST_TYPE_RD_IMML:
++ print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm16 (inst));
++ break;
+ /* For mbar insn. */
+ case INST_TYPE_IMM5:
+ print_func (stream, "\t%s", get_field_imm5_mbar (inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index d59ee0a95f..0774f70e08 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -69,6 +69,7 @@
+ #define INST_TYPE_RD_R1_IMMW_IMMS 21
+
+ #define INST_TYPE_NONE 25
++#define INST_TYPE_RD_IMML 26
+
+
+
+@@ -84,6 +85,7 @@
+ #define IMMVAL_MASK_MFS 0x0000
+
+ #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */
++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
+ #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */
+ #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */
+ #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */
+@@ -106,6 +108,33 @@
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+ #define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */
+
++/*Defines to identify 64-bit single reg instructions */
++#define ADDLI_ONE_REG_MASK 0x68000000
++#define ADDLIC_ONE_REG_MASK 0x68020000
++#define ADDLIK_ONE_REG_MASK 0x68040000
++#define ADDLIKC_ONE_REG_MASK 0x68060000
++#define RSUBLI_ONE_REG_MASK 0x68010000
++#define RSUBLIC_ONE_REG_MASK 0x68030000
++#define RSUBLIK_ONE_REG_MASK 0x68050000
++#define RSUBLIKC_ONE_REG_MASK 0x68070000
++#define ORLI_ONE_REG_MASK 0x68100000
++#define ANDLI_ONE_REG_MASK 0x68110000
++#define XORLI_ONE_REG_MASK 0x68120000
++#define ANDLNI_ONE_REG_MASK 0x68130000
++#define ADDLI_MASK 0x20000000
++#define ADDLIC_MASK 0x28000000
++#define ADDLIK_MASK 0x30000000
++#define ADDLIKC_MASK 0x38000000
++#define RSUBLI_MASK 0x24000000
++#define RSUBLIC_MASK 0x2C000000
++#define RSUBLIK_MASK 0x34000000
++#define RSUBLIKC_MASK 0x3C000000
++#define ANDLI_MASK 0xA4000000
++#define ANDLNI_MASK 0xAC000000
++#define ORLI_MASK 0xA0000000
++#define XORLI_MASK 0xA8000000
++
++
+ /* New Mask for msrset, msrclr insns. */
+ #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
+ /* Mask for mbar insn. */
+@@ -114,7 +143,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 412
++#define MAX_OPCODES 424
+
+ struct op_code_struct
+ {
+@@ -444,13 +473,21 @@ struct op_code_struct
+ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
+ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
+ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
+ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
+ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
+ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
+ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
+ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
+ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
+ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
+ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
+ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
+ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
+@@ -501,9 +538,13 @@ struct op_code_struct
+ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
+ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
+ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
+ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
+ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
+ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
+ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
+ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
+ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 5f2e190d23..4d2ee2dd0d 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -61,7 +61,9 @@ enum microblaze_instr
+ eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
+
+ /* 64-bit instructions */
+- addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++ addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
++ addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++ andli, andnli, orli, xorli,
+ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
+ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
+ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
+@@ -166,5 +168,6 @@ enum microblaze_instr_type
+
+ /* Imm mask for msrset, msrclr instructions. */
+ #define IMM15_MASK 0x00007FFF
++#define IMM16_MASK 0x0000FFFF
+
+ #endif /* MICROBLAZE-OPCM */
+--
+2.17.1
+