meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0001-plat-corstone1000-add-corstone1000-platform.patch

Upstream-Status: Pending [Not submitted to upstream yet]
Signed-off-by: Arpita S.K <arpita.s.k@arm.com>

From 439a87df6a9f60f2b29afd988ad58a67e6f0b603 Mon Sep 17 00:00:00 2001
From: Vishnu Banavath <vishnu.banavath@arm.com>
Date: Tue, 22 Jun 2021 22:09:28 +0100
Subject: [PATCH] plat-corstone1000: add corstone1000 platform

These changes are to add corstone1000 platform to optee core

Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

diff --git a/core/arch/arm/plat-corstone1000/conf.mk b/core/arch/arm/plat-corstone1000/conf.mk
new file mode 100644
index 00000000..b14dd442
--- /dev/null
+++ b/core/arch/arm/plat-corstone1000/conf.mk
@@ -0,0 +1,37 @@
+PLATFORM_FLAVOR ?= mps3
+
+$(call force,CFG_HWSUPP_MEM_PERM_WXN,y)
+$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
+$(call force,CFG_ENABLE_SCTLR_RR,n)
+$(call force,CFG_ENABLE_SCTLR_Z,n)
+
+arm64-platform-cpuarch := cortex-a35
+arm64-platform-cflags += -mcpu=$(arm64-platform-cpuarch)
+arm64-platform-aflags += -mcpu=$(arm64-platform-cpuarch)
+platform-flavor-armv8 := 1
+
+$(call force,CFG_GIC,y)
+$(call force,CFG_PL011,y)
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+
+$(call force,CFG_ARM64_core,y)
+
+CFG_WITH_STATS ?= y
+
+CFG_WITH_ARM_TRUSTED_FW ?= y
+CFG_WITH_LPAE ?=y
+
+CFG_TEE_CORE_NB_CORE = 1
+CFG_TZDRAM_START ?= 0x02002000
+CFG_TZDRAM_SIZE  ?= 0x000FE000
+CFG_TEE_RAM_VA_SIZE ?= 0x00AF000
+CFG_SHMEM_START  ?= 0x86000000
+CFG_SHMEM_SIZE   ?= 0x00200000
+
+CFG_DDR_SIZE ?= 0x80000000
+CFG_DT_ADDR ?= 0x82100000
+CFG_DTB_MAX_SIZE ?= 0x100000
+
+$(call force,CFG_PSCI_ARM64,y)
+$(call force,CFG_DT,y)
+$(call force,CFG_EXTERNAL_DTB_OVERLAY,y)
diff --git a/core/arch/arm/plat-corstone1000/main.c b/core/arch/arm/plat-corstone1000/main.c
new file mode 100644
index 00000000..35d89535
--- /dev/null
+++ b/core/arch/arm/plat-corstone1000/main.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#include <arm64.h>
+#include <console.h>
+#include <drivers/gic.h>
+#include <drivers/pl011.h>
+#include <drivers/tzc400.h>
+#include <initcall.h>
+#include <keep.h>
+#include <kernel/boot.h>
+#include <kernel/interrupt.h>
+#include <kernel/misc.h>
+#include <kernel/panic.h>
+#include <kernel/tee_time.h>
+#include <mm/core_memprot.h>
+#include <mm/core_mmu.h>
+#include <platform_config.h>
+#include <sm/psci.h>
+#include <stdint.h>
+#include <string.h>
+#include <trace.h>
+
+static struct gic_data gic_data __nex_bss;
+static struct pl011_data console_data __nex_bss;
+
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
+#ifdef DRAM0_BASE
+register_ddr(DRAM0_BASE, DRAM0_SIZE);
+#endif
+
+#ifdef GIC_BASE
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
+
+void main_init_gic(void)
+{
+	vaddr_t gicc_base;
+	vaddr_t gicd_base;
+
+	gicc_base = core_mmu_get_va(GICC_BASE, MEM_AREA_IO_SEC);
+	gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC);
+
+	if (!gicc_base || !gicd_base)
+		panic();
+
+	/* Initialize GIC */
+	gic_init(&gic_data, gicc_base, gicd_base);
+	itr_init(&gic_data.chip);
+
+}
+
+void main_secondary_init_gic(void)
+{
+	gic_cpu_init(&gic_data);
+}
+
+void itr_core_handler(void)
+{
+	gic_it_handle(&gic_data);
+}
+#endif
+
+void console_init(void)
+{
+	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
+		   CONSOLE_BAUDRATE);
+	register_serial_console(&console_data.chip);
+}
+
+void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie)
+{
+	DMSG("This is single core platform\n");
+}
+
diff --git a/core/arch/arm/plat-corstone1000/platform_config.h b/core/arch/arm/plat-corstone1000/platform_config.h
new file mode 100644
index 00000000..cfee6fa4
--- /dev/null
+++ b/core/arch/arm/plat-corstone1000/platform_config.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#ifndef PLATFORM_CONFIG_H
+#define PLATFORM_CONFIG_H
+
+#include <mm/generic_ram_layout.h>
+#include <stdint.h>
+
+/* Make stacks aligned to data cache line length */
+#define STACK_ALIGNMENT		64
+
+
+#define GIC_BASE		0x1c000000
+#define UART0_BASE		0x1a510000
+#define UART1_BASE		0x1a520000
+
+#define CONSOLE_UART_BASE	UART1_BASE
+
+#define DRAM0_BASE		0x80000000
+#define DRAM0_SIZE		0x7f000000
+
+#define GICD_OFFSET		0x10000
+#define GICC_OFFSET		0x2f000
+
+#ifdef GIC_BASE
+#define GICD_BASE		(GIC_BASE + GICD_OFFSET)
+#define GICC_BASE		(GIC_BASE + GICC_OFFSET)
+#endif
+
+#ifndef UART_BAUDRATE
+#define UART_BAUDRATE		115200
+#endif
+#ifndef CONSOLE_BAUDRATE
+#define CONSOLE_BAUDRATE	UART_BAUDRATE
+#endif
+
+#ifndef SYS_COUNTER_FREQ_IN_TICKS
+#define SYS_COUNTER_FREQ_IN_TICKS	UL(50000000) /* 32MHz */
+#endif
+
+#define CONSOLE_UART_CLK_IN_HZ	UL(50000000) /* 32MHz*/
+
+#endif /*PLATFORM_CONFIG_H*/
diff --git a/core/arch/arm/plat-corstone1000/sub.mk b/core/arch/arm/plat-corstone1000/sub.mk
new file mode 100644
index 00000000..8ddc2fd4
--- /dev/null
+++ b/core/arch/arm/plat-corstone1000/sub.mk
@@ -0,0 +1,2 @@
+global-incdirs-y += .
+srcs-y += main.c
-- 
2.17.1