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gerrit.openbmc.org / openbmc / openbmc / e71c689b0034a68d173d308dc66c31b6325ae2aa / . / meta-arm / meta-arm-bsp / recipes-security / optee / files / optee-os / corstone1000 / 0001-plat-corstone1000-add-corstone1000-platform.patch
blob: 7666486d7e11408ead66ac6b17350cbead2adfee [file] [log] [blame]
Brad Bishopbec4ebc2022-08-03 09:55:16 -0400[diff] [blame]1Upstream-Status: Pending [Not submitted to upstream yet]
2Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
3
4From 439a87df6a9f60f2b29afd988ad58a67e6f0b603 Mon Sep 17 00:00:00 2001
5From: Vishnu Banavath <vishnu.banavath@arm.com>
6Date: Tue, 22 Jun 2021 22:09:28 +0100
7Subject: [PATCH] plat-corstone1000: add corstone1000 platform
8
9These changes are to add corstone1000 platform to optee core
10
11Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
12
13diff --git a/core/arch/arm/plat-corstone1000/conf.mk b/core/arch/arm/plat-corstone1000/conf.mk
14new file mode 100644
15index 00000000..b14dd442
16--- /dev/null
17+++ b/core/arch/arm/plat-corstone1000/conf.mk
18@@ -0,0 +1,37 @@
19+PLATFORM_FLAVOR ?= mps3
20+
21+$(call force,CFG_HWSUPP_MEM_PERM_WXN,y)
22+$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
23+$(call force,CFG_ENABLE_SCTLR_RR,n)
24+$(call force,CFG_ENABLE_SCTLR_Z,n)
25+
26+arm64-platform-cpuarch := cortex-a35
27+arm64-platform-cflags += -mcpu=$(arm64-platform-cpuarch)
28+arm64-platform-aflags += -mcpu=$(arm64-platform-cpuarch)
29+platform-flavor-armv8 := 1
30+
31+$(call force,CFG_GIC,y)
32+$(call force,CFG_PL011,y)
33+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
34+
35+$(call force,CFG_ARM64_core,y)
36+
37+CFG_WITH_STATS ?= y
38+
39+CFG_WITH_ARM_TRUSTED_FW ?= y
40+CFG_WITH_LPAE ?=y
41+
42+CFG_TEE_CORE_NB_CORE = 1
43+CFG_TZDRAM_START ?= 0x02002000
44+CFG_TZDRAM_SIZE ?= 0x000FE000
45+CFG_TEE_RAM_VA_SIZE ?= 0x00AF000
46+CFG_SHMEM_START ?= 0x86000000
47+CFG_SHMEM_SIZE ?= 0x00200000
48+
49+CFG_DDR_SIZE ?= 0x80000000
50+CFG_DT_ADDR ?= 0x82100000
51+CFG_DTB_MAX_SIZE ?= 0x100000
52+
53+$(call force,CFG_PSCI_ARM64,y)
54+$(call force,CFG_DT,y)
55+$(call force,CFG_EXTERNAL_DTB_OVERLAY,y)
56diff --git a/core/arch/arm/plat-corstone1000/main.c b/core/arch/arm/plat-corstone1000/main.c
57new file mode 100644
58index 00000000..35d89535
59--- /dev/null
60+++ b/core/arch/arm/plat-corstone1000/main.c
61@@ -0,0 +1,77 @@
62+// SPDX-License-Identifier: BSD-2-Clause
63+/*
64+ * Copyright (c) 2020, Linaro Limited
65+ */
66+
67+#include <arm64.h>
68+#include <console.h>
69+#include <drivers/gic.h>
70+#include <drivers/pl011.h>
71+#include <drivers/tzc400.h>
72+#include <initcall.h>
73+#include <keep.h>
74+#include <kernel/boot.h>
75+#include <kernel/interrupt.h>
76+#include <kernel/misc.h>
77+#include <kernel/panic.h>
78+#include <kernel/tee_time.h>
79+#include <mm/core_memprot.h>
80+#include <mm/core_mmu.h>
81+#include <platform_config.h>
82+#include <sm/psci.h>
83+#include <stdint.h>
84+#include <string.h>
85+#include <trace.h>
86+
87+static struct gic_data gic_data __nex_bss;
88+static struct pl011_data console_data __nex_bss;
89+
90+register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
91+#ifdef DRAM0_BASE
92+register_ddr(DRAM0_BASE, DRAM0_SIZE);
93+#endif
94+
95+#ifdef GIC_BASE
96+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
97+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
98+
99+void main_init_gic(void)
100+{
101+ vaddr_t gicc_base;
102+ vaddr_t gicd_base;
103+
104+ gicc_base = core_mmu_get_va(GICC_BASE, MEM_AREA_IO_SEC);
105+ gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC);
106+
107+ if (!gicc_base || !gicd_base)
108+ panic();
109+
110+ /* Initialize GIC */
111+ gic_init(&gic_data, gicc_base, gicd_base);
112+ itr_init(&gic_data.chip);
113+
114+}
115+
116+void main_secondary_init_gic(void)
117+{
118+ gic_cpu_init(&gic_data);
119+}
120+
121+void itr_core_handler(void)
122+{
123+ gic_it_handle(&gic_data);
124+}
125+#endif
126+
127+void console_init(void)
128+{
129+ pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
130+ CONSOLE_BAUDRATE);
131+ register_serial_console(&console_data.chip);
132+}
133+
134+void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie)
135+{
136+ DMSG("This is single core platform\n");
137+}
138+
139diff --git a/core/arch/arm/plat-corstone1000/platform_config.h b/core/arch/arm/plat-corstone1000/platform_config.h
140new file mode 100644
141index 00000000..cfee6fa4
142--- /dev/null
143+++ b/core/arch/arm/plat-corstone1000/platform_config.h
144@@ -0,0 +1,46 @@
145+/* SPDX-License-Identifier: BSD-2-Clause */
146+/*
147+ * Copyright (c) 2020, Linaro Limited
148+ */
149+
150+#ifndef PLATFORM_CONFIG_H
151+#define PLATFORM_CONFIG_H
152+
153+#include <mm/generic_ram_layout.h>
154+#include <stdint.h>
155+
156+/* Make stacks aligned to data cache line length */
157+#define STACK_ALIGNMENT 64
158+
159+
160+#define GIC_BASE 0x1c000000
161+#define UART0_BASE 0x1a510000
162+#define UART1_BASE 0x1a520000
163+
164+#define CONSOLE_UART_BASE UART1_BASE
165+
166+#define DRAM0_BASE 0x80000000
167+#define DRAM0_SIZE 0x7f000000
168+
169+#define GICD_OFFSET 0x10000
170+#define GICC_OFFSET 0x2f000
171+
172+#ifdef GIC_BASE
173+#define GICD_BASE (GIC_BASE + GICD_OFFSET)
174+#define GICC_BASE (GIC_BASE + GICC_OFFSET)
175+#endif
176+
177+#ifndef UART_BAUDRATE
178+#define UART_BAUDRATE 115200
179+#endif
180+#ifndef CONSOLE_BAUDRATE
181+#define CONSOLE_BAUDRATE UART_BAUDRATE
182+#endif
183+
184+#ifndef SYS_COUNTER_FREQ_IN_TICKS
185+#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 32MHz */
186+#endif
187+
188+#define CONSOLE_UART_CLK_IN_HZ UL(50000000) /* 32MHz*/
189+
190+#endif /*PLATFORM_CONFIG_H*/
191diff --git a/core/arch/arm/plat-corstone1000/sub.mk b/core/arch/arm/plat-corstone1000/sub.mk
192new file mode 100644
193index 00000000..8ddc2fd4
194--- /dev/null
195+++ b/core/arch/arm/plat-corstone1000/sub.mk
196@@ -0,0 +1,2 @@
197+global-incdirs-y += .
198+srcs-y += main.c
199--
2002.17.1
201