| Upstream-Status: Pending [Not submitted to upstream yet] |
| Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> |
| |
| From 2eb1da30564428551ca687d456d848129105abac Mon Sep 17 00:00:00 2001 |
| From: Vishnu Banavath <vishnu.banavath@arm.com> |
| Date: Tue, 25 Oct 2022 19:08:49 +0100 |
| Subject: [PATCH] plat-n1sdp: register DRAM1 to optee-os |
| |
| N1SDP supports two DRAM's. This change is to add 2nd DRAM |
| starting at 0x8080000000 address. |
| |
| Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> |
| |
| diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk |
| index 06b4975a..5374e406 100644 |
| --- a/core/arch/arm/plat-n1sdp/conf.mk |
| +++ b/core/arch/arm/plat-n1sdp/conf.mk |
| @@ -38,4 +38,4 @@ CFG_SHMEM_START ?= 0x83000000 |
| CFG_SHMEM_SIZE ?= 0x00210000 |
| # DRAM1 is defined above 4G |
| $(call force,CFG_CORE_LARGE_PHYS_ADDR,y) |
| -$(call force,CFG_CORE_ARM64_PA_BITS,36) |
| +$(call force,CFG_CORE_ARM64_PA_BITS,42) |
| diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c |
| index cfb7f19b..bb951ce6 100644 |
| --- a/core/arch/arm/plat-n1sdp/main.c |
| +++ b/core/arch/arm/plat-n1sdp/main.c |
| @@ -33,6 +33,7 @@ static struct pl011_data console_data __nex_bss; |
| register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); |
| |
| register_ddr(DRAM0_BASE, DRAM0_SIZE); |
| +register_ddr(DRAM1_BASE, DRAM1_SIZE); |
| |
| register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); |
| register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); |
| diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h |
| index 81b99409..bf0a3c83 100644 |
| --- a/core/arch/arm/plat-n1sdp/platform_config.h |
| +++ b/core/arch/arm/plat-n1sdp/platform_config.h |
| @@ -35,6 +35,9 @@ |
| #define DRAM0_BASE 0x80000000 |
| #define DRAM0_SIZE 0x80000000 |
| |
| +#define DRAM1_BASE 0x8080000000ULL |
| +#define DRAM1_SIZE 0x80000000ULL |
| + |
| #define GICD_BASE 0x30000000 |
| #define GICC_BASE 0x2C000000 |
| #define GICR_BASE 0x300C0000 |
| -- |
| 2.17.1 |
| |