commit b4d1cba25c7a6564ea7789007c2675f738d571a6
author Andrew Geissler <openbmcbump-github@yahoo.com> Tue Sep 21 18:31:17 2021 +0000
committer Andrew Geissler <geissonator@yahoo.com> Thu Sep 23 02:06:18 2021 +0000
tree 9484f2b82f4d3eeb0b56a560b7fd4405baf58f42
parent 449954afe3b57ccbe2e292cf80620ca2b85d6a91

x86-power-control: srcrev bump 1aa08b2364..61b4a5bf7e

Jason M. Bills (1):
      Start the watchdog each time waitForSIOPowerGood is set

Jean-Marie Verdun (2):
      Fix gpio logic following parity code insertion
      SioPowerGoodAssert check at boot for HPE Proliant

Change-Id: Ie9dcb53cd9249bc5657adc4b4a73da0bf29ed5af
Signed-off-by: Andrew Geissler <openbmcbump-github@yahoo.com>

meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb

diff --git a/meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb b/meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb
index e9bad06..102b3fc 100755
--- a/meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb
+++ b/meta-phosphor/recipes-x86/chassis/x86-power-control_git.bb
@@ -2,7 +2,7 @@
 DESCRIPTION = "Chassis Power Control service for Intel based platforms"
 
 SRC_URI = "git://github.com/openbmc/x86-power-control.git;protocol=ssh"
-SRCREV = "1aa08b23645a85c655fe4712fe7bbb81c7f46dfc"
+SRCREV = "61b4a5bf7e8e7be92807fcb85a9780075e8893b4"
 
 PV = "1.0+git${SRCPV}"