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gerrit.openbmc.org / openbmc / openbmc / 061a8d8b8c4a2bad786b3cfbd59f5c992333c783 / . / meta-ibm / recipes-bsp / u-boot / u-boot-aspeed-sdk / p10bmc / ips.json
blob: a59d30bd223a8e369d3b16b2de9ae910d21c446c [file] [log] [blame]
Andrew Jeffery096c6002022-08-08 20:48:00 +0930[diff] [blame]1{
2 "name": "p10bmc",
3 "version": "A3",
4 "data_region": {
Joel Stanley2011bd12022-12-15 12:21:45 +1030[diff] [blame]5 "patch": true,
Andrew Jeffery096c6002022-08-08 20:48:00 +0930[diff] [blame]6 "ecc_region": true,
7 "key": [
8 {
9 "types": "rsa_pub_oem",
10 "key_pem": "rsa_pub_oem_dss_key.pem",
11 "offset": "0x40",
12 "number_id": 0,
13 "sha_mode": "SHA512"
14 },
15 {
16 "types": "rsa_pub_oem",
17 "key_pem": "IPS_P10BMCAspeedSBPubKey_1.pem",
18 "offset": "0x240",
19 "number_id": 1,
20 "sha_mode": "SHA512"
21 },
22 {
23 "types": "rsa_pub_oem",
24 "key_pem": "IPS_P10BMCAspeedSBPubKey_2.pem",
25 "offset": "0x440",
26 "number_id": 2,
27 "sha_mode": "SHA512"
28 },
29 {
30 "types": "rsa_pub_oem",
31 "key_pem": "IPS_P10BMCAspeedSBPubKey_3.pem",
32 "offset": "0x640",
33 "number_id": 2,
34 "sha_mode": "SHA512"
35 }
Joel Stanley2011bd12022-12-15 12:21:45 +1030[diff] [blame]36 ],
37 "user_data": [
38 {
39 "types": "dw_hex",
40 "file": "emmc_patch.hex",
41 "offset": "0x1B80"
42 }
Andrew Jeffery096c6002022-08-08 20:48:00 +0930[diff] [blame]43 ]
44 },
45 "config_region": {
46 "Disable OTP Memory BIST Mode": true,
47 "Enable Secure Boot": false,
48 "User region ECC enable": true,
49 "Secure Region ECC enable": false,
50 "Disable low security key": false,
51 "Ignore Secure Boot hardware strap": false,
52 "Secure Boot Mode": "Mode_2",
53 "Disable Uart Message of ROM code": false,
54 "Secure crypto RSA length": "RSA4096",
55 "Hash mode": "SHA512",
Joel Stanley2011bd12022-12-15 12:21:45 +1030[diff] [blame]56 "Disable patch code": false,
Andrew Jeffery096c6002022-08-08 20:48:00 +0930[diff] [blame]57 "Disable Boot from Uart": false,
58 "Secure Region size": "0x0",
59 "Write Protect: Secure Region": true,
60 "Write Protect: User region": true,
61 "Write Protect: Configure region": true,
62 "Write Protect: OTP strap region": true,
63 "Copy Boot Image to Internal SRAM": true,
64 "Enable image encryption": false,
65 "Enable write Protect of OTP key retire bits": false,
66 "Disable Auto Boot from UART or VUART": false,
67 "OTP memory lock enable": false,
68 "Key Revision": "0x0",
69 "Secure boot header offset": "0x0",
70 "Boot From UART Port Selection": "UART5",
71 "Disable Auto Boot from UART": false,
72 "Disable Auto Boot from VUART2 over PCIE": true,
73 "Disable Auto Boot from VUART2 over LPC": true,
74 "Disable ROM code based programming control": true,
75 "Rollback prevention shift bit number": "0x0",
76 "Extra Data Write Protection Region Size": "0x0",
77 "Erase signature data after secure boot check": false,
78 "Erase RSA public key after secure boot check": false,
Andrew Jeffery096c6002022-08-08 20:48:00 +0930[diff] [blame]79 "User define data: random number low": "0x0",
80 "User define data: random number high": "0x0",
81 "Manifest ID": "0x0",
Joel Stanley2011bd12022-12-15 12:21:45 +1030[diff] [blame]82 "Patch code location": "0x6E0",
83 "Patch code size": "0x18"
Andrew Jeffery096c6002022-08-08 20:48:00 +0930[diff] [blame]84 },
85 "otp_strap": {
86 "Enable secure boot": { "value": false },
87 "Enable boot from eMMC": { "value": true },
88 "Boot from debug SPI": { "value": false },
89 "Disable ARM CM3": { "value": true },
90 "Enable dedicated VGA BIOS ROM": { "value": false },
91 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
92 "MAC 2 RMII mode": { "value": "RMII/NCSI" },
93 "CPU frequency": { "value": "1.2GHz" },
94 "HCLK ratio": { "value": "default" },
95 "VGA memory size": { "value": "16MB" },
96 "CPU/AXI clock ratio": { "value": "2:1" },
97 "Disable ARM JTAG debug": { "value": true },
98 "VGA class code": { "value": "vga_device" },
99 "Disable debug 0": { "value": false },
100 "Boot from eMMC speed mode": { "value": "normal" },
101 "Enable PCIe EHCI": { "value": false },
102 "Disable ARM JTAG trust world debug": { "value": true },
103 "Disable dedicated BMC function": { "value": false },
104 "Enable dedicate PCIe RC reset": { "value": false },
105 "Disable watchdog to reset full chip": { "value": false },
106 "Internal bridge speed selection": { "value": "1x" },
107 "Disable RVAS function": { "value": false },
108 "MAC 3 RMII mode": { "value": "RMII/NCSI" },
109 "MAC 4 RMII mode": { "value": "RMII/NCSI" },
110 "SuperIO configuration address selection": { "value": "0x2e" },
111 "Disable LPC to decode SuperIO": { "value": true },
112 "Disable debug 1": { "value": false },
113 "Enable ACPI": { "value": false },
114 "Select LPC/eSPI": { "value": "LPC" },
115 "Enable SAFS": { "value": false },
116 "Enable boot from uart5": { "value": false },
117 "Enable boot SPI 3B address mode auto-clear": { "value": false },
118 "Enable SPI 3B/4B address mode auto detection": { "value": false },
119 "Enable boot SPI or eMMC ABR": { "value": true },
120 "Boot SPI ABR Mode": { "value": "dual" },
121 "Boot SPI flash size": { "value": "0" },
122 "Enable host SPI ABR": { "value": false },
123 "Enable host SPI ABR mode select pin": { "value": false },
124 "Host SPI ABR Mode": { "value": "dual" },
125 "Host SPI flash size": { "value": "0" },
126 "Enable boot SPI auxiliary control pins": { "value": false },
127 "Boot SPI CRTM size": { "value": "0" },
128 "Host SPI CRTM size": { "value": "0" },
129 "Enable host SPI auxiliary control pins": { "value": false },
130 "Enable GPIO Pass Through": { "value": false },
131 "Enable Dedicate GPIO Strap Pins": { "value": false }
132 }
133}