blob: a98d84c559e5b551f18a20004e1b7dce4fe85891 [file] [log] [blame]
Brad Bishop286d45c2018-10-02 15:21:57 -04001From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 2 May 2016 23:46:42 +1000
4Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on
5
6Fix the issues where the VTC is reset (losing its timing config).
7
8Also fix the issue where the plane destroys its DMA descriptors and
9marks the DMA channels as inactive but never recreates the descriptors
10and never updates the active state when turning DPMS back on.
11
12Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
13Upstream-Status: Pending [This is a workaround]
14---
15 drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 -
16 drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++-
17 2 files changed, 2 insertions(+), 2 deletions(-)
18
19diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
20index 631d35b921..93dbd4b58a 100644
21--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
22+++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
23@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
24 default:
25 if (crtc->vtc) {
26 xilinx_vtc_disable(crtc->vtc);
27- xilinx_vtc_reset(crtc->vtc);
28 }
29 if (crtc->cresample) {
30 xilinx_cresample_disable(crtc->cresample);
31diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
32index 6a248b72d4..d2518a4bdf 100644
33--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
34+++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
35@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
36 for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
37 struct xilinx_drm_plane_dma *dma = &plane->dma[i];
38
39- if (dma->chan && dma->is_active) {
40+ if (dma->chan) {
41 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
42 desc = dmaengine_prep_interleaved_dma(dma->chan,
43 &dma->xt,
44@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
45 dmaengine_submit(desc);
46
47 dma_async_issue_pending(dma->chan);
48+ dma->is_active = true;
49 }
50 }
51 }
52--
532.14.2
54