blob: 389232c1e3ee7f6e376a6e957ed6015dd95cbb93 [file] [log] [blame]
Patrick Williams213cb262021-08-07 19:21:33 -05001From b77c5a67d4ac2513d0b4bab5e4dd1c33b339689b Mon Sep 17 00:00:00 2001
Andrew Geissler635e0e42020-08-21 15:58:33 -05002From: Zhenhua Luo <zhenhua.luo@nxp.com>
3Date: Sat, 11 Jun 2016 22:08:29 -0500
Andrew Geisslerd1e89492021-02-12 15:35:20 -06004Subject: [PATCH] fix the incorrect assembling for ppc wait mnemonic
Andrew Geissler635e0e42020-08-21 15:58:33 -05005
6Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com>
7
8Upstream-Status: Pending
9---
10 opcodes/ppc-opc.c | 4 +---
11 1 file changed, 1 insertion(+), 3 deletions(-)
12
13diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
Patrick Williams213cb262021-08-07 19:21:33 -050014index 13d8b6c3c07..cd979f9c80c 100644
Andrew Geissler635e0e42020-08-21 15:58:33 -050015--- a/opcodes/ppc-opc.c
16+++ b/opcodes/ppc-opc.c
Patrick Williams213cb262021-08-07 19:21:33 -050017@@ -6378,8 +6378,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
Andrew Geissler635e0e42020-08-21 15:58:33 -050018 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
Patrick Williams213cb262021-08-07 19:21:33 -050019 {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, EXT, {0}},
20 {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, EXT, {0}},
Andrew Geissler635e0e42020-08-21 15:58:33 -050021-{"wait", X(31,30), XWCPL_MASK, POWER10, 0, {WC, PL}},
22-{"wait", X(31,30), XWC_MASK, POWER9, POWER10, {WC}},
23
24 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
25
Patrick Williams213cb262021-08-07 19:21:33 -050026@@ -6433,7 +6431,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
Andrew Geissler635e0e42020-08-21 15:58:33 -050027
Patrick Williams213cb262021-08-07 19:21:33 -050028 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}},
29 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}},
Andrew Geissler635e0e42020-08-21 15:58:33 -050030-{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
31+{"wait", X(31,62), XWC_MASK, E500MC|PPCA2|POWER9|POWER10, 0, {WC}},
32
33 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
34