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gerrit.openbmc.org / openbmc / openbmc / 2142aac77bbc7b869a91f374e254d9d752b63cac / . / meta-ibm / recipes-bsp / u-boot / u-boot-aspeed-sdk / p10bmc / ibm.json
blob: 59c92a08988688eae58bc756491d2ae9b5128815 [file] [log] [blame]
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]1{
Joel Stanley6c1b2422022-06-07 11:27:12 +0930[diff] [blame]2 "name": "p10bmc",
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]3 "version": "A3",
4 "data_region": {
Andrew Jeffery352822e2022-12-15 12:21:45 +1030[diff] [blame]5 "patch": true,
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]6 "ecc_region": true,
7 "key": [
8 {
9 "types": "rsa_pub_oem",
10 "key_pem": "rsa_pub_oem_dss_key.pem",
11 "offset": "0x40",
12 "number_id": 0,
13 "sha_mode": "SHA512"
14 },
15 {
16 "types": "rsa_pub_oem",
Andrew Jeffery7ecd9d92022-05-24 10:08:30 +0930[diff] [blame]17 "key_pem": "P10BMCAspeedSBPubKey_2.pem",
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]18 "offset": "0x240",
19 "number_id": 1,
20 "sha_mode": "SHA512"
21 },
22 {
23 "types": "rsa_pub_oem",
Andrew Jeffery7ecd9d92022-05-24 10:08:30 +0930[diff] [blame]24 "key_pem": "P10BMCAspeedSBPubKey_3.pem",
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]25 "offset": "0x440",
26 "number_id": 2,
27 "sha_mode": "SHA512"
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]28 }
Andrew Jeffery352822e2022-12-15 12:21:45 +1030[diff] [blame]29 ],
30 "user_data": [
31 {
32 "types": "dw_hex",
33 "file": "emmc_patch.hex",
34 "offset": "0x1B80"
35 }
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]36 ]
37 },
38 "config_region": {
39 "Disable OTP Memory BIST Mode": true,
40 "Enable Secure Boot": false,
41 "User region ECC enable": true,
42 "Secure Region ECC enable": false,
43 "Disable low security key": false,
44 "Ignore Secure Boot hardware strap": false,
45 "Secure Boot Mode": "Mode_2",
46 "Disable Uart Message of ROM code": false,
47 "Secure crypto RSA length": "RSA4096",
48 "Hash mode": "SHA512",
Andrew Jeffery352822e2022-12-15 12:21:45 +1030[diff] [blame]49 "Disable patch code": false,
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]50 "Disable Boot from Uart": false,
51 "Secure Region size": "0x0",
52 "Write Protect: Secure Region": true,
53 "Write Protect: User region": true,
54 "Write Protect: Configure region": true,
55 "Write Protect: OTP strap region": true,
56 "Copy Boot Image to Internal SRAM": true,
57 "Enable image encryption": false,
58 "Enable write Protect of OTP key retire bits": false,
59 "Disable Auto Boot from UART or VUART": false,
60 "OTP memory lock enable": false,
61 "Key Revision": "0x0",
62 "Secure boot header offset": "0x0",
63 "Boot From UART Port Selection": "UART5",
64 "Disable Auto Boot from UART": false,
65 "Disable Auto Boot from VUART2 over PCIE": true,
66 "Disable Auto Boot from VUART2 over LPC": true,
67 "Disable ROM code based programming control": true,
68 "Rollback prevention shift bit number": "0x0",
69 "Extra Data Write Protection Region Size": "0x0",
70 "Erase signature data after secure boot check": false,
71 "Erase RSA public key after secure boot check": false,
72 "Keys Retire ID": 0,
73 "User define data: random number low": "0x0",
74 "User define data: random number high": "0x0",
75 "Manifest ID": "0x0",
Andrew Jeffery352822e2022-12-15 12:21:45 +1030[diff] [blame]76 "Patch code location": "0x6E0",
77 "Patch code size": "0x18"
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +1030[diff] [blame]78 },
79 "otp_strap": {
80 "Enable secure boot": { "value": false },
81 "Enable boot from eMMC": { "value": true },
82 "Boot from debug SPI": { "value": false },
83 "Disable ARM CM3": { "value": true },
84 "Enable dedicated VGA BIOS ROM": { "value": false },
85 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
86 "MAC 2 RMII mode": { "value": "RMII/NCSI" },
87 "CPU frequency": { "value": "1.2GHz" },
88 "HCLK ratio": { "value": "default" },
89 "VGA memory size": { "value": "16MB" },
90 "CPU/AXI clock ratio": { "value": "2:1" },
91 "Disable ARM JTAG debug": { "value": true },
92 "VGA class code": { "value": "vga_device" },
93 "Disable debug 0": { "value": false },
94 "Boot from eMMC speed mode": { "value": "normal" },
95 "Enable PCIe EHCI": { "value": false },
96 "Disable ARM JTAG trust world debug": { "value": true },
97 "Disable dedicated BMC function": { "value": false },
98 "Enable dedicate PCIe RC reset": { "value": false },
99 "Disable watchdog to reset full chip": { "value": false },
100 "Internal bridge speed selection": { "value": "1x" },
101 "Disable RVAS function": { "value": false },
102 "MAC 3 RMII mode": { "value": "RMII/NCSI" },
103 "MAC 4 RMII mode": { "value": "RMII/NCSI" },
104 "SuperIO configuration address selection": { "value": "0x2e" },
105 "Disable LPC to decode SuperIO": { "value": true },
106 "Disable debug 1": { "value": false },
107 "Enable ACPI": { "value": false },
108 "Select LPC/eSPI": { "value": "LPC" },
109 "Enable SAFS": { "value": false },
110 "Enable boot from uart5": { "value": false },
111 "Enable boot SPI 3B address mode auto-clear": { "value": false },
112 "Enable SPI 3B/4B address mode auto detection": { "value": false },
113 "Enable boot SPI or eMMC ABR": { "value": true },
114 "Boot SPI ABR Mode": { "value": "dual" },
115 "Boot SPI flash size": { "value": "0" },
116 "Enable host SPI ABR": { "value": false },
117 "Enable host SPI ABR mode select pin": { "value": false },
118 "Host SPI ABR Mode": { "value": "dual" },
119 "Host SPI flash size": { "value": "0" },
120 "Enable boot SPI auxiliary control pins": { "value": false },
121 "Boot SPI CRTM size": { "value": "0" },
122 "Host SPI CRTM size": { "value": "0" },
123 "Enable host SPI auxiliary control pins": { "value": false },
124 "Enable GPIO Pass Through": { "value": false },
125 "Enable Dedicate GPIO Strap Pins": { "value": false }
126 }
127}