| Patrick Williams | 2390b1b | 2022-11-03 13:47:49 -0500 | [diff] [blame^] | 1 | Upstream-Status: Pending [Not submitted to upstream yet] |
| 2 | Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> |
| 3 | |
| 4 | From 2eb1da30564428551ca687d456d848129105abac Mon Sep 17 00:00:00 2001 |
| 5 | From: Vishnu Banavath <vishnu.banavath@arm.com> |
| 6 | Date: Tue, 25 Oct 2022 19:08:49 +0100 |
| 7 | Subject: [PATCH] plat-n1sdp: register DRAM1 to optee-os |
| 8 | |
| 9 | N1SDP supports two DRAM's. This change is to add 2nd DRAM |
| 10 | starting at 0x8080000000 address. |
| 11 | |
| 12 | Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> |
| 13 | |
| 14 | diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk |
| 15 | index 06b4975a..5374e406 100644 |
| 16 | --- a/core/arch/arm/plat-n1sdp/conf.mk |
| 17 | +++ b/core/arch/arm/plat-n1sdp/conf.mk |
| 18 | @@ -38,4 +38,4 @@ CFG_SHMEM_START ?= 0x83000000 |
| 19 | CFG_SHMEM_SIZE ?= 0x00210000 |
| 20 | # DRAM1 is defined above 4G |
| 21 | $(call force,CFG_CORE_LARGE_PHYS_ADDR,y) |
| 22 | -$(call force,CFG_CORE_ARM64_PA_BITS,36) |
| 23 | +$(call force,CFG_CORE_ARM64_PA_BITS,42) |
| 24 | diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c |
| 25 | index cfb7f19b..bb951ce6 100644 |
| 26 | --- a/core/arch/arm/plat-n1sdp/main.c |
| 27 | +++ b/core/arch/arm/plat-n1sdp/main.c |
| 28 | @@ -33,6 +33,7 @@ static struct pl011_data console_data __nex_bss; |
| 29 | register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); |
| 30 | |
| 31 | register_ddr(DRAM0_BASE, DRAM0_SIZE); |
| 32 | +register_ddr(DRAM1_BASE, DRAM1_SIZE); |
| 33 | |
| 34 | register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); |
| 35 | register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); |
| 36 | diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h |
| 37 | index 81b99409..bf0a3c83 100644 |
| 38 | --- a/core/arch/arm/plat-n1sdp/platform_config.h |
| 39 | +++ b/core/arch/arm/plat-n1sdp/platform_config.h |
| 40 | @@ -35,6 +35,9 @@ |
| 41 | #define DRAM0_BASE 0x80000000 |
| 42 | #define DRAM0_SIZE 0x80000000 |
| 43 | |
| 44 | +#define DRAM1_BASE 0x8080000000ULL |
| 45 | +#define DRAM1_SIZE 0x80000000ULL |
| 46 | + |
| 47 | #define GICD_BASE 0x30000000 |
| 48 | #define GICC_BASE 0x2C000000 |
| 49 | #define GICR_BASE 0x300C0000 |
| 50 | -- |
| 51 | 2.17.1 |
| 52 | |