| Brad Bishop | 26bdd44 | 2019-08-16 17:08:17 -0400 | [diff] [blame^] | 1 | From d55eff09f175ddbc66e4e800fa5650ce9e2f599e Mon Sep 17 00:00:00 2001 |
| 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
| 3 | Date: Wed, 17 Oct 2018 16:56:14 +0530 |
| 4 | Subject: [PATCH 52/54] fixing the 32bit LTO related issue9(1014024) |
| 5 | |
| 6 | --- |
| 7 | gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- |
| 8 | 1 file changed, 14 insertions(+), 10 deletions(-) |
| 9 | |
| 10 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
| 11 | index 0a5ff0a..740b8d9 100644 |
| 12 | --- a/gcc/config/microblaze/microblaze.h |
| 13 | +++ b/gcc/config/microblaze/microblaze.h |
| 14 | @@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; |
| 15 | #define WORD_REGISTER_OPERATIONS 1 |
| 16 | |
| 17 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
| 18 | -/* |
| 19 | -#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
| 20 | - if (GET_MODE_CLASS (MODE) == MODE_INT \ |
| 21 | - && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ |
| 22 | - (MODE) = TARGET_MB_64 ? DImode : SImode; |
| 23 | -*/ |
| 24 | + |
| 25 | +#ifndef __arch64__ |
| 26 | +#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
| 27 | + if (GET_MODE_CLASS (MODE) == MODE_INT \ |
| 28 | + && GET_MODE_SIZE (MODE) < 4) \ |
| 29 | + (MODE) = SImode; |
| 30 | +#endif |
| 31 | + |
| 32 | /* Standard register usage. */ |
| 33 | |
| 34 | /* On the MicroBlaze, we have 32 integer registers */ |
| 35 | @@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info; |
| 36 | |
| 37 | #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS |
| 38 | |
| 39 | +#ifdef __aarch64__ |
| 40 | #define LIBCALL_VALUE(MODE) \ |
| 41 | gen_rtx_REG (MODE,GP_RETURN) |
| 42 | - |
| 43 | -/*#define LIBCALL_VALUE(MODE) \ |
| 44 | +#else |
| 45 | +#define LIBCALL_VALUE(MODE) \ |
| 46 | gen_rtx_REG ( \ |
| 47 | ((GET_MODE_CLASS (MODE) != MODE_INT \ |
| 48 | || GET_MODE_SIZE (MODE) >= 4) \ |
| 49 | ? (MODE) \ |
| 50 | : SImode), GP_RETURN) |
| 51 | -*/ |
| 52 | +#endif |
| 53 | + |
| 54 | /* 1 if N is a possible register number for a function value. |
| 55 | On the MicroBlaze, R2 R3 are the only register thus used. |
| 56 | Currently, R2 are only implemented here (C has no complex type) */ |
| 57 | @@ -518,7 +522,7 @@ typedef struct microblaze_args |
| 58 | /* 4 insns + 2 words of data. */ |
| 59 | #define TRAMPOLINE_SIZE (6 * 4) |
| 60 | |
| 61 | -#define TRAMPOLINE_ALIGNMENT 64 |
| 62 | +#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32) |
| 63 | |
| 64 | #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) |
| 65 | |
| 66 | -- |
| 67 | 2.7.4 |
| 68 | |