blob: 0f678d39ccccf1b934f9179f20d39825752712a9 [file] [log] [blame]
Brad Bishop286d45c2018-10-02 15:21:57 -04001/*
2 * CAUTION: This file is automatically generated by Xilinx.
3 * Version: HSI 2015.4
4 * Today is: Fri Mar 4 15:40:49 2016
5*/
6
7
8/ {
9 cpus {
10 cpu@0 {
11 operating-points = <650000 1000000 325000 1000000>;
12 };
13 };
14};
15&gem0 {
16 phy-mode = "rgmii-id";
17 status = "okay";
18 xlnx,ptp-enet-clock = <0x6750918>;
19};
20&gpio0 {
21 emio-gpio-width = <64>;
22 gpio-mask-high = <0x0>;
23 gpio-mask-low = <0x5600>;
24};
25&i2c0 {
26 clock-frequency = <400000>;
27 status = "okay";
28};
29&i2c1 {
30 clock-frequency = <400000>;
31 status = "okay";
32};
33&intc {
34 num_cpus = <2>;
35 num_interrupts = <96>;
36};
37&qspi {
38 is-dual = <0>;
39 num-cs = <1>;
40 status = "okay";
41};
42&sdhci0 {
43 status = "okay";
44 xlnx,has-cd = <0x1>;
45 xlnx,has-power = <0x0>;
46 xlnx,has-wp = <0x1>;
47};
48&uart1 {
49 current-speed = <115200>;
50 device_type = "serial";
51 port-number = <0>;
52 status = "okay";
53};
54&usb0 {
55 dr_mode = "host";
56 phy_type = "ulpi";
57 status = "okay";
58 usb-reset = <&gpio0 46 0>;
59};
60&clkc {
61 fclk-enable = <0x3>;
62 ps-clk-frequency = <50000000>;
63};