blob: 7cd11905442b29ee99719503f61481695a8a7849 [file] [log] [blame]
Brad Bishop286d45c2018-10-02 15:21:57 -04001From fb2af2fffb673dbb14d743c8da94c4a83b71c792 Mon Sep 17 00:00:00 2001
2From: David Holsgrove <david.holsgrove@xilinx.com>
3Date: Mon, 26 Nov 2012 17:39:17 +1000
4Subject: [PATCH 07/16] [Patch, microblaze]: Add slr and shr regs and
5 little-endian breakpoint
6
7Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
8Upstream-Status: Pending
9---
10 gdb/microblaze-tdep.c | 10 ++++++++--
11 gdb/microblaze-tdep.h | 6 ++++--
12 gdb/regformats/reg-microblaze.dat | 2 ++
13 3 files changed, 14 insertions(+), 4 deletions(-)
14
15diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
16index 1c6dbfe..0ce4947 100644
17--- a/gdb/microblaze-tdep.c
18+++ b/gdb/microblaze-tdep.c
19@@ -73,7 +73,8 @@ static const char *microblaze_register_names[] =
20 "rpc", "rmsr", "rear", "resr", "rfsr", "rbtr",
21 "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
22 "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
23- "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi"
24+ "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
25+ "rslr", "rshr"
26 };
27
28 #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
29@@ -201,10 +202,15 @@ static const gdb_byte *
30 microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc,
31 int *len)
32 {
33+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
34 static gdb_byte break_insn[] = MICROBLAZE_BREAKPOINT;
35+ static gdb_byte break_insn_le[] = MICROBLAZE_BREAKPOINT_LE;
36
37 *len = sizeof (break_insn);
38- return break_insn;
39+ if (byte_order == BFD_ENDIAN_BIG)
40+ return break_insn;
41+ else
42+ return break_insn_le;
43 }
44
45 /* Allocate and initialize a frame cache. */
46diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
47index 98aa0f5..cd32e9f 100644
48--- a/gdb/microblaze-tdep.h
49+++ b/gdb/microblaze-tdep.h
50@@ -56,7 +56,7 @@ struct microblaze_frame_cache
51 int fp_regnum;
52
53 /* Offsets to saved registers. */
54- int register_offsets[57]; /* Must match MICROBLAZE_NUM_REGS. */
55+ int register_offsets[59]; /* Must match MICROBLAZE_NUM_REGS. */
56
57 /* Table of saved registers. */
58 struct trad_frame_saved_reg *saved_regs;
59@@ -121,7 +121,9 @@ enum microblaze_regnum
60 MICROBLAZE_RTLBX_REGNUM,
61 MICROBLAZE_RTLBSX_REGNUM,
62 MICROBLAZE_RTLBLO_REGNUM,
63- MICROBLAZE_RTLBHI_REGNUM
64+ MICROBLAZE_RTLBHI_REGNUM,
65+ MICROBLAZE_SLR_REGNUM,
66+ MICROBLAZE_SHR_REGNUM
67 };
68
69 /* All registers are 32 bits. */
70diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
71index a5dd0a0..bd8a438 100644
72--- a/gdb/regformats/reg-microblaze.dat
73+++ b/gdb/regformats/reg-microblaze.dat
74@@ -37,3 +37,5 @@ expedite:r1,pc
75 32:ear
76 32:esr
77 32:fsr
78+32:slr
79+32:shr
80--
811.9.0
82