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gerrit.openbmc.org / openbmc / openbmc / 353dbdaaa97d78d064f0638221f57311f21f0bb3 / . / yocto-poky / meta / recipes-devtools / binutils / binutils / 0012-Add-XLP-instructions-support.patch
blob: c56ff915b48cbd697627f976d42bd51a413c6cfe [file] [log] [blame]
Patrick Williamsc124f4f2015-09-15 14:41:29 -0500[diff] [blame]1From 448329ea097447aee73d050045295c5a0ae8519e Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Mon, 2 Mar 2015 01:51:05 +0000
4Subject: [PATCH 12/13] Add XLP instructions support
5
6From 26adb06ce515aadfec08ce13109b4b98287f677b Mon Sep 17 00:00:00 2001
7From: Nebu Philips <nphilips@netlogicmicro.com>
8Date: Fri, 30 Jul 2010 15:10:03 -0700
9Subject: [PATCH] Add support for Netlogic XLP
10
11Using the mipsisa64r2nlm target, add support for XLP from
12Netlogic. Also, update vendor name to NLM wherever applicable.
13---
14 bfd/aoutx.h | 1 +
15 bfd/archures.c | 1 +
16 bfd/bfd-in2.h | 1 +
17 bfd/config.bfd | 5 +++++
18 bfd/cpu-mips.c | 6 ++++--
19 bfd/elfxx-mips.c | 8 ++++++++
20 binutils/readelf.c | 1 +
21 gas/config/tc-mips.c | 4 +++-
22 gas/configure | 3 +++
23 gas/configure.tgt | 2 +-
24 include/elf/mips.h | 1 +
25 include/opcode/mips.h | 10 ++++++++--
26 ld/configure.tgt | 2 ++
27 opcodes/mips-dis.c | 12 +++++-------
28 opcodes/mips-opc.c | 33 +++++++++++++++++++++------------
29 15 files changed, 65 insertions(+), 25 deletions(-)
30
31Upstream-Status: Pending
32
33Signed-off-by: Khem Raj <raj.khem@gmail.com>
34---
35 bfd/aoutx.h | 1 +
36 bfd/archures.c | 1 +
37 bfd/bfd-in2.h | 1 +
38 bfd/config.bfd | 5 +++++
39 bfd/cpu-mips.c | 6 ++++--
40 bfd/elfxx-mips.c | 8 ++++++++
41 binutils/readelf.c | 1 +
42 gas/config/tc-mips.c | 4 +++-
43 gas/configure | 3 +++
44 gas/configure.tgt | 2 +-
45 include/elf/mips.h | 1 +
46 include/opcode/mips.h | 10 ++++++++--
47 ld/configure.tgt | 2 ++
48 opcodes/mips-dis.c | 12 +++++-------
49 opcodes/mips-opc.c | 33 +++++++++++++++++++++------------
50 15 files changed, 65 insertions(+), 25 deletions(-)
51
52diff --git a/bfd/aoutx.h b/bfd/aoutx.h
53index 9385a98..a88df99 100644
54--- a/bfd/aoutx.h
55+++ b/bfd/aoutx.h
56@@ -802,6 +802,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
57 case bfd_mach_mipsisa64r6:
58 case bfd_mach_mips_sb1:
59 case bfd_mach_mips_xlr:
60+ case bfd_mach_mips_xlp:
61 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
62 arch_flags = M_MIPS2;
63 break;
64diff --git a/bfd/archures.c b/bfd/archures.c
65index c9fd6c8..547bd09 100644
66--- a/bfd/archures.c
67+++ b/bfd/archures.c
68@@ -180,6 +180,7 @@ DESCRIPTION
69 .#define bfd_mach_mips_octeonp 6601
70 .#define bfd_mach_mips_octeon2 6502
71 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
72+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *}
73 .#define bfd_mach_mipsisa32 32
74 .#define bfd_mach_mipsisa32r2 33
75 .#define bfd_mach_mipsisa32r3 34
76diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
77index c7a2bb5..413b773 100644
78--- a/bfd/bfd-in2.h
79+++ b/bfd/bfd-in2.h
80@@ -1967,6 +1967,7 @@ enum bfd_architecture
81 #define bfd_mach_mips_octeonp 6601
82 #define bfd_mach_mips_octeon2 6502
83 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
84+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */
85 #define bfd_mach_mipsisa32 32
86 #define bfd_mach_mipsisa32r2 33
87 #define bfd_mach_mipsisa32r3 34
88diff --git a/bfd/config.bfd b/bfd/config.bfd
89index 03d2c6f..27086db 100644
90--- a/bfd/config.bfd
91+++ b/bfd/config.bfd
92@@ -1041,6 +1041,11 @@ case "${targ}" in
93 targ_defvec=mips_elf32_le_vec
94 targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
95 ;;
96+ mipsisa64*-*-elf*)
97+ targ_defvec=mips_elf32_trad_be_vec
98+ targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
99+ want64=true
100+ ;;
101 mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss)
102 targ_defvec=mips_elf32_be_vec
103 targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
104diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
105index b617aaa..19a99d1 100644
106--- a/bfd/cpu-mips.c
107+++ b/bfd/cpu-mips.c
108@@ -103,7 +103,8 @@ enum
109 I_mipsocteonp,
110 I_mipsocteon2,
111 I_xlr,
112- I_micromips
113+ I_micromips,
114+ I_xlp
115 };
116
117 #define NN(index) (&arch_info_struct[(index) + 1])
118@@ -153,7 +154,8 @@ static const bfd_arch_info_type arch_info_struct[] =
119 N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
120 N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
121 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
122- N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
123+ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
124+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0)
125 };
126
127 /* The default architecture is mips:3000, but with a machine number of
128diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
129index 0df7abf..d268e86 100644
130--- a/bfd/elfxx-mips.c
131+++ b/bfd/elfxx-mips.c
132@@ -6608,6 +6608,9 @@ _bfd_elf_mips_mach (flagword flags)
133 case E_MIPS_MACH_XLR:
134 return bfd_mach_mips_xlr;
135
136+ case E_MIPS_MACH_XLP:
137+ return bfd_mach_mips_xlp;
138+
139 default:
140 switch (flags & EF_MIPS_ARCH)
141 {
142@@ -11878,6 +11881,10 @@ mips_set_isa_flags (bfd *abfd)
143 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
144 break;
145
146+ case bfd_mach_mips_xlp:
147+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
148+ break;
149+
150 case bfd_mach_mipsisa32:
151 val = E_MIPS_ARCH_32;
152 break;
153@@ -14765,6 +14772,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
154 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
155 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
156 { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
157+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
158
159 /* MIPS64 extensions. */
160 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
161diff --git a/binutils/readelf.c b/binutils/readelf.c
162index 0c00b2f..6e9d5e4 100644
163--- a/binutils/readelf.c
164+++ b/binutils/readelf.c
165@@ -2898,6 +2898,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
166 case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
167 case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
168 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
169+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
170 case 0:
171 /* We simply ignore the field in this case to avoid confusion:
172 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
173diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
174index c3e3e2a..8d64344 100644
175--- a/gas/config/tc-mips.c
176+++ b/gas/config/tc-mips.c
177@@ -551,6 +551,7 @@ static int mips_32bitmode = 0;
178 || mips_opts.arch == CPU_RM7000 \
179 || mips_opts.arch == CPU_VR5500 \
180 || mips_opts.micromips \
181+ || mips_opts.arch == CPU_XLP \
182 )
183
184 /* Whether the processor uses hardware interlocks to protect reads
185@@ -580,6 +581,7 @@ static int mips_32bitmode = 0;
186 && mips_opts.isa != ISA_MIPS3) \
187 || mips_opts.arch == CPU_R4300 \
188 || mips_opts.micromips \
189+ || mips_opts.arch == CPU_XLP \
190 )
191
192 /* Whether the processor uses hardware interlocks to protect reads
193@@ -18682,7 +18684,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
194 /* Broadcom XLP.
195 XLP is mostly like XLR, with the prominent exception that it is
196 MIPS64R2 rather than MIPS64. */
197- { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
198+ { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP },
199
200 /* End marker */
201 { NULL, 0, 0, 0, 0 }
202diff --git a/gas/configure b/gas/configure
203index 074886f..8091f2f 100755
204--- a/gas/configure
205+++ b/gas/configure
206@@ -12808,6 +12808,9 @@ _ACEOF
207 mipsisa64r6 | mipsisa64r6el)
208 mips_cpu=mips64r6
209 ;;
210+ mipsisa64r2nlm | mipsisa64r2nlmel)
211+ mips_cpu=xlp
212+ ;;
213 mipstx39 | mipstx39el)
214 mips_cpu=r3900
215 ;;
216diff --git a/gas/configure.tgt b/gas/configure.tgt
217index 1d92f55..06e8b4f 100644
218--- a/gas/configure.tgt
219+++ b/gas/configure.tgt
220@@ -332,7 +332,7 @@ case ${generic_target} in
221 mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;;
222 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
223 fmt=elf em=tmips ;;
224- mips-*-elf* | mips-*-rtems*) fmt=elf ;;
225+ mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;;
226 mips-*-netbsd*) fmt=elf em=tmips ;;
227 mips-*-openbsd*) fmt=elf em=tmips ;;
228
229diff --git a/include/elf/mips.h b/include/elf/mips.h
230index 2ed6acd..e541f50 100644
231--- a/include/elf/mips.h
232+++ b/include/elf/mips.h
233@@ -285,6 +285,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
234 #define E_MIPS_MACH_SB1 0x008a0000
235 #define E_MIPS_MACH_OCTEON 0x008b0000
236 #define E_MIPS_MACH_XLR 0x008c0000
237+#define E_MIPS_MACH_XLP 0x008f0000
238 #define E_MIPS_MACH_OCTEON2 0x008d0000
239 #define E_MIPS_MACH_OCTEON3 0x008e0000
240 #define E_MIPS_MACH_5400 0x00910000
241diff --git a/include/opcode/mips.h b/include/opcode/mips.h
242index ef26167..ef53ec6 100644
243--- a/include/opcode/mips.h
244+++ b/include/opcode/mips.h
245@@ -1227,8 +1227,10 @@ static const unsigned int mips_isa_table[] = {
246 #define INSN_LOONGSON_2F 0x80000000
247 /* Loongson 3A. */
248 #define INSN_LOONGSON_3A 0x00000400
249-/* RMI Xlr instruction */
250-#define INSN_XLR 0x00000020
251+/* Netlogic Xlr instruction */
252+#define INSN_XLR 0x00000020
253+/* Netlogic XlP instruction */
254+#define INSN_XLP 0x00000040
255
256 /* DSP ASE */
257 #define ASE_DSP 0x00000001
258@@ -1324,6 +1326,7 @@ static const unsigned int mips_isa_table[] = {
259 #define CPU_OCTEONP 6601
260 #define CPU_OCTEON2 6502
261 #define CPU_XLR 887682 /* decimal 'XLR' */
262+#define CPU_XLP 887680 /* decimal 'XLP' */
263
264 /* Return true if the given CPU is included in INSN_* mask MASK. */
265
266@@ -1398,6 +1401,9 @@ cpu_is_member (int cpu, unsigned int mask)
267 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
268 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
269
270+ case CPU_XLP:
271+ return (mask & INSN_XLP) != 0;
272+
273 default:
274 return FALSE;
275 }
276diff --git a/ld/configure.tgt b/ld/configure.tgt
277index 740b2ea..4df13a7 100644
278--- a/ld/configure.tgt
279+++ b/ld/configure.tgt
280@@ -462,6 +462,8 @@ mips*el-sde-elf*) targ_emul=elf32ltsmip
281 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
282 targ_emul=elf32btsmip
283 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
284+mipsisa64*-*-elf*) targ_emul=elf32btsmip
285+ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;;
286 mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
287 targ_extra_emuls="elf32lr5900"
288 targ_extra_libpath=$targ_extra_emuls ;;
289diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
290index 1eb1d45..d6881af 100644
291--- a/opcodes/mips-dis.c
292+++ b/opcodes/mips-dis.c
293@@ -655,13 +655,11 @@ const struct mips_arch_choice mips_arch_choices[] =
294 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
295 mips_cp1_names_mips3264, mips_hwr_names_numeric },
296
297- /* XLP is mostly like XLR, with the prominent exception it is being
298- MIPS64R2. */
299- { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
300- ISA_MIPS64R2 | INSN_XLR, 0,
301- mips_cp0_names_xlr,
302- mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
303- mips_cp1_names_mips3264, mips_hwr_names_numeric },
304+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
305+ ISA_MIPS64R2 | INSN_XLP, 0,
306+ mips_cp0_names_mips3264r2,
307+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
308+ mips_hwr_names_mips3264r2 },
309
310 /* This entry, mips16, is here only for ISA/processor selection; do
311 not print its name. */
312diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
313index 2c3bbad..9785a7e 100644
314--- a/opcodes/mips-opc.c
315+++ b/opcodes/mips-opc.c
316@@ -319,7 +319,8 @@ decode_mips_operand (const char *p)
317 #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
318 #define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
319 #define IOCT2 INSN_OCTEON2
320-#define XLR INSN_XLR
321+#define XLR INSN_XLR
322+#define XLP INSN_XLP
323 #define IVIRT ASE_VIRT
324 #define IVIRT64 ASE_VIRT64
325
326@@ -956,6 +957,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
327 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
328 {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
329 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
330+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
331 /* ctc0 is at the bottom of the table. */
332 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
333 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
334@@ -988,12 +990,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
335 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
336 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
337 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
338-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
339+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 },
340 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
341 {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
342 {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
343 {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
344 {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
345+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
346 /* dctr and dctw are used on the r5000. */
347 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
348 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
349@@ -1065,6 +1068,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
350 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
351 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
352 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
353+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 },
354 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
355 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
356 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
357@@ -1080,6 +1084,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
358 /* dmfc3 is at the bottom of the table. */
359 /* dmtc3 is at the bottom of the table. */
360 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
361+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 },
362+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
363 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
364 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
365 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
366@@ -1229,9 +1235,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
367 {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
368 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
369 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
370-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
371-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
372-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
373+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
374+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
375+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
376 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
377 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
378 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
379@@ -1396,7 +1402,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
380 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
381 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
382 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
383-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 },
384+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 },
385 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
386 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
387 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
388@@ -1441,10 +1447,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
389 /* move is at the top of the table. */
390 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
391 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
392+{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
393 {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 },
394 {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 },
395-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 },
396-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 },
397+{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
398+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 },
399+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 },
400+{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 },
401 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
402 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
403 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
404@@ -1494,7 +1503,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
405 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
406 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
407 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
408-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
409+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
410 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
411 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
412 {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
413@@ -1924,9 +1933,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
414 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
415 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
416 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
417-{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
418-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
419-{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
420+{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
421+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
422+{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
423 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
424 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
425 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
426--
4272.1.4
428