Andrew Geissler | 0903674 | 2021-06-25 14:25:14 -0500 | [diff] [blame] | 1 | From 4186b7e93be73f8d68dc0fcc00a4cc8cc83e99a8 Mon Sep 17 00:00:00 2001 |
| 2 | From: Claudiu Zissulescu <claziss@synopsys.com> |
| 3 | Date: Wed, 9 Jun 2021 12:12:57 +0300 |
| 4 | Subject: [PATCH] arc: Fix (u)maddhisi patterns |
| 5 | |
| 6 | Rework the (u)maddhisi4 patterns and use VMAC2H(U) instruction instead |
| 7 | of the 64bit MAC(U) instruction. |
| 8 | This fixes the next execute.exp failures: |
| 9 | arith-rand-ll.c -O2 execution test |
| 10 | arith-rand-ll.c -O3 execution test |
| 11 | pr78726.c -O2 execution test |
| 12 | pr78726.c -O3 execution test |
| 13 | |
| 14 | gcc/ |
| 15 | 2021-06-09 Claudiu Zissulescu <claziss@synopsys.com> |
| 16 | |
| 17 | * config/arc/arc.md (maddhisi4): Use VMAC2H instruction. |
| 18 | (machi): New pattern. |
| 19 | (umaddhisi4): Use VMAC2HU instruction. |
| 20 | (umachi): New pattern. |
| 21 | |
| 22 | Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4186b7e93be73f8d68dc0fcc00a4cc8cc83e99a8] |
| 23 | |
| 24 | Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> |
| 25 | (cherry picked from commit dd4778a59b4693777c732075021375e19eee6a76) |
| 26 | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> |
| 27 | --- |
| 28 | gcc/config/arc/arc.md | 66 ++++++++++++++++++++++++++++++++------------------- |
| 29 | 1 file changed, 41 insertions(+), 25 deletions(-) |
| 30 | |
| 31 | diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md |
| 32 | index 91a838a38e4..2a7e087ff72 100644 |
| 33 | --- a/gcc/config/arc/arc.md |
| 34 | +++ b/gcc/config/arc/arc.md |
| 35 | @@ -6053,48 +6053,64 @@ core_3, archs4x, archs4xd, archs4xd_slow" |
| 36 | |
| 37 | ;; MAC and DMPY instructions |
| 38 | |
| 39 | -; Use MAC instruction to emulate 16bit mac. |
| 40 | +; Use VMAC2H(U) instruction to emulate scalar 16bit mac. |
| 41 | (define_expand "maddhisi4" |
| 42 | [(match_operand:SI 0 "register_operand" "") |
| 43 | (match_operand:HI 1 "register_operand" "") |
| 44 | (match_operand:HI 2 "extend_operand" "") |
| 45 | (match_operand:SI 3 "register_operand" "")] |
| 46 | - "TARGET_PLUS_DMPY" |
| 47 | + "TARGET_PLUS_MACD" |
| 48 | "{ |
| 49 | - rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); |
| 50 | - rtx tmp1 = gen_reg_rtx (SImode); |
| 51 | - rtx tmp2 = gen_reg_rtx (SImode); |
| 52 | - rtx accl = gen_lowpart (SImode, acc_reg); |
| 53 | - |
| 54 | - emit_move_insn (accl, operands[3]); |
| 55 | - emit_insn (gen_rtx_SET (tmp1, gen_rtx_SIGN_EXTEND (SImode, operands[1]))); |
| 56 | - emit_insn (gen_rtx_SET (tmp2, gen_rtx_SIGN_EXTEND (SImode, operands[2]))); |
| 57 | - emit_insn (gen_mac (tmp1, tmp2)); |
| 58 | - emit_move_insn (operands[0], accl); |
| 59 | + rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST); |
| 60 | + |
| 61 | + emit_move_insn (acc_reg, operands[3]); |
| 62 | + emit_insn (gen_machi (operands[1], operands[2])); |
| 63 | + emit_move_insn (operands[0], acc_reg); |
| 64 | DONE; |
| 65 | }") |
| 66 | |
| 67 | -; The same for the unsigned variant, but using MACU instruction. |
| 68 | +(define_insn "machi" |
| 69 | + [(set (reg:SI ARCV2_ACC) |
| 70 | + (plus:SI |
| 71 | + (mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r")) |
| 72 | + (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))) |
| 73 | + (reg:SI ARCV2_ACC)))] |
| 74 | + "TARGET_PLUS_MACD" |
| 75 | + "vmac2h\\t0,%0,%1" |
| 76 | + [(set_attr "length" "4") |
| 77 | + (set_attr "type" "multi") |
| 78 | + (set_attr "predicable" "no") |
| 79 | + (set_attr "cond" "nocond")]) |
| 80 | + |
| 81 | +; The same for the unsigned variant, but using VMAC2HU instruction. |
| 82 | (define_expand "umaddhisi4" |
| 83 | [(match_operand:SI 0 "register_operand" "") |
| 84 | (match_operand:HI 1 "register_operand" "") |
| 85 | - (match_operand:HI 2 "extend_operand" "") |
| 86 | + (match_operand:HI 2 "register_operand" "") |
| 87 | (match_operand:SI 3 "register_operand" "")] |
| 88 | - "TARGET_PLUS_DMPY" |
| 89 | + "TARGET_PLUS_MACD" |
| 90 | "{ |
| 91 | - rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); |
| 92 | - rtx tmp1 = gen_reg_rtx (SImode); |
| 93 | - rtx tmp2 = gen_reg_rtx (SImode); |
| 94 | - rtx accl = gen_lowpart (SImode, acc_reg); |
| 95 | - |
| 96 | - emit_move_insn (accl, operands[3]); |
| 97 | - emit_insn (gen_rtx_SET (tmp1, gen_rtx_ZERO_EXTEND (SImode, operands[1]))); |
| 98 | - emit_insn (gen_rtx_SET (tmp2, gen_rtx_ZERO_EXTEND (SImode, operands[2]))); |
| 99 | - emit_insn (gen_macu (tmp1, tmp2)); |
| 100 | - emit_move_insn (operands[0], accl); |
| 101 | + rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST); |
| 102 | + |
| 103 | + emit_move_insn (acc_reg, operands[3]); |
| 104 | + emit_insn (gen_umachi (operands[1], operands[2])); |
| 105 | + emit_move_insn (operands[0], acc_reg); |
| 106 | DONE; |
| 107 | }") |
| 108 | |
| 109 | +(define_insn "umachi" |
| 110 | + [(set (reg:SI ARCV2_ACC) |
| 111 | + (plus:SI |
| 112 | + (mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r")) |
| 113 | + (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))) |
| 114 | + (reg:SI ARCV2_ACC)))] |
| 115 | + "TARGET_PLUS_MACD" |
| 116 | + "vmac2hu\\t0,%0,%1" |
| 117 | + [(set_attr "length" "4") |
| 118 | + (set_attr "type" "multi") |
| 119 | + (set_attr "predicable" "no") |
| 120 | + (set_attr "cond" "nocond")]) |
| 121 | + |
| 122 | (define_expand "maddsidi4" |
| 123 | [(match_operand:DI 0 "register_operand" "") |
| 124 | (match_operand:SI 1 "register_operand" "") |
| 125 | -- |
| 126 | 2.16.2 |
| 127 | |