Brad Bishop | bec4ebc | 2022-08-03 09:55:16 -0400 | [diff] [blame] | 1 | From 5cc889db3279ef4944ab64e36db3dbab1bf9ffa5 Mon Sep 17 00:00:00 2001 |
| 2 | From: Rui Miguel Silva <rui.silva@linaro.org> |
| 3 | Date: Tue, 15 Feb 2022 09:44:10 +0000 |
| 4 | Subject: [PATCH 02/27] arm: add support to corstone1000 platform |
| 5 | |
| 6 | Corstone1000 is a platform from arm, which includes pre |
| 7 | verified Corstone SSE710 sub-system that combines Cortex-A and |
| 8 | Cortex-M processors [0]. |
| 9 | |
| 10 | This code adds the support for the Cortex-A35 implementation |
| 11 | at host side, it contains also the necessary bits to support |
| 12 | the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the |
| 13 | FPGA MPS3 board implementation of this platform. [2] |
| 14 | |
| 15 | 0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16 |
| 16 | 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps |
| 17 | 2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf |
| 18 | |
| 19 | Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
| 20 | Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> |
| 21 | --- |
| 22 | arch/arm/Kconfig | 8 ++ |
| 23 | arch/arm/dts/Makefile | 3 + |
| 24 | arch/arm/dts/corstone1000-fvp.dts | 23 +++ |
| 25 | arch/arm/dts/corstone1000-mps3.dts | 32 +++++ |
| 26 | arch/arm/dts/corstone1000.dtsi | 169 +++++++++++++++++++++++ |
| 27 | board/armltd/corstone1000/Kconfig | 12 ++ |
| 28 | board/armltd/corstone1000/MAINTAINERS | 7 + |
| 29 | board/armltd/corstone1000/Makefile | 7 + |
| 30 | board/armltd/corstone1000/corstone1000.c | 121 ++++++++++++++++ |
| 31 | configs/corstone1000_defconfig | 80 +++++++++++ |
| 32 | include/configs/corstone1000.h | 86 ++++++++++++ |
| 33 | 11 files changed, 548 insertions(+) |
| 34 | create mode 100644 arch/arm/dts/corstone1000-fvp.dts |
| 35 | create mode 100644 arch/arm/dts/corstone1000-mps3.dts |
| 36 | create mode 100644 arch/arm/dts/corstone1000.dtsi |
| 37 | create mode 100644 board/armltd/corstone1000/Kconfig |
| 38 | create mode 100644 board/armltd/corstone1000/MAINTAINERS |
| 39 | create mode 100644 board/armltd/corstone1000/Makefile |
| 40 | create mode 100644 board/armltd/corstone1000/corstone1000.c |
| 41 | create mode 100644 configs/corstone1000_defconfig |
| 42 | create mode 100644 include/configs/corstone1000.h |
| 43 | |
| 44 | diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig |
| 45 | index 4567c183fb84..d64051b533a7 100644 |
| 46 | --- a/arch/arm/Kconfig |
| 47 | +++ b/arch/arm/Kconfig |
| 48 | @@ -1266,6 +1266,12 @@ config TARGET_VEXPRESS64_JUNO |
| 49 | select USB |
| 50 | imply OF_HAS_PRIOR_STAGE |
| 51 | |
| 52 | +config TARGET_CORSTONE1000 |
| 53 | + bool "Support Corstone1000 Platform" |
| 54 | + select ARM64 |
| 55 | + select PL01X_SERIAL |
| 56 | + select DM |
| 57 | + |
| 58 | config TARGET_TOTAL_COMPUTE |
| 59 | bool "Support Total Compute Platform" |
| 60 | select ARM64 |
| 61 | @@ -2198,6 +2204,8 @@ source "arch/arm/mach-nexell/Kconfig" |
| 62 | |
| 63 | source "board/armltd/total_compute/Kconfig" |
| 64 | |
| 65 | +source "board/armltd/corstone1000/Kconfig" |
| 66 | + |
| 67 | source "board/bosch/shc/Kconfig" |
| 68 | source "board/bosch/guardian/Kconfig" |
| 69 | source "board/Marvell/octeontx/Kconfig" |
| 70 | diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile |
| 71 | index 644ba961a223..7de25d09c9fe 100644 |
| 72 | --- a/arch/arm/dts/Makefile |
| 73 | +++ b/arch/arm/dts/Makefile |
| 74 | @@ -1215,6 +1215,9 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb |
| 75 | |
| 76 | dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb |
| 77 | |
| 78 | +dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ |
| 79 | + corstone1000-fvp.dtb |
| 80 | + |
| 81 | include $(srctree)/scripts/Makefile.dts |
| 82 | |
| 83 | targets += $(dtb-y) |
| 84 | diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts |
| 85 | new file mode 100644 |
| 86 | index 000000000000..1fcc137a493c |
| 87 | --- /dev/null |
| 88 | +++ b/arch/arm/dts/corstone1000-fvp.dts |
| 89 | @@ -0,0 +1,23 @@ |
| 90 | +// SPDX-License-Identifier: GPL-2.0 or MIT |
| 91 | +/* |
| 92 | + * Copyright (c) 2022, Arm Limited. All rights reserved. |
| 93 | + * Copyright (c) 2022, Linaro Limited. All rights reserved. |
| 94 | + * |
| 95 | + */ |
| 96 | + |
| 97 | +/dts-v1/; |
| 98 | + |
| 99 | +#include "corstone1000.dtsi" |
| 100 | + |
| 101 | +/ { |
| 102 | + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; |
| 103 | + compatible = "arm,corstone1000-fvp"; |
| 104 | + |
| 105 | + smsc: ethernet@4010000 { |
| 106 | + compatible = "smsc,lan91c111"; |
| 107 | + reg = <0x40100000 0x10000>; |
| 108 | + phy-mode = "mii"; |
| 109 | + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| 110 | + reg-io-width = <2>; |
| 111 | + }; |
| 112 | +}; |
| 113 | diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts |
| 114 | new file mode 100644 |
| 115 | index 000000000000..e3146747c2d9 |
| 116 | --- /dev/null |
| 117 | +++ b/arch/arm/dts/corstone1000-mps3.dts |
| 118 | @@ -0,0 +1,32 @@ |
| 119 | +// SPDX-License-Identifier: GPL-2.0 or MIT |
| 120 | +/* |
| 121 | + * Copyright (c) 2022, Arm Limited. All rights reserved. |
| 122 | + * Copyright (c) 2022, Linaro Limited. All rights reserved. |
| 123 | + * |
| 124 | + */ |
| 125 | + |
| 126 | +/dts-v1/; |
| 127 | + |
| 128 | +#include "corstone1000.dtsi" |
| 129 | + |
| 130 | +/ { |
| 131 | + model = "ARM Corstone1000 FPGA MPS3 board"; |
| 132 | + compatible = "arm,corstone1000-mps3"; |
| 133 | + |
| 134 | + smsc: ethernet@4010000 { |
| 135 | + compatible = "smsc,lan9220", "smsc,lan9115"; |
| 136 | + reg = <0x40100000 0x10000>; |
| 137 | + phy-mode = "mii"; |
| 138 | + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| 139 | + reg-io-width = <2>; |
| 140 | + smsc,irq-push-pull; |
| 141 | + }; |
| 142 | + |
| 143 | + usb_host: usb@40200000 { |
| 144 | + compatible = "nxp,usb-isp1763"; |
| 145 | + reg = <0x40200000 0x100000>; |
| 146 | + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| 147 | + bus-width = <16>; |
| 148 | + dr_mode = "host"; |
| 149 | + }; |
| 150 | +}; |
| 151 | diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi |
| 152 | new file mode 100644 |
| 153 | index 000000000000..d0194aa893f2 |
| 154 | --- /dev/null |
| 155 | +++ b/arch/arm/dts/corstone1000.dtsi |
| 156 | @@ -0,0 +1,169 @@ |
| 157 | +// SPDX-License-Identifier: GPL-2.0 or MIT |
| 158 | +/* |
| 159 | + * Copyright (c) 2022, Arm Limited. All rights reserved. |
| 160 | + * Copyright (c) 2022, Linaro Limited. All rights reserved. |
| 161 | + * |
| 162 | + */ |
| 163 | + |
| 164 | +#include <dt-bindings/interrupt-controller/arm-gic.h> |
| 165 | + |
| 166 | +/ { |
| 167 | + interrupt-parent = <&gic>; |
| 168 | + #address-cells = <1>; |
| 169 | + #size-cells = <1>; |
| 170 | + |
| 171 | + aliases { |
| 172 | + serial0 = &uart0; |
| 173 | + serial1 = &uart1; |
| 174 | + }; |
| 175 | + |
| 176 | + chosen { |
| 177 | + stdout-path = "serial0:115200n8"; |
| 178 | + }; |
| 179 | + |
| 180 | + cpus { |
| 181 | + #address-cells = <1>; |
| 182 | + #size-cells = <0>; |
| 183 | + |
| 184 | + cpu: cpu@0 { |
| 185 | + device_type = "cpu"; |
| 186 | + compatible = "arm,cortex-a35"; |
| 187 | + reg = <0>; |
| 188 | + next-level-cache = <&L2_0>; |
| 189 | + }; |
| 190 | + }; |
| 191 | + |
| 192 | + memory@88200000 { |
| 193 | + device_type = "memory"; |
| 194 | + reg = <0x88200000 0x77e00000>; |
| 195 | + }; |
| 196 | + |
| 197 | + gic: interrupt-controller@1c000000 { |
| 198 | + compatible = "arm,gic-400"; |
| 199 | + #interrupt-cells = <3>; |
| 200 | + #address-cells = <0>; |
| 201 | + interrupt-controller; |
| 202 | + reg = <0x1c010000 0x1000>, |
| 203 | + <0x1c02f000 0x2000>, |
| 204 | + <0x1c04f000 0x1000>, |
| 205 | + <0x1c06f000 0x2000>; |
| 206 | + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | |
| 207 | + IRQ_TYPE_LEVEL_LOW)>; |
| 208 | + }; |
| 209 | + |
| 210 | + L2_0: l2-cache0 { |
| 211 | + compatible = "cache"; |
| 212 | + cache-level = <2>; |
| 213 | + cache-size = <0x80000>; |
| 214 | + cache-line-size = <64>; |
| 215 | + cache-sets = <1024>; |
| 216 | + }; |
| 217 | + |
| 218 | + refclk100mhz: refclk100mhz { |
| 219 | + compatible = "fixed-clock"; |
| 220 | + #clock-cells = <0>; |
| 221 | + clock-frequency = <100000000>; |
| 222 | + clock-output-names = "apb_pclk"; |
| 223 | + }; |
| 224 | + |
| 225 | + smbclk: refclk24mhzx2 { |
| 226 | + /* Reference 24MHz clock x 2 */ |
| 227 | + compatible = "fixed-clock"; |
| 228 | + #clock-cells = <0>; |
| 229 | + clock-frequency = <48000000>; |
| 230 | + clock-output-names = "smclk"; |
| 231 | + }; |
| 232 | + |
| 233 | + timer { |
| 234 | + compatible = "arm,armv8-timer"; |
| 235 | + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | |
| 236 | + IRQ_TYPE_LEVEL_LOW)>, |
| 237 | + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | |
| 238 | + IRQ_TYPE_LEVEL_LOW)>, |
| 239 | + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | |
| 240 | + IRQ_TYPE_LEVEL_LOW)>, |
| 241 | + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | |
| 242 | + IRQ_TYPE_LEVEL_LOW)>; |
| 243 | + }; |
| 244 | + |
| 245 | + uartclk: uartclk { |
| 246 | + /* UART clock - 50MHz */ |
| 247 | + compatible = "fixed-clock"; |
| 248 | + #clock-cells = <0>; |
| 249 | + clock-frequency = <50000000>; |
| 250 | + clock-output-names = "uartclk"; |
| 251 | + }; |
| 252 | + |
| 253 | + psci { |
| 254 | + compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| 255 | + method = "smc"; |
| 256 | + }; |
| 257 | + |
| 258 | + soc { |
| 259 | + compatible = "simple-bus"; |
| 260 | + #address-cells = <1>; |
| 261 | + #size-cells = <1>; |
| 262 | + interrupt-parent = <&gic>; |
| 263 | + ranges; |
| 264 | + |
| 265 | + timer@1a220000 { |
| 266 | + compatible = "arm,armv7-timer-mem"; |
| 267 | + reg = <0x1a220000 0x1000>; |
| 268 | + #address-cells = <1>; |
| 269 | + #size-cells = <1>; |
| 270 | + clock-frequency = <50000000>; |
| 271 | + ranges; |
| 272 | + |
| 273 | + frame@1a230000 { |
| 274 | + frame-number = <0>; |
| 275 | + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 276 | + reg = <0x1a230000 0x1000>; |
| 277 | + }; |
| 278 | + }; |
| 279 | + |
| 280 | + uart0: serial@1a510000 { |
| 281 | + compatible = "arm,pl011", "arm,primecell"; |
| 282 | + reg = <0x1a510000 0x1000>; |
| 283 | + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 284 | + clocks = <&uartclk>, <&refclk100mhz>; |
| 285 | + clock-names = "uartclk", "apb_pclk"; |
| 286 | + }; |
| 287 | + |
| 288 | + uart1: serial@1a520000 { |
| 289 | + compatible = "arm,pl011", "arm,primecell"; |
| 290 | + reg = <0x1a520000 0x1000>; |
| 291 | + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 292 | + clocks = <&uartclk>, <&refclk100mhz>; |
| 293 | + clock-names = "uartclk", "apb_pclk"; |
| 294 | + }; |
| 295 | + |
| 296 | + mhu_hse1: mailbox@1b820000 { |
| 297 | + compatible = "arm,mhuv2-tx", "arm,primecell"; |
| 298 | + reg = <0x1b820000 0x1000>; |
| 299 | + clocks = <&refclk100mhz>; |
| 300 | + clock-names = "apb_pclk"; |
| 301 | + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 302 | + #mbox-cells = <2>; |
| 303 | + arm,mhuv2-protocols = <0 0>; |
| 304 | + secure-status = "okay"; /* secure-world-only */ |
| 305 | + status = "disabled"; |
| 306 | + }; |
| 307 | + |
| 308 | + mhu_seh1: mailbox@1b830000 { |
| 309 | + compatible = "arm,mhuv2-rx", "arm,primecell"; |
| 310 | + reg = <0x1b830000 0x1000>; |
| 311 | + clocks = <&refclk100mhz>; |
| 312 | + clock-names = "apb_pclk"; |
| 313 | + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 314 | + #mbox-cells = <2>; |
| 315 | + arm,mhuv2-protocols = <0 0>; |
| 316 | + secure-status = "okay"; /* secure-world-only */ |
| 317 | + status = "disabled"; |
| 318 | + }; |
| 319 | + }; |
| 320 | + |
| 321 | + arm_ffa: arm_ffa { |
| 322 | + compatible = "arm,ffa"; |
| 323 | + method = "smc"; |
| 324 | + }; |
| 325 | +}; |
| 326 | diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig |
| 327 | new file mode 100644 |
| 328 | index 000000000000..709674d4cf7d |
| 329 | --- /dev/null |
| 330 | +++ b/board/armltd/corstone1000/Kconfig |
| 331 | @@ -0,0 +1,12 @@ |
| 332 | +if TARGET_CORSTONE1000 |
| 333 | + |
| 334 | +config SYS_BOARD |
| 335 | + default "corstone1000" |
| 336 | + |
| 337 | +config SYS_VENDOR |
| 338 | + default "armltd" |
| 339 | + |
| 340 | +config SYS_CONFIG_NAME |
| 341 | + default "corstone1000" |
| 342 | + |
| 343 | +endif |
| 344 | diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS |
| 345 | new file mode 100644 |
| 346 | index 000000000000..8c905686de76 |
| 347 | --- /dev/null |
| 348 | +++ b/board/armltd/corstone1000/MAINTAINERS |
| 349 | @@ -0,0 +1,7 @@ |
| 350 | +CORSTONE1000 BOARD |
| 351 | +M: Rui Miguel Silva <rui.silva@linaro.org> |
| 352 | +M: Vishnu Banavath <vishnu.banavath@arm.com> |
| 353 | +S: Maintained |
| 354 | +F: board/armltd/corstone1000/ |
| 355 | +F: include/configs/corstone1000.h |
| 356 | +F: configs/corstone1000_defconfig |
| 357 | diff --git a/board/armltd/corstone1000/Makefile b/board/armltd/corstone1000/Makefile |
| 358 | new file mode 100644 |
| 359 | index 000000000000..77a82c28929b |
| 360 | --- /dev/null |
| 361 | +++ b/board/armltd/corstone1000/Makefile |
| 362 | @@ -0,0 +1,7 @@ |
| 363 | +# SPDX-License-Identifier: GPL-2.0+ |
| 364 | +# |
| 365 | +# (C) Copyright 2022 Arm Limited |
| 366 | +# (C) Copyright 2022 Linaro |
| 367 | +# Rui Miguel Silva <rui.silva@linaro.org> |
| 368 | + |
| 369 | +obj-y := corstone1000.o |
| 370 | diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c |
| 371 | new file mode 100644 |
| 372 | index 000000000000..eff1739f0b02 |
| 373 | --- /dev/null |
| 374 | +++ b/board/armltd/corstone1000/corstone1000.c |
| 375 | @@ -0,0 +1,121 @@ |
| 376 | +// SPDX-License-Identifier: GPL-2.0+ |
| 377 | +/* |
| 378 | + * (C) Copyright 2022 ARM Limited |
| 379 | + * (C) Copyright 2022 Linaro |
| 380 | + * Rui Miguel Silva <rui.silva@linaro.org> |
| 381 | + */ |
| 382 | + |
| 383 | +#include <common.h> |
| 384 | +#include <dm.h> |
| 385 | +#include <dm/platform_data/serial_pl01x.h> |
| 386 | +#include <asm/armv8/mmu.h> |
| 387 | +#include <asm/global_data.h> |
| 388 | + |
| 389 | + |
| 390 | +static const struct pl01x_serial_plat serial_plat = { |
| 391 | + .base = V2M_UART0, |
| 392 | + .type = TYPE_PL011, |
| 393 | + .clock = CONFIG_PL011_CLOCK, |
| 394 | +}; |
| 395 | + |
| 396 | +U_BOOT_DRVINFO(corstone1000_serials) = { |
| 397 | + .name = "serial_pl01x", |
| 398 | + .plat = &serial_plat, |
| 399 | +}; |
| 400 | + |
| 401 | +static struct mm_region corstone1000_mem_map[] = { |
| 402 | + { |
| 403 | + /* CVM */ |
| 404 | + .virt = 0x02000000UL, |
| 405 | + .phys = 0x02000000UL, |
| 406 | + .size = 0x02000000UL, |
| 407 | + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 408 | + PTE_BLOCK_INNER_SHARE |
| 409 | + }, { |
| 410 | + /* QSPI */ |
| 411 | + .virt = 0x08000000UL, |
| 412 | + .phys = 0x08000000UL, |
| 413 | + .size = 0x08000000UL, |
| 414 | + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 415 | + PTE_BLOCK_INNER_SHARE |
| 416 | + }, { |
| 417 | + /* Host Peripherals */ |
| 418 | + .virt = 0x1A000000UL, |
| 419 | + .phys = 0x1A000000UL, |
| 420 | + .size = 0x26000000UL, |
| 421 | + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 422 | + PTE_BLOCK_NON_SHARE | |
| 423 | + PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 424 | + }, { |
| 425 | + /* USB */ |
| 426 | + .virt = 0x40200000UL, |
| 427 | + .phys = 0x40200000UL, |
| 428 | + .size = 0x00100000UL, |
| 429 | + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 430 | + PTE_BLOCK_NON_SHARE | |
| 431 | + PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 432 | + }, { |
| 433 | + /* ethernet */ |
| 434 | + .virt = 0x40100000UL, |
| 435 | + .phys = 0x40100000UL, |
| 436 | + .size = 0x00100000UL, |
| 437 | + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 438 | + PTE_BLOCK_NON_SHARE | |
| 439 | + PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 440 | + }, { |
| 441 | + /* OCVM */ |
| 442 | + .virt = 0x80000000UL, |
| 443 | + .phys = 0x80000000UL, |
| 444 | + .size = 0x80000000UL, |
| 445 | + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 446 | + PTE_BLOCK_INNER_SHARE |
| 447 | + }, { |
| 448 | + /* List terminator */ |
| 449 | + 0, |
| 450 | + } |
| 451 | +}; |
| 452 | + |
| 453 | +struct mm_region *mem_map = corstone1000_mem_map; |
| 454 | + |
| 455 | +int board_init(void) |
| 456 | +{ |
| 457 | + return 0; |
| 458 | +} |
| 459 | + |
| 460 | +int dram_init(void) |
| 461 | +{ |
| 462 | + gd->ram_size = PHYS_SDRAM_1_SIZE; |
| 463 | + |
| 464 | + return 0; |
| 465 | +} |
| 466 | + |
| 467 | +int dram_init_banksize(void) |
| 468 | +{ |
| 469 | + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 470 | + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 471 | + |
| 472 | + return 0; |
| 473 | +} |
| 474 | + |
| 475 | +/* |
| 476 | + * Board specific ethernet initialization routine. |
| 477 | + * */ |
| 478 | +int board_eth_init(struct bd_info *bis) |
| 479 | +{ |
| 480 | + int rc = 0; |
| 481 | + |
| 482 | +#ifndef CONFIG_DM_ETH |
| 483 | +#ifdef CONFIG_SMC91111 |
| 484 | + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); |
| 485 | +#endif |
| 486 | +#ifdef CONFIG_SMC911X |
| 487 | + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
| 488 | +#endif |
| 489 | +#endif |
| 490 | + |
| 491 | + return rc; |
| 492 | +} |
| 493 | + |
| 494 | +void reset_cpu(ulong addr) |
| 495 | +{ |
| 496 | +} |
| 497 | diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig |
| 498 | new file mode 100644 |
| 499 | index 000000000000..02f931b0d469 |
| 500 | --- /dev/null |
| 501 | +++ b/configs/corstone1000_defconfig |
| 502 | @@ -0,0 +1,80 @@ |
| 503 | +CONFIG_ARM=y |
| 504 | +CONFIG_TARGET_CORSTONE1000=y |
| 505 | +CONFIG_SYS_TEXT_BASE=0x80000000 |
| 506 | +CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 507 | +CONFIG_SYS_MALLOC_LEN=0x2000000 |
| 508 | +CONFIG_SYS_LOAD_ADDR=0x82100000 |
| 509 | +CONFIG_NR_DRAM_BANKS=1 |
| 510 | +CONFIG_IDENT_STRING=" corstone1000 aarch64 " |
| 511 | +CONFIG_FIT=y |
| 512 | +CONFIG_BOOTDELAY=3 |
| 513 | +CONFIG_USE_BOOTARGS=y |
| 514 | +CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" |
| 515 | +CONFIG_LOGLEVEL=7 |
| 516 | +# CONFIG_DISPLAY_CPUINFO is not set |
| 517 | +# CONFIG_DISPLAY_BOARDINFO is not set |
| 518 | +CONFIG_HUSH_PARSER=y |
| 519 | +CONFIG_SYS_PROMPT="corstone1000# " |
| 520 | +# CONFIG_CMD_CONSOLE is not set |
| 521 | +CONFIG_CMD_BOOTZ=y |
| 522 | +CONFIG_CMD_BOOTM=y |
| 523 | +CONFIG_CMD_LOADM=y |
| 524 | +CONFIG_CMD_BOOTEFI=y |
| 525 | +CONFIG_EFI_LOADER=y |
| 526 | +CONFIG_EFI_PARTITION=y |
| 527 | +CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y |
| 528 | +CONFIG_CMD_BOOTEFI_HELLO=y |
| 529 | +# CONFIG_CMD_XIMG is not set |
| 530 | +# CONFIG_CMD_ENV_EXISTS is not set |
| 531 | +CONFIG_CMD_NVEDIT_EFI=y |
| 532 | +# CONFIG_CMD_LOADS is not set |
| 533 | +CONFIG_CMD_USB=y |
| 534 | +CONFIG_CMD_ITEST=y |
| 535 | +# CONFIG_CMD_SETEXPR is not set |
| 536 | +# CONFIG_CMD_NFS is not set |
| 537 | +CONFIG_CMD_MII=y |
| 538 | +CONFIG_CMD_CACHE=y |
| 539 | +CONFIG_CMD_EFIDEBUG=y |
| 540 | +CONFIG_CMD_FAT=y |
| 541 | +CONFIG_OF_CONTROL=y |
| 542 | +CONFIG_REGMAP=y |
| 543 | +# CONFIG_MMC is not set |
| 544 | +CONFIG_DM_SERIAL=y |
| 545 | +CONFIG_USB=y |
| 546 | +CONFIG_DM_USB=y |
| 547 | +CONFIG_USB_STORAGE=y |
| 548 | +CONFIG_EFI_MM_COMM_TEE=y |
| 549 | +# CONFIG_OPTEE is not set |
| 550 | +# CONFIG_GENERATE_SMBIOS_TABLE is not set |
| 551 | +# CONFIG_HEXDUMP is not set |
| 552 | +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y |
| 553 | +CONFIG_EFI_CAPSULE_ON_DISK=y |
| 554 | +# CONFIG_EFI_CAPSULE_ON_DISK_EARLY is not set |
| 555 | +# CONFIG_EFI_CAPSULE_AUTHENTICATE is not set |
| 556 | +CONFIG_EFI_HAVE_CAPSULE_SUPPORT=y |
| 557 | +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y |
| 558 | +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y |
| 559 | +CONFIG_EFI_SECURE_BOOT=y |
| 560 | +CONFIG_DM_RTC=y |
| 561 | +CONFIG_CMD_RTC=y |
| 562 | +CONFIG_EFI_GET_TIME=y |
| 563 | +CONFIG_EFI_SET_TIME=y |
| 564 | +CONFIG_RTC_EMULATION=y |
| 565 | +CONFIG_PSCI_RESET=y |
| 566 | +CONFIG_DISTRO_DEFAULTS=y |
| 567 | +CONFIG_CMD_DHCP=y |
| 568 | +CONFIG_SMC911X=y |
| 569 | +CONFIG_SMC911X_BASE=0x40100000 |
| 570 | +CONFIG_DM_ETH=y |
| 571 | +CONFIG_PHY_SMSC=y |
| 572 | +CONFIG_CMD_BOOTEFI_SELFTEST=y |
| 573 | +CONFIG_CMD_TIME=y |
| 574 | +CONFIG_CMD_GETTIME=y |
| 575 | +CONFIG_NET_RANDOM_ETHADDR=y |
| 576 | +CONFIG_VERSION_VARIABLE=y |
| 577 | +CONFIG_PHYLIB=y |
| 578 | +CONFIG_PHY=y |
| 579 | +CONFIG_RAM=y |
| 580 | +CONFIG_ERRNO_STR=y |
| 581 | +CONFIG_CMD_EDITENV=y |
| 582 | +CONFIG_MISC=y |
| 583 | diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h |
| 584 | new file mode 100644 |
| 585 | index 000000000000..cf166f107efd |
| 586 | --- /dev/null |
| 587 | +++ b/include/configs/corstone1000.h |
| 588 | @@ -0,0 +1,86 @@ |
| 589 | +/* SPDX-License-Identifier: GPL-2.0+ */ |
| 590 | +/* |
| 591 | + * (C) Copyright 2022 ARM Limited |
| 592 | + * (C) Copyright 2022 Linaro |
| 593 | + * Rui Miguel Silva <rui.silva@linaro.org> |
| 594 | + * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> |
| 595 | + * |
| 596 | + * Configuration for Corstone1000. Parts were derived from other ARM |
| 597 | + * configurations. |
| 598 | + */ |
| 599 | + |
| 600 | +#ifndef __CORSTONE1000_H |
| 601 | +#define __CORSTONE1000_H |
| 602 | + |
| 603 | +#include <linux/sizes.h> |
| 604 | + |
| 605 | +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) |
| 606 | +#define CONFIG_SKIP_LOWLEVEL_INIT |
| 607 | + |
| 608 | +#define CONFIG_SYS_HZ 1000 |
| 609 | + |
| 610 | +#define V2M_SRAM0 0x02000000 |
| 611 | +#define V2M_QSPI 0x08000000 |
| 612 | + |
| 613 | +#define V2M_DEBUG 0x10000000 |
| 614 | +#define V2M_BASE_PERIPH 0x1A000000 |
| 615 | + |
| 616 | +#define V2M_BASE 0x80000000 |
| 617 | + |
| 618 | +#define V2M_PERIPH_OFFSET(x) (x << 16) |
| 619 | + |
| 620 | +#define V2M_SYSID (V2M_BASE_PERIPH) |
| 621 | +#define V2M_SYSCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1)) |
| 622 | + |
| 623 | +#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32)) |
| 624 | +#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33)) |
| 625 | + |
| 626 | +#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34)) |
| 627 | +#define V2M_TIMER_BASE0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35)) |
| 628 | + |
| 629 | +#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(81)) |
| 630 | +#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(82)) |
| 631 | + |
| 632 | +#define CONFIG_PL011_CLOCK 50000000 |
| 633 | + |
| 634 | +/* Physical Memory Map */ |
| 635 | +#define PHYS_SDRAM_1 (V2M_BASE) |
| 636 | +#define PHYS_SDRAM_1_SIZE 0x80000000 |
| 637 | + |
| 638 | +#define CONFIG_ENV_SECT_SIZE SZ_64K |
| 639 | + |
| 640 | +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 641 | + |
| 642 | +/* Monitor Command Prompt */ |
| 643 | +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 644 | +#define CONFIG_SYS_MAXARGS 64 /* max command args */ |
| 645 | + |
| 646 | +#define CONFIG_EXTRA_ENV_SETTINGS \ |
| 647 | + "usb_pgood_delay=250\0" \ |
| 648 | + "boot_bank_flag=0x08002000\0" \ |
| 649 | + "kernel_addr_bank_0=0x083EE000\0" \ |
| 650 | + "kernel_addr_bank_1=0x0936E000\0" \ |
| 651 | + "retrieve_kernel_load_addr=" \ |
| 652 | + "if itest.l *${boot_bank_flag} == 0; then " \ |
| 653 | + "setenv kernel_addr $kernel_addr_bank_0;" \ |
| 654 | + "else " \ |
| 655 | + "setenv kernel_addr $kernel_addr_bank_1;" \ |
| 656 | + "fi;" \ |
| 657 | + "\0" \ |
| 658 | + "kernel_addr_r=0x88200000\0" \ |
| 659 | + "fdt_high=0xffffffff\0" |
| 660 | + |
| 661 | +/* |
| 662 | + * config_distro_bootcmd define the boot command to distro_bootcmd, but we here |
| 663 | + * want to first try to load a kernel if exists, override that config then |
| 664 | + */ |
| 665 | +#undef CONFIG_BOOTCOMMAND |
| 666 | + |
| 667 | +#define CONFIG_BOOTCOMMAND \ |
| 668 | + "run retrieve_kernel_load_addr;" \ |
| 669 | + "echo Loading kernel from $kernel_addr to memory ... ;" \ |
| 670 | + "loadm $kernel_addr $kernel_addr_r 0xc00000;" \ |
| 671 | + "usb start; usb reset;" \ |
| 672 | + "run distro_bootcmd;" \ |
| 673 | + "bootefi $kernel_addr_r $fdtcontroladdr;" |
| 674 | +#endif |
| 675 | -- |
| 676 | 2.30.2 |
| 677 | |