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gerrit.openbmc.org / openbmc / openbmc / 497a421571ce561308d0501e73cb2c8128296fa7 / . / meta-arm / meta-arm-bsp / recipes-bsp / u-boot / u-boot / corstone500 / 0002-board-arm-add-corstone500-board.patch
blob: 29b29438c8ac87346e9b658b41870d5d4ca9ab83 [file] [log] [blame]
Brad Bishopbec4ebc2022-08-03 09:55:16 -0400[diff] [blame]1From 73c319a1096259652853fa2538a733a8ebea96a8 Mon Sep 17 00:00:00 2001
2From: Rui Miguel Silva <rui.silva@linaro.org>
3Date: Wed, 8 Jan 2020 09:48:11 +0000
4Subject: [PATCH 2/2] board: arm: add corstone500 board
5
6Upstream-Status: Pending [Not submitted to upstream yet]
7Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
8
9Add support for the Arm corstone500 platform, with a cortex-a5
10chip, add the default configuration, initialization and
11makefile for this system.
12
13Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
14
15%% original patch: 0002-board-arm-add-corstone500-board.patch
16---
17 arch/arm/Kconfig | 10 +++
18 board/armltd/corstone500/Kconfig | 12 +++
19 board/armltd/corstone500/Makefile | 8 ++
20 board/armltd/corstone500/corstone500.c | 48 +++++++++++
21 configs/corstone500_defconfig | 40 +++++++++
22 include/configs/corstone500.h | 109 +++++++++++++++++++++++++
23 6 files changed, 227 insertions(+)
24 create mode 100644 board/armltd/corstone500/Kconfig
25 create mode 100644 board/armltd/corstone500/Makefile
26 create mode 100644 board/armltd/corstone500/corstone500.c
27 create mode 100644 configs/corstone500_defconfig
28 create mode 100644 include/configs/corstone500.h
29
30diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
31index 4567c183fb..66f99fdf4f 100644
32--- a/arch/arm/Kconfig
33+++ b/arch/arm/Kconfig
34@@ -641,6 +641,15 @@ config ARCH_BCMSTB
35 This enables support for Broadcom ARM-based set-top box
36 chipsets, including the 7445 family of chips.
37
38+config TARGET_CORSTONE500
39+ bool "Support Corstone500"
40+ select CPU_V7A
41+ select SEMIHOSTING
42+ select PL01X_SERIAL
43+ help
44+ This enables support for Corstone500 ARM which is a
45+ Cortex-A5 system
46+
47 config TARGET_VEXPRESS_CA9X4
48 bool "Support vexpress_ca9x4"
49 select CPU_V7A
50@@ -2202,6 +2211,7 @@ source "board/bosch/shc/Kconfig"
51 source "board/bosch/guardian/Kconfig"
52 source "board/Marvell/octeontx/Kconfig"
53 source "board/Marvell/octeontx2/Kconfig"
54+source "board/armltd/corstone500/Kconfig"
55 source "board/armltd/vexpress/Kconfig"
56 source "board/armltd/vexpress64/Kconfig"
57 source "board/cortina/presidio-asic/Kconfig"
58diff --git a/board/armltd/corstone500/Kconfig b/board/armltd/corstone500/Kconfig
59new file mode 100644
60index 0000000000..8e689bd1fd
61--- /dev/null
62+++ b/board/armltd/corstone500/Kconfig
63@@ -0,0 +1,12 @@
64+if TARGET_CORSTONE500
65+
66+config SYS_BOARD
67+ default "corstone500"
68+
69+config SYS_VENDOR
70+ default "armltd"
71+
72+config SYS_CONFIG_NAME
73+ default "corstone500"
74+
75+endif
76diff --git a/board/armltd/corstone500/Makefile b/board/armltd/corstone500/Makefile
77new file mode 100644
78index 0000000000..6598fdd3ae
79--- /dev/null
80+++ b/board/armltd/corstone500/Makefile
81@@ -0,0 +1,8 @@
82+# SPDX-License-Identifier: GPL-2.0+
83+#
84+# (C) Copyright 2022 ARM Limited
85+# (C) Copyright 2022 Linaro
86+# Rui Miguel Silva <rui.silva@linaro.org>
87+#
88+
89+obj-y := corstone500.o
90diff --git a/board/armltd/corstone500/corstone500.c b/board/armltd/corstone500/corstone500.c
91new file mode 100644
92index 0000000000..e878f5c6a5
93--- /dev/null
94+++ b/board/armltd/corstone500/corstone500.c
95@@ -0,0 +1,48 @@
96+// SPDX-License-Identifier: GPL-2.0+
97+/*
98+ * (C) Copyright 2022 ARM Limited
99+ * (C) Copyright 2022 Linaro
100+ * Rui Miguel Silva <rui.silva@linaro.org>
101+ */
102+
103+#include <common.h>
104+#include <dm.h>
105+#include <dm/platform_data/serial_pl01x.h>
106+#include <malloc.h>
107+#include <asm/global_data.h>
108+
109+static const struct pl01x_serial_plat serial_platdata = {
110+ .base = V2M_UART0,
111+ .type = TYPE_PL011,
112+ .clock = CONFIG_PL011_CLOCK,
113+};
114+
115+U_BOOT_DRVINFO(corstone500_serials) = {
116+ .name = "serial_pl01x",
117+ .plat = &serial_platdata,
118+};
119+
120+int board_init(void)
121+{
122+ return 0;
123+}
124+
125+int dram_init(void)
126+{
127+ gd->ram_size = PHYS_SDRAM_1_SIZE;
128+
129+ return 0;
130+}
131+
132+int dram_init_banksize(void)
133+{
134+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
135+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
136+
137+ return 0;
138+}
139+
140+void reset_cpu(ulong addr)
141+{
142+}
143+
144diff --git a/configs/corstone500_defconfig b/configs/corstone500_defconfig
145new file mode 100644
146index 0000000000..d3161a4b40
147--- /dev/null
148+++ b/configs/corstone500_defconfig
149@@ -0,0 +1,40 @@
150+CONFIG_ARM=y
151+CONFIG_SKIP_LOWLEVEL_INIT=y
152+CONFIG_TARGET_CORSTONE500=y
153+CONFIG_SYS_TEXT_BASE=0x88000000
154+CONFIG_SYS_MALLOC_LEN=0x840000
155+CONFIG_SYS_MALLOC_F_LEN=0x2000
156+CONFIG_NR_DRAM_BANKS=1
157+CONFIG_SYS_MEMTEST_START=0x80000000
158+CONFIG_SYS_MEMTEST_END=0xff000000
159+CONFIG_ENV_SIZE=0x40000
160+CONFIG_IDENT_STRING=" corstone500 aarch32"
161+CONFIG_SYS_LOAD_ADDR=0x90000000
162+CONFIG_SUPPORT_RAW_INITRD=y
163+CONFIG_BOOTDELAY=1
164+CONFIG_USE_BOOTARGS=y
165+CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1a200000 root=/dev/ram0 rw loglevel=9"
166+# CONFIG_DISPLAY_CPUINFO is not set
167+# CONFIG_DISPLAY_BOARDINFO is not set
168+CONFIG_HUSH_PARSER=y
169+CONFIG_SYS_PROMPT="corstone500# "
170+# CONFIG_CMD_CONSOLE is not set
171+CONFIG_CMD_BOOTZ=y
172+# CONFIG_CMD_XIMG is not set
173+# CONFIG_CMD_EDITENV is not set
174+# CONFIG_CMD_ENV_EXISTS is not set
175+CONFIG_CMD_MEMTEST=y
176+CONFIG_CMD_ARMFLASH=y
177+# CONFIG_CMD_LOADS is not set
178+# CONFIG_CMD_ITEST is not set
179+# CONFIG_CMD_SETEXPR is not set
180+CONFIG_CMD_DHCP=y
181+# CONFIG_CMD_NFS is not set
182+CONFIG_CMD_MII=y
183+CONFIG_CMD_PING=y
184+CONFIG_CMD_CACHE=y
185+CONFIG_CMD_FAT=y
186+CONFIG_DM=y
187+CONFIG_MTD_NOR_FLASH=y
188+CONFIG_DM_SERIAL=y
189+CONFIG_OF_LIBFDT=y
190diff --git a/include/configs/corstone500.h b/include/configs/corstone500.h
191new file mode 100644
192index 0000000000..93c397d2f5
193--- /dev/null
194+++ b/include/configs/corstone500.h
195@@ -0,0 +1,109 @@
196+/* SPDX-License-Identifier: GPL-2.0+ */
197+/*
198+ * (C) Copyright 2022 ARM Limited
199+ * (C) Copyright 2022 Linaro
200+ * Rui Miguel Silva <rui.silva@linaro.org>
201+ *
202+ * Configuration for Cortex-A5 Corstone500. Parts were derived from other ARM
203+ * configurations.
204+ */
205+
206+#ifndef __CORSTONE500_H
207+#define __CORSTONE500_H
208+
209+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
210+
211+/* Generic Timer Definitions */
212+#define CONFIG_SYS_HZ_CLOCK 7500000
213+#define CONFIG_SYS_HZ 1000
214+#define COUNTER_FREQUENCY CONFIG_SYS_HZ_CLOCK
215+
216+#ifdef CONFIG_CORSTONE500_MEMORY_MAP_EXTENDED
217+#define V2M_SRAM0 0x00010000
218+#define V2M_SRAM1 0x02200000
219+#define V2M_QSPI 0x0a800000
220+#else
221+#define V2M_SRAM0 0x00000000
222+#define V2M_SRAM1 0x02000000
223+#define V2M_QSPI 0x08000000
224+#endif
225+
226+#define V2M_DEBUG 0x10000000
227+#define V2M_BASE_PERIPH 0x1a000000
228+#define V2M_A5_PERIPH 0x1c000000
229+#define V2M_L2CC_PERIPH 0x1c010000
230+
231+#define V2M_MASTER_EXPANSION0 0x40000000
232+#define V2M_MASTER_EXPANSION1 0x60000000
233+
234+#define V2M_BASE 0x80000000
235+
236+#define V2M_PERIPH_OFFSET(x) (x << 16)
237+
238+#define V2M_SYSID (V2M_BASE_PERIPH)
239+#define V2M_SYCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1))
240+#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(2))
241+#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(3))
242+#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(4))
243+#define V2M_TIMER0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(5))
244+
245+#define V2M_WATCHDOG_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(16))
246+#define V2M_WATCHDOG_REFRESH (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(17))
247+
248+#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32))
249+#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33))
250+
251+#define V2M_RTC (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34))
252+#define V2M_TRNG (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35))
253+
254+/* PL011 Serial Configuration */
255+#define CONFIG_CONS_INDEX 0
256+#define CONFIG_PL011_CLOCK 7500000
257+
258+/* Physical Memory Map */
259+#define PHYS_SDRAM_1 (V2M_BASE)
260+
261+/* Top 16MB reserved for secure world use */
262+#define DRAM_SEC_SIZE 0x01000000
263+#define PHYS_SDRAM_1_SIZE (0x80000000 - DRAM_SEC_SIZE)
264+
265+/* Miscellaneous configurable options */
266+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
267+
268+#define CONFIG_SYS_MMIO_TIMER
269+
270+#define CONFIG_EXTRA_ENV_SETTINGS \
271+ "kernel_name=Image\0" \
272+ "kernel_addr=0x80f00000\0" \
273+ "initrd_name=ramdisk.img\0" \
274+ "initrd_addr=0x84000000\0" \
275+ "fdt_name=devtree.dtb\0" \
276+ "fdt_addr=0x83000000\0" \
277+ "fdt_high=0xffffffff\0" \
278+ "initrd_high=0xffffffff\0"
279+
280+#define CONFIG_BOOTCOMMAND "echo copy to RAM...; " \
281+ "cp.b 0x80100000 $kernel_addr 0xb00000; " \
282+ "cp.b 0x80d00000 $initrd_addr 0x800000; " \
283+ "bootz $kernel_addr $initrd_addr:0x800000 $fdt_addr"
284+
285+/* Monitor Command Prompt */
286+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
287+#define CONFIG_SYS_MAXARGS 64 /* max command args */
288+
289+#define CONFIG_SYS_FLASH_BASE 0x80000000
290+/* 256 x 256KiB sectors */
291+#define CONFIG_SYS_MAX_FLASH_SECT 256
292+/* Store environment at top of flash */
293+#define CONFIG_ENV_ADDR 0x0a7c0000
294+#define CONFIG_ENV_SECT_SIZE 0x0040000
295+
296+#define CONFIG_SYS_FLASH_CFI 1
297+#define CONFIG_FLASH_CFI_DRIVER 1
298+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
299+#define CONFIG_SYS_MAX_FLASH_BANKS 1
300+
301+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
302+#define FLASH_MAX_SECTOR_SI 0x00040000
303+#define CONFIG_ENV_IS_IN_FLASH 1
304+#endif
305--
3062.30.2
307