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gerrit.openbmc.org / openbmc / openbmc / 497a421571ce561308d0501e73cb2c8128296fa7 / . / meta-arm / meta-arm-bsp / recipes-kernel / linux / files / juno / juno-dts-mhu-doorbell.patch
blob: 81f641c4787fad8703ffc9160854a682800db66b [file] [log] [blame]
Brad Bishopbec4ebc2022-08-03 09:55:16 -0400[diff] [blame]1Add MHU doorbell support and SCMI device nodes to the Juno DeviceTree.
2
3Patch taken from https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git/log/?h=scmi_dt_defconfig
4
5Upstream-Status: Pending
6Signed-off-by: Ross Burton <ross.burton@arm.com>
7
8From 821ffd8e5dc4d2fb2716d5fb912b343b932e1e77 Mon Sep 17 00:00:00 2001
9From: Sudeep Holla <sudeep.holla@arm.com>
10Date: Thu, 20 Apr 2017 11:58:01 +0100
11Subject: [PATCH] arm64: dts: juno: add mhu doorbell support and scmi device
12 nodes
13
14Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
15---
16 arch/arm64/boot/dts/arm/juno-base.dtsi | 139 ++++++++++++----------
17 arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 6 +-
18 arch/arm64/boot/dts/arm/juno-r1.dts | 12 +-
19 arch/arm64/boot/dts/arm/juno-r2.dts | 12 +-
20 arch/arm64/boot/dts/arm/juno.dts | 12 +-
21 5 files changed, 96 insertions(+), 85 deletions(-)
22
23diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
24index 6288e104a089..36844f7d861e 100644
25--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
26+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
27@@ -23,11 +23,12 @@ frame@2a830000 {
28 };
29
30 mailbox: mhu@2b1f0000 {
31- compatible = "arm,mhu", "arm,primecell";
32+ compatible = "arm,mhu-doorbell", "arm,primecell";
33 reg = <0x0 0x2b1f0000 0x0 0x1000>;
34 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
35 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
36- #mbox-cells = <1>;
37+ #mbox-cells = <2>;
38+ mbox-name = "ARM-MHU";
39 clocks = <&soc_refclk100mhz>;
40 clock-names = "apb_pclk";
41 };
42@@ -39,7 +40,7 @@ smmu_gpu: iommu@2b400000 {
43 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
44 #iommu-cells = <1>;
45 #global-interrupts = <1>;
46- power-domains = <&scpi_devpd 1>;
47+ power-domains = <&scmi_devpd 9>;
48 dma-coherent;
49 status = "disabled";
50 };
51@@ -63,7 +64,7 @@ smmu_etr: iommu@2b600000 {
52 #iommu-cells = <1>;
53 #global-interrupts = <1>;
54 dma-coherent;
55- power-domains = <&scpi_devpd 0>;
56+ power-domains = <&scmi_devpd 8>;
57 };
58
59 gic: interrupt-controller@2c010000 {
60@@ -123,7 +124,7 @@ etf@20010000 { /* etf0 */
61
62 clocks = <&soc_smc50mhz>;
63 clock-names = "apb_pclk";
64- power-domains = <&scpi_devpd 0>;
65+ power-domains = <&scmi_devpd 8>;
66
67 in-ports {
68 port {
69@@ -147,7 +148,7 @@ tpiu@20030000 {
70
71 clocks = <&soc_smc50mhz>;
72 clock-names = "apb_pclk";
73- power-domains = <&scpi_devpd 0>;
74+ power-domains = <&scmi_devpd 8>;
75 in-ports {
76 port {
77 tpiu_in_port: endpoint {
78@@ -164,7 +165,7 @@ main_funnel: funnel@20040000 {
79
80 clocks = <&soc_smc50mhz>;
81 clock-names = "apb_pclk";
82- power-domains = <&scpi_devpd 0>;
83+ power-domains = <&scmi_devpd 8>;
84
85 out-ports {
86 port {
87@@ -201,7 +202,7 @@ etr@20070000 {
88
89 clocks = <&soc_smc50mhz>;
90 clock-names = "apb_pclk";
91- power-domains = <&scpi_devpd 0>;
92+ power-domains = <&scmi_devpd 8>;
93 arm,scatter-gather;
94 in-ports {
95 port {
96@@ -220,7 +221,7 @@ stm@20100000 {
97
98 clocks = <&soc_smc50mhz>;
99 clock-names = "apb_pclk";
100- power-domains = <&scpi_devpd 0>;
101+ power-domains = <&scmi_devpd 8>;
102 out-ports {
103 port {
104 stm_out_port: endpoint {
105@@ -235,7 +236,7 @@ replicator@20120000 {
106
107 clocks = <&soc_smc50mhz>;
108 clock-names = "apb_pclk";
109- power-domains = <&scpi_devpd 0>;
110+ power-domains = <&scmi_devpd 8>;
111
112 out-ports {
113 #address-cells = <1>;
114@@ -270,7 +271,7 @@ cpu_debug0: cpu-debug@22010000 {
115
116 clocks = <&soc_smc50mhz>;
117 clock-names = "apb_pclk";
118- power-domains = <&scpi_devpd 0>;
119+ power-domains = <&scmi_devpd 8>;
120 };
121
122 etm0: etm@22040000 {
123@@ -279,7 +280,7 @@ etm0: etm@22040000 {
124
125 clocks = <&soc_smc50mhz>;
126 clock-names = "apb_pclk";
127- power-domains = <&scpi_devpd 0>;
128+ power-domains = <&scmi_devpd 8>;
129 out-ports {
130 port {
131 cluster0_etm0_out_port: endpoint {
132@@ -295,7 +296,7 @@ funnel@220c0000 { /* cluster0 funnel */
133
134 clocks = <&soc_smc50mhz>;
135 clock-names = "apb_pclk";
136- power-domains = <&scpi_devpd 0>;
137+ power-domains = <&scmi_devpd 8>;
138 out-ports {
139 port {
140 cluster0_funnel_out_port: endpoint {
141@@ -330,7 +331,7 @@ cpu_debug1: cpu-debug@22110000 {
142
143 clocks = <&soc_smc50mhz>;
144 clock-names = "apb_pclk";
145- power-domains = <&scpi_devpd 0>;
146+ power-domains = <&scmi_devpd 8>;
147 };
148
149 etm1: etm@22140000 {
150@@ -339,7 +340,7 @@ etm1: etm@22140000 {
151
152 clocks = <&soc_smc50mhz>;
153 clock-names = "apb_pclk";
154- power-domains = <&scpi_devpd 0>;
155+ power-domains = <&scmi_devpd 8>;
156 out-ports {
157 port {
158 cluster0_etm1_out_port: endpoint {
159@@ -355,7 +356,7 @@ cpu_debug2: cpu-debug@23010000 {
160
161 clocks = <&soc_smc50mhz>;
162 clock-names = "apb_pclk";
163- power-domains = <&scpi_devpd 0>;
164+ power-domains = <&scmi_devpd 8>;
165 };
166
167 etm2: etm@23040000 {
168@@ -364,7 +365,7 @@ etm2: etm@23040000 {
169
170 clocks = <&soc_smc50mhz>;
171 clock-names = "apb_pclk";
172- power-domains = <&scpi_devpd 0>;
173+ power-domains = <&scmi_devpd 8>;
174 out-ports {
175 port {
176 cluster1_etm0_out_port: endpoint {
177@@ -380,7 +381,7 @@ funnel@230c0000 { /* cluster1 funnel */
178
179 clocks = <&soc_smc50mhz>;
180 clock-names = "apb_pclk";
181- power-domains = <&scpi_devpd 0>;
182+ power-domains = <&scmi_devpd 8>;
183 out-ports {
184 port {
185 cluster1_funnel_out_port: endpoint {
186@@ -427,7 +428,7 @@ cpu_debug3: cpu-debug@23110000 {
187
188 clocks = <&soc_smc50mhz>;
189 clock-names = "apb_pclk";
190- power-domains = <&scpi_devpd 0>;
191+ power-domains = <&scmi_devpd 8>;
192 };
193
194 etm3: etm@23140000 {
195@@ -436,7 +437,7 @@ etm3: etm@23140000 {
196
197 clocks = <&soc_smc50mhz>;
198 clock-names = "apb_pclk";
199- power-domains = <&scpi_devpd 0>;
200+ power-domains = <&scmi_devpd 8>;
201 out-ports {
202 port {
203 cluster1_etm1_out_port: endpoint {
204@@ -452,7 +453,7 @@ cpu_debug4: cpu-debug@23210000 {
205
206 clocks = <&soc_smc50mhz>;
207 clock-names = "apb_pclk";
208- power-domains = <&scpi_devpd 0>;
209+ power-domains = <&scmi_devpd 8>;
210 };
211
212 etm4: etm@23240000 {
213@@ -461,7 +462,7 @@ etm4: etm@23240000 {
214
215 clocks = <&soc_smc50mhz>;
216 clock-names = "apb_pclk";
217- power-domains = <&scpi_devpd 0>;
218+ power-domains = <&scmi_devpd 8>;
219 out-ports {
220 port {
221 cluster1_etm2_out_port: endpoint {
222@@ -477,7 +478,7 @@ cpu_debug5: cpu-debug@23310000 {
223
224 clocks = <&soc_smc50mhz>;
225 clock-names = "apb_pclk";
226- power-domains = <&scpi_devpd 0>;
227+ power-domains = <&scmi_devpd 8>;
228 };
229
230 etm5: etm@23340000 {
231@@ -486,7 +487,7 @@ etm5: etm@23340000 {
232
233 clocks = <&soc_smc50mhz>;
234 clock-names = "apb_pclk";
235- power-domains = <&scpi_devpd 0>;
236+ power-domains = <&scmi_devpd 8>;
237 out-ports {
238 port {
239 cluster1_etm3_out_port: endpoint {
240@@ -503,8 +504,8 @@ gpu: gpu@2d000000 {
241 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-names = "job", "mmu", "gpu";
244- clocks = <&scpi_dvfs 2>;
245- power-domains = <&scpi_devpd 1>;
246+ clocks = <&scmi_dvfs 2>;
247+ power-domains = <&scmi_devpd 9>;
248 dma-coherent;
249 /* The SMMU is only really of interest to bare-metal hypervisors */
250 /* iommus = <&smmu_gpu 0>; */
251@@ -519,14 +520,24 @@ sram: sram@2e000000 {
252 #size-cells = <1>;
253 ranges = <0 0x0 0x2e000000 0x8000>;
254
255- cpu_scp_lpri: scp-sram@0 {
256- compatible = "arm,juno-scp-shmem";
257- reg = <0x0 0x200>;
258+ cpu_scp_lpri0: scp-sram@0 {
259+ compatible = "arm,scmi-shmem";
260+ reg = <0x0 0x80>;
261 };
262
263- cpu_scp_hpri: scp-sram@200 {
264- compatible = "arm,juno-scp-shmem";
265- reg = <0x200 0x200>;
266+ cpu_scp_lpri1: scp-sram@80 {
267+ compatible = "arm,scmi-shmem";
268+ reg = <0x80 0x80>;
269+ };
270+
271+ cpu_scp_hpri0: scp-sram@100 {
272+ compatible = "arm,scmi-shmem";
273+ reg = <0x100 0x80>;
274+ };
275+
276+ cpu_scp_hpri1: scp-sram@180 {
277+ compatible = "arm,scmi-shmem";
278+ reg = <0x180 0x80>;
279 };
280 };
281
282@@ -558,37 +569,37 @@ pcie_ctlr: pcie@40000000 {
283 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
284 };
285
286- scpi {
287- compatible = "arm,scpi";
288- mboxes = <&mailbox 1>;
289- shmem = <&cpu_scp_hpri>;
290+ firmware {
291+ scmi {
292+ compatible = "arm,scmi";
293+ mbox-names = "tx", "rx";
294+ mboxes = <&mailbox 0 0 &mailbox 0 1>;
295+ shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
296+ #address-cells = <1>;
297+ #size-cells = <0>;
298
299- clocks {
300- compatible = "arm,scpi-clocks";
301+ scmi_devpd: protocol@11 {
302+ reg = <0x11>;
303+ #power-domain-cells = <1>;
304+ };
305
306- scpi_dvfs: clocks-0 {
307- compatible = "arm,scpi-dvfs-clocks";
308+ scmi_dvfs: protocol@13 {
309+ reg = <0x13>;
310 #clock-cells = <1>;
311- clock-indices = <0>, <1>, <2>;
312- clock-output-names = "atlclk", "aplclk","gpuclk";
313+ mbox-names = "tx", "rx";
314+ mboxes = <&mailbox 1 0 &mailbox 1 1>;
315+ shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
316 };
317- scpi_clk: clocks-1 {
318- compatible = "arm,scpi-variable-clocks";
319+
320+ scmi_clk: protocol@14 {
321+ reg = <0x14>;
322 #clock-cells = <1>;
323- clock-indices = <3>;
324- clock-output-names = "pxlclk";
325 };
326- };
327
328- scpi_devpd: power-controller {
329- compatible = "arm,scpi-power-domains";
330- num-domains = <2>;
331- #power-domain-cells = <1>;
332- };
333-
334- scpi_sensors0: sensors {
335- compatible = "arm,scpi-sensors";
336- #thermal-sensor-cells = <1>;
337+ scmi_sensors0: protocol@15 {
338+ reg = <0x15>;
339+ #thermal-sensor-cells = <1>;
340+ };
341 };
342 };
343
344@@ -596,40 +607,40 @@ thermal-zones {
345 pmic {
346 polling-delay = <1000>;
347 polling-delay-passive = <100>;
348- thermal-sensors = <&scpi_sensors0 0>;
349+ thermal-sensors = <&scmi_sensors0 0>;
350 };
351
352 soc {
353 polling-delay = <1000>;
354 polling-delay-passive = <100>;
355- thermal-sensors = <&scpi_sensors0 3>;
356+ thermal-sensors = <&scmi_sensors0 3>;
357 };
358
359 big_cluster_thermal_zone: big-cluster {
360 polling-delay = <1000>;
361 polling-delay-passive = <100>;
362- thermal-sensors = <&scpi_sensors0 21>;
363+ thermal-sensors = <&scmi_sensors0 21>;
364 status = "disabled";
365 };
366
367 little_cluster_thermal_zone: little-cluster {
368 polling-delay = <1000>;
369 polling-delay-passive = <100>;
370- thermal-sensors = <&scpi_sensors0 22>;
371+ thermal-sensors = <&scmi_sensors0 22>;
372 status = "disabled";
373 };
374
375 gpu0_thermal_zone: gpu0 {
376 polling-delay = <1000>;
377 polling-delay-passive = <100>;
378- thermal-sensors = <&scpi_sensors0 23>;
379+ thermal-sensors = <&scmi_sensors0 23>;
380 status = "disabled";
381 };
382
383 gpu1_thermal_zone: gpu1 {
384 polling-delay = <1000>;
385 polling-delay-passive = <100>;
386- thermal-sensors = <&scpi_sensors0 24>;
387+ thermal-sensors = <&scmi_sensors0 24>;
388 status = "disabled";
389 };
390 };
391@@ -705,7 +716,7 @@ hdlcd@7ff50000 {
392 reg = <0 0x7ff50000 0 0x1000>;
393 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
394 iommus = <&smmu_hdlcd1 0>;
395- clocks = <&scpi_clk 3>;
396+ clocks = <&scmi_clk 3>;
397 clock-names = "pxlclk";
398
399 port {
400@@ -720,7 +731,7 @@ hdlcd@7ff60000 {
401 reg = <0 0x7ff60000 0 0x1000>;
402 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
403 iommus = <&smmu_hdlcd0 0>;
404- clocks = <&scpi_clk 3>;
405+ clocks = <&scmi_clk 3>;
406 clock-names = "pxlclk";
407
408 port {
409diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
410index eda3d9e18af6..e6ecb0dfcbcd 100644
411--- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
412+++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
413@@ -6,7 +6,7 @@ funnel@20130000 { /* cssys1 */
414
415 clocks = <&soc_smc50mhz>;
416 clock-names = "apb_pclk";
417- power-domains = <&scpi_devpd 0>;
418+ power-domains = <&scmi_devpd 8>;
419 out-ports {
420 port {
421 csys1_funnel_out_port: endpoint {
422@@ -29,7 +29,7 @@ etf@20140000 { /* etf1 */
423
424 clocks = <&soc_smc50mhz>;
425 clock-names = "apb_pclk";
426- power-domains = <&scpi_devpd 0>;
427+ power-domains = <&scmi_devpd 8>;
428 in-ports {
429 port {
430 etf1_in_port: endpoint {
431@@ -52,7 +52,7 @@ funnel@20150000 { /* cssys2 */
432
433 clocks = <&soc_smc50mhz>;
434 clock-names = "apb_pclk";
435- power-domains = <&scpi_devpd 0>;
436+ power-domains = <&scmi_devpd 8>;
437 out-ports {
438 port {
439 csys2_funnel_out_port: endpoint {
440diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
441index 0e24e29eb9b1..fee67943f4d5 100644
442--- a/arch/arm64/boot/dts/arm/juno-r1.dts
443+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
444@@ -96,7 +96,7 @@ A57_0: cpu@0 {
445 d-cache-line-size = <64>;
446 d-cache-sets = <256>;
447 next-level-cache = <&A57_L2>;
448- clocks = <&scpi_dvfs 0>;
449+ clocks = <&scmi_dvfs 0>;
450 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
451 capacity-dmips-mhz = <1024>;
452 };
453@@ -113,7 +113,7 @@ A57_1: cpu@1 {
454 d-cache-line-size = <64>;
455 d-cache-sets = <256>;
456 next-level-cache = <&A57_L2>;
457- clocks = <&scpi_dvfs 0>;
458+ clocks = <&scmi_dvfs 0>;
459 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
460 capacity-dmips-mhz = <1024>;
461 };
462@@ -130,7 +130,7 @@ A53_0: cpu@100 {
463 d-cache-line-size = <64>;
464 d-cache-sets = <128>;
465 next-level-cache = <&A53_L2>;
466- clocks = <&scpi_dvfs 1>;
467+ clocks = <&scmi_dvfs 1>;
468 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
469 capacity-dmips-mhz = <578>;
470 };
471@@ -147,7 +147,7 @@ A53_1: cpu@101 {
472 d-cache-line-size = <64>;
473 d-cache-sets = <128>;
474 next-level-cache = <&A53_L2>;
475- clocks = <&scpi_dvfs 1>;
476+ clocks = <&scmi_dvfs 1>;
477 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
478 capacity-dmips-mhz = <578>;
479 };
480@@ -164,7 +164,7 @@ A53_2: cpu@102 {
481 d-cache-line-size = <64>;
482 d-cache-sets = <128>;
483 next-level-cache = <&A53_L2>;
484- clocks = <&scpi_dvfs 1>;
485+ clocks = <&scmi_dvfs 1>;
486 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
487 capacity-dmips-mhz = <578>;
488 };
489@@ -181,7 +181,7 @@ A53_3: cpu@103 {
490 d-cache-line-size = <64>;
491 d-cache-sets = <128>;
492 next-level-cache = <&A53_L2>;
493- clocks = <&scpi_dvfs 1>;
494+ clocks = <&scmi_dvfs 1>;
495 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
496 capacity-dmips-mhz = <578>;
497 };
498diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
499index e609420ce3e4..7792626eb29e 100644
500--- a/arch/arm64/boot/dts/arm/juno-r2.dts
501+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
502@@ -96,7 +96,7 @@ A72_0: cpu@0 {
503 d-cache-line-size = <64>;
504 d-cache-sets = <256>;
505 next-level-cache = <&A72_L2>;
506- clocks = <&scpi_dvfs 0>;
507+ clocks = <&scmi_dvfs 0>;
508 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
509 capacity-dmips-mhz = <1024>;
510 dynamic-power-coefficient = <450>;
511@@ -114,7 +114,7 @@ A72_1: cpu@1 {
512 d-cache-line-size = <64>;
513 d-cache-sets = <256>;
514 next-level-cache = <&A72_L2>;
515- clocks = <&scpi_dvfs 0>;
516+ clocks = <&scmi_dvfs 0>;
517 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
518 capacity-dmips-mhz = <1024>;
519 dynamic-power-coefficient = <450>;
520@@ -132,7 +132,7 @@ A53_0: cpu@100 {
521 d-cache-line-size = <64>;
522 d-cache-sets = <128>;
523 next-level-cache = <&A53_L2>;
524- clocks = <&scpi_dvfs 1>;
525+ clocks = <&scmi_dvfs 1>;
526 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
527 capacity-dmips-mhz = <485>;
528 dynamic-power-coefficient = <140>;
529@@ -150,7 +150,7 @@ A53_1: cpu@101 {
530 d-cache-line-size = <64>;
531 d-cache-sets = <128>;
532 next-level-cache = <&A53_L2>;
533- clocks = <&scpi_dvfs 1>;
534+ clocks = <&scmi_dvfs 1>;
535 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
536 capacity-dmips-mhz = <485>;
537 dynamic-power-coefficient = <140>;
538@@ -168,7 +168,7 @@ A53_2: cpu@102 {
539 d-cache-line-size = <64>;
540 d-cache-sets = <128>;
541 next-level-cache = <&A53_L2>;
542- clocks = <&scpi_dvfs 1>;
543+ clocks = <&scmi_dvfs 1>;
544 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
545 capacity-dmips-mhz = <485>;
546 dynamic-power-coefficient = <140>;
547@@ -186,7 +186,7 @@ A53_3: cpu@103 {
548 d-cache-line-size = <64>;
549 d-cache-sets = <128>;
550 next-level-cache = <&A53_L2>;
551- clocks = <&scpi_dvfs 1>;
552+ clocks = <&scmi_dvfs 1>;
553 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
554 capacity-dmips-mhz = <485>;
555 dynamic-power-coefficient = <140>;
556diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
557index f00cffbd032c..a28316c65c1b 100644
558--- a/arch/arm64/boot/dts/arm/juno.dts
559+++ b/arch/arm64/boot/dts/arm/juno.dts
560@@ -95,7 +95,7 @@ A57_0: cpu@0 {
561 d-cache-line-size = <64>;
562 d-cache-sets = <256>;
563 next-level-cache = <&A57_L2>;
564- clocks = <&scpi_dvfs 0>;
565+ clocks = <&scmi_dvfs 0>;
566 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
567 capacity-dmips-mhz = <1024>;
568 dynamic-power-coefficient = <530>;
569@@ -113,7 +113,7 @@ A57_1: cpu@1 {
570 d-cache-line-size = <64>;
571 d-cache-sets = <256>;
572 next-level-cache = <&A57_L2>;
573- clocks = <&scpi_dvfs 0>;
574+ clocks = <&scmi_dvfs 0>;
575 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
576 capacity-dmips-mhz = <1024>;
577 dynamic-power-coefficient = <530>;
578@@ -131,7 +131,7 @@ A53_0: cpu@100 {
579 d-cache-line-size = <64>;
580 d-cache-sets = <128>;
581 next-level-cache = <&A53_L2>;
582- clocks = <&scpi_dvfs 1>;
583+ clocks = <&scmi_dvfs 1>;
584 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
585 capacity-dmips-mhz = <578>;
586 dynamic-power-coefficient = <140>;
587@@ -149,7 +149,7 @@ A53_1: cpu@101 {
588 d-cache-line-size = <64>;
589 d-cache-sets = <128>;
590 next-level-cache = <&A53_L2>;
591- clocks = <&scpi_dvfs 1>;
592+ clocks = <&scmi_dvfs 1>;
593 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
594 capacity-dmips-mhz = <578>;
595 dynamic-power-coefficient = <140>;
596@@ -167,7 +167,7 @@ A53_2: cpu@102 {
597 d-cache-line-size = <64>;
598 d-cache-sets = <128>;
599 next-level-cache = <&A53_L2>;
600- clocks = <&scpi_dvfs 1>;
601+ clocks = <&scmi_dvfs 1>;
602 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
603 capacity-dmips-mhz = <578>;
604 dynamic-power-coefficient = <140>;
605@@ -185,7 +185,7 @@ A53_3: cpu@103 {
606 d-cache-line-size = <64>;
607 d-cache-sets = <128>;
608 next-level-cache = <&A53_L2>;
609- clocks = <&scpi_dvfs 1>;
610+ clocks = <&scmi_dvfs 1>;
611 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
612 capacity-dmips-mhz = <578>;
613 dynamic-power-coefficient = <140>;
614--
6152.25.1
616