blob: 74c94e0afefba717ff2f8adff021e15225347d5d [file] [log] [blame]
Andrew Geissler517393d2023-01-13 08:55:19 -06001Upstream-Status: Pending [Not submitted to upstream yet]
2Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
3
4From 1a9aeedda58228893add545e49d2d6cd4c316b4f Mon Sep 17 00:00:00 2001
5From: Emekcan <emekcan.aras@arm.com>
6Date: Tue, 13 Dec 2022 13:45:06 +0000
7Subject: [PATCH] plat-n1sdp: add external device tree base and size
8
9Adds external device tree address and size. It also
10register this physical memory so optee can read the device tree.
11---
12 core/arch/arm/plat-n1sdp/main.c | 1 +
13 core/arch/arm/plat-n1sdp/platform_config.h | 3 +++
14 2 files changed, 4 insertions(+)
15
16diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
17index bb951ce6b..ab76f60c6 100644
18--- a/core/arch/arm/plat-n1sdp/main.c
19+++ b/core/arch/arm/plat-n1sdp/main.c
20@@ -31,6 +31,7 @@ static struct gic_data gic_data __nex_bss;
21 static struct pl011_data console_data __nex_bss;
22
23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
24+register_phys_mem_pgdir(MEM_AREA_EXT_DT, EXT_DT_BASE, EXT_DT_SIZE);
25
26 register_ddr(DRAM0_BASE, DRAM0_SIZE);
27 register_ddr(DRAM1_BASE, DRAM1_SIZE);
28diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
29index bf0a3c834..8741a2503 100644
30--- a/core/arch/arm/plat-n1sdp/platform_config.h
31+++ b/core/arch/arm/plat-n1sdp/platform_config.h
32@@ -42,6 +42,9 @@
33 #define GICC_BASE 0x2C000000
34 #define GICR_BASE 0x300C0000
35
36+#define EXT_DT_BASE 0x04001600
37+#define EXT_DT_SIZE 0x200
38+
39 #ifndef UART_BAUDRATE
40 #define UART_BAUDRATE 115200
41 #endif
42--
432.17.1
44