blob: 941e9d10b84973e7cee466e00a911823444d1701 [file] [log] [blame]
Patrick Williams520786c2023-06-25 16:20:36 -05001From 25467e433f02f40f5999ed6e6b0d3adb4c9cf16d Mon Sep 17 00:00:00 2001
2From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
3Date: Fri, 9 Jun 2023 13:08:37 +0100
4Subject: [PATCH 30/42] sandbox64: add support for NVMXIP QSPI
5
6enable NVMXIP QSPI for sandbox 64-bit
7
8Adding two NVM XIP QSPI storage devices.
9
10Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
11Reviewed-by: Simon Glass <sjg@chromium.org>
12Upstream-Status: Backport [https://github.com/u-boot/u-boot/commit/c9c2c95d4cd27fe0cd41fe13a863899d268f973c]
13
14Changelog:
15===============
16
17v2:
18
19* address nits
20---
21 arch/sandbox/dts/sandbox64.dts | 13 +++++++++++++
22 arch/sandbox/dts/test.dts | 14 ++++++++++++++
23 configs/sandbox64_defconfig | 3 ++-
24 doc/develop/driver-model/nvmxip.rst | 2 +-
25 doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt | 6 +++---
26 drivers/mtd/nvmxip/nvmxip-uclass.c | 7 +++++++
27 6 files changed, 40 insertions(+), 5 deletions(-)
28
29diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts
30index 3eb0457089..c9a2f4b4a4 100644
31--- a/arch/sandbox/dts/sandbox64.dts
32+++ b/arch/sandbox/dts/sandbox64.dts
33@@ -89,6 +89,19 @@
34 cs-gpios = <0>, <&gpio_a 0>;
35 };
36
37+ nvmxip-qspi1@08000000 {
38+ compatible = "nvmxip,qspi";
39+ reg = /bits/ 64 <0x08000000 0x00200000>;
40+ lba_shift = <9>;
41+ lba = <4096>;
42+ };
43+
44+ nvmxip-qspi2@08200000 {
45+ compatible = "nvmxip,qspi";
46+ reg = /bits/ 64 <0x08200000 0x00100000>;
47+ lba_shift = <9>;
48+ lba = <2048>;
49+ };
50 };
51
52 #include "sandbox.dtsi"
53diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
54index dffe10adbf..c3ba0a225e 100644
55--- a/arch/sandbox/dts/test.dts
56+++ b/arch/sandbox/dts/test.dts
57@@ -1745,6 +1745,20 @@
58 compatible = "u-boot,fwu-mdata-gpt";
59 fwu-mdata-store = <&mmc0>;
60 };
61+
62+ nvmxip-qspi1@08000000 {
63+ compatible = "nvmxip,qspi";
64+ reg = <0x08000000 0x00200000>;
65+ lba_shift = <9>;
66+ lba = <4096>;
67+ };
68+
69+ nvmxip-qspi2@08200000 {
70+ compatible = "nvmxip,qspi";
71+ reg = <0x08200000 0x00100000>;
72+ lba_shift = <9>;
73+ lba = <2048>;
74+ };
75 };
76
77 #include "sandbox_pmic.dtsi"
78diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
79index 4b8a1ec42b..2dca176ae3 100644
80--- a/configs/sandbox64_defconfig
81+++ b/configs/sandbox64_defconfig
82@@ -260,4 +260,5 @@ CONFIG_UNIT_TEST=y
83 CONFIG_UT_TIME=y
84 CONFIG_UT_DM=y
85 CONFIG_ARM_FFA_TRANSPORT=y
86-CONFIG_SANDBOX_FFA=y
87\ No newline at end of file
88+CONFIG_SANDBOX_FFA=y
89+CONFIG_NVMXIP_QSPI=y
90\ No newline at end of file
91diff --git a/doc/develop/driver-model/nvmxip.rst b/doc/develop/driver-model/nvmxip.rst
92index 09afdbcccf..e85dc220b9 100644
93--- a/doc/develop/driver-model/nvmxip.rst
94+++ b/doc/develop/driver-model/nvmxip.rst
95@@ -56,7 +56,7 @@ The implementation is generic and can be used by different platforms.
96 Supported hardware
97 --------------------------------
98
99-Any 64-bit plaform.
100+Any plaform supporting readq().
101
102 Configuration
103 ----------------------
104diff --git a/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt b/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
105index cc60e9efdc..882728d541 100644
106--- a/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
107+++ b/doc/device-tree-bindings/nvmxip/nvmxip_qspi.txt
108@@ -16,7 +16,7 @@ If a platform has its own driver, please provide your own compatible
109 string.
110
111 2)
112- reg = <0x0 0x08000000 0x0 0x00200000>;
113+ reg = /bits/ 64 <0x08000000 0x00200000>;
114
115 The start address and size of the flash device. The values give here are an
116 example (when the cell size is 2).
117@@ -43,14 +43,14 @@ Example of multiple flash devices
118
119 nvmxip-qspi1@08000000 {
120 compatible = "nvmxip,qspi";
121- reg = <0x0 0x08000000 0x0 0x00200000>;
122+ reg = /bits/ 64 <0x08000000 0x00200000>;
123 lba_shift = <9>;
124 lba = <4096>;
125 };
126
127 nvmxip-qspi2@08200000 {
128 compatible = "nvmxip,qspi";
129- reg = <0x0 0x08200000 0x0 0x00100000>;
130+ reg = /bits/ 64 <0x08200000 0x00100000>;
131 lba_shift = <9>;
132 lba = <2048>;
133 };
134diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c
135index 9f96041e3d..6d8eb177b5 100644
136--- a/drivers/mtd/nvmxip/nvmxip-uclass.c
137+++ b/drivers/mtd/nvmxip/nvmxip-uclass.c
138@@ -9,6 +9,9 @@
139 #include <common.h>
140 #include <dm.h>
141 #include <log.h>
142+#if CONFIG_IS_ENABLED(SANDBOX64)
143+#include <asm/test.h>
144+#endif
145 #include <linux/bitops.h>
146 #include "nvmxip.h"
147
148@@ -36,6 +39,10 @@ static int nvmxip_post_bind(struct udevice *udev)
149 char bdev_name[NVMXIP_BLKDEV_NAME_SZ + 1];
150 int devnum;
151
152+#if CONFIG_IS_ENABLED(SANDBOX64)
153+ sandbox_set_enable_memio(true);
154+#endif
155+
156 devnum = uclass_id_count(UCLASS_NVMXIP);
157 snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "blk#%d", devnum);
158
159--
1602.25.1
161