Andrew Geissler | 82c905d | 2020-04-13 13:39:40 -0500 | [diff] [blame] | 1 | From 05909fea93f29b2b6e1d554dd64201551bd7a022 Mon Sep 17 00:00:00 2001 |
| 2 | From: Liwei Song <liwei.song@windriver.com> |
| 3 | Date: Fri, 17 Apr 2020 16:11:59 +0800 |
| 4 | Subject: [PATCH] Sync i915_pciids upto 8717c6b7414f |
| 5 | |
| 6 | Import the kernel's i915_pciids.h, up to: |
| 7 | |
| 8 | commit 8717c6b7414ffb890672276dccc284c23078ac0e |
| 9 | Author: Lee Shawn C <shawn.c.lee@intel.com> |
| 10 | Date: Tue Dec 10 23:04:15 2019 +0800 |
| 11 | |
| 12 | drm/i915/cml: Separate U series pci id from origianl list. |
| 13 | |
| 14 | Upstream-Status: Submitted [https://patchwork.kernel.org/patch/11494645/] |
| 15 | |
| 16 | Signed-off-by: Liwei Song <liwei.song@windriver.com> |
| 17 | --- |
| 18 | src/i915_pciids.h | 265 ++++++++++++++++++++++++++++++++++----------- |
| 19 | src/intel_module.c | 2 +- |
| 20 | test/dri3-test.c | 2 +- |
| 21 | 3 files changed, 206 insertions(+), 63 deletions(-) |
| 22 | |
| 23 | diff --git a/src/i915_pciids.h b/src/i915_pciids.h |
| 24 | index fd965ffbb92e..1d2c12219f44 100644 |
| 25 | --- a/src/i915_pciids.h |
| 26 | +++ b/src/i915_pciids.h |
| 27 | @@ -108,8 +108,10 @@ |
| 28 | INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ |
| 29 | INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ |
| 30 | |
| 31 | -#define INTEL_PINEVIEW_IDS(info) \ |
| 32 | - INTEL_VGA_DEVICE(0xa001, info), \ |
| 33 | +#define INTEL_PINEVIEW_G_IDS(info) \ |
| 34 | + INTEL_VGA_DEVICE(0xa001, info) |
| 35 | + |
| 36 | +#define INTEL_PINEVIEW_M_IDS(info) \ |
| 37 | INTEL_VGA_DEVICE(0xa011, info) |
| 38 | |
| 39 | #define INTEL_IRONLAKE_D_IDS(info) \ |
| 40 | @@ -166,7 +168,18 @@ |
| 41 | #define INTEL_IVB_Q_IDS(info) \ |
| 42 | INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ |
| 43 | |
| 44 | +#define INTEL_HSW_ULT_GT1_IDS(info) \ |
| 45 | + INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ |
| 46 | + INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ |
| 47 | + INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ |
| 48 | + INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */ |
| 49 | + |
| 50 | +#define INTEL_HSW_ULX_GT1_IDS(info) \ |
| 51 | + INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */ |
| 52 | + |
| 53 | #define INTEL_HSW_GT1_IDS(info) \ |
| 54 | + INTEL_HSW_ULT_GT1_IDS(info), \ |
| 55 | + INTEL_HSW_ULX_GT1_IDS(info), \ |
| 56 | INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ |
| 57 | INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ |
| 58 | INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ |
| 59 | @@ -175,20 +188,26 @@ |
| 60 | INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ |
| 61 | INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ |
| 62 | INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ |
| 63 | - INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ |
| 64 | - INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ |
| 65 | - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ |
| 66 | INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ |
| 67 | INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ |
| 68 | INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ |
| 69 | INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ |
| 70 | INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ |
| 71 | INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ |
| 72 | - INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ |
| 73 | - INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ |
| 74 | INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */ |
| 75 | |
| 76 | +#define INTEL_HSW_ULT_GT2_IDS(info) \ |
| 77 | + INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ |
| 78 | + INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ |
| 79 | + INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ |
| 80 | + INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */ |
| 81 | + |
| 82 | +#define INTEL_HSW_ULX_GT2_IDS(info) \ |
| 83 | + INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \ |
| 84 | + |
| 85 | #define INTEL_HSW_GT2_IDS(info) \ |
| 86 | + INTEL_HSW_ULT_GT2_IDS(info), \ |
| 87 | + INTEL_HSW_ULX_GT2_IDS(info), \ |
| 88 | INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ |
| 89 | INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ |
| 90 | INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ |
| 91 | @@ -197,9 +216,6 @@ |
| 92 | INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ |
| 93 | INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ |
| 94 | INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ |
| 95 | - INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ |
| 96 | - INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ |
| 97 | - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ |
| 98 | INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ |
| 99 | INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ |
| 100 | INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ |
| 101 | @@ -207,11 +223,17 @@ |
| 102 | INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ |
| 103 | INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ |
| 104 | INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ |
| 105 | - INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ |
| 106 | - INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ |
| 107 | INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */ |
| 108 | |
| 109 | +#define INTEL_HSW_ULT_GT3_IDS(info) \ |
| 110 | + INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ |
| 111 | + INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ |
| 112 | + INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ |
| 113 | + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ |
| 114 | + INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */ |
| 115 | + |
| 116 | #define INTEL_HSW_GT3_IDS(info) \ |
| 117 | + INTEL_HSW_ULT_GT3_IDS(info), \ |
| 118 | INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ |
| 119 | INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ |
| 120 | INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ |
| 121 | @@ -220,16 +242,11 @@ |
| 122 | INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ |
| 123 | INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ |
| 124 | INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ |
| 125 | - INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ |
| 126 | - INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ |
| 127 | - INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ |
| 128 | INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ |
| 129 | INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ |
| 130 | INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ |
| 131 | INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ |
| 132 | INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ |
| 133 | - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ |
| 134 | - INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ |
| 135 | INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ |
| 136 | |
| 137 | #define INTEL_HSW_IDS(info) \ |
| 138 | @@ -245,35 +262,59 @@ |
| 139 | INTEL_VGA_DEVICE(0x0157, info), \ |
| 140 | INTEL_VGA_DEVICE(0x0155, info) |
| 141 | |
| 142 | -#define INTEL_BDW_GT1_IDS(info) \ |
| 143 | - INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ |
| 144 | +#define INTEL_BDW_ULT_GT1_IDS(info) \ |
| 145 | INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ |
| 146 | - INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ |
| 147 | - INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ |
| 148 | + INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */ |
| 149 | + |
| 150 | +#define INTEL_BDW_ULX_GT1_IDS(info) \ |
| 151 | + INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */ |
| 152 | + |
| 153 | +#define INTEL_BDW_GT1_IDS(info) \ |
| 154 | + INTEL_BDW_ULT_GT1_IDS(info), \ |
| 155 | + INTEL_BDW_ULX_GT1_IDS(info), \ |
| 156 | + INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ |
| 157 | INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ |
| 158 | INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ |
| 159 | |
| 160 | -#define INTEL_BDW_GT2_IDS(info) \ |
| 161 | - INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ |
| 162 | +#define INTEL_BDW_ULT_GT2_IDS(info) \ |
| 163 | INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ |
| 164 | - INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ |
| 165 | - INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ |
| 166 | + INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */ |
| 167 | + |
| 168 | +#define INTEL_BDW_ULX_GT2_IDS(info) \ |
| 169 | + INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */ |
| 170 | + |
| 171 | +#define INTEL_BDW_GT2_IDS(info) \ |
| 172 | + INTEL_BDW_ULT_GT2_IDS(info), \ |
| 173 | + INTEL_BDW_ULX_GT2_IDS(info), \ |
| 174 | + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ |
| 175 | INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ |
| 176 | INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ |
| 177 | |
| 178 | +#define INTEL_BDW_ULT_GT3_IDS(info) \ |
| 179 | + INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ |
| 180 | + INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \ |
| 181 | + |
| 182 | +#define INTEL_BDW_ULX_GT3_IDS(info) \ |
| 183 | + INTEL_VGA_DEVICE(0x162E, info) /* ULX */ |
| 184 | + |
| 185 | #define INTEL_BDW_GT3_IDS(info) \ |
| 186 | + INTEL_BDW_ULT_GT3_IDS(info), \ |
| 187 | + INTEL_BDW_ULX_GT3_IDS(info), \ |
| 188 | INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ |
| 189 | - INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ |
| 190 | - INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ |
| 191 | - INTEL_VGA_DEVICE(0x162E, info), /* ULX */\ |
| 192 | INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ |
| 193 | INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ |
| 194 | |
| 195 | +#define INTEL_BDW_ULT_RSVD_IDS(info) \ |
| 196 | + INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ |
| 197 | + INTEL_VGA_DEVICE(0x163B, info) /* Iris */ |
| 198 | + |
| 199 | +#define INTEL_BDW_ULX_RSVD_IDS(info) \ |
| 200 | + INTEL_VGA_DEVICE(0x163E, info) /* ULX */ |
| 201 | + |
| 202 | #define INTEL_BDW_RSVD_IDS(info) \ |
| 203 | + INTEL_BDW_ULT_RSVD_IDS(info), \ |
| 204 | + INTEL_BDW_ULX_RSVD_IDS(info), \ |
| 205 | INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ |
| 206 | - INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ |
| 207 | - INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ |
| 208 | - INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \ |
| 209 | INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ |
| 210 | INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ |
| 211 | |
| 212 | @@ -289,25 +330,40 @@ |
| 213 | INTEL_VGA_DEVICE(0x22b2, info), \ |
| 214 | INTEL_VGA_DEVICE(0x22b3, info) |
| 215 | |
| 216 | +#define INTEL_SKL_ULT_GT1_IDS(info) \ |
| 217 | + INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */ |
| 218 | + |
| 219 | +#define INTEL_SKL_ULX_GT1_IDS(info) \ |
| 220 | + INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */ |
| 221 | + |
| 222 | #define INTEL_SKL_GT1_IDS(info) \ |
| 223 | - INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ |
| 224 | - INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ |
| 225 | + INTEL_SKL_ULT_GT1_IDS(info), \ |
| 226 | + INTEL_SKL_ULX_GT1_IDS(info), \ |
| 227 | INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ |
| 228 | INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ |
| 229 | INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ |
| 230 | |
| 231 | -#define INTEL_SKL_GT2_IDS(info) \ |
| 232 | +#define INTEL_SKL_ULT_GT2_IDS(info) \ |
| 233 | INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ |
| 234 | - INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ |
| 235 | - INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ |
| 236 | + INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */ |
| 237 | + |
| 238 | +#define INTEL_SKL_ULX_GT2_IDS(info) \ |
| 239 | + INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */ |
| 240 | + |
| 241 | +#define INTEL_SKL_GT2_IDS(info) \ |
| 242 | + INTEL_SKL_ULT_GT2_IDS(info), \ |
| 243 | + INTEL_SKL_ULX_GT2_IDS(info), \ |
| 244 | INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ |
| 245 | INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ |
| 246 | INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ |
| 247 | INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ |
| 248 | |
| 249 | +#define INTEL_SKL_ULT_GT3_IDS(info) \ |
| 250 | + INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */ |
| 251 | + |
| 252 | #define INTEL_SKL_GT3_IDS(info) \ |
| 253 | + INTEL_SKL_ULT_GT3_IDS(info), \ |
| 254 | INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ |
| 255 | - INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ |
| 256 | INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ |
| 257 | INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ |
| 258 | INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ |
| 259 | @@ -336,45 +392,91 @@ |
| 260 | INTEL_VGA_DEVICE(0x3184, info), \ |
| 261 | INTEL_VGA_DEVICE(0x3185, info) |
| 262 | |
| 263 | -#define INTEL_KBL_GT1_IDS(info) \ |
| 264 | - INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ |
| 265 | - INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ |
| 266 | +#define INTEL_KBL_ULT_GT1_IDS(info) \ |
| 267 | INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ |
| 268 | + INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */ |
| 269 | + |
| 270 | +#define INTEL_KBL_ULX_GT1_IDS(info) \ |
| 271 | INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ |
| 272 | + INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */ |
| 273 | + |
| 274 | +#define INTEL_KBL_GT1_IDS(info) \ |
| 275 | + INTEL_KBL_ULT_GT1_IDS(info), \ |
| 276 | + INTEL_KBL_ULX_GT1_IDS(info), \ |
| 277 | INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ |
| 278 | INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ |
| 279 | INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ |
| 280 | INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ |
| 281 | |
| 282 | -#define INTEL_KBL_GT2_IDS(info) \ |
| 283 | +#define INTEL_KBL_ULT_GT2_IDS(info) \ |
| 284 | INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ |
| 285 | + INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */ |
| 286 | + |
| 287 | +#define INTEL_KBL_ULX_GT2_IDS(info) \ |
| 288 | + INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */ |
| 289 | + |
| 290 | +#define INTEL_KBL_GT2_IDS(info) \ |
| 291 | + INTEL_KBL_ULT_GT2_IDS(info), \ |
| 292 | + INTEL_KBL_ULX_GT2_IDS(info), \ |
| 293 | INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ |
| 294 | - INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ |
| 295 | - INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ |
| 296 | INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ |
| 297 | INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ |
| 298 | INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ |
| 299 | INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ |
| 300 | |
| 301 | +#define INTEL_KBL_ULT_GT3_IDS(info) \ |
| 302 | + INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */ |
| 303 | + |
| 304 | #define INTEL_KBL_GT3_IDS(info) \ |
| 305 | + INTEL_KBL_ULT_GT3_IDS(info), \ |
| 306 | INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ |
| 307 | - INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ |
| 308 | INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ |
| 309 | |
| 310 | #define INTEL_KBL_GT4_IDS(info) \ |
| 311 | INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ |
| 312 | |
| 313 | /* AML/KBL Y GT2 */ |
| 314 | -#define INTEL_AML_GT2_IDS(info) \ |
| 315 | +#define INTEL_AML_KBL_GT2_IDS(info) \ |
| 316 | INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \ |
| 317 | INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */ |
| 318 | |
| 319 | +/* AML/CFL Y GT2 */ |
| 320 | +#define INTEL_AML_CFL_GT2_IDS(info) \ |
| 321 | + INTEL_VGA_DEVICE(0x87CA, info) |
| 322 | + |
| 323 | +/* CML GT1 */ |
| 324 | +#define INTEL_CML_GT1_IDS(info) \ |
| 325 | + INTEL_VGA_DEVICE(0x9BA5, info), \ |
| 326 | + INTEL_VGA_DEVICE(0x9BA8, info), \ |
| 327 | + INTEL_VGA_DEVICE(0x9BA4, info), \ |
| 328 | + INTEL_VGA_DEVICE(0x9BA2, info) |
| 329 | + |
| 330 | +#define INTEL_CML_U_GT1_IDS(info) \ |
| 331 | + INTEL_VGA_DEVICE(0x9B21, info), \ |
| 332 | + INTEL_VGA_DEVICE(0x9BAA, info), \ |
| 333 | + INTEL_VGA_DEVICE(0x9BAC, info) |
| 334 | + |
| 335 | +/* CML GT2 */ |
| 336 | +#define INTEL_CML_GT2_IDS(info) \ |
| 337 | + INTEL_VGA_DEVICE(0x9BC5, info), \ |
| 338 | + INTEL_VGA_DEVICE(0x9BC8, info), \ |
| 339 | + INTEL_VGA_DEVICE(0x9BC4, info), \ |
| 340 | + INTEL_VGA_DEVICE(0x9BC2, info), \ |
| 341 | + INTEL_VGA_DEVICE(0x9BC6, info), \ |
| 342 | + INTEL_VGA_DEVICE(0x9BE6, info), \ |
| 343 | + INTEL_VGA_DEVICE(0x9BF6, info) |
| 344 | + |
| 345 | +#define INTEL_CML_U_GT2_IDS(info) \ |
| 346 | + INTEL_VGA_DEVICE(0x9B41, info), \ |
| 347 | + INTEL_VGA_DEVICE(0x9BCA, info), \ |
| 348 | + INTEL_VGA_DEVICE(0x9BCC, info) |
| 349 | + |
| 350 | #define INTEL_KBL_IDS(info) \ |
| 351 | INTEL_KBL_GT1_IDS(info), \ |
| 352 | INTEL_KBL_GT2_IDS(info), \ |
| 353 | INTEL_KBL_GT3_IDS(info), \ |
| 354 | INTEL_KBL_GT4_IDS(info), \ |
| 355 | - INTEL_AML_GT2_IDS(info) |
| 356 | + INTEL_AML_KBL_GT2_IDS(info) |
| 357 | |
| 358 | /* CFL S */ |
| 359 | #define INTEL_CFL_S_GT1_IDS(info) \ |
| 360 | @@ -390,6 +492,9 @@ |
| 361 | INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ |
| 362 | |
| 363 | /* CFL H */ |
| 364 | +#define INTEL_CFL_H_GT1_IDS(info) \ |
| 365 | + INTEL_VGA_DEVICE(0x3E9C, info) |
| 366 | + |
| 367 | #define INTEL_CFL_H_GT2_IDS(info) \ |
| 368 | INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ |
| 369 | INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ |
| 370 | @@ -407,30 +512,43 @@ |
| 371 | |
| 372 | /* WHL/CFL U GT1 */ |
| 373 | #define INTEL_WHL_U_GT1_IDS(info) \ |
| 374 | - INTEL_VGA_DEVICE(0x3EA1, info) |
| 375 | + INTEL_VGA_DEVICE(0x3EA1, info), \ |
| 376 | + INTEL_VGA_DEVICE(0x3EA4, info) |
| 377 | |
| 378 | /* WHL/CFL U GT2 */ |
| 379 | #define INTEL_WHL_U_GT2_IDS(info) \ |
| 380 | - INTEL_VGA_DEVICE(0x3EA0, info) |
| 381 | + INTEL_VGA_DEVICE(0x3EA0, info), \ |
| 382 | + INTEL_VGA_DEVICE(0x3EA3, info) |
| 383 | |
| 384 | /* WHL/CFL U GT3 */ |
| 385 | #define INTEL_WHL_U_GT3_IDS(info) \ |
| 386 | - INTEL_VGA_DEVICE(0x3EA2, info), \ |
| 387 | - INTEL_VGA_DEVICE(0x3EA3, info), \ |
| 388 | - INTEL_VGA_DEVICE(0x3EA4, info) |
| 389 | + INTEL_VGA_DEVICE(0x3EA2, info) |
| 390 | |
| 391 | #define INTEL_CFL_IDS(info) \ |
| 392 | INTEL_CFL_S_GT1_IDS(info), \ |
| 393 | INTEL_CFL_S_GT2_IDS(info), \ |
| 394 | + INTEL_CFL_H_GT1_IDS(info), \ |
| 395 | INTEL_CFL_H_GT2_IDS(info), \ |
| 396 | INTEL_CFL_U_GT2_IDS(info), \ |
| 397 | INTEL_CFL_U_GT3_IDS(info), \ |
| 398 | INTEL_WHL_U_GT1_IDS(info), \ |
| 399 | INTEL_WHL_U_GT2_IDS(info), \ |
| 400 | - INTEL_WHL_U_GT3_IDS(info) |
| 401 | + INTEL_WHL_U_GT3_IDS(info), \ |
| 402 | + INTEL_AML_CFL_GT2_IDS(info), \ |
| 403 | + INTEL_CML_GT1_IDS(info), \ |
| 404 | + INTEL_CML_GT2_IDS(info), \ |
| 405 | + INTEL_CML_U_GT1_IDS(info), \ |
| 406 | + INTEL_CML_U_GT2_IDS(info) |
| 407 | |
| 408 | /* CNL */ |
| 409 | +#define INTEL_CNL_PORT_F_IDS(info) \ |
| 410 | + INTEL_VGA_DEVICE(0x5A54, info), \ |
| 411 | + INTEL_VGA_DEVICE(0x5A5C, info), \ |
| 412 | + INTEL_VGA_DEVICE(0x5A44, info), \ |
| 413 | + INTEL_VGA_DEVICE(0x5A4C, info) |
| 414 | + |
| 415 | #define INTEL_CNL_IDS(info) \ |
| 416 | + INTEL_CNL_PORT_F_IDS(info), \ |
| 417 | INTEL_VGA_DEVICE(0x5A51, info), \ |
| 418 | INTEL_VGA_DEVICE(0x5A59, info), \ |
| 419 | INTEL_VGA_DEVICE(0x5A41, info), \ |
| 420 | @@ -440,22 +558,47 @@ |
| 421 | INTEL_VGA_DEVICE(0x5A42, info), \ |
| 422 | INTEL_VGA_DEVICE(0x5A4A, info), \ |
| 423 | INTEL_VGA_DEVICE(0x5A50, info), \ |
| 424 | - INTEL_VGA_DEVICE(0x5A40, info), \ |
| 425 | - INTEL_VGA_DEVICE(0x5A54, info), \ |
| 426 | - INTEL_VGA_DEVICE(0x5A5C, info), \ |
| 427 | - INTEL_VGA_DEVICE(0x5A44, info), \ |
| 428 | - INTEL_VGA_DEVICE(0x5A4C, info) |
| 429 | + INTEL_VGA_DEVICE(0x5A40, info) |
| 430 | |
| 431 | /* ICL */ |
| 432 | -#define INTEL_ICL_11_IDS(info) \ |
| 433 | +#define INTEL_ICL_PORT_F_IDS(info) \ |
| 434 | INTEL_VGA_DEVICE(0x8A50, info), \ |
| 435 | - INTEL_VGA_DEVICE(0x8A51, info), \ |
| 436 | INTEL_VGA_DEVICE(0x8A5C, info), \ |
| 437 | - INTEL_VGA_DEVICE(0x8A5D, info), \ |
| 438 | + INTEL_VGA_DEVICE(0x8A59, info), \ |
| 439 | + INTEL_VGA_DEVICE(0x8A58, info), \ |
| 440 | INTEL_VGA_DEVICE(0x8A52, info), \ |
| 441 | INTEL_VGA_DEVICE(0x8A5A, info), \ |
| 442 | INTEL_VGA_DEVICE(0x8A5B, info), \ |
| 443 | + INTEL_VGA_DEVICE(0x8A57, info), \ |
| 444 | + INTEL_VGA_DEVICE(0x8A56, info), \ |
| 445 | INTEL_VGA_DEVICE(0x8A71, info), \ |
| 446 | - INTEL_VGA_DEVICE(0x8A70, info) |
| 447 | + INTEL_VGA_DEVICE(0x8A70, info), \ |
| 448 | + INTEL_VGA_DEVICE(0x8A53, info), \ |
| 449 | + INTEL_VGA_DEVICE(0x8A54, info) |
| 450 | + |
| 451 | +#define INTEL_ICL_11_IDS(info) \ |
| 452 | + INTEL_ICL_PORT_F_IDS(info), \ |
| 453 | + INTEL_VGA_DEVICE(0x8A51, info), \ |
| 454 | + INTEL_VGA_DEVICE(0x8A5D, info) |
| 455 | + |
| 456 | +/* EHL/JSL */ |
| 457 | +#define INTEL_EHL_IDS(info) \ |
| 458 | + INTEL_VGA_DEVICE(0x4500, info), \ |
| 459 | + INTEL_VGA_DEVICE(0x4571, info), \ |
| 460 | + INTEL_VGA_DEVICE(0x4551, info), \ |
| 461 | + INTEL_VGA_DEVICE(0x4541, info), \ |
| 462 | + INTEL_VGA_DEVICE(0x4E71, info), \ |
| 463 | + INTEL_VGA_DEVICE(0x4E61, info), \ |
| 464 | + INTEL_VGA_DEVICE(0x4E51, info) |
| 465 | + |
| 466 | +/* TGL */ |
| 467 | +#define INTEL_TGL_12_IDS(info) \ |
| 468 | + INTEL_VGA_DEVICE(0x9A49, info), \ |
| 469 | + INTEL_VGA_DEVICE(0x9A40, info), \ |
| 470 | + INTEL_VGA_DEVICE(0x9A59, info), \ |
| 471 | + INTEL_VGA_DEVICE(0x9A60, info), \ |
| 472 | + INTEL_VGA_DEVICE(0x9A68, info), \ |
| 473 | + INTEL_VGA_DEVICE(0x9A70, info), \ |
| 474 | + INTEL_VGA_DEVICE(0x9A78, info) |
| 475 | |
| 476 | #endif /* _I915_PCIIDS_H */ |
| 477 | diff --git a/src/intel_module.c b/src/intel_module.c |
| 478 | index a71c2e40b774..e0b94c190254 100644 |
| 479 | --- a/src/intel_module.c |
| 480 | +++ b/src/intel_module.c |
| 481 | @@ -357,7 +357,7 @@ static const struct pci_id_match intel_device_match[] = { |
| 482 | INTEL_I945GM_IDS(&intel_i945_info), |
| 483 | |
| 484 | INTEL_G33_IDS(&intel_g33_info), |
| 485 | - INTEL_PINEVIEW_IDS(&intel_g33_info), |
| 486 | + INTEL_PINEVIEW_G_IDS(&intel_g33_info), |
| 487 | |
| 488 | INTEL_I965G_IDS(&intel_i965_info), |
| 489 | INTEL_I965GM_IDS(&intel_i965_info), |
| 490 | diff --git a/test/dri3-test.c b/test/dri3-test.c |
| 491 | index 78e105a8b64a..5265a30cea1b 100644 |
| 492 | --- a/test/dri3-test.c |
| 493 | +++ b/test/dri3-test.c |
| 494 | @@ -76,7 +76,7 @@ static const struct pci_id_match ids[] = { |
| 495 | INTEL_I945GM_IDS(031), |
| 496 | |
| 497 | INTEL_G33_IDS(033), |
| 498 | - INTEL_PINEVIEW_IDS(033), |
| 499 | + INTEL_PINEVIEW_G_IDS(033), |
| 500 | |
| 501 | INTEL_I965G_IDS(040), |
| 502 | INTEL_I965GM_IDS(040), |
| 503 | -- |
| 504 | 2.17.1 |
| 505 | |