poky/meta/recipes-devtools/binutils/binutils/0010-Add-support-for-Netlogic-XLP.patch

From 69ab45c16f80f18fa78121f6e774750b9e9a200b Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Sun, 14 Feb 2016 17:06:19 +0000
Subject: [PATCH 10/17] Add support for Netlogic XLP

Patch From: Nebu Philips <nphilips@netlogicmicro.com>

Using the mipsisa64r2nlm target, add support for XLP from
Netlogic. Also, update vendor name to NLM wherever applicable.

Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been
assigned to INSN_OCTEON3

Upstream-Status: Pending

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com>
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
---
 bfd/aoutx.h           |  1 +
 bfd/archures.c        |  1 +
 bfd/bfd-in2.h         |  1 +
 bfd/config.bfd        |  5 +++++
 bfd/cpu-mips.c        |  6 ++++--
 bfd/elfxx-mips.c      |  8 ++++++++
 binutils/readelf.c    |  1 +
 gas/config/tc-mips.c  |  4 +++-
 gas/configure         |  3 +++
 gas/configure.ac      |  3 +++
 include/elf/mips.h    |  1 +
 include/opcode/mips.h |  6 ++++++
 ld/configure.tgt      |  3 +++
 opcodes/mips-dis.c    | 12 +++++-------
 opcodes/mips-opc.c    | 31 ++++++++++++++++++++-----------
 15 files changed, 65 insertions(+), 21 deletions(-)

diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index d352a1a3e44..2e2c3c1af86 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -810,6 +810,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
 	case bfd_mach_mipsisa64r6:
 	case bfd_mach_mips_sb1:
 	case bfd_mach_mips_xlr:
+	case bfd_mach_mips_xlp:
 	  /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc.  */
 	  arch_flags = M_MIPS2;
 	  break;
diff --git a/bfd/archures.c b/bfd/archures.c
index 551ec8732f0..2665b378623 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -185,6 +185,7 @@ DESCRIPTION
 .#define bfd_mach_mips_octeon3		6503
 .#define bfd_mach_mips_xlr		887682	 {* decimal 'XLR'.  *}
 .#define bfd_mach_mips_interaptiv_mr2	736550	 {* decimal 'IA2'.  *}
+.#define bfd_mach_mips_xlp              887680   {* decimal 'XLP'.  *}
 .#define bfd_mach_mipsisa32		32
 .#define bfd_mach_mipsisa32r2		33
 .#define bfd_mach_mipsisa32r3		34
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 35ef4d755bb..48db00af80b 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1585,6 +1585,7 @@ enum bfd_architecture
 #define bfd_mach_mips_octeon3          6503
 #define bfd_mach_mips_xlr              887682   /* decimal 'XLR'.  */
 #define bfd_mach_mips_interaptiv_mr2   736550   /* decimal 'IA2'.  */
+#define bfd_mach_mips_xlp              887680   /* decimal 'XLP'.  */
 #define bfd_mach_mipsisa32             32
 #define bfd_mach_mipsisa32r2           33
 #define bfd_mach_mipsisa32r3           34
diff --git a/bfd/config.bfd b/bfd/config.bfd
index e5233cd1f7e..2e4ae6bbdff 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -877,6 +877,11 @@ case "${targ}" in
     targ_defvec=mips_elf32_le_vec
     targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
     ;;
+  mipsisa64*-*-elf*)
+	targ_defvec=mips_elf32_trad_be_vec
+	targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
+	want64=true
+	;;
   mips*-*-elf* | mips*-*-rtems* | mips*-*-windiss | mips*-*-none)
     targ_defvec=mips_elf32_be_vec
     targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 802acb45f1e..fd9ec4c0ad4 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -108,7 +108,8 @@ enum
   I_mipsocteon3,
   I_xlr,
   I_interaptiv_mr2,
-  I_micromips
+  I_micromips,
+  I_xlp
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
@@ -163,7 +164,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips_xlr, "mips:xlr",	   FALSE, NN(I_xlr)),
   N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", FALSE,
      NN(I_interaptiv_mr2)),
-  N (64, 64, bfd_mach_mips_micromips, "mips:micromips", FALSE, NULL)
+  N (64, 64, bfd_mach_mips_micromips, "mips:micromips", FALSE, NN(I_micromips)),
+  N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, NULL)
 };
 
 /* The default architecture is mips:3000, but with a machine number of
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 160febec94c..4c9499cc2cf 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -6982,6 +6982,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_IAMR2:
       return bfd_mach_mips_interaptiv_mr2;
 
+    case E_MIPS_MACH_XLP:
+      return bfd_mach_mips_xlp;
+
     default:
       switch (flags & EF_MIPS_ARCH)
 	{
@@ -12356,6 +12359,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
       break;
 
+	case bfd_mach_mips_xlp:
+	  val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
+	  break;
+
     case bfd_mach_mipsisa32:
       val = E_MIPS_ARCH_32;
       break;
@@ -14373,6 +14380,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
   { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
   { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
   { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
+  { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
 
   /* MIPS64 extensions.  */
   { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 6057515a89b..ea119b0b254 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3483,6 +3483,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
 	    case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
 	    case E_MIPS_MACH_XLR:  strcat (buf, ", xlr"); break;
 	    case E_MIPS_MACH_IAMR2:  strcat (buf, ", interaptiv-mr2"); break;
+	    case E_MIPS_MACH_XLP:  strcat (buf, ", xlp"); break;
 	    case 0:
 	    /* We simply ignore the field in this case to avoid confusion:
 	       MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 31acb77d78a..0ead168d51e 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -568,6 +568,7 @@ static int mips_32bitmode = 0;
    || mips_opts.arch == CPU_RM7000                    \
    || mips_opts.arch == CPU_VR5500                    \
    || mips_opts.micromips                             \
+   || mips_opts.arch == CPU_XLP                       \
    )
 
 /* Whether the processor uses hardware interlocks to protect reads
@@ -597,6 +598,7 @@ static int mips_32bitmode = 0;
     && mips_opts.isa != ISA_MIPS3)                    \
    || mips_opts.arch == CPU_R4300                     \
    || mips_opts.micromips                             \
+   || mips_opts.arch == CPU_XLP                       \
    )
 
 /* Whether the processor uses hardware interlocks to protect reads
@@ -20174,7 +20176,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   /* Broadcom XLP.
      XLP is mostly like XLR, with the prominent exception that it is
      MIPS64R2 rather than MIPS64.  */
-  { "xlp",	      0, 0,			ISA_MIPS64R2, CPU_XLR },
+  { "xlp",	      0, 0,			ISA_MIPS64R2, CPU_XLP },
 
   /* MIPS 64 Release 6.  */
   { "i6400",	      0, ASE_VIRT | ASE_MSA,	ISA_MIPS64R6, CPU_MIPS64R6},
diff --git a/gas/configure b/gas/configure
index 5bccfd9d1b7..d4b13e6fc8b 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12722,6 +12722,9 @@ _ACEOF
 	  mipsisa64r6 | mipsisa64r6el)
 	    mips_cpu=mips64r6
 	    ;;
+	  mipsisa64r2nlm | mipsisa64r2nlmel)
+	    mips_cpu=xlp
+	    ;;
 	  mipstx39 | mipstx39el)
 	    mips_cpu=r3900
 	    ;;
diff --git a/gas/configure.ac b/gas/configure.ac
index b65108fecb2..ce1f2dad9bc 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -325,6 +325,9 @@ changequote([,])dnl
 	  mipsisa64r6 | mipsisa64r6el)
 	    mips_cpu=mips64r6
 	    ;;
+	  mipsisa64r2nlm | mipsisa64r2nlmel)
+	    mips_cpu=xlp
+	    ;;
 	  mipstx39 | mipstx39el)
 	    mips_cpu=r3900
 	    ;;
diff --git a/include/elf/mips.h b/include/elf/mips.h
index cc08ebd4318..bb518575ce1 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_SB1         0x008a0000
 #define E_MIPS_MACH_OCTEON	0x008b0000
 #define E_MIPS_MACH_XLR     	0x008c0000
+#define E_MIPS_MACH_XLP         0x008f0000
 #define E_MIPS_MACH_OCTEON2	0x008d0000
 #define E_MIPS_MACH_OCTEON3	0x008e0000
 #define E_MIPS_MACH_5400	0x00910000
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index fd031f37588..a96a44df840 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1260,6 +1260,8 @@ static const unsigned int mips_isa_table[] = {
 #define INSN_XLR                 0x00000020
 /* Imagination interAptiv MR2.  */
 #define INSN_INTERAPTIV_MR2	  0x04000000
+/* Netlogic XlP instruction */
+#define INSN_XLP		0x00000080
 
 /* DSP ASE */
 #define ASE_DSP			0x00000001
@@ -1384,6 +1386,7 @@ static const unsigned int mips_isa_table[] = {
 #define CPU_OCTEON3	6503
 #define CPU_XLR     	887682   	/* decimal 'XLR'   */
 #define CPU_INTERAPTIV_MR2 736550	/* decimal 'IA2'  */
+#define CPU_XLP         887680      /* decimal 'XLP'   */
 
 /* Return true if the given CPU is included in INSN_* mask MASK.  */
 
@@ -1461,6 +1464,9 @@ cpu_is_member (int cpu, unsigned int mask)
       return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
 	     || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
 
+    case CPU_XLP:
+      return (mask & INSN_XLP) != 0;
+
     default:
       return FALSE;
     }
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 9b4bf2ca964..f6d7171dff7 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -510,6 +510,9 @@ mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
 			targ_emul=elf32btsmip
 			targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip"
 			;;
+mipsisa64*-*-elf*)	targ_emul=elf32btsmip
+			targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip"
+			;;
 mips64*el-ps2-elf*)	targ_emul=elf32lr5900n32
 			targ_extra_emuls="elf32lr5900"
 			targ_extra_libpath=$targ_extra_emuls
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 755bbe294bd..ce22ef683a6 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -674,13 +674,11 @@ const struct mips_arch_choice mips_arch_choices[] =
     mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
     mips_cp1_names_mips3264, mips_hwr_names_numeric },
 
-  /* XLP is mostly like XLR, with the prominent exception it is being
-     MIPS64R2.  */
-  { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
-    ISA_MIPS64R2 | INSN_XLR, 0,
-    mips_cp0_names_xlr,
-    mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
-    mips_cp1_names_mips3264, mips_hwr_names_numeric },
+  { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
+    ISA_MIPS64R2 | INSN_XLP, 0,
+    mips_cp0_names_mips3264r2,
+    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+    mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
 
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 5270aeefa80..d17dc78cd71 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -328,6 +328,7 @@ decode_mips_operand (const char *p)
 #define IOCT3	INSN_OCTEON3
 #define XLR     INSN_XLR
 #define IAMR2	INSN_INTERAPTIV_MR2
+#define XLP	INSN_XLP
 #define IVIRT	ASE_VIRT
 #define IVIRT64	ASE_VIRT64
 
@@ -990,6 +991,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"clo",			"U,s",		0x70000021, 0xfc0007ff, WR_1|RD_2,		0,		I32|N55,	0,	I37 },
 {"clz",			"d,s",		0x00000050, 0xfc1f07ff, WR_1|RD_2,		0,		I37,		0,	0 },
 {"clz",			"U,s",		0x70000020, 0xfc0007ff, WR_1|RD_2,		0,		I32|N55,	0,	I37 },
+{"crc",			"d,s,t",	0x7000001c, 0xfc0007ff,	WR_1|RD_2|RD_3,	0,		XLP, 		0,	0 },
 /* ctc0 is at the bottom of the table.  */
 {"ctc1",		"t,G",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	0 },
 {"ctc1",		"t,S",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	0 },
@@ -1022,12 +1024,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"daddiu",		"t,r,j",	0x64000000, 0xfc000000, WR_1|RD_2,		0,		I3,		0,	0 },
 {"daddu",		"d,v,t",	0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I3,		0,	0 },
 {"daddu",		"t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,		0,		I3,		0,	0 },
-{"daddwc",		"d,s,t", 	0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0,		XLR,		0,	0 },
+{"daddwc",		"d,s,t", 	0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0,		XLR|XLP,	0,	0 },
 {"dbreak",		"",		0x7000003f, 0xffffffff,	0,			0,		N5,		0,	0 },
 {"dclo",		"d,s",		0x00000053, 0xfc1f07ff, WR_1|RD_2,		0,		I69,		0,	0 },
 {"dclo",		"U,s",	 	0x70000025, 0xfc0007ff, WR_1|RD_2, 	0,		I64|N55,	0,	I69 },
 {"dclz",		"d,s",		0x00000052, 0xfc1f07ff, WR_1|RD_2,		0,		I69,		0,	0 },
 {"dclz",		"U,s",	 	0x70000024, 0xfc0007ff, WR_1|RD_2, 	0,		I64|N55,	0,	I69 },
+{"dcrc",		"d,s,t",	0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3,	0,		XLP, 		0,	0 },
 /* dctr and dctw are used on the r5000.  */
 {"dctr",		"o(b)",	 	0xbc050000, 0xfc1f0000, RD_2,			0,		I3,		0,	0 },
 {"dctw",		"o(b)",		0xbc090000, 0xfc1f0000, RD_2,			0,		I3,		0,	0 },
@@ -1099,6 +1102,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmfc0",		"t,G,H",	0x40200000, 0xffe007f8,	WR_1|RD_C0|LC,		0,		I64,		0,	0 },
 {"dmfgc0",		"t,G",		0x40600100, 0xffe007ff, WR_1|RD_C0|LC,		0,		0,		IVIRT64, 0 },
 {"dmfgc0",		"t,G,H",	0x40600100, 0xffe007f8, WR_1|RD_C0|LC,		0,		0,		IVIRT64, 0 },
+{"dmfur",		"t,d",		0x7000001e, 0xffe007ff, WR_1,			0,		XLP,		0,	0 },
 {"dmt",			"",		0x41600bc1, 0xffffffff, TRAP,			0,		0,		MT32,	0 },
 {"dmt",			"t",		0x41600bc1, 0xffe0ffff, WR_1|TRAP,		0,		0,		MT32,	0 },
 {"dmtc0",		"t,G",		0x40a00000, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		I3,		0,	EE },
@@ -1114,6 +1118,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* dmfc3 is at the bottom of the table.  */
 /* dmtc3 is at the bottom of the table.  */
 {"dmuh",		"d,s,t",	0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
+{"dmtur",		"t,d",		0x7000001f, 0xffe007ff,	RD_1,			0,		XLP,		0,	0 },
+{"dmul",		"d,s,t",	0x70000006, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		XLP,		0,	0 },
 {"dmul",		"d,s,t",	0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
 {"dmul",		"d,v,t",	0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,	0,		IOCT,		0,	0 },
 {"dmul",		"d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
@@ -1267,9 +1273,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ld",			"s,-b(+R)",	0xec180000, 0xfc1c0000, WR_1,			RD_pc,		I69,		0,	0 },
 {"ld",			"t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"ld",			"t,o(b)",	0xdc000000, 0xfc000000, WR_1|RD_3|LM,		0,		I3,		0,	0 },
-{"ldaddw",		"t,b",		0x70000010, 0xfc00ffff,	MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
-{"ldaddwu",		"t,b",		0x70000011, 0xfc00ffff,	MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
-{"ldaddd",		"t,b",		0x70000012, 0xfc00ffff,	MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
+{"ldaddw",		"t,b",		0x70000010, 0xfc00ffff,	MOD_1|RD_2|SM,		0,		XLR|XLP,	0,	0 },
+{"ldaddwu",		"t,b",		0x70000011, 0xfc00ffff,	MOD_1|RD_2|SM,		0,		XLR|XLP,	0,	0 },
+{"ldaddd",		"t,b",		0x70000012, 0xfc00ffff,	MOD_1|RD_2|SM,		0,		XLR|XLP,	0,	0 },
 {"ldc1",		"T,o(b)",	0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,	0,		I2,		0,	SF },
 {"ldc1",		"E,o(b)",	0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,	0,		I2,		0,	SF },
 {"ldc1",		"T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2,		0,	SF },
@@ -1438,7 +1444,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mflo",		"d,9",		0x00000012, 0xff9f07ff, WR_1|RD_LO,		0,		0,		D32,	0 },
 {"mflo1",		"d",		0x70000012, 0xffff07ff,	WR_1|RD_LO,		0,		EE,		0,	0 },
 {"mflhxu",		"d",		0x00000052, 0xffff07ff,	WR_1|MOD_HILO,		0,		0,		SMT,	0 },
-{"mfcr",		"t,s",		0x70000018, 0xfc00ffff, WR_1|RD_2,		0,		XLR,		0,	0 },
+{"mfcr",		"t,s",		0x70000018, 0xfc00ffff, WR_1,			0,		XLR|XLP,	0,	0 },
 {"mfsa",		"d",		0x00000028, 0xffff07ff,	WR_1,			0,		EE,		0,	0 },
 {"min.ob",		"X,Y,Q",	0x78000006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"min.ob",		"D,S,Q",	0x48000006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
@@ -1483,10 +1489,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* move is at the top of the table.  */
 {"msgn.qh",		"X,Y,Q",	0x78200000, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
 {"msgsnd",		"t",		0,    (int) M_MSGSND,	INSN_MACRO,		0,		XLR,		0,	0 },
+{"msgsnds",		"d,t",		0x4a000001, 0xffe007ff,	WR_1|RD_2|RD_C0|WR_C0,	0,		XLP,		0,	0 },
 {"msgld",		"", 		0,    (int) M_MSGLD,	INSN_MACRO,		0,		XLR,		0,	0 },
 {"msgld",		"t",		0,    (int) M_MSGLD_T,	INSN_MACRO,		0,		XLR,		0,	0 },
-{"msgwait",		"", 		0,    (int) M_MSGWAIT,	INSN_MACRO,		0,		XLR,		0,	0 },
-{"msgwait",		"t",		0,    (int) M_MSGWAIT_T,INSN_MACRO,		0,		XLR,		0,	0 },
+{"msglds",		"d,t",		0x4a000002, 0xffe007ff,	WR_1|RD_2|RD_C0|WR_C0,	0,		XLP,		0,	0 },
+{"msgwait",		"",		0,    (int) M_MSGWAIT,  INSN_MACRO,		0,		XLR|XLP,	0,	0 },
+{"msgwait",		"t",		0,    (int) M_MSGWAIT_T,INSN_MACRO,		0,		XLR|XLP,	0,	0 },
+{"msgsync",		"",		0x4a000004, 0xffffffff,0,			0,		XLP,		0,	0 },
 {"msub.d",		"D,R,S,T",	0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I4_33,		0,	I37 },
 {"msub.d",		"D,S,T",	0x46200019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"msub.d",		"D,S,T",	0x72200019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
@@ -1536,7 +1545,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtlo",		"s,7",		0x00000013, 0xfc1fe7ff, RD_1|WR_LO,		0,		0,		D32,	0 },
 {"mtlo1",		"s",		0x70000013, 0xfc1fffff,	RD_1|WR_LO,		0,		EE,		0,	0 },
 {"mtlhx",		"s",		0x00000053, 0xfc1fffff,	RD_1|MOD_HILO,		0,		0,		SMT,	0 },
-{"mtcr",		"t,s",		0x70000019, 0xfc00ffff, RD_1|RD_2,		0,		XLR,		0,	0 },
+{"mtcr",		"t,s",		0x70000019, 0xfc00ffff, RD_1,			0,		XLR|XLP,	0,	0 },
 {"mtm0",		"s",		0x70000008, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
 {"mtm0",    		"s,t",		0x70000008, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtm1",		"s",		0x7000000c, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
@@ -1978,9 +1987,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"suxc1",		"S,t(b)",	0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D,	0,		I5_33|N55,	0,	I37},
 {"sw",			"t,o(b)",	0xac000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I1,		0,	0 },
 {"sw",			"t,A(b)",	0,    (int) M_SW_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-{"swapw",		"t,b",		0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
-{"swapwu",		"t,b",		0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
-{"swapd",		"t,b",		0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM,	0,		XLR,		0,	0 },
+{"swapw",		"t,b",		0x70000014, 0xfc00ffff, MOD_1|RD_2|SM,		0,		XLR|XLP,	0,	0 },
+{"swapwu",		"t,b",		0x70000015, 0xfc00ffff, MOD_1|RD_2|SM,		0,		XLR|XLP,	0,	0 },
+{"swapd",		"t,b",		0x70000016, 0xfc00ffff, MOD_1|RD_2|SM,		0,		XLR|XLP,	0,	0 },
 {"swc0",		"E,o(b)",	0xe0000000, 0xfc000000,	RD_3|RD_C0|SM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
 {"swc0",		"E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,		0,		I1,		0,	IOCT|IOCTP|IOCT2|I37 },
 {"swc1",		"T,o(b)",	0xe4000000, 0xfc000000,	RD_1|RD_3|SM|FP_S,	0,		I1,		0,	0 },
-- 
2.28.0