blob: fdcfd5d81e707e898e28b035f4964b231ec6a1ad [file] [log] [blame]
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +10301{
2 "name": "rainier",
3 "version": "A3",
4 "data_region": {
5 "ecc_region": true,
6 "key": [
7 {
8 "types": "rsa_pub_oem",
9 "key_pem": "rsa_pub_oem_dss_key.pem",
10 "offset": "0x40",
11 "number_id": 0,
12 "sha_mode": "SHA512"
13 },
14 {
15 "types": "rsa_pub_oem",
16 "key_pem": "P10BMCAspeedSBPubKey_1.pem",
17 "offset": "0x240",
18 "number_id": 1,
19 "sha_mode": "SHA512"
20 },
21 {
22 "types": "rsa_pub_oem",
23 "key_pem": "P10BMCAspeedSBPubKey_2.pem",
24 "offset": "0x440",
25 "number_id": 2,
26 "sha_mode": "SHA512"
27 },
28 {
29 "types": "rsa_pub_oem",
30 "key_pem": "P10BMCAspeedSBPubKey_3.pem",
31 "offset": "0x640",
32 "number_id": 3,
33 "sha_mode": "SHA512"
34 }
35 ]
36 },
37 "config_region": {
38 "Disable OTP Memory BIST Mode": true,
39 "Enable Secure Boot": false,
40 "User region ECC enable": true,
41 "Secure Region ECC enable": false,
42 "Disable low security key": false,
43 "Ignore Secure Boot hardware strap": false,
44 "Secure Boot Mode": "Mode_2",
45 "Disable Uart Message of ROM code": false,
46 "Secure crypto RSA length": "RSA4096",
47 "Hash mode": "SHA512",
48 "Disable patch code": true,
49 "Disable Boot from Uart": false,
50 "Secure Region size": "0x0",
51 "Write Protect: Secure Region": true,
52 "Write Protect: User region": true,
53 "Write Protect: Configure region": true,
54 "Write Protect: OTP strap region": true,
55 "Copy Boot Image to Internal SRAM": true,
56 "Enable image encryption": false,
57 "Enable write Protect of OTP key retire bits": false,
58 "Disable Auto Boot from UART or VUART": false,
59 "OTP memory lock enable": false,
60 "Key Revision": "0x0",
61 "Secure boot header offset": "0x0",
62 "Boot From UART Port Selection": "UART5",
63 "Disable Auto Boot from UART": false,
64 "Disable Auto Boot from VUART2 over PCIE": true,
65 "Disable Auto Boot from VUART2 over LPC": true,
66 "Disable ROM code based programming control": true,
67 "Rollback prevention shift bit number": "0x0",
68 "Extra Data Write Protection Region Size": "0x0",
69 "Erase signature data after secure boot check": false,
70 "Erase RSA public key after secure boot check": false,
71 "Keys Retire ID": 0,
72 "User define data: random number low": "0x0",
73 "User define data: random number high": "0x0",
74 "Manifest ID": "0x0",
75 "Patch code location": "0x0",
76 "Patch code size": "0x0"
77 },
78 "otp_strap": {
79 "Enable secure boot": { "value": false },
80 "Enable boot from eMMC": { "value": true },
81 "Boot from debug SPI": { "value": false },
82 "Disable ARM CM3": { "value": true },
83 "Enable dedicated VGA BIOS ROM": { "value": false },
84 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
85 "MAC 2 RMII mode": { "value": "RMII/NCSI" },
86 "CPU frequency": { "value": "1.2GHz" },
87 "HCLK ratio": { "value": "default" },
88 "VGA memory size": { "value": "16MB" },
89 "CPU/AXI clock ratio": { "value": "2:1" },
90 "Disable ARM JTAG debug": { "value": true },
91 "VGA class code": { "value": "vga_device" },
92 "Disable debug 0": { "value": false },
93 "Boot from eMMC speed mode": { "value": "normal" },
94 "Enable PCIe EHCI": { "value": false },
95 "Disable ARM JTAG trust world debug": { "value": true },
96 "Disable dedicated BMC function": { "value": false },
97 "Enable dedicate PCIe RC reset": { "value": false },
98 "Disable watchdog to reset full chip": { "value": false },
99 "Internal bridge speed selection": { "value": "1x" },
100 "Disable RVAS function": { "value": false },
101 "MAC 3 RMII mode": { "value": "RMII/NCSI" },
102 "MAC 4 RMII mode": { "value": "RMII/NCSI" },
103 "SuperIO configuration address selection": { "value": "0x2e" },
104 "Disable LPC to decode SuperIO": { "value": true },
105 "Disable debug 1": { "value": false },
106 "Enable ACPI": { "value": false },
107 "Select LPC/eSPI": { "value": "LPC" },
108 "Enable SAFS": { "value": false },
109 "Enable boot from uart5": { "value": false },
110 "Enable boot SPI 3B address mode auto-clear": { "value": false },
111 "Enable SPI 3B/4B address mode auto detection": { "value": false },
112 "Enable boot SPI or eMMC ABR": { "value": true },
113 "Boot SPI ABR Mode": { "value": "dual" },
114 "Boot SPI flash size": { "value": "0" },
115 "Enable host SPI ABR": { "value": false },
116 "Enable host SPI ABR mode select pin": { "value": false },
117 "Host SPI ABR Mode": { "value": "dual" },
118 "Host SPI flash size": { "value": "0" },
119 "Enable boot SPI auxiliary control pins": { "value": false },
120 "Boot SPI CRTM size": { "value": "0" },
121 "Host SPI CRTM size": { "value": "0" },
122 "Enable host SPI auxiliary control pins": { "value": false },
123 "Enable GPIO Pass Through": { "value": false },
124 "Enable Dedicate GPIO Strap Pins": { "value": false }
125 }
126}