Patrick Williams | c124f4f | 2015-09-15 14:41:29 -0500 | [diff] [blame] | 1 | From: Xin Ouyang <Xin.Ouyang@windriver.com> |
| 2 | Date: Mon, 16 Jul 2012 13:29:34 +0800 |
| 3 | Subject: [PATCH] tremor: add IT instructions for arm thumb2 tune flags. |
| 4 | |
| 5 | Upstream-Status: Pending |
| 6 | |
| 7 | In Thumb-2, most instructions do not have a built in condition code (except for |
| 8 | conditional branches). Instead, short sequences of instructions which are to be |
| 9 | executed conditionally can be preceded by a special "IT instruction" which |
| 10 | describes the condition and which of the following instructions should be |
| 11 | executed if the condition is false respectively. |
| 12 | |
| 13 | For the ARM/Thumb IT(If-Then) instruction: |
| 14 | http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Cjabicci.html |
| 15 | |
| 16 | Signed-off-by: Xin Ouyang <Xin.Ouyang@windriver.com> |
| 17 | --- |
| 18 | asm_arm.h | 14 ++++++++++++++ |
| 19 | 1 file changed, 14 insertions(+) |
| 20 | |
| 21 | diff --git a/asm_arm.h b/asm_arm.h |
| 22 | index c3bda00..823c54f 100755 |
| 23 | --- a/asm_arm.h |
| 24 | +++ b/asm_arm.h |
| 25 | @@ -108,9 +108,11 @@ static inline void XNPROD31(ogg_int32_t a, ogg_int32_t b, |
| 26 | static inline ogg_int32_t CLIP_TO_15(ogg_int32_t x) { |
| 27 | int tmp; |
| 28 | asm volatile("subs %1, %0, #32768\n\t" |
| 29 | + "itt pl\n\t" |
| 30 | "movpl %0, #0x7f00\n\t" |
| 31 | "orrpl %0, %0, #0xff\n" |
| 32 | "adds %1, %0, #32768\n\t" |
| 33 | + "it mi\n\t" |
| 34 | "movmi %0, #0x8000" |
| 35 | : "+r"(x),"=r"(tmp) |
| 36 | : |
| 37 | @@ -139,10 +141,12 @@ static inline void lsp_loop_asm(ogg_uint32_t *qip,ogg_uint32_t *pip, |
| 38 | |
| 39 | "ldmdb r0!,{r1,r3};" |
| 40 | "subs r1,r1,%4;" //ilsp[j]-wi |
| 41 | + "it mi;" |
| 42 | "rsbmi r1,r1,#0;" //labs(ilsp[j]-wi) |
| 43 | "umull %0,r2,r1,%0;" //qi*=labs(ilsp[j]-wi) |
| 44 | |
| 45 | "subs r1,r3,%4;" //ilsp[j+1]-wi |
| 46 | + "it mi;" |
| 47 | "rsbmi r1,r1,#0;" //labs(ilsp[j+1]-wi) |
| 48 | "umull %1,r3,r1,%1;" //pi*=labs(ilsp[j+1]-wi) |
| 49 | |
| 50 | @@ -167,6 +171,7 @@ static inline void lsp_loop_asm(ogg_uint32_t *qip,ogg_uint32_t *pip, |
| 51 | "mov r0,#0x4000;\n" |
| 52 | |
| 53 | "subs r1,r1,%4;\n" //ilsp[j]-wi |
| 54 | + "it mi;\n" |
| 55 | "rsbmi r1,r1,#0;\n" //labs(ilsp[j]-wi) |
| 56 | "umull %0,r2,r1,%0;\n" //qi*=labs(ilsp[j]-wi) |
| 57 | "umull %1,r3,r0,%1;\n" //pi*=labs(ilsp[j+1]-wi) |
| 58 | @@ -190,18 +195,23 @@ static inline void lsp_loop_asm(ogg_uint32_t *qip,ogg_uint32_t *pip, |
| 59 | "mov r2,#0;" |
| 60 | "orr r1,%0,%1;" |
| 61 | "tst r1,#0xff000000;" |
| 62 | + "itt ne;" |
| 63 | "addne r2,r2,#8;" |
| 64 | "movne r1,r1,lsr #8;" |
| 65 | "tst r1,#0x00f00000;" |
| 66 | + "itt ne;" |
| 67 | "addne r2,r2,#4;" |
| 68 | "movne r1,r1,lsr #4;" |
| 69 | "tst r1,#0x000c0000;" |
| 70 | + "itt ne;" |
| 71 | "addne r2,r2,#2;" |
| 72 | "movne r1,r1,lsr #2;" |
| 73 | "tst r1,#0x00020000;" |
| 74 | + "itt ne;" |
| 75 | "addne r2,r2,#1;" |
| 76 | "movne r1,r1,lsr #1;" |
| 77 | "tst r1,#0x00010000;" |
| 78 | + "it ne;" |
| 79 | "addne r2,r2,#1;" |
| 80 | "mov %0,%0,lsr r2;" |
| 81 | "mov %1,%1,lsr r2;" |
| 82 | @@ -222,15 +232,19 @@ static inline void lsp_norm_asm(ogg_uint32_t *qip,ogg_int32_t *qexpp){ |
| 83 | ogg_int32_t qexp=*qexpp; |
| 84 | |
| 85 | asm("tst %0,#0x0000ff00;" |
| 86 | + "itt eq;" |
| 87 | "moveq %0,%0,lsl #8;" |
| 88 | "subeq %1,%1,#8;" |
| 89 | "tst %0,#0x0000f000;" |
| 90 | + "itt eq;" |
| 91 | "moveq %0,%0,lsl #4;" |
| 92 | "subeq %1,%1,#4;" |
| 93 | "tst %0,#0x0000c000;" |
| 94 | + "itt eq;" |
| 95 | "moveq %0,%0,lsl #2;" |
| 96 | "subeq %1,%1,#2;" |
| 97 | "tst %0,#0x00008000;" |
| 98 | + "itt eq;" |
| 99 | "moveq %0,%0,lsl #1;" |
| 100 | "subeq %1,%1,#1;" |
| 101 | : "+r"(qi),"+r"(qexp) |
| 102 | -- |
| 103 | 1.7.9.5 |
| 104 | |